diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
--- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -1161,6 +1161,13 @@
 def : Pat<(v16i8 (srl (sub v16i8:$vA, (v16i8 (bitconvert(vnot v4i32:$vB)))),
           (v16i8 (immEQOneV)))), (v16i8 (VAVGUB $vA, $vB))>;
 
+def : Pat<(v16i8 (shl v16i8:$vA, (v16i8 (immEQOneV)))),
+          (v16i8 (VADDUBM $vA, $vA))>;
+def : Pat<(v8i16 (shl v8i16:$vA, (v8i16 (immEQOneV)))),
+          (v8i16 (VADDUHM $vA, $vA))>;
+def : Pat<(v4i32 (shl v4i32:$vA, (v4i32 (immEQOneV)))),
+          (v4i32 (VADDUWM $vA, $vA))>;
+
 } // end HasAltivec
 
 // [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set.
diff --git a/llvm/test/CodeGen/PowerPC/optimize-vector.ll b/llvm/test/CodeGen/PowerPC/optimize-vector.ll
--- a/llvm/test/CodeGen/PowerPC/optimize-vector.ll
+++ b/llvm/test/CodeGen/PowerPC/optimize-vector.ll
@@ -6,8 +6,7 @@
 define dso_local <16 x i8> @x2(<16 x i8> noundef %x) {
 ; CHECK-LABEL: x2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vspltisb v3, 1
-; CHECK-NEXT:    vslb v2, v2, v3
+; CHECK-NEXT:    vaddubm v2, v2, v2
 ; CHECK-NEXT:    blr
 entry:
   %add = shl <16 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -17,8 +16,7 @@
 define dso_local <8 x i16> @x2h(<8 x i16> noundef %x) {
 ; CHECK-LABEL: x2h:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vspltish v3, 1
-; CHECK-NEXT:    vslh v2, v2, v3
+; CHECK-NEXT:    vadduhm v2, v2, v2
 ; CHECK-NEXT:    blr
 entry:
   %add = shl <8 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -28,8 +26,7 @@
 define dso_local <4 x i32> @x2w(<4 x i32> noundef %x) {
 ; CHECK-LABEL: x2w:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vspltisw v3, 1
-; CHECK-NEXT:    vslw v2, v2, v3
+; CHECK-NEXT:    vadduwm v2, v2, v2
 ; CHECK-NEXT:    blr
 entry:
   %add = shl <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>