Index: llvm/lib/Target/Mips/MipsISelLowering.cpp
===================================================================
--- llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -102,29 +102,37 @@
   if (!VT.isVector())
     return getRegisterType(Context, VT);
 
-  return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32
-                                                           : MVT::i64;
+  if (VT.isPow2VectorType() && VT.getVectorElementType().isRound())
+    return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32
+                                                             : MVT::i64;
+  return getRegisterType(Context, VT.getVectorElementType());
 }
 
 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
                                                            CallingConv::ID CC,
                                                            EVT VT) const {
-  if (VT.isVector())
-    return divideCeil(VT.getSizeInBits(), Subtarget.isABI_O32() ? 32 : 64);
+  if (VT.isVector()) {
+    if (VT.isPow2VectorType() && VT.getVectorElementType().isRound())
+      return divideCeil(VT.getSizeInBits(), Subtarget.isABI_O32() ? 32 : 64);
+    return VT.getVectorNumElements() *
+           getNumRegisters(Context, VT.getVectorElementType());
+  }
   return MipsTargetLowering::getNumRegisters(Context, VT);
 }
 
 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv(
     LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
     unsigned &NumIntermediates, MVT &RegisterVT) const {
-  // Break down vector types to either 2 i64s or 4 i32s.
-  RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT);
-  IntermediateVT = RegisterVT;
-  NumIntermediates =
-      VT.getFixedSizeInBits() < RegisterVT.getFixedSizeInBits()
-          ? VT.getVectorNumElements()
-          : divideCeil(VT.getSizeInBits(), RegisterVT.getSizeInBits());
-  return NumIntermediates;
+  if (VT.isPow2VectorType()) {
+    IntermediateVT = getRegisterTypeForCallingConv(Context, CC, VT);
+    RegisterVT = IntermediateVT.getSimpleVT();
+    NumIntermediates = getNumRegistersForCallingConv(Context, CC, VT);
+    return NumIntermediates;
+  }
+  IntermediateVT = VT.getVectorElementType();
+  NumIntermediates = VT.getVectorNumElements();
+  RegisterVT = getRegisterType(Context, IntermediateVT);
+  return NumIntermediates * getNumRegisters(Context, IntermediateVT);
 }
 
 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
Index: llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll
@@ -0,0 +1,792 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=mips64 < %s | FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips < %s | FileCheck %s --check-prefix=MIPS32
+
+define void @v1i32(<1 x i32> %vec, ptr %p) {
+; MIPS64-LABEL: v1i32:
+; MIPS64:       # %bb.0:
+; MIPS64-NEXT:    jr $ra
+; MIPS64-NEXT:    sw $4, 0($5)
+;
+; MIPS32-LABEL: v1i32:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    sw $4, 0($5)
+  store <1 x i32> %vec, ptr %p
+  ret void
+}
+
+define void @v2i32(<2 x i32> %vec, ptr %p) {
+; MIPS64-LABEL: v2i32:
+; MIPS64:       # %bb.0:
+; MIPS64-NEXT:    jr $ra
+; MIPS64-NEXT:    sd $4, 0($5)
+;
+; MIPS32-LABEL: v2i32:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    sw $5, 4($6)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    sw $4, 0($6)
+  store <2 x i32> %vec, ptr %p
+  ret void
+}
+
+define void @v3i32(<3 x i32> %vec, ptr %p) {
+; MIPS64-LABEL: v3i32:
+; MIPS64:       # %bb.0:
+; MIPS64-NEXT:    daddiu $1, $zero, 1
+; MIPS64-NEXT:    dsll $1, $1, 32
+; MIPS64-NEXT:    sw $6, 8($7)
+; MIPS64-NEXT:    daddiu $1, $1, -1
+; MIPS64-NEXT:    and $1, $5, $1
+; MIPS64-NEXT:    dsll $2, $4, 32
+; MIPS64-NEXT:    or $1, $1, $2
+; MIPS64-NEXT:    jr $ra
+; MIPS64-NEXT:    sd $1, 0($7)
+;
+; MIPS32-LABEL: v3i32:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    sw $6, 8($7)
+; MIPS32-NEXT:    sw $5, 4($7)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    sw $4, 0($7)
+  store <3 x i32> %vec, ptr %p
+  ret void
+}
+
+define void @v4i32(<4 x i32> %vec, ptr %p) {
+; MIPS64-LABEL: v4i32:
+; MIPS64:       # %bb.0:
+; MIPS64-NEXT:    sd $5, 8($6)
+; MIPS64-NEXT:    jr $ra
+; MIPS64-NEXT:    sd $4, 0($6)
+;
+; MIPS32-LABEL: v4i32:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    lw $1, 16($sp)
+; MIPS32-NEXT:    sw $7, 12($1)
+; MIPS32-NEXT:    sw $6, 8($1)
+; MIPS32-NEXT:    sw $5, 4($1)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    sw $4, 0($1)
+  store <4 x i32> %vec, ptr %p
+  ret void
+}
+
+define void @v5i32(<5 x i32> %vec, ptr %p) {
+; MIPS64-LABEL: v5i32:
+; MIPS64:       # %bb.0:
+; MIPS64-NEXT:    daddiu $1, $zero, 1
+; MIPS64-NEXT:    dsll $1, $1, 32
+; MIPS64-NEXT:    daddiu $1, $1, -1
+; MIPS64-NEXT:    and $2, $7, $1
+; MIPS64-NEXT:    dsll $3, $6, 32
+; MIPS64-NEXT:    or $2, $2, $3
+; MIPS64-NEXT:    sw $8, 16($9)
+; MIPS64-NEXT:    sd $2, 8($9)
+; MIPS64-NEXT:    and $1, $5, $1
+; MIPS64-NEXT:    dsll $2, $4, 32
+; MIPS64-NEXT:    or $1, $1, $2
+; MIPS64-NEXT:    jr $ra
+; MIPS64-NEXT:    sd $1, 0($9)
+;
+; MIPS32-LABEL: v5i32:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    lw $1, 20($sp)
+; MIPS32-NEXT:    lw $2, 16($sp)
+; MIPS32-NEXT:    sw $2, 16($1)
+; MIPS32-NEXT:    sw $7, 12($1)
+; MIPS32-NEXT:    sw $6, 8($1)
+; MIPS32-NEXT:    sw $5, 4($1)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    sw $4, 0($1)
+  store <5 x i32> %vec, ptr %p
+  ret void
+}
+
+define void @v16i32(<16 x i32> %vec, ptr %p) {
+; MIPS64-LABEL: v16i32:
+; MIPS64:       # %bb.0:
+; MIPS64-NEXT:    ld $1, 0($sp)
+; MIPS64-NEXT:    sd $11, 56($1)
+; MIPS64-NEXT:    sd $10, 48($1)
+; MIPS64-NEXT:    sd $9, 40($1)
+; MIPS64-NEXT:    sd $8, 32($1)
+; MIPS64-NEXT:    sd $7, 24($1)
+; MIPS64-NEXT:    sd $6, 16($1)
+; MIPS64-NEXT:    sd $5, 8($1)
+; MIPS64-NEXT:    jr $ra
+; MIPS64-NEXT:    sd $4, 0($1)
+;
+; MIPS32-LABEL: v16i32:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    lw $1, 16($sp)
+; MIPS32-NEXT:    lw $2, 20($sp)
+; MIPS32-NEXT:    lw $3, 24($sp)
+; MIPS32-NEXT:    lw $8, 28($sp)
+; MIPS32-NEXT:    lw $9, 32($sp)
+; MIPS32-NEXT:    lw $10, 36($sp)
+; MIPS32-NEXT:    lw $11, 40($sp)
+; MIPS32-NEXT:    lw $12, 44($sp)
+; MIPS32-NEXT:    lw $13, 48($sp)
+; MIPS32-NEXT:    lw $14, 52($sp)
+; MIPS32-NEXT:    lw $15, 56($sp)
+; MIPS32-NEXT:    lw $24, 64($sp)
+; MIPS32-NEXT:    lw $25, 60($sp)
+; MIPS32-NEXT:    sw $25, 60($24)
+; MIPS32-NEXT:    sw $15, 56($24)
+; MIPS32-NEXT:    sw $14, 52($24)
+; MIPS32-NEXT:    sw $13, 48($24)
+; MIPS32-NEXT:    sw $12, 44($24)
+; MIPS32-NEXT:    sw $11, 40($24)
+; MIPS32-NEXT:    sw $10, 36($24)
+; MIPS32-NEXT:    sw $9, 32($24)
+; MIPS32-NEXT:    sw $8, 28($24)
+; MIPS32-NEXT:    sw $3, 24($24)
+; MIPS32-NEXT:    sw $2, 20($24)
+; MIPS32-NEXT:    sw $1, 16($24)
+; MIPS32-NEXT:    sw $7, 12($24)
+; MIPS32-NEXT:    sw $6, 8($24)
+; MIPS32-NEXT:    sw $5, 4($24)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    sw $4, 0($24)
+  store <16 x i32> %vec, ptr %p
+  ret void
+}
+
+define void @v4i24(<4 x i24> %vec, ptr %p) {
+; MIPS64-LABEL: v4i24:
+; MIPS64:       # %bb.0:
+; MIPS64-NEXT:    sll $1, $7, 0
+; MIPS64-NEXT:    sll $2, $6, 0
+; MIPS64-NEXT:    srl $3, $2, 8
+; MIPS64-NEXT:    srl $6, $1, 16
+; MIPS64-NEXT:    srl $7, $1, 8
+; MIPS64-NEXT:    sll $4, $4, 0
+; MIPS64-NEXT:    sll $5, $5, 0
+; MIPS64-NEXT:    sb $1, 11($8)
+; MIPS64-NEXT:    sb $2, 8($8)
+; MIPS64-NEXT:    sb $5, 5($8)
+; MIPS64-NEXT:    sb $4, 2($8)
+; MIPS64-NEXT:    sb $7, 10($8)
+; MIPS64-NEXT:    sb $6, 9($8)
+; MIPS64-NEXT:    sh $3, 6($8)
+; MIPS64-NEXT:    srl $1, $5, 8
+; MIPS64-NEXT:    sb $1, 4($8)
+; MIPS64-NEXT:    srl $1, $5, 16
+; MIPS64-NEXT:    sb $1, 3($8)
+; MIPS64-NEXT:    srl $1, $4, 8
+; MIPS64-NEXT:    jr $ra
+; MIPS64-NEXT:    sh $1, 0($8)
+;
+; MIPS32-LABEL: v4i24:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    srl $1, $6, 8
+; MIPS32-NEXT:    srl $2, $7, 16
+; MIPS32-NEXT:    srl $3, $7, 8
+; MIPS32-NEXT:    lw $8, 16($sp)
+; MIPS32-NEXT:    sb $7, 11($8)
+; MIPS32-NEXT:    sb $6, 8($8)
+; MIPS32-NEXT:    sb $5, 5($8)
+; MIPS32-NEXT:    sb $4, 2($8)
+; MIPS32-NEXT:    sb $3, 10($8)
+; MIPS32-NEXT:    sb $2, 9($8)
+; MIPS32-NEXT:    sh $1, 6($8)
+; MIPS32-NEXT:    srl $1, $5, 8
+; MIPS32-NEXT:    sb $1, 4($8)
+; MIPS32-NEXT:    srl $1, $5, 16
+; MIPS32-NEXT:    sb $1, 3($8)
+; MIPS32-NEXT:    srl $1, $4, 8
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    sh $1, 0($8)
+  store <4 x i24> %vec, ptr %p
+  ret void
+}
+
+define void @v5i24(<5 x i24> %vec, ptr %p) {
+; MIPS64-LABEL: v5i24:
+; MIPS64:       # %bb.0:
+; MIPS64-NEXT:    sll $1, $8, 0
+; MIPS64-NEXT:    sll $2, $7, 0
+; MIPS64-NEXT:    sll $3, $6, 0
+; MIPS64-NEXT:    srl $6, $3, 8
+; MIPS64-NEXT:    srl $7, $2, 16
+; MIPS64-NEXT:    srl $8, $2, 8
+; MIPS64-NEXT:    srl $10, $1, 8
+; MIPS64-NEXT:    sll $4, $4, 0
+; MIPS64-NEXT:    sll $5, $5, 0
+; MIPS64-NEXT:    sb $1, 14($9)
+; MIPS64-NEXT:    sb $2, 11($9)
+; MIPS64-NEXT:    sb $3, 8($9)
+; MIPS64-NEXT:    sb $5, 5($9)
+; MIPS64-NEXT:    sb $4, 2($9)
+; MIPS64-NEXT:    sh $10, 12($9)
+; MIPS64-NEXT:    sb $8, 10($9)
+; MIPS64-NEXT:    sb $7, 9($9)
+; MIPS64-NEXT:    sh $6, 6($9)
+; MIPS64-NEXT:    srl $1, $5, 8
+; MIPS64-NEXT:    sb $1, 4($9)
+; MIPS64-NEXT:    srl $1, $5, 16
+; MIPS64-NEXT:    sb $1, 3($9)
+; MIPS64-NEXT:    srl $1, $4, 8
+; MIPS64-NEXT:    jr $ra
+; MIPS64-NEXT:    sh $1, 0($9)
+;
+; MIPS32-LABEL: v5i24:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    lw $1, 16($sp)
+; MIPS32-NEXT:    srl $2, $6, 8
+; MIPS32-NEXT:    srl $3, $7, 16
+; MIPS32-NEXT:    srl $8, $7, 8
+; MIPS32-NEXT:    srl $9, $1, 8
+; MIPS32-NEXT:    lw $10, 20($sp)
+; MIPS32-NEXT:    sb $1, 14($10)
+; MIPS32-NEXT:    sb $7, 11($10)
+; MIPS32-NEXT:    sb $6, 8($10)
+; MIPS32-NEXT:    sb $5, 5($10)
+; MIPS32-NEXT:    sb $4, 2($10)
+; MIPS32-NEXT:    sh $9, 12($10)
+; MIPS32-NEXT:    sb $8, 10($10)
+; MIPS32-NEXT:    sb $3, 9($10)
+; MIPS32-NEXT:    sh $2, 6($10)
+; MIPS32-NEXT:    srl $1, $5, 8
+; MIPS32-NEXT:    sb $1, 4($10)
+; MIPS32-NEXT:    srl $1, $5, 16
+; MIPS32-NEXT:    sb $1, 3($10)
+; MIPS32-NEXT:    srl $1, $4, 8
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    sh $1, 0($10)
+  store <5 x i24> %vec, ptr %p
+  ret void
+}
+
+define void @v4i18(<4 x i18> %vec, ptr %p) {
+; MIPS64-LABEL: v4i18:
+; MIPS64:       # %bb.0:
+; MIPS64-NEXT:    lui $1, 3
+; MIPS64-NEXT:    ori $2, $1, 65535
+; MIPS64-NEXT:    and $3, $5, $2
+; MIPS64-NEXT:    dsll $3, $3, 36
+; MIPS64-NEXT:    dsll $5, $4, 54
+; MIPS64-NEXT:    or $3, $5, $3
+; MIPS64-NEXT:    and $2, $6, $2
+; MIPS64-NEXT:    dsll $2, $2, 18
+; MIPS64-NEXT:    or $2, $3, $2
+; MIPS64-NEXT:    ori $1, $1, 65280
+; MIPS64-NEXT:    and $1, $7, $1
+; MIPS64-NEXT:    sb $7, 8($8)
+; MIPS64-NEXT:    or $1, $2, $1
+; MIPS64-NEXT:    daddiu $2, $zero, 255
+; MIPS64-NEXT:    dsrl $1, $1, 8
+; MIPS64-NEXT:    dsll $2, $2, 56
+; MIPS64-NEXT:    dsll $3, $4, 46
+; MIPS64-NEXT:    and $2, $3, $2
+; MIPS64-NEXT:    or $1, $2, $1
+; MIPS64-NEXT:    jr $ra
+; MIPS64-NEXT:    sd $1, 0($8)
+;
+; MIPS32-LABEL: v4i18:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    sll $1, $4, 14
+; MIPS32-NEXT:    lui $2, 63
+; MIPS32-NEXT:    lui $3, 65280
+; MIPS32-NEXT:    and $1, $1, $3
+; MIPS32-NEXT:    ori $2, $2, 65280
+; MIPS32-NEXT:    sll $3, $5, 4
+; MIPS32-NEXT:    and $2, $3, $2
+; MIPS32-NEXT:    sll $4, $4, 22
+; MIPS32-NEXT:    or $2, $4, $2
+; MIPS32-NEXT:    srl $2, $2, 8
+; MIPS32-NEXT:    lui $4, 3
+; MIPS32-NEXT:    or $1, $1, $2
+; MIPS32-NEXT:    ori $2, $4, 65280
+; MIPS32-NEXT:    and $2, $7, $2
+; MIPS32-NEXT:    sll $5, $6, 18
+; MIPS32-NEXT:    or $2, $5, $2
+; MIPS32-NEXT:    lw $5, 16($sp)
+; MIPS32-NEXT:    sb $7, 8($5)
+; MIPS32-NEXT:    sw $1, 0($5)
+; MIPS32-NEXT:    srl $1, $2, 8
+; MIPS32-NEXT:    ori $2, $4, 49152
+; MIPS32-NEXT:    and $2, $6, $2
+; MIPS32-NEXT:    srl $2, $2, 14
+; MIPS32-NEXT:    or $2, $3, $2
+; MIPS32-NEXT:    sll $2, $2, 24
+; MIPS32-NEXT:    or $1, $1, $2
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    sw $1, 4($5)
+  store <4 x i18> %vec, ptr %p
+  ret void
+}
+
+define void @v7i18(<7 x i18> %vec, ptr %p) {
+; MIPS64-LABEL: v7i18:
+; MIPS64:       # %bb.0:
+; MIPS64-NEXT:    lui $1, 3
+; MIPS64-NEXT:    ori $2, $1, 65535
+; MIPS64-NEXT:    and $3, $8, $2
+; MIPS64-NEXT:    dsll $3, $3, 36
+; MIPS64-NEXT:    dsll $8, $7, 54
+; MIPS64-NEXT:    or $3, $8, $3
+; MIPS64-NEXT:    and $8, $9, $2
+; MIPS64-NEXT:    dsll $8, $8, 18
+; MIPS64-NEXT:    or $3, $3, $8
+; MIPS64-NEXT:    and $5, $5, $2
+; MIPS64-NEXT:    and $8, $10, $2
+; MIPS64-NEXT:    or $3, $3, $8
+; MIPS64-NEXT:    dsll $5, $5, 26
+; MIPS64-NEXT:    dsll $4, $4, 44
+; MIPS64-NEXT:    or $4, $4, $5
+; MIPS64-NEXT:    and $2, $6, $2
+; MIPS64-NEXT:    dsll $2, $2, 8
+; MIPS64-NEXT:    sd $3, 8($11)
+; MIPS64-NEXT:    or $2, $4, $2
+; MIPS64-NEXT:    ori $1, $1, 64512
+; MIPS64-NEXT:    and $1, $7, $1
+; MIPS64-NEXT:    dsrl $1, $1, 10
+; MIPS64-NEXT:    or $1, $2, $1
+; MIPS64-NEXT:    daddiu $2, $zero, 1
+; MIPS64-NEXT:    dsll $2, $2, 62
+; MIPS64-NEXT:    daddiu $2, $2, -1
+; MIPS64-NEXT:    and $1, $1, $2
+; MIPS64-NEXT:    jr $ra
+; MIPS64-NEXT:    sd $1, 0($11)
+;
+; MIPS32-LABEL: v7i18:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    lui $1, 3
+; MIPS32-NEXT:    ori $2, $1, 65535
+; MIPS32-NEXT:    and $3, $6, $2
+; MIPS32-NEXT:    sll $3, $3, 8
+; MIPS32-NEXT:    ori $6, $1, 65472
+; MIPS32-NEXT:    and $6, $5, $6
+; MIPS32-NEXT:    srl $6, $6, 6
+; MIPS32-NEXT:    sll $5, $5, 26
+; MIPS32-NEXT:    sll $4, $4, 12
+; MIPS32-NEXT:    or $4, $4, $6
+; MIPS32-NEXT:    or $3, $5, $3
+; MIPS32-NEXT:    ori $5, $1, 64512
+; MIPS32-NEXT:    and $5, $7, $5
+; MIPS32-NEXT:    srl $5, $5, 10
+; MIPS32-NEXT:    lui $6, 16383
+; MIPS32-NEXT:    ori $6, $6, 65535
+; MIPS32-NEXT:    lw $8, 24($sp)
+; MIPS32-NEXT:    lw $9, 16($sp)
+; MIPS32-NEXT:    or $3, $3, $5
+; MIPS32-NEXT:    and $5, $9, $2
+; MIPS32-NEXT:    and $4, $4, $6
+; MIPS32-NEXT:    and $2, $8, $2
+; MIPS32-NEXT:    lw $6, 20($sp)
+; MIPS32-NEXT:    sll $8, $6, 18
+; MIPS32-NEXT:    or $2, $8, $2
+; MIPS32-NEXT:    lw $8, 28($sp)
+; MIPS32-NEXT:    sw $2, 12($8)
+; MIPS32-NEXT:    sw $4, 0($8)
+; MIPS32-NEXT:    sw $3, 4($8)
+; MIPS32-NEXT:    sll $2, $5, 4
+; MIPS32-NEXT:    sll $3, $7, 22
+; MIPS32-NEXT:    or $2, $3, $2
+; MIPS32-NEXT:    ori $1, $1, 49152
+; MIPS32-NEXT:    and $1, $6, $1
+; MIPS32-NEXT:    srl $1, $1, 14
+; MIPS32-NEXT:    or $1, $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    sw $1, 8($8)
+  store <7 x i18> %vec, ptr %p
+  ret void
+}
+
+define void @v2i128(<2 x i128> %vec, ptr %p) {
+; MIPS64-LABEL: v2i128:
+; MIPS64:       # %bb.0:
+; MIPS64-NEXT:    sd $7, 24($8)
+; MIPS64-NEXT:    sd $6, 16($8)
+; MIPS64-NEXT:    sd $5, 8($8)
+; MIPS64-NEXT:    jr $ra
+; MIPS64-NEXT:    sd $4, 0($8)
+;
+; MIPS32-LABEL: v2i128:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    lw $1, 16($sp)
+; MIPS32-NEXT:    lw $2, 20($sp)
+; MIPS32-NEXT:    lw $3, 24($sp)
+; MIPS32-NEXT:    lw $8, 32($sp)
+; MIPS32-NEXT:    lw $9, 28($sp)
+; MIPS32-NEXT:    sw $9, 28($8)
+; MIPS32-NEXT:    sw $3, 24($8)
+; MIPS32-NEXT:    sw $2, 20($8)
+; MIPS32-NEXT:    sw $1, 16($8)
+; MIPS32-NEXT:    sw $7, 12($8)
+; MIPS32-NEXT:    sw $6, 8($8)
+; MIPS32-NEXT:    sw $5, 4($8)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    sw $4, 0($8)
+  store <2 x i128> %vec, ptr %p
+  ret void
+}
+
+define void @v3i128(<3 x i128> %vec, ptr %p) {
+; MIPS64-LABEL: v3i128:
+; MIPS64:       # %bb.0:
+; MIPS64-NEXT:    sd $9, 40($10)
+; MIPS64-NEXT:    sd $8, 32($10)
+; MIPS64-NEXT:    sd $7, 24($10)
+; MIPS64-NEXT:    sd $6, 16($10)
+; MIPS64-NEXT:    sd $5, 8($10)
+; MIPS64-NEXT:    jr $ra
+; MIPS64-NEXT:    sd $4, 0($10)
+;
+; MIPS32-LABEL: v3i128:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    lw $1, 16($sp)
+; MIPS32-NEXT:    lw $2, 20($sp)
+; MIPS32-NEXT:    lw $3, 24($sp)
+; MIPS32-NEXT:    lw $8, 28($sp)
+; MIPS32-NEXT:    lw $9, 32($sp)
+; MIPS32-NEXT:    lw $10, 36($sp)
+; MIPS32-NEXT:    lw $11, 40($sp)
+; MIPS32-NEXT:    lw $12, 48($sp)
+; MIPS32-NEXT:    lw $13, 44($sp)
+; MIPS32-NEXT:    sw $13, 44($12)
+; MIPS32-NEXT:    sw $11, 40($12)
+; MIPS32-NEXT:    sw $10, 36($12)
+; MIPS32-NEXT:    sw $9, 32($12)
+; MIPS32-NEXT:    sw $8, 28($12)
+; MIPS32-NEXT:    sw $3, 24($12)
+; MIPS32-NEXT:    sw $2, 20($12)
+; MIPS32-NEXT:    sw $1, 16($12)
+; MIPS32-NEXT:    sw $7, 12($12)
+; MIPS32-NEXT:    sw $6, 8($12)
+; MIPS32-NEXT:    sw $5, 4($12)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    sw $4, 0($12)
+  store <3 x i128> %vec, ptr %p
+  ret void
+}
+
+define void @test(ptr %p) nounwind {
+; MIPS64-LABEL: test:
+; MIPS64:       # %bb.0:
+; MIPS64-NEXT:    daddiu $sp, $sp, -16
+; MIPS64-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
+; MIPS64-NEXT:    sd $16, 0($sp) # 8-byte Folded Spill
+; MIPS64-NEXT:    move $16, $4
+; MIPS64-NEXT:    lw $4, 0($4)
+; MIPS64-NEXT:    jal v1i32
+; MIPS64-NEXT:    nop
+; MIPS64-NEXT:    ld $4, 0($16)
+; MIPS64-NEXT:    jal v2i32
+; MIPS64-NEXT:    nop
+; MIPS64-NEXT:    lw $6, 8($16)
+; MIPS64-NEXT:    ld $5, 0($16)
+; MIPS64-NEXT:    jal v3i32
+; MIPS64-NEXT:    dsrl $4, $5, 32
+; MIPS64-NEXT:    ld $5, 8($16)
+; MIPS64-NEXT:    ld $4, 0($16)
+; MIPS64-NEXT:    jal v4i32
+; MIPS64-NEXT:    nop
+; MIPS64-NEXT:    lw $8, 16($16)
+; MIPS64-NEXT:    ld $7, 8($16)
+; MIPS64-NEXT:    ld $5, 0($16)
+; MIPS64-NEXT:    dsrl $4, $5, 32
+; MIPS64-NEXT:    jal v5i32
+; MIPS64-NEXT:    dsrl $6, $7, 32
+; MIPS64-NEXT:    ld $11, 56($16)
+; MIPS64-NEXT:    ld $10, 48($16)
+; MIPS64-NEXT:    ld $9, 40($16)
+; MIPS64-NEXT:    ld $8, 32($16)
+; MIPS64-NEXT:    ld $7, 24($16)
+; MIPS64-NEXT:    ld $6, 16($16)
+; MIPS64-NEXT:    ld $5, 8($16)
+; MIPS64-NEXT:    ld $4, 0($16)
+; MIPS64-NEXT:    jal v16i32
+; MIPS64-NEXT:    nop
+; MIPS64-NEXT:    lbu $1, 4($16)
+; MIPS64-NEXT:    dsll $1, $1, 8
+; MIPS64-NEXT:    lb $2, 3($16)
+; MIPS64-NEXT:    dsll $2, $2, 16
+; MIPS64-NEXT:    or $1, $2, $1
+; MIPS64-NEXT:    lbu $2, 10($16)
+; MIPS64-NEXT:    lbu $3, 5($16)
+; MIPS64-NEXT:    lbu $5, 8($16)
+; MIPS64-NEXT:    lh $4, 6($16)
+; MIPS64-NEXT:    dsll $6, $4, 8
+; MIPS64-NEXT:    lbu $4, 2($16)
+; MIPS64-NEXT:    lh $7, 0($16)
+; MIPS64-NEXT:    dsll $7, $7, 8
+; MIPS64-NEXT:    or $4, $4, $7
+; MIPS64-NEXT:    or $6, $5, $6
+; MIPS64-NEXT:    or $5, $3, $1
+; MIPS64-NEXT:    dsll $1, $2, 8
+; MIPS64-NEXT:    lb $2, 9($16)
+; MIPS64-NEXT:    dsll $2, $2, 16
+; MIPS64-NEXT:    or $1, $2, $1
+; MIPS64-NEXT:    lbu $2, 11($16)
+; MIPS64-NEXT:    jal v4i24
+; MIPS64-NEXT:    or $7, $2, $1
+; MIPS64-NEXT:    lbu $1, 4($16)
+; MIPS64-NEXT:    lh $2, 12($16)
+; MIPS64-NEXT:    dsll $1, $1, 8
+; MIPS64-NEXT:    lb $3, 3($16)
+; MIPS64-NEXT:    dsll $3, $3, 16
+; MIPS64-NEXT:    or $1, $3, $1
+; MIPS64-NEXT:    lbu $3, 10($16)
+; MIPS64-NEXT:    lbu $5, 5($16)
+; MIPS64-NEXT:    lbu $7, 14($16)
+; MIPS64-NEXT:    dsll $2, $2, 8
+; MIPS64-NEXT:    lbu $6, 8($16)
+; MIPS64-NEXT:    lh $4, 6($16)
+; MIPS64-NEXT:    dsll $8, $4, 8
+; MIPS64-NEXT:    lbu $4, 2($16)
+; MIPS64-NEXT:    lh $9, 0($16)
+; MIPS64-NEXT:    dsll $9, $9, 8
+; MIPS64-NEXT:    or $4, $4, $9
+; MIPS64-NEXT:    or $6, $6, $8
+; MIPS64-NEXT:    or $8, $7, $2
+; MIPS64-NEXT:    or $5, $5, $1
+; MIPS64-NEXT:    dsll $1, $3, 8
+; MIPS64-NEXT:    lb $2, 9($16)
+; MIPS64-NEXT:    dsll $2, $2, 16
+; MIPS64-NEXT:    or $1, $2, $1
+; MIPS64-NEXT:    lbu $2, 11($16)
+; MIPS64-NEXT:    jal v5i24
+; MIPS64-NEXT:    or $7, $2, $1
+; MIPS64-NEXT:    lui $1, 3
+; MIPS64-NEXT:    ori $1, $1, 65535
+; MIPS64-NEXT:    ld $2, 8($16)
+; MIPS64-NEXT:    dsrl $3, $2, 18
+; MIPS64-NEXT:    dsrl $4, $2, 36
+; MIPS64-NEXT:    ld $11, 0($16)
+; MIPS64-NEXT:    dsrl $6, $11, 8
+; MIPS64-NEXT:    dsrl $5, $11, 26
+; MIPS64-NEXT:    and $10, $2, $1
+; MIPS64-NEXT:    and $5, $5, $1
+; MIPS64-NEXT:    and $6, $6, $1
+; MIPS64-NEXT:    and $8, $4, $1
+; MIPS64-NEXT:    and $9, $3, $1
+; MIPS64-NEXT:    dsll $3, $11, 10
+; MIPS64-NEXT:    dsrl $2, $2, 54
+; MIPS64-NEXT:    or $2, $2, $3
+; MIPS64-NEXT:    and $7, $2, $1
+; MIPS64-NEXT:    jal v7i18
+; MIPS64-NEXT:    dsrl $4, $11, 44
+; MIPS64-NEXT:    ld $7, 24($16)
+; MIPS64-NEXT:    ld $6, 16($16)
+; MIPS64-NEXT:    ld $5, 8($16)
+; MIPS64-NEXT:    ld $4, 0($16)
+; MIPS64-NEXT:    jal v2i128
+; MIPS64-NEXT:    nop
+; MIPS64-NEXT:    ld $9, 40($16)
+; MIPS64-NEXT:    ld $8, 32($16)
+; MIPS64-NEXT:    ld $7, 24($16)
+; MIPS64-NEXT:    ld $6, 16($16)
+; MIPS64-NEXT:    ld $5, 8($16)
+; MIPS64-NEXT:    ld $4, 0($16)
+; MIPS64-NEXT:    jal v3i128
+; MIPS64-NEXT:    nop
+; MIPS64-NEXT:    ld $16, 0($sp) # 8-byte Folded Reload
+; MIPS64-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
+; MIPS64-NEXT:    jr $ra
+; MIPS64-NEXT:    daddiu $sp, $sp, 16
+;
+; MIPS32-LABEL: test:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    addiu $sp, $sp, -72
+; MIPS32-NEXT:    sw $ra, 68($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    sw $16, 64($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    move $16, $4
+; MIPS32-NEXT:    lw $4, 0($4)
+; MIPS32-NEXT:    jal v1i32
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:    lw $5, 4($16)
+; MIPS32-NEXT:    lw $4, 0($16)
+; MIPS32-NEXT:    jal v2i32
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:    lw $6, 8($16)
+; MIPS32-NEXT:    lw $5, 4($16)
+; MIPS32-NEXT:    lw $4, 0($16)
+; MIPS32-NEXT:    jal v3i32
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:    lw $7, 12($16)
+; MIPS32-NEXT:    lw $6, 8($16)
+; MIPS32-NEXT:    lw $5, 4($16)
+; MIPS32-NEXT:    lw $4, 0($16)
+; MIPS32-NEXT:    jal v4i32
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:    lw $7, 12($16)
+; MIPS32-NEXT:    lw $6, 8($16)
+; MIPS32-NEXT:    lw $5, 4($16)
+; MIPS32-NEXT:    lw $4, 0($16)
+; MIPS32-NEXT:    lw $1, 16($16)
+; MIPS32-NEXT:    jal v5i32
+; MIPS32-NEXT:    sw $1, 16($sp)
+; MIPS32-NEXT:    lw $7, 12($16)
+; MIPS32-NEXT:    lw $6, 8($16)
+; MIPS32-NEXT:    lw $5, 4($16)
+; MIPS32-NEXT:    lw $4, 0($16)
+; MIPS32-NEXT:    lw $1, 16($16)
+; MIPS32-NEXT:    lw $2, 20($16)
+; MIPS32-NEXT:    lw $3, 24($16)
+; MIPS32-NEXT:    lw $8, 28($16)
+; MIPS32-NEXT:    lw $9, 32($16)
+; MIPS32-NEXT:    lw $10, 36($16)
+; MIPS32-NEXT:    lw $11, 40($16)
+; MIPS32-NEXT:    lw $12, 44($16)
+; MIPS32-NEXT:    lw $13, 48($16)
+; MIPS32-NEXT:    lw $14, 52($16)
+; MIPS32-NEXT:    lw $15, 56($16)
+; MIPS32-NEXT:    lw $24, 60($16)
+; MIPS32-NEXT:    sw $24, 60($sp)
+; MIPS32-NEXT:    sw $15, 56($sp)
+; MIPS32-NEXT:    sw $14, 52($sp)
+; MIPS32-NEXT:    sw $13, 48($sp)
+; MIPS32-NEXT:    sw $12, 44($sp)
+; MIPS32-NEXT:    sw $11, 40($sp)
+; MIPS32-NEXT:    sw $10, 36($sp)
+; MIPS32-NEXT:    sw $9, 32($sp)
+; MIPS32-NEXT:    sw $8, 28($sp)
+; MIPS32-NEXT:    sw $3, 24($sp)
+; MIPS32-NEXT:    sw $2, 20($sp)
+; MIPS32-NEXT:    jal v16i32
+; MIPS32-NEXT:    sw $1, 16($sp)
+; MIPS32-NEXT:    lbu $1, 4($16)
+; MIPS32-NEXT:    sll $1, $1, 8
+; MIPS32-NEXT:    lbu $2, 3($16)
+; MIPS32-NEXT:    sll $2, $2, 16
+; MIPS32-NEXT:    or $1, $2, $1
+; MIPS32-NEXT:    lbu $2, 10($16)
+; MIPS32-NEXT:    lbu $3, 5($16)
+; MIPS32-NEXT:    lbu $5, 8($16)
+; MIPS32-NEXT:    lhu $4, 6($16)
+; MIPS32-NEXT:    sll $6, $4, 8
+; MIPS32-NEXT:    lbu $4, 2($16)
+; MIPS32-NEXT:    lhu $7, 0($16)
+; MIPS32-NEXT:    sll $7, $7, 8
+; MIPS32-NEXT:    or $4, $4, $7
+; MIPS32-NEXT:    or $6, $5, $6
+; MIPS32-NEXT:    or $5, $3, $1
+; MIPS32-NEXT:    sll $1, $2, 8
+; MIPS32-NEXT:    lbu $2, 9($16)
+; MIPS32-NEXT:    sll $2, $2, 16
+; MIPS32-NEXT:    or $1, $2, $1
+; MIPS32-NEXT:    lbu $2, 11($16)
+; MIPS32-NEXT:    jal v4i24
+; MIPS32-NEXT:    or $7, $2, $1
+; MIPS32-NEXT:    lbu $1, 14($16)
+; MIPS32-NEXT:    lh $2, 12($16)
+; MIPS32-NEXT:    sll $2, $2, 8
+; MIPS32-NEXT:    or $1, $1, $2
+; MIPS32-NEXT:    lbu $2, 11($16)
+; MIPS32-NEXT:    lb $3, 9($16)
+; MIPS32-NEXT:    lbu $7, 10($16)
+; MIPS32-NEXT:    lbu $5, 5($16)
+; MIPS32-NEXT:    lb $8, 3($16)
+; MIPS32-NEXT:    lbu $9, 4($16)
+; MIPS32-NEXT:    lbu $6, 8($16)
+; MIPS32-NEXT:    lbu $4, 2($16)
+; MIPS32-NEXT:    lhu $10, 0($16)
+; MIPS32-NEXT:    lh $11, 6($16)
+; MIPS32-NEXT:    sll $11, $11, 8
+; MIPS32-NEXT:    sll $10, $10, 8
+; MIPS32-NEXT:    sw $1, 16($sp)
+; MIPS32-NEXT:    or $4, $4, $10
+; MIPS32-NEXT:    or $6, $6, $11
+; MIPS32-NEXT:    sll $1, $9, 8
+; MIPS32-NEXT:    sll $8, $8, 16
+; MIPS32-NEXT:    or $1, $8, $1
+; MIPS32-NEXT:    or $5, $5, $1
+; MIPS32-NEXT:    sll $1, $7, 8
+; MIPS32-NEXT:    sll $3, $3, 16
+; MIPS32-NEXT:    or $1, $3, $1
+; MIPS32-NEXT:    jal v5i24
+; MIPS32-NEXT:    or $7, $2, $1
+; MIPS32-NEXT:    lui $1, 3
+; MIPS32-NEXT:    ori $1, $1, 65535
+; MIPS32-NEXT:    lw $2, 8($16)
+; MIPS32-NEXT:    sll $3, $2, 14
+; MIPS32-NEXT:    lw $4, 12($16)
+; MIPS32-NEXT:    srl $5, $4, 18
+; MIPS32-NEXT:    or $3, $5, $3
+; MIPS32-NEXT:    srl $5, $2, 4
+; MIPS32-NEXT:    and $3, $3, $1
+; MIPS32-NEXT:    and $5, $5, $1
+; MIPS32-NEXT:    and $4, $4, $1
+; MIPS32-NEXT:    lw $7, 4($16)
+; MIPS32-NEXT:    lw $8, 0($16)
+; MIPS32-NEXT:    sll $6, $8, 6
+; MIPS32-NEXT:    srl $9, $7, 26
+; MIPS32-NEXT:    sw $4, 24($sp)
+; MIPS32-NEXT:    sw $5, 16($sp)
+; MIPS32-NEXT:    sw $3, 20($sp)
+; MIPS32-NEXT:    or $3, $9, $6
+; MIPS32-NEXT:    srl $4, $7, 8
+; MIPS32-NEXT:    and $6, $4, $1
+; MIPS32-NEXT:    and $5, $3, $1
+; MIPS32-NEXT:    sll $3, $7, 10
+; MIPS32-NEXT:    srl $2, $2, 22
+; MIPS32-NEXT:    or $2, $2, $3
+; MIPS32-NEXT:    and $7, $2, $1
+; MIPS32-NEXT:    jal v7i18
+; MIPS32-NEXT:    srl $4, $8, 12
+; MIPS32-NEXT:    lw $7, 12($16)
+; MIPS32-NEXT:    lw $6, 8($16)
+; MIPS32-NEXT:    lw $5, 4($16)
+; MIPS32-NEXT:    lw $4, 0($16)
+; MIPS32-NEXT:    lw $1, 16($16)
+; MIPS32-NEXT:    lw $2, 20($16)
+; MIPS32-NEXT:    lw $3, 24($16)
+; MIPS32-NEXT:    lw $8, 28($16)
+; MIPS32-NEXT:    sw $8, 28($sp)
+; MIPS32-NEXT:    sw $3, 24($sp)
+; MIPS32-NEXT:    sw $2, 20($sp)
+; MIPS32-NEXT:    jal v2i128
+; MIPS32-NEXT:    sw $1, 16($sp)
+; MIPS32-NEXT:    lw $7, 12($16)
+; MIPS32-NEXT:    lw $6, 8($16)
+; MIPS32-NEXT:    lw $5, 4($16)
+; MIPS32-NEXT:    lw $4, 0($16)
+; MIPS32-NEXT:    lw $1, 16($16)
+; MIPS32-NEXT:    lw $2, 20($16)
+; MIPS32-NEXT:    lw $3, 24($16)
+; MIPS32-NEXT:    lw $8, 28($16)
+; MIPS32-NEXT:    lw $9, 32($16)
+; MIPS32-NEXT:    lw $10, 36($16)
+; MIPS32-NEXT:    lw $11, 40($16)
+; MIPS32-NEXT:    lw $12, 44($16)
+; MIPS32-NEXT:    sw $12, 44($sp)
+; MIPS32-NEXT:    sw $11, 40($sp)
+; MIPS32-NEXT:    sw $10, 36($sp)
+; MIPS32-NEXT:    sw $9, 32($sp)
+; MIPS32-NEXT:    sw $8, 28($sp)
+; MIPS32-NEXT:    sw $3, 24($sp)
+; MIPS32-NEXT:    sw $2, 20($sp)
+; MIPS32-NEXT:    jal v3i128
+; MIPS32-NEXT:    sw $1, 16($sp)
+; MIPS32-NEXT:    lw $16, 64($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    lw $ra, 68($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    addiu $sp, $sp, 72
+  %v1 = load <1 x i32>, ptr %p
+  call void @v1i32(<1 x i32> %v1)
+  %v2 = load <2 x i32>, ptr %p
+  call void @v2i32(<2 x i32> %v2)
+  %v3 = load <3 x i32>, ptr %p
+  call void @v3i32(<3 x i32> %v3)
+  %v4 = load <4 x i32>, ptr %p
+  call void @v4i32(<4 x i32> %v4)
+  %v5 = load <5 x i32>, ptr %p
+  call void @v5i32(<5 x i32> %v5)
+  %v16i32 = load <16 x i32>, ptr %p
+  call void @v16i32(<16 x i32> %v16i32)
+  %v4i24 = load <4 x i24>, ptr %p
+  call void @v4i24(<4 x i24> %v4i24)
+  %v5i24 = load <5 x i24>, ptr %p
+  call void @v5i24(<5 x i24> %v5i24)
+  %v7i18 = load <7 x i18>, ptr %p
+  call void @v7i18(<7 x i18> %v7i18)
+  %v2i128 = load <2 x i128>, ptr %p
+  call void @v2i128(<2 x i128> %v2i128)
+  %v3i128 = load <3 x i128>, ptr %p
+  call void @v3i128(<3 x i128> %v3i128)
+  ret void
+}
Index: llvm/test/CodeGen/Mips/cconv/vector.ll
===================================================================
--- llvm/test/CodeGen/Mips/cconv/vector.ll
+++ llvm/test/CodeGen/Mips/cconv/vector.ll
@@ -6563,24 +6563,12 @@
 ;
 ; MIPS64-LABEL: i24x2:
 ; MIPS64:       # %bb.0: # %Entry
-; MIPS64-NEXT:    lui $1, 256
-; MIPS64-NEXT:    daddiu $1, $1, -1
-; MIPS64-NEXT:    dsll $1, $1, 24
-; MIPS64-NEXT:    and $2, $5, $1
-; MIPS64-NEXT:    dsrl $2, $2, 24
-; MIPS64-NEXT:    sll $2, $2, 0
-; MIPS64-NEXT:    and $1, $4, $1
-; MIPS64-NEXT:    dsrl $1, $1, 24
-; MIPS64-NEXT:    sll $1, $1, 0
-; MIPS64-NEXT:    addu $1, $1, $2
-; MIPS64-NEXT:    sll $2, $5, 0
-; MIPS64-NEXT:    sll $3, $4, 0
-; MIPS64-NEXT:    dsll $1, $1, 24
-; MIPS64-NEXT:    addu $2, $3, $2
-; MIPS64-NEXT:    lui $3, 255
-; MIPS64-NEXT:    ori $3, $3, 65535
-; MIPS64-NEXT:    and $2, $2, $3
-; MIPS64-NEXT:    or $2, $2, $1
+; MIPS64-NEXT:    sll $1, $6, 0
+; MIPS64-NEXT:    sll $2, $4, 0
+; MIPS64-NEXT:    addu $2, $2, $1
+; MIPS64-NEXT:    sll $1, $7, 0
+; MIPS64-NEXT:    sll $3, $5, 0
+; MIPS64-NEXT:    addu $3, $3, $1
 ; MIPS64-NEXT:    jr $ra
 ; MIPS64-NEXT:    nop
 ;
@@ -6615,56 +6603,14 @@
 ;
 ; MIPS64R5EB-LABEL: i24x2:
 ; MIPS64R5EB:       # %bb.0: # %Entry
-; MIPS64R5EB-NEXT:    daddiu $sp, $sp, -32
-; MIPS64R5EB-NEXT:    .cfi_def_cfa_offset 32
-; MIPS64R5EB-NEXT:    sh $5, 20($sp)
-; MIPS64R5EB-NEXT:    dsrl $1, $5, 16
-; MIPS64R5EB-NEXT:    sw $1, 16($sp)
-; MIPS64R5EB-NEXT:    sh $4, 28($sp)
-; MIPS64R5EB-NEXT:    dsrl $1, $4, 16
-; MIPS64R5EB-NEXT:    sw $1, 24($sp)
-; MIPS64R5EB-NEXT:    lbu $1, 20($sp)
-; MIPS64R5EB-NEXT:    dsll $1, $1, 8
-; MIPS64R5EB-NEXT:    lb $2, 19($sp)
-; MIPS64R5EB-NEXT:    dsll $2, $2, 16
-; MIPS64R5EB-NEXT:    or $1, $2, $1
-; MIPS64R5EB-NEXT:    lbu $2, 28($sp)
-; MIPS64R5EB-NEXT:    dsll $2, $2, 8
-; MIPS64R5EB-NEXT:    lb $3, 27($sp)
-; MIPS64R5EB-NEXT:    dsll $3, $3, 16
-; MIPS64R5EB-NEXT:    lbu $4, 21($sp)
-; MIPS64R5EB-NEXT:    or $2, $3, $2
-; MIPS64R5EB-NEXT:    or $1, $4, $1
-; MIPS64R5EB-NEXT:    lh $3, 16($sp)
-; MIPS64R5EB-NEXT:    dsll $3, $3, 8
-; MIPS64R5EB-NEXT:    lbu $4, 18($sp)
-; MIPS64R5EB-NEXT:    or $3, $4, $3
-; MIPS64R5EB-NEXT:    lbu $4, 29($sp)
-; MIPS64R5EB-NEXT:    insert.d $w0[0], $3
-; MIPS64R5EB-NEXT:    insert.d $w0[1], $1
-; MIPS64R5EB-NEXT:    or $1, $4, $2
-; MIPS64R5EB-NEXT:    lh $2, 24($sp)
-; MIPS64R5EB-NEXT:    dsll $2, $2, 8
-; MIPS64R5EB-NEXT:    lbu $3, 26($sp)
-; MIPS64R5EB-NEXT:    or $2, $3, $2
-; MIPS64R5EB-NEXT:    insert.d $w1[0], $2
-; MIPS64R5EB-NEXT:    insert.d $w1[1], $1
+; MIPS64R5EB-NEXT:    insert.d $w0[0], $6
+; MIPS64R5EB-NEXT:    insert.d $w0[1], $7
+; MIPS64R5EB-NEXT:    insert.d $w1[0], $4
+; MIPS64R5EB-NEXT:    insert.d $w1[1], $5
 ; MIPS64R5EB-NEXT:    addv.d $w0, $w1, $w0
-; MIPS64R5EB-NEXT:    copy_s.d $1, $w0[1]
-; MIPS64R5EB-NEXT:    copy_s.d $2, $w0[0]
-; MIPS64R5EB-NEXT:    sb $2, 10($sp)
-; MIPS64R5EB-NEXT:    dsrl $3, $1, 16
-; MIPS64R5EB-NEXT:    sb $3, 11($sp)
-; MIPS64R5EB-NEXT:    dsrl $2, $2, 8
-; MIPS64R5EB-NEXT:    sh $2, 8($sp)
-; MIPS64R5EB-NEXT:    sb $1, 13($sp)
-; MIPS64R5EB-NEXT:    dsrl $1, $1, 8
-; MIPS64R5EB-NEXT:    sb $1, 12($sp)
-; MIPS64R5EB-NEXT:    lw $1, 8($sp)
-; MIPS64R5EB-NEXT:    dsll $1, $1, 16
-; MIPS64R5EB-NEXT:    lhu $2, 12($sp)
-; MIPS64R5EB-NEXT:    or $2, $2, $1
-; MIPS64R5EB-NEXT:    daddiu $sp, $sp, 32
+; MIPS64R5EB-NEXT:    shf.w $w0, $w0, 177
+; MIPS64R5EB-NEXT:    copy_s.w $2, $w0[1]
+; MIPS64R5EB-NEXT:    copy_s.w $3, $w0[3]
 ; MIPS64R5EB-NEXT:    jr $ra
 ; MIPS64R5EB-NEXT:    nop
 ;
@@ -6698,56 +6644,13 @@
 ;
 ; MIPS64R5EL-LABEL: i24x2:
 ; MIPS64R5EL:       # %bb.0: # %Entry
-; MIPS64R5EL-NEXT:    daddiu $sp, $sp, -32
-; MIPS64R5EL-NEXT:    .cfi_def_cfa_offset 32
-; MIPS64R5EL-NEXT:    dsrl $1, $5, 32
-; MIPS64R5EL-NEXT:    sh $1, 20($sp)
-; MIPS64R5EL-NEXT:    sw $5, 16($sp)
-; MIPS64R5EL-NEXT:    dsrl $1, $4, 32
-; MIPS64R5EL-NEXT:    sh $1, 28($sp)
-; MIPS64R5EL-NEXT:    lbu $1, 20($sp)
-; MIPS64R5EL-NEXT:    sw $4, 24($sp)
-; MIPS64R5EL-NEXT:    dsll $1, $1, 8
-; MIPS64R5EL-NEXT:    lbu $2, 19($sp)
-; MIPS64R5EL-NEXT:    or $1, $1, $2
-; MIPS64R5EL-NEXT:    lb $2, 21($sp)
-; MIPS64R5EL-NEXT:    dsll $2, $2, 16
-; MIPS64R5EL-NEXT:    lbu $3, 28($sp)
-; MIPS64R5EL-NEXT:    dsll $3, $3, 8
-; MIPS64R5EL-NEXT:    lb $4, 18($sp)
-; MIPS64R5EL-NEXT:    lbu $5, 27($sp)
-; MIPS64R5EL-NEXT:    or $3, $3, $5
-; MIPS64R5EL-NEXT:    or $1, $1, $2
-; MIPS64R5EL-NEXT:    dsll $2, $4, 16
-; MIPS64R5EL-NEXT:    lhu $4, 16($sp)
-; MIPS64R5EL-NEXT:    or $2, $4, $2
-; MIPS64R5EL-NEXT:    lb $4, 29($sp)
-; MIPS64R5EL-NEXT:    dsll $4, $4, 16
-; MIPS64R5EL-NEXT:    insert.d $w0[0], $2
-; MIPS64R5EL-NEXT:    insert.d $w0[1], $1
-; MIPS64R5EL-NEXT:    or $1, $3, $4
-; MIPS64R5EL-NEXT:    lb $2, 26($sp)
-; MIPS64R5EL-NEXT:    dsll $2, $2, 16
-; MIPS64R5EL-NEXT:    lhu $3, 24($sp)
-; MIPS64R5EL-NEXT:    or $2, $3, $2
-; MIPS64R5EL-NEXT:    insert.d $w1[0], $2
-; MIPS64R5EL-NEXT:    insert.d $w1[1], $1
+; MIPS64R5EL-NEXT:    insert.d $w0[0], $6
+; MIPS64R5EL-NEXT:    insert.d $w0[1], $7
+; MIPS64R5EL-NEXT:    insert.d $w1[0], $4
+; MIPS64R5EL-NEXT:    insert.d $w1[1], $5
 ; MIPS64R5EL-NEXT:    addv.d $w0, $w1, $w0
-; MIPS64R5EL-NEXT:    copy_s.d $1, $w0[0]
-; MIPS64R5EL-NEXT:    copy_s.d $2, $w0[1]
-; MIPS64R5EL-NEXT:    dsrl $3, $2, 8
-; MIPS64R5EL-NEXT:    sb $3, 12($sp)
-; MIPS64R5EL-NEXT:    dsrl $3, $2, 16
-; MIPS64R5EL-NEXT:    sb $3, 13($sp)
-; MIPS64R5EL-NEXT:    sb $2, 11($sp)
-; MIPS64R5EL-NEXT:    sh $1, 8($sp)
-; MIPS64R5EL-NEXT:    dsrl $1, $1, 16
-; MIPS64R5EL-NEXT:    sb $1, 10($sp)
-; MIPS64R5EL-NEXT:    lh $1, 12($sp)
-; MIPS64R5EL-NEXT:    dsll $1, $1, 32
-; MIPS64R5EL-NEXT:    lwu $2, 8($sp)
-; MIPS64R5EL-NEXT:    or $2, $2, $1
-; MIPS64R5EL-NEXT:    daddiu $sp, $sp, 32
+; MIPS64R5EL-NEXT:    copy_s.w $2, $w0[0]
+; MIPS64R5EL-NEXT:    copy_s.w $3, $w0[2]
 ; MIPS64R5EL-NEXT:    jr $ra
 ; MIPS64R5EL-NEXT:    nop
 Entry:
@@ -6794,17 +6697,22 @@
 ; MIPS64EB-NEXT:    lui $1, %hi(%neg(%gp_rel(call_i24x2)))
 ; MIPS64EB-NEXT:    daddu $1, $1, $25
 ; MIPS64EB-NEXT:    daddiu $gp, $1, %lo(%neg(%gp_rel(call_i24x2)))
-; MIPS64EB-NEXT:    lui $1, 1536
-; MIPS64EB-NEXT:    ori $4, $1, 7
-; MIPS64EB-NEXT:    lui $1, 3072
-; MIPS64EB-NEXT:    ori $5, $1, 8
 ; MIPS64EB-NEXT:    ld $25, %call16(i24x2)($gp)
+; MIPS64EB-NEXT:    daddiu $4, $zero, 6
+; MIPS64EB-NEXT:    daddiu $5, $zero, 7
+; MIPS64EB-NEXT:    daddiu $6, $zero, 12
+; MIPS64EB-NEXT:    daddiu $7, $zero, 8
 ; MIPS64EB-NEXT:    jalr $25
 ; MIPS64EB-NEXT:    nop
 ; MIPS64EB-NEXT:    ld $1, %got_disp(gv2i24)($gp)
-; MIPS64EB-NEXT:    sh $2, 4($1)
-; MIPS64EB-NEXT:    dsrl $2, $2, 16
-; MIPS64EB-NEXT:    sw $2, 0($1)
+; MIPS64EB-NEXT:    sb $3, 5($1)
+; MIPS64EB-NEXT:    sb $2, 2($1)
+; MIPS64EB-NEXT:    srl $4, $3, 8
+; MIPS64EB-NEXT:    sb $4, 4($1)
+; MIPS64EB-NEXT:    srl $3, $3, 16
+; MIPS64EB-NEXT:    sb $3, 3($1)
+; MIPS64EB-NEXT:    srl $2, $2, 8
+; MIPS64EB-NEXT:    sh $2, 0($1)
 ; MIPS64EB-NEXT:    ld $gp, 0($sp) # 8-byte Folded Reload
 ; MIPS64EB-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
 ; MIPS64EB-NEXT:    daddiu $sp, $sp, 16
@@ -6849,31 +6757,27 @@
 ; MIPS64R5EB-NEXT:    lui $1, %hi(%neg(%gp_rel(call_i24x2)))
 ; MIPS64R5EB-NEXT:    daddu $1, $1, $25
 ; MIPS64R5EB-NEXT:    daddiu $gp, $1, %lo(%neg(%gp_rel(call_i24x2)))
-; MIPS64R5EB-NEXT:    lui $1, 1536
-; MIPS64R5EB-NEXT:    ori $1, $1, 7
-; MIPS64R5EB-NEXT:    swl $1, 2($sp)
-; MIPS64R5EB-NEXT:    lui $2, 3072
-; MIPS64R5EB-NEXT:    ori $2, $2, 8
-; MIPS64R5EB-NEXT:    swl $2, 10($sp)
-; MIPS64R5EB-NEXT:    sh $zero, 0($sp)
-; MIPS64R5EB-NEXT:    swr $1, 5($sp)
-; MIPS64R5EB-NEXT:    sh $zero, 8($sp)
-; MIPS64R5EB-NEXT:    swr $2, 13($sp)
-; MIPS64R5EB-NEXT:    lw $1, 0($sp)
-; MIPS64R5EB-NEXT:    dsll $1, $1, 16
-; MIPS64R5EB-NEXT:    lhu $2, 4($sp)
-; MIPS64R5EB-NEXT:    or $4, $2, $1
-; MIPS64R5EB-NEXT:    lw $1, 8($sp)
-; MIPS64R5EB-NEXT:    dsll $1, $1, 16
-; MIPS64R5EB-NEXT:    lhu $2, 12($sp)
-; MIPS64R5EB-NEXT:    or $5, $2, $1
 ; MIPS64R5EB-NEXT:    ld $25, %call16(i24x2)($gp)
+; MIPS64R5EB-NEXT:    daddiu $4, $zero, 6
+; MIPS64R5EB-NEXT:    daddiu $5, $zero, 7
+; MIPS64R5EB-NEXT:    daddiu $6, $zero, 12
+; MIPS64R5EB-NEXT:    daddiu $7, $zero, 8
 ; MIPS64R5EB-NEXT:    jalr $25
 ; MIPS64R5EB-NEXT:    nop
-; MIPS64R5EB-NEXT:    ld $1, %got_disp(gv2i24)($gp)
-; MIPS64R5EB-NEXT:    sh $2, 4($1)
+; MIPS64R5EB-NEXT:    sw $3, 12($sp)
+; MIPS64R5EB-NEXT:    sw $2, 4($sp)
+; MIPS64R5EB-NEXT:    ld.d $w0, 0($sp)
+; MIPS64R5EB-NEXT:    copy_s.d $1, $w0[0]
+; MIPS64R5EB-NEXT:    copy_s.d $2, $w0[1]
+; MIPS64R5EB-NEXT:    ld $3, %got_disp(gv2i24)($gp)
+; MIPS64R5EB-NEXT:    sb $2, 5($3)
+; MIPS64R5EB-NEXT:    sb $1, 2($3)
+; MIPS64R5EB-NEXT:    dsrl $4, $2, 8
+; MIPS64R5EB-NEXT:    sb $4, 4($3)
 ; MIPS64R5EB-NEXT:    dsrl $2, $2, 16
-; MIPS64R5EB-NEXT:    sw $2, 0($1)
+; MIPS64R5EB-NEXT:    sb $2, 3($3)
+; MIPS64R5EB-NEXT:    dsrl $1, $1, 8
+; MIPS64R5EB-NEXT:    sh $1, 0($3)
 ; MIPS64R5EB-NEXT:    ld $gp, 16($sp) # 8-byte Folded Reload
 ; MIPS64R5EB-NEXT:    ld $ra, 24($sp) # 8-byte Folded Reload
 ; MIPS64R5EB-NEXT:    daddiu $sp, $sp, 32
@@ -6918,17 +6822,22 @@
 ; MIPS64EL-NEXT:    lui $1, %hi(%neg(%gp_rel(call_i24x2)))
 ; MIPS64EL-NEXT:    daddu $1, $1, $25
 ; MIPS64EL-NEXT:    daddiu $gp, $1, %lo(%neg(%gp_rel(call_i24x2)))
-; MIPS64EL-NEXT:    lui $1, 1792
-; MIPS64EL-NEXT:    ori $4, $1, 6
-; MIPS64EL-NEXT:    lui $1, 2048
-; MIPS64EL-NEXT:    ori $5, $1, 12
 ; MIPS64EL-NEXT:    ld $25, %call16(i24x2)($gp)
+; MIPS64EL-NEXT:    daddiu $4, $zero, 6
+; MIPS64EL-NEXT:    daddiu $5, $zero, 7
+; MIPS64EL-NEXT:    daddiu $6, $zero, 12
+; MIPS64EL-NEXT:    daddiu $7, $zero, 8
 ; MIPS64EL-NEXT:    jalr $25
 ; MIPS64EL-NEXT:    nop
 ; MIPS64EL-NEXT:    ld $1, %got_disp(gv2i24)($gp)
-; MIPS64EL-NEXT:    sw $2, 0($1)
-; MIPS64EL-NEXT:    dsrl $2, $2, 32
-; MIPS64EL-NEXT:    sh $2, 4($1)
+; MIPS64EL-NEXT:    sb $3, 3($1)
+; MIPS64EL-NEXT:    sh $2, 0($1)
+; MIPS64EL-NEXT:    srl $4, $3, 8
+; MIPS64EL-NEXT:    sb $4, 4($1)
+; MIPS64EL-NEXT:    srl $3, $3, 16
+; MIPS64EL-NEXT:    sb $3, 5($1)
+; MIPS64EL-NEXT:    srl $2, $2, 16
+; MIPS64EL-NEXT:    sb $2, 2($1)
 ; MIPS64EL-NEXT:    ld $gp, 0($sp) # 8-byte Folded Reload
 ; MIPS64EL-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
 ; MIPS64EL-NEXT:    daddiu $sp, $sp, 16
@@ -6973,31 +6882,27 @@
 ; MIPS64R5EL-NEXT:    lui $1, %hi(%neg(%gp_rel(call_i24x2)))
 ; MIPS64R5EL-NEXT:    daddu $1, $1, $25
 ; MIPS64R5EL-NEXT:    daddiu $gp, $1, %lo(%neg(%gp_rel(call_i24x2)))
-; MIPS64R5EL-NEXT:    addiu $1, $zero, 1792
-; MIPS64R5EL-NEXT:    swl $1, 5($sp)
-; MIPS64R5EL-NEXT:    addiu $2, $zero, 2048
-; MIPS64R5EL-NEXT:    swl $2, 13($sp)
-; MIPS64R5EL-NEXT:    swr $1, 2($sp)
-; MIPS64R5EL-NEXT:    daddiu $1, $zero, 6
-; MIPS64R5EL-NEXT:    sh $1, 0($sp)
-; MIPS64R5EL-NEXT:    swr $2, 10($sp)
-; MIPS64R5EL-NEXT:    daddiu $1, $zero, 12
-; MIPS64R5EL-NEXT:    sh $1, 8($sp)
-; MIPS64R5EL-NEXT:    lh $1, 4($sp)
-; MIPS64R5EL-NEXT:    dsll $1, $1, 32
-; MIPS64R5EL-NEXT:    lwu $2, 0($sp)
-; MIPS64R5EL-NEXT:    or $4, $2, $1
-; MIPS64R5EL-NEXT:    lh $1, 12($sp)
-; MIPS64R5EL-NEXT:    dsll $1, $1, 32
-; MIPS64R5EL-NEXT:    lwu $2, 8($sp)
-; MIPS64R5EL-NEXT:    or $5, $2, $1
 ; MIPS64R5EL-NEXT:    ld $25, %call16(i24x2)($gp)
+; MIPS64R5EL-NEXT:    daddiu $4, $zero, 6
+; MIPS64R5EL-NEXT:    daddiu $5, $zero, 7
+; MIPS64R5EL-NEXT:    daddiu $6, $zero, 12
+; MIPS64R5EL-NEXT:    daddiu $7, $zero, 8
 ; MIPS64R5EL-NEXT:    jalr $25
 ; MIPS64R5EL-NEXT:    nop
-; MIPS64R5EL-NEXT:    ld $1, %got_disp(gv2i24)($gp)
-; MIPS64R5EL-NEXT:    sw $2, 0($1)
-; MIPS64R5EL-NEXT:    dsrl $2, $2, 32
-; MIPS64R5EL-NEXT:    sh $2, 4($1)
+; MIPS64R5EL-NEXT:    sw $3, 8($sp)
+; MIPS64R5EL-NEXT:    sw $2, 0($sp)
+; MIPS64R5EL-NEXT:    ld.d $w0, 0($sp)
+; MIPS64R5EL-NEXT:    copy_s.d $1, $w0[0]
+; MIPS64R5EL-NEXT:    copy_s.d $2, $w0[1]
+; MIPS64R5EL-NEXT:    ld $3, %got_disp(gv2i24)($gp)
+; MIPS64R5EL-NEXT:    sb $2, 3($3)
+; MIPS64R5EL-NEXT:    sh $1, 0($3)
+; MIPS64R5EL-NEXT:    dsrl $4, $2, 8
+; MIPS64R5EL-NEXT:    sb $4, 4($3)
+; MIPS64R5EL-NEXT:    dsrl $2, $2, 16
+; MIPS64R5EL-NEXT:    sb $2, 5($3)
+; MIPS64R5EL-NEXT:    dsrl $1, $1, 16
+; MIPS64R5EL-NEXT:    sb $1, 2($3)
 ; MIPS64R5EL-NEXT:    ld $gp, 16($sp) # 8-byte Folded Reload
 ; MIPS64R5EL-NEXT:    ld $ra, 24($sp) # 8-byte Folded Reload
 ; MIPS64R5EL-NEXT:    daddiu $sp, $sp, 32