diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h @@ -47,9 +47,6 @@ const MCSubtargetInfo &STI, raw_ostream &O); void printNamedBit(const MCInst *MI, unsigned OpNo, raw_ostream &O, StringRef BitName); - void printOffen(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printIdxen(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printAddr64(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, @@ -67,32 +64,14 @@ const MCSubtargetInfo &STI, raw_ostream &O); void printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printGDS(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); void printCPol(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printTFE(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); void printDMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printDim(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printUNorm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printDA(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); void printR128A16(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printA16(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printLWE(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printD16(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printExpCompr(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printExpVM(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); void printFORMAT(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printSymbolicFormat(const MCInst *MI, @@ -202,12 +181,8 @@ protected: void printAbs(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printHigh(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); void printClamp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printClampSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); void printOModSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printLiteral(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -100,21 +100,6 @@ } } -void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - printNamedBit(MI, OpNo, O, "offen"); -} - -void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - printNamedBit(MI, OpNo, O, "idxen"); -} - -void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - printNamedBit(MI, OpNo, O, "addr64"); -} - void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { @@ -186,11 +171,6 @@ printU32ImmOperand(MI, OpNo, STI, O); } -void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - printNamedBit(MI, OpNo, O, "gds"); -} - void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { auto Imm = MI->getOperand(OpNo).getImm(); @@ -208,11 +188,6 @@ O << " /* unexpected cache policy bit */"; } -void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - printNamedBit(MI, OpNo, O, "tfe"); -} - void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { if (MI->getOperand(OpNo).getImm()) { @@ -233,16 +208,6 @@ O << Dim; } -void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - printNamedBit(MI, OpNo, O, "unorm"); -} - -void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - printNamedBit(MI, OpNo, O, "da"); -} - void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { if (STI.hasFeature(AMDGPU::FeatureR128A16)) @@ -251,33 +216,6 @@ printNamedBit(MI, OpNo, O, "r128"); } -void AMDGPUInstPrinter::printA16(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - printNamedBit(MI, OpNo, O, "a16"); -} - -void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - printNamedBit(MI, OpNo, O, "lwe"); -} - -void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - printNamedBit(MI, OpNo, O, "d16"); -} - -void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printNamedBit(MI, OpNo, O, "compr"); -} - -void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printNamedBit(MI, OpNo, O, "vm"); -} - void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { @@ -1324,18 +1262,6 @@ O << Asm; } -void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printNamedBit(MI, OpNo, O, "high"); -} - -void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printNamedBit(MI, OpNo, O, "clamp"); -} - void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1047,12 +1047,16 @@ let ParserMethod = "[this](OperandVector &Operands) -> ParseStatus { "# "return parseNamedBit(\""#Id#"\", Operands, AMDGPUOperand::"#ImmTy#"); }"; + let PrintMethod = "[this](const MCInst *MI, unsigned OpNo, "# + "const MCSubtargetInfo &STI, raw_ostream &O) { "# + "printNamedBit(MI, OpNo, O, \""#Id#"\"); }"; } class DefaultOperand : OperandWithDefaultOps, CustomOperandProps<1, Op.ParserMatchClass.Name> { let ParserMethod = Op.ParserMatchClass.ParserMethod; + let PrintMethod = Op.PrintMethod; } class SDWAOperand