diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -277,5 +277,8 @@ ``XCVsimd`` LLVM implements `version 1.0.0 of the CORE-V SIMD custom instructions specification `_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. +``XCVbi`` + LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification `_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. + ``XSfcie`` LLVM implements `version 1.0.0 of the SiFive Custom Instruction Extension (CIE) Software Specification `_ by SiFive. All custom instruction are added as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for S76 processor at this time. diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -67,6 +67,7 @@ // vendor-defined ('X') extensions {"xcvalu", RISCVExtensionVersion{1, 0}}, + {"xcvbi", RISCVExtensionVersion{1, 0}}, {"xcvbitmanip", RISCVExtensionVersion{1, 0}}, {"xcvmac", RISCVExtensionVersion{1, 0}}, {"xcvsimd", RISCVExtensionVersion{1, 0}}, diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -569,6 +569,8 @@ "CORE-V ALU custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableCoreVSIMD32, "CORE-V SIMD extensions custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32, + "CORE-V Immediate Branching custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -816,6 +816,13 @@ AssemblerPredicate<(any_of FeatureVendorXCVsimd), "'XCVsimd' (CORE-V SIMD ALU)">; +def FeatureVendorXCVbi + : SubtargetFeature<"xcvbi", "HasVendorXCVbi", "true", + "'XCVbi' (CORE-V Immediate Branching)">; +def HasVendorXCVbi : Predicate<"Subtarget->hasVendorXCVbi()">, + AssemblerPredicate<(all_of FeatureVendorXCVbi), + "'XCVbi' (CORE-V Immediate Branching)">; + //===----------------------------------------------------------------------===// // LLVM specific features and extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td @@ -519,3 +519,22 @@ def CV_SUB_DIV4 : CVSIMDRR<0b01110, 1, 0, 0b100, "cv.sub.div4">; def CV_SUB_DIV8 : CVSIMDRR<0b01110, 1, 0, 0b110, "cv.sub.div8">; } + +class CVInstImmBranch funct3, dag outs, dag ins, + string opcodestr, string argstr> + : RVInstB { + bits<5> imm5; + let rs2 = imm5; + let DecoderNamespace = "XCVbi"; +} + +let Predicates = [HasVendorXCVbi, IsRV32], hasSideEffects = 0, mayLoad = 0, + mayStore = 0, isBranch = 1, isTerminator = 1 in { + // Immediate branching operations + def CV_BEQIMM : CVInstImmBranch<0b110, (outs), + (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12), + "cv.beqimm", "$rs1, $imm5, $imm12">, Sched<[]>; + def CV_BNEIMM : CVInstImmBranch<0b111, (outs), + (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12), + "cv.bneimm", "$rs1, $imm5, $imm12">, Sched<[]>; +} diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -44,7 +44,11 @@ ; RUN: llc -mtriple=riscv32 -mattr=+xcvalu %s -o - | FileCheck --check-prefix=RV32XCVALU %s ; RUN: llc -mtriple=riscv32 -mattr=+xcvbitmanip %s -o - | FileCheck --check-prefix=RV32XCVBITMANIP %s ; RUN: llc -mtriple=riscv32 -mattr=+xcvmac %s -o - | FileCheck --check-prefix=RV32XCVMAC %s +<<<<<<< HEAD ; RUN: llc -mtriple=riscv32 -mattr=+xcvsimd %s -o - | FileCheck --check-prefix=RV32XCVSIMD %s +======= +; RUN: llc -mtriple=riscv32 -mattr=+xcvbi %s -o - | FileCheck --check-prefix=RV32XCVBI %s +>>>>>>> 0d564dd452ae ([RISCV] Add support for XCVbi extension in CV32E40P) ; RUN: llc -mtriple=riscv32 -mattr=+xtheadcmo %s -o - | FileCheck --check-prefix=RV32XTHEADCMO %s ; RUN: llc -mtriple=riscv32 -mattr=+xtheadcondmov %s -o - | FileCheck --check-prefix=RV32XTHEADCONDMOV %s ; RUN: llc -mtriple=riscv32 -mattr=+xtheadfmemidx %s -o - | FileCheck --check-prefix=RV32XTHEADFMEMIDX %s @@ -220,6 +224,7 @@ ; RV32XCVBITMANIP: .attribute 5, "rv32i2p1_xcvbitmanip1p0" ; RV32XCVMAC: .attribute 5, "rv32i2p1_xcvmac1p0" ; RV32XCVSIMD: .attribute 5, "rv32i2p1_xcvsimd1p0" +; RV32XCVBI: .attribute 5, "rv32i2p1_xcvbi1p0" ; RV32XTHEADCMO: .attribute 5, "rv32i2p1_xtheadcmo1p0" ; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p1_xtheadcondmov1p0" ; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -296,3 +296,6 @@ .attribute arch, "rv32i_xcvsimd" # CHECK: attribute 5, "rv32i2p1_xcvsimd1p0" + +.attribute arch, "rv32i_xcvbi" +# CHECK: attribute 5, "rv32i2p1_xcvbi1p0" diff --git a/llvm/test/MC/RISCV/corev/XCVbi-invalid.s b/llvm/test/MC/RISCV/corev/XCVbi-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/corev/XCVbi-invalid.s @@ -0,0 +1,58 @@ +# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvbi %s 2>&1 \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR + +//===----------------------------------------------------------------------===// +// cv.beqimm +//===----------------------------------------------------------------------===// + +cv.beqimm 0, 0, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.beqimm t0, t1, 0 +# CHECK-ERROR: immediate must be an integer in the range [-16, 15] + +cv.beqimm t0, 0, t1 +# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094] + +cv.beqimm t0, 16, 0 +# CHECK-ERROR: immediate must be an integer in the range [-16, 15] + +cv.beqimm t0, -17, 0 +# CHECK-ERROR: immediate must be an integer in the range [-16, 15] + +cv.beqimm t0, 0, 1 +# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094] + +cv.beqimm t0, 0, 4096 +# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094] + +cv.beqimm t0, 0, -4098 +# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094] + +//===----------------------------------------------------------------------===// +// cv.bneimm +//===----------------------------------------------------------------------===// + +cv.bneimm 0, 0, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.bneimm t0, t1, 0 +# CHECK-ERROR: immediate must be an integer in the range [-16, 15] + +cv.bneimm t0, 0, t1 +# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094] + +cv.bneimm t0, 16, 0 +# CHECK-ERROR: immediate must be an integer in the range [-16, 15] + +cv.bneimm t0, -17, 0 +# CHECK-ERROR: immediate must be an integer in the range [-16, 15] + +cv.bneimm t0, 0, 1 +# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094] + +cv.bneimm t0, 0, 4096 +# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094] + +cv.bneimm t0, 0, -4098 +# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094] \ No newline at end of file diff --git a/llvm/test/MC/RISCV/corev/XCVbi.s b/llvm/test/MC/RISCV/corev/XCVbi.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/corev/XCVbi.s @@ -0,0 +1,57 @@ +# RUN: llvm-mc -triple=riscv32 --mattr=+xcvbi -show-encoding %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvbi < %s \ +# RUN: | llvm-objdump --mattr=+xcvbi -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-OBJDUMP %s +# RUN: not llvm-mc -triple riscv32 %s 2>&1 \ +# RUN: | FileCheck -check-prefix=CHECK-NO-EXT %s + +//===----------------------------------------------------------------------===// +// cv.beqimm +//===----------------------------------------------------------------------===// + +label1: + +cv.beqimm t0, 0, 0 +# CHECK-INSTR: cv.beqimm t0, 0, 0 +# CHECK-OBJDUMP: cv.beqimm t0, 0, 0x0 +# CHECK-ENCODING: [0x0b,0xe0,0x02,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}} + +cv.beqimm a0, 5, 42 +# CHECK-INSTR: cv.beqimm a0, 5, 42 +# CHECK-OBJDUMP: cv.beqimm a0, 5, 0x2e +# CHECK-ENCODING: [0x0b,0x65,0x55,0x02] +# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}} + +cv.beqimm a0, -5, label1 +# CHECK-INSTR: cv.beqimm a0, -5, label1 +# CHECK-OBJDUMP: cv.beqimm a0, -5, 0x0 +# CHECK-ENCODING: [0x0b'A',0x60'A',0xb5'A',0x01'A'] +# CHECK-ENCODING: fixup A - offset: 0, value: label1, kind: fixup_riscv_branch +# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}} + +//===----------------------------------------------------------------------===// +// cv.bneimm +//===----------------------------------------------------------------------===// + +label2: + +cv.bneimm t0, 0, 0 +# CHECK-INSTR: cv.bneimm t0, 0, 0 +# CHECK-OBJDUMP: cv.bneimm t0, 0, 0xc +# CHECK-ENCODING: [0x0b,0xf0,0x02,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}} + +cv.bneimm a0, 5, 42 +# CHECK-INSTR: cv.bneimm a0, 5, 42 +# CHECK-OBJDUMP: cv.bneimm a0, 5, 0x3a +# CHECK-ENCODING: [0x0b,0x75,0x55,0x02] +# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}} + +cv.bneimm a0, -5, label2 +# CHECK-INSTR: cv.bneimm a0, -5, label2 +# CHECK-OBJDUMP: cv.bneimm a0, -5, 0xc +# CHECK-ENCODING: [0x0b'A',0x70'A',0xb5'A',0x01'A'] +# CHECK-ENCODING: fixup A - offset: 0, value: label2, kind: fixup_riscv_branch +# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}}