diff --git a/llvm/lib/Target/PowerPC/PPCInstrDFP.td b/llvm/lib/Target/PowerPC/PPCInstrDFP.td --- a/llvm/lib/Target/PowerPC/PPCInstrDFP.td +++ b/llvm/lib/Target/PowerPC/PPCInstrDFP.td @@ -56,6 +56,31 @@ def DCMPOQ : XForm_17<63, 130, (outs crrc:$BF), (ins fpairrc:$RA, fpairrc:$RB), "dcmpoq $BF, $RA, $RB", IIC_FPCompare>; } -} -} +// 5.6.5 DFP Conversion Instructions +defm DCTDP: XForm_26r<59, 258, (outs f8rc:$RST), (ins f8rc:$RB), + "dctdp", "$RST, $RB", IIC_FPGeneral, []>; +defm DCTQPQ: XForm_26r<63, 258, (outs fpairrc:$RST), (ins f8rc:$RB), + "dctqpq", "$RST, $RB", IIC_FPGeneral, []>; +defm DRSP: XForm_26r<59, 770, (outs f8rc:$RST), (ins f8rc:$RB), + "drsp", "$RST, $RB", IIC_FPGeneral, []>; +defm DRDPQ: XForm_26r<63, 770, (outs fpairrc:$RST), (ins fpairrc:$RB), + "drdpq", "$RST, $RB", IIC_FPGeneral, []>; +defm DCFFIX: XForm_26r<59, 802, (outs f8rc:$RST), (ins f8rc:$RB), + "dcffix", "$RST, $RB", IIC_FPGeneral, []>; +defm DCFFIXQ: XForm_26r<63, 802, (outs fpairrc:$RST), (ins f8rc:$RB), + "dcffixq", "$RST, $RB", IIC_FPGeneral, []>; +defm DCTFIX: XForm_26r<59, 290, (outs f8rc:$RST), (ins f8rc:$RB), + "dctfix", "$RST, $RB", IIC_FPGeneral, []>; +defm DCTFIXQ: XForm_26r<63, 290, (outs f8rc:$RST), (ins fpairrc:$RB), + "dctfixq", "$RST, $RB", IIC_FPGeneral, []>; +let Predicates = [HasP10Vector] in { + def DCFFIXQQ: XForm_26<63, 994, (outs fpairrc:$RST), (ins vrrc:$RB), + "dcffixqq $RST, $RB", IIC_FPGeneral, []>; +let RA = 1 in + def DCTFIXQQ: XForm_base_r3xo<63, 994, (outs vrrc:$RST), (ins fpairrc:$RB), + "dctfixqq $RST, $RB", IIC_FPGeneral, []>; +} // HasP10Vector + +} // mayRaiseFPException +} // hasNoSchedulingInfo diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -129,6 +129,7 @@ def HasP9Vector : Predicate<"Subtarget->hasP9Vector()">; def NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">; def NoP10Vector: Predicate<"!Subtarget->hasP10Vector()">; +def HasP10Vector: Predicate<"Subtarget->hasP10Vector()">; def PPCldsplatAlign16 : PatFrag<(ops node:$ptr), (PPCldsplat node:$ptr), [{ return cast(N)->getAlign() >= Align(16) && diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt --- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt @@ -59,3 +59,57 @@ # CHECK: dcmpoq 2, 6, 4 0xfd 0x06 0x21 0x04 + +# CHECK: dctdp 8, 2 +0xed 0x00 0x12 0x04 + +# CHECK: dctdp. 8, 2 +0xed 0x00 0x12 0x05 + +# CHECK: dctqpq 8, 2 +0xfd 0x00 0x12 0x04 + +# CHECK: dctqpq. 8, 2 +0xfd 0x00 0x12 0x05 + +# CHECK: drsp 20, 8 +0xee 0x80 0x46 0x04 + +# CHECK: drsp. 20, 8 +0xee 0x80 0x46 0x05 + +# CHECK: drdpq 20, 8 +0xfe 0x80 0x46 0x04 + +# CHECK: drdpq. 20, 8 +0xfe 0x80 0x46 0x05 + +# CHECK: dcffix 12, 7 +0xed 0x80 0x3e 0x44 + +# CHECK: dcffix. 12, 7 +0xed 0x80 0x3e 0x45 + +# CHECK: dcffixq 12, 8 +0xfd 0x80 0x46 0x44 + +# CHECK: dcffixq. 12, 8 +0xfd 0x80 0x46 0x45 + +# CHECK : dcffixqq 18, 20 +0xfe 0x40 0xa7 0xc4 + +# CHECK: dctfix 8, 4 +0xed 0x00 0x22 0x44 + +# CHECK: dctfix. 8, 4 +0xed 0x00 0x22 0x45 + +# CHECK: dctfixq 8, 4 +0xfd 0x00 0x22 0x44 + +# CHECK: dctfixq. 8, 4 +0xfd 0x00 0x22 0x45 + +# CHECK: dctfixqq 8, 10 +0xfd 0x01 0x57 0xc4 diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s b/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s --- a/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s +++ b/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s @@ -62,3 +62,57 @@ # CHECK-BE: dcmpoq 2, 6, 4 # encoding: [0xfd,0x06,0x21,0x04] # CHECK-LE: dcmpoq 2, 6, 4 # encoding: [0x04,0x21,0x06,0xfd] dcmpoq 2, 6, 4 +# CHECK-LE: dctdp 8, 2 # encoding: [0x04,0x12,0x00,0xed] +# CHECK-BE: dctdp 8, 2 # encoding: [0xed,0x00,0x12,0x04] + dctdp 8, 2 +# CHECK-LE: dctdp. 8, 2 # encoding: [0x05,0x12,0x00,0xed] +# CHECK-BE: dctdp. 8, 2 # encoding: [0xed,0x00,0x12,0x05] + dctdp. 8, 2 +# CHECK-LE: dctqpq 8, 2 # encoding: [0x04,0x12,0x00,0xfd] +# CHECK-BE: dctqpq 8, 2 # encoding: [0xfd,0x00,0x12,0x04] + dctqpq 8, 2 +# CHECK-LE: dctqpq. 8, 2 # encoding: [0x05,0x12,0x00,0xfd] +# CHECK-BE: dctqpq. 8, 2 # encoding: [0xfd,0x00,0x12,0x05] + dctqpq. 8, 2 +# CHECK-LE: drsp 20, 8 # encoding: [0x04,0x46,0x80,0xee] +# CHECK-BE: drsp 20, 8 # encoding: [0xee,0x80,0x46,0x04] + drsp 20, 8 +# CHECK-LE: drsp. 20, 8 # encoding: [0x05,0x46,0x80,0xee] +# CHECK-BE: drsp. 20, 8 # encoding: [0xee,0x80,0x46,0x05] + drsp. 20, 8 +# CHECK-LE: drdpq 20, 8 # encoding: [0x04,0x46,0x80,0xfe] +# CHECK-BE: drdpq 20, 8 # encoding: [0xfe,0x80,0x46,0x04] + drdpq 20, 8 +# CHECK-LE: drdpq. 20, 8 # encoding: [0x05,0x46,0x80,0xfe] +# CHECK-BE: drdpq. 20, 8 # encoding: [0xfe,0x80,0x46,0x05] + drdpq. 20, 8 +# CHECK-LE: dcffix 12, 7 # encoding: [0x44,0x3e,0x80,0xed] +# CHECK-BE: dcffix 12, 7 # encoding: [0xed,0x80,0x3e,0x44] + dcffix 12, 7 +# CHECK-LE: dcffix. 12, 7 # encoding: [0x45,0x3e,0x80,0xed] +# CHECK-BE: dcffix. 12, 7 # encoding: [0xed,0x80,0x3e,0x45] + dcffix. 12, 7 +# CHECK-LE: dcffixq 12, 8 # encoding: [0x44,0x46,0x80,0xfd] +# CHECK-BE: dcffixq 12, 8 # encoding: [0xfd,0x80,0x46,0x44] + dcffixq 12, 8 +# CHECK-LE: dcffixq. 12, 8 # encoding: [0x45,0x46,0x80,0xfd] +# CHECK-BE: dcffixq. 12, 8 # encoding: [0xfd,0x80,0x46,0x45] + dcffixq. 12, 8 +# CHECK-LE: dctfix 8, 4 # encoding: [0x44,0x22,0x00,0xed] +# CHECK-BE: dctfix 8, 4 # encoding: [0xed,0x00,0x22,0x44] + dctfix 8, 4 +# CHECK-LE: dctfix. 8, 4 # encoding: [0x45,0x22,0x00,0xed] +# CHECK-BE: dctfix. 8, 4 # encoding: [0xed,0x00,0x22,0x45] + dctfix. 8, 4 +# CHECK-LE: dctfixq 8, 4 # encoding: [0x44,0x22,0x00,0xfd] +# CHECK-BE: dctfixq 8, 4 # encoding: [0xfd,0x00,0x22,0x44] + dctfixq 8, 4 +# CHECK-LE: dctfixq. 8, 4 # encoding: [0x45,0x22,0x00,0xfd] +# CHECK-BE: dctfixq. 8, 4 # encoding: [0xfd,0x00,0x22,0x45] + dctfixq. 8, 4 +# CHECK-LE: dcffixqq 18, 20 # encoding: [0xc4,0xa7,0x40,0xfe] +# CHECK-BE: dcffixqq 18, 20 # encoding: [0xfe,0x40,0xa7,0xc4] + dcffixqq 18, 20 +# CHECK-LE: dctfixqq 8, 10 # encoding: [0xc4,0x57,0x01,0xfd] +# CHECK-BE: dctfixqq 8, 10 # encoding: [0xfd,0x01,0x57,0xc4] + dctfixqq 8, 10