diff --git a/llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp b/llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp --- a/llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp +++ b/llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp @@ -109,6 +109,15 @@ return MCDisassembler::Success; } +static DecodeStatus DecodeLASX256RegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { + if (RegNo >= 32) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::createReg(LoongArch::XR0 + RegNo)); + return MCDisassembler::Success; +} + template static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td --- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td @@ -526,6 +526,7 @@ include "LoongArchInstrFormats.td" include "LoongArchFloatInstrFormats.td" include "LoongArchLSXInstrFormats.td" +include "LoongArchLASXInstrFormats.td" //===----------------------------------------------------------------------===// // Instruction Class Templates @@ -2013,3 +2014,8 @@ // LSX Instructions //===----------------------------------------------------------------------===// include "LoongArchLSXInstrInfo.td" + +//===----------------------------------------------------------------------===// +// LASX Instructions +//===----------------------------------------------------------------------===// +include "LoongArchLASXInstrInfo.td" diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrFormats.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrFormats.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrFormats.td @@ -0,0 +1,459 @@ +// LoongArchLASXInstrFormats.td - LoongArch LASX Instr Formats - tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Describe LoongArch LASX instructions format +// +// opcode - operation code. +// xd/rd/cd - destination register operand. +// {r/x}{j/k} - source register operand. +// immN - immediate data operand. +// +//===----------------------------------------------------------------------===// + +// 1RI13-type +// +class Fmt1RI13_XI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<13> imm13; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{17-5} = imm13; + let Inst{4-0} = xd; +} + +// 2R-type +// +class Fmt2R_XX op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<5> xj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{9-5} = xj; + let Inst{4-0} = xd; +} + +// +class Fmt2R_XR op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<5> rj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{9-5} = rj; + let Inst{4-0} = xd; +} + +// +class Fmt2R_CX op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<5> xj; + bits<3> cd; + + let Inst{31-0} = op; + let Inst{9-5} = xj; + let Inst{2-0} = cd; +} + +// 2RI1-type +// +class Fmt2RI1_XXI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<1> imm1; + bits<5> xj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{10} = imm1; + let Inst{9-5} = xj; + let Inst{4-0} = xd; +} + +// 2RI2-type +// +class Fmt2RI2_XXI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<2> imm2; + bits<5> xj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{11-10} = imm2; + let Inst{9-5} = xj; + let Inst{4-0} = xd; +} + +// +class Fmt2RI2_XRI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<2> imm2; + bits<5> rj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{11-10} = imm2; + let Inst{9-5} = rj; + let Inst{4-0} = xd; +} + +// +class Fmt2RI2_RXI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<2> imm2; + bits<5> xj; + bits<5> rd; + + let Inst{31-0} = op; + let Inst{11-10} = imm2; + let Inst{9-5} = xj; + let Inst{4-0} = rd; +} + +// 2RI3-type +// +class Fmt2RI3_XXI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<3> imm3; + bits<5> xj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{12-10} = imm3; + let Inst{9-5} = xj; + let Inst{4-0} = xd; +} + +// +class Fmt2RI3_XRI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<3> imm3; + bits<5> rj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{12-10} = imm3; + let Inst{9-5} = rj; + let Inst{4-0} = xd; +} + +// +class Fmt2RI3_RXI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<3> imm3; + bits<5> xj; + bits<5> rd; + + let Inst{31-0} = op; + let Inst{12-10} = imm3; + let Inst{9-5} = xj; + let Inst{4-0} = rd; +} + +// 2RI4-type +// +class Fmt2RI4_XXI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<4> imm4; + bits<5> xj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{13-10} = imm4; + let Inst{9-5} = xj; + let Inst{4-0} = xd; +} + +// +class Fmt2RI4_XRI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<4> imm4; + bits<5> rj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{13-10} = imm4; + let Inst{9-5} = rj; + let Inst{4-0} = xd; +} + +// +class Fmt2RI4_RXI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<4> imm4; + bits<5> xj; + bits<5> rd; + + let Inst{31-0} = op; + let Inst{13-10} = imm4; + let Inst{9-5} = xj; + let Inst{4-0} = rd; +} + +// 2RI5-type +// +class Fmt2RI5_XXI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<5> imm5; + bits<5> xj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{14-10} = imm5; + let Inst{9-5} = xj; + let Inst{4-0} = xd; +} + +// 2RI6-type +// +class Fmt2RI6_XXI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<6> imm6; + bits<5> xj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{15-10} = imm6; + let Inst{9-5} = xj; + let Inst{4-0} = xd; +} + +// 2RI7-type +// +class Fmt2RI7_XXI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<7> imm7; + bits<5> xj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{16-10} = imm7; + let Inst{9-5} = xj; + let Inst{4-0} = xd; +} + +// 2RI8-type +// +class Fmt2RI8_XXI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<8> imm8; + bits<5> xj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{17-10} = imm8; + let Inst{9-5} = xj; + let Inst{4-0} = xd; +} + +// 2RI8I2-type +// +class Fmt2RI8I2_XRII op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<2> imm2; + bits<8> imm8; + bits<5> rj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{19-18} = imm2; + let Inst{17-10} = imm8; + let Inst{9-5} = rj; + let Inst{4-0} = xd; +} + +// 2RI8I3-type +// +class Fmt2RI8I3_XRII op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<3> imm3; + bits<8> imm8; + bits<5> rj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{20-18} = imm3; + let Inst{17-10} = imm8; + let Inst{9-5} = rj; + let Inst{4-0} = xd; +} + +// 2RI8I4-type +// +class Fmt2RI8I4_XRII op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<4> imm4; + bits<8> imm8; + bits<5> rj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{21-18} = imm4; + let Inst{17-10} = imm8; + let Inst{9-5} = rj; + let Inst{4-0} = xd; +} + +// 2RI8I5-type +// +class Fmt2RI8I5_XRII op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<5> imm5; + bits<8> imm8; + bits<5> rj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{22-18} = imm5; + let Inst{17-10} = imm8; + let Inst{9-5} = rj; + let Inst{4-0} = xd; +} + +// 2RI9-type +// +class Fmt2RI9_XRI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<9> imm9; + bits<5> rj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{18-10} = imm9; + let Inst{9-5} = rj; + let Inst{4-0} = xd; +} + +// 2RI10-type +// +class Fmt2RI10_XRI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<10> imm10; + bits<5> rj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{19-10} = imm10; + let Inst{9-5} = rj; + let Inst{4-0} = xd; +} + +// 2RI11-type +// +class Fmt2RI11_XRI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<11> imm11; + bits<5> rj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{20-10} = imm11; + let Inst{9-5} = rj; + let Inst{4-0} = xd; +} + +// 2RI12-type +// +class Fmt2RI12_XRI op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<12> imm12; + bits<5> rj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{21-10} = imm12; + let Inst{9-5} = rj; + let Inst{4-0} = xd; +} + +// 3R-type +// +class Fmt3R_XXX op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<5> xk; + bits<5> xj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{14-10} = xk; + let Inst{9-5} = xj; + let Inst{4-0} = xd; +} + +// +class Fmt3R_XXR op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<5> rk; + bits<5> xj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{14-10} = rk; + let Inst{9-5} = xj; + let Inst{4-0} = xd; +} + +// +class Fmt3R_XRR op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<5> rk; + bits<5> rj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{14-10} = rk; + let Inst{9-5} = rj; + let Inst{4-0} = xd; +} + +// 4R-type +// +class Fmt4R_XXXX op, dag outs, dag ins, string opcstr, string opnstr, + list pattern = []> + : LAInst { + bits<5> xa; + bits<5> xk; + bits<5> xj; + bits<5> xd; + + let Inst{31-0} = op; + let Inst{19-15} = xa; + let Inst{14-10} = xk; + let Inst{9-5} = xj; + let Inst{4-0} = xd; +} diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td @@ -0,0 +1,1025 @@ +//=- LoongArchLASXInstrInfo.td - LoongArch LASX instructions -*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the Adxanced SIMD extension instructions. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction class templates +//===----------------------------------------------------------------------===// + +class LASX1RI13_XI op, Operand ImmOpnd = simm13> + : Fmt1RI13_XI; + +class LASX2R_XX op> + : Fmt2R_XX; + +class LASX2R_XR op> + : Fmt2R_XR; + +class LASX2R_CX op> + : Fmt2R_CX; + +class LASX2RI1_XXI op, Operand ImmOpnd = uimm1> + : Fmt2RI1_XXI; + +class LASX2RI2_XXI op, Operand ImmOpnd = uimm2> + : Fmt2RI2_XXI; + +class LASX2RI2_XRI op, Operand ImmOpnd = uimm2> + : Fmt2RI2_XRI; + +class LASX2RI2_RXI op, Operand ImmOpnd = uimm2> + : Fmt2RI2_RXI; + +class LASX2RI3_XXI op, Operand ImmOpnd = uimm3> + : Fmt2RI3_XXI; + +class LASX2RI3_XRI op, Operand ImmOpnd = uimm3> + : Fmt2RI3_XRI; + +class LASX2RI3_RXI op, Operand ImmOpnd = uimm3> + : Fmt2RI3_RXI; + +class LASX2RI4_XXI op, Operand ImmOpnd = uimm4> + : Fmt2RI4_XXI; + +class LASX2RI4_XRI op, Operand ImmOpnd = uimm4> + : Fmt2RI4_XRI; + +class LASX2RI4_RXI op, Operand ImmOpnd = uimm4> + : Fmt2RI4_RXI; + +class LASX2RI5_XXI op, Operand ImmOpnd = uimm5> + : Fmt2RI5_XXI; + +class LASX2RI6_XXI op, Operand ImmOpnd = uimm6> + : Fmt2RI6_XXI; + +class LASX2RI8_XXI op, Operand ImmOpnd = uimm8> + : Fmt2RI8_XXI; + +class LASX2RI8I2_XRII op, Operand ImmOpnd = simm8, + Operand IdxOpnd = uimm2> + : Fmt2RI8I2_XRII; +class LASX2RI8I3_XRII op, Operand ImmOpnd = simm8, + Operand IdxOpnd = uimm3> + : Fmt2RI8I3_XRII; +class LASX2RI8I4_XRII op, Operand ImmOpnd = simm8, + Operand IdxOpnd = uimm4> + : Fmt2RI8I4_XRII; +class LASX2RI8I5_XRII op, Operand ImmOpnd = simm8, + Operand IdxOpnd = uimm5> + : Fmt2RI8I5_XRII; + +class LASX2RI9_XRI op, Operand ImmOpnd = simm9_lsl3> + : Fmt2RI9_XRI; + +class LASX2RI10_XRI op, Operand ImmOpnd = simm10_lsl2> + : Fmt2RI10_XRI; + +class LASX2RI11_XRI op, Operand ImmOpnd = simm11_lsl1> + : Fmt2RI11_XRI; + +class LASX2RI12_XRI op, Operand ImmOpnd = simm12> + : Fmt2RI12_XRI; + +class LASX3R_XXX op> + : Fmt3R_XXX; + +class LASX3R_XXR op> + : Fmt3R_XXR; + +class LASX3R_XRR op> + : Fmt3R_XRR; + +class LASX4R_XXXX op> + : Fmt4R_XXXX; + +let Constraints = "$xd = $dst" in { + +class LASX2RI4_XXXI op, Operand ImmOpnd = uimm4> + : Fmt2RI4_XXI; +class LASX2RI5_XXXI op, Operand ImmOpnd = uimm5> + : Fmt2RI5_XXI; +class LASX2RI6_XXXI op, Operand ImmOpnd = uimm6> + : Fmt2RI6_XXI; +class LASX2RI7_XXXI op, Operand ImmOpnd = uimm7> + : Fmt2RI7_XXI; + +class LASX2RI8_XXXI op, Operand ImmOpnd = uimm8> + : Fmt2RI8_XXI; + +class LASX3R_XXXX op> + : Fmt3R_XXX; + +} // Constraints = "$xd = $dst" + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [HasExtLASX] in { + +def XVADD_B : LASX3R_XXX<0x740a0000>; +def XVADD_H : LASX3R_XXX<0x740a8000>; +def XVADD_W : LASX3R_XXX<0x740b0000>; +def XVADD_D : LASX3R_XXX<0x740b8000>; +def XVADD_Q : LASX3R_XXX<0x752d0000>; + +def XVSUB_B : LASX3R_XXX<0x740c0000>; +def XVSUB_H : LASX3R_XXX<0x740c8000>; +def XVSUB_W : LASX3R_XXX<0x740d0000>; +def XVSUB_D : LASX3R_XXX<0x740d8000>; +def XVSUB_Q : LASX3R_XXX<0x752d8000>; + +def XVADDI_BU : LASX2RI5_XXI<0x768a0000>; +def XVADDI_HU : LASX2RI5_XXI<0x768a8000>; +def XVADDI_WU : LASX2RI5_XXI<0x768b0000>; +def XVADDI_DU : LASX2RI5_XXI<0x768b8000>; + +def XVSUBI_BU : LASX2RI5_XXI<0x768c0000>; +def XVSUBI_HU : LASX2RI5_XXI<0x768c8000>; +def XVSUBI_WU : LASX2RI5_XXI<0x768d0000>; +def XVSUBI_DU : LASX2RI5_XXI<0x768d8000>; + +def XVNEG_B : LASX2R_XX<0x769c3000>; +def XVNEG_H : LASX2R_XX<0x769c3400>; +def XVNEG_W : LASX2R_XX<0x769c3800>; +def XVNEG_D : LASX2R_XX<0x769c3c00>; + +def XVSADD_B : LASX3R_XXX<0x74460000>; +def XVSADD_H : LASX3R_XXX<0x74468000>; +def XVSADD_W : LASX3R_XXX<0x74470000>; +def XVSADD_D : LASX3R_XXX<0x74478000>; +def XVSADD_BU : LASX3R_XXX<0x744a0000>; +def XVSADD_HU : LASX3R_XXX<0x744a8000>; +def XVSADD_WU : LASX3R_XXX<0x744b0000>; +def XVSADD_DU : LASX3R_XXX<0x744b8000>; + +def XVSSUB_B : LASX3R_XXX<0x74480000>; +def XVSSUB_H : LASX3R_XXX<0x74488000>; +def XVSSUB_W : LASX3R_XXX<0x74490000>; +def XVSSUB_D : LASX3R_XXX<0x74498000>; +def XVSSUB_BU : LASX3R_XXX<0x744c0000>; +def XVSSUB_HU : LASX3R_XXX<0x744c8000>; +def XVSSUB_WU : LASX3R_XXX<0x744d0000>; +def XVSSUB_DU : LASX3R_XXX<0x744d8000>; + +def XVHADDW_H_B : LASX3R_XXX<0x74540000>; +def XVHADDW_W_H : LASX3R_XXX<0x74548000>; +def XVHADDW_D_W : LASX3R_XXX<0x74550000>; +def XVHADDW_Q_D : LASX3R_XXX<0x74558000>; +def XVHADDW_HU_BU : LASX3R_XXX<0x74580000>; +def XVHADDW_WU_HU : LASX3R_XXX<0x74588000>; +def XVHADDW_DU_WU : LASX3R_XXX<0x74590000>; +def XVHADDW_QU_DU : LASX3R_XXX<0x74598000>; + +def XVHSUBW_H_B : LASX3R_XXX<0x74560000>; +def XVHSUBW_W_H : LASX3R_XXX<0x74568000>; +def XVHSUBW_D_W : LASX3R_XXX<0x74570000>; +def XVHSUBW_Q_D : LASX3R_XXX<0x74578000>; +def XVHSUBW_HU_BU : LASX3R_XXX<0x745a0000>; +def XVHSUBW_WU_HU : LASX3R_XXX<0x745a8000>; +def XVHSUBW_DU_WU : LASX3R_XXX<0x745b0000>; +def XVHSUBW_QU_DU : LASX3R_XXX<0x745b8000>; + +def XVADDWEV_H_B : LASX3R_XXX<0x741e0000>; +def XVADDWEV_W_H : LASX3R_XXX<0x741e8000>; +def XVADDWEV_D_W : LASX3R_XXX<0x741f0000>; +def XVADDWEV_Q_D : LASX3R_XXX<0x741f8000>; +def XVADDWOD_H_B : LASX3R_XXX<0x74220000>; +def XVADDWOD_W_H : LASX3R_XXX<0x74228000>; +def XVADDWOD_D_W : LASX3R_XXX<0x74230000>; +def XVADDWOD_Q_D : LASX3R_XXX<0x74238000>; + +def XVSUBWEV_H_B : LASX3R_XXX<0x74200000>; +def XVSUBWEV_W_H : LASX3R_XXX<0x74208000>; +def XVSUBWEV_D_W : LASX3R_XXX<0x74210000>; +def XVSUBWEV_Q_D : LASX3R_XXX<0x74218000>; +def XVSUBWOD_H_B : LASX3R_XXX<0x74240000>; +def XVSUBWOD_W_H : LASX3R_XXX<0x74248000>; +def XVSUBWOD_D_W : LASX3R_XXX<0x74250000>; +def XVSUBWOD_Q_D : LASX3R_XXX<0x74258000>; + +def XVADDWEV_H_BU : LASX3R_XXX<0x742e0000>; +def XVADDWEV_W_HU : LASX3R_XXX<0x742e8000>; +def XVADDWEV_D_WU : LASX3R_XXX<0x742f0000>; +def XVADDWEV_Q_DU : LASX3R_XXX<0x742f8000>; +def XVADDWOD_H_BU : LASX3R_XXX<0x74320000>; +def XVADDWOD_W_HU : LASX3R_XXX<0x74328000>; +def XVADDWOD_D_WU : LASX3R_XXX<0x74330000>; +def XVADDWOD_Q_DU : LASX3R_XXX<0x74338000>; + +def XVSUBWEV_H_BU : LASX3R_XXX<0x74300000>; +def XVSUBWEV_W_HU : LASX3R_XXX<0x74308000>; +def XVSUBWEV_D_WU : LASX3R_XXX<0x74310000>; +def XVSUBWEV_Q_DU : LASX3R_XXX<0x74318000>; +def XVSUBWOD_H_BU : LASX3R_XXX<0x74340000>; +def XVSUBWOD_W_HU : LASX3R_XXX<0x74348000>; +def XVSUBWOD_D_WU : LASX3R_XXX<0x74350000>; +def XVSUBWOD_Q_DU : LASX3R_XXX<0x74358000>; + +def XVADDWEV_H_BU_B : LASX3R_XXX<0x743e0000>; +def XVADDWEV_W_HU_H : LASX3R_XXX<0x743e8000>; +def XVADDWEV_D_WU_W : LASX3R_XXX<0x743f0000>; +def XVADDWEV_Q_DU_D : LASX3R_XXX<0x743f8000>; +def XVADDWOD_H_BU_B : LASX3R_XXX<0x74400000>; +def XVADDWOD_W_HU_H : LASX3R_XXX<0x74408000>; +def XVADDWOD_D_WU_W : LASX3R_XXX<0x74410000>; +def XVADDWOD_Q_DU_D : LASX3R_XXX<0x74418000>; + +def XVAVG_B : LASX3R_XXX<0x74640000>; +def XVAVG_H : LASX3R_XXX<0x74648000>; +def XVAVG_W : LASX3R_XXX<0x74650000>; +def XVAVG_D : LASX3R_XXX<0x74658000>; +def XVAVG_BU : LASX3R_XXX<0x74660000>; +def XVAVG_HU : LASX3R_XXX<0x74668000>; +def XVAVG_WU : LASX3R_XXX<0x74670000>; +def XVAVG_DU : LASX3R_XXX<0x74678000>; +def XVAVGR_B : LASX3R_XXX<0x74680000>; +def XVAVGR_H : LASX3R_XXX<0x74688000>; +def XVAVGR_W : LASX3R_XXX<0x74690000>; +def XVAVGR_D : LASX3R_XXX<0x74698000>; +def XVAVGR_BU : LASX3R_XXX<0x746a0000>; +def XVAVGR_HU : LASX3R_XXX<0x746a8000>; +def XVAVGR_WU : LASX3R_XXX<0x746b0000>; +def XVAVGR_DU : LASX3R_XXX<0x746b8000>; + +def XVABSD_B : LASX3R_XXX<0x74600000>; +def XVABSD_H : LASX3R_XXX<0x74608000>; +def XVABSD_W : LASX3R_XXX<0x74610000>; +def XVABSD_D : LASX3R_XXX<0x74618000>; +def XVABSD_BU : LASX3R_XXX<0x74620000>; +def XVABSD_HU : LASX3R_XXX<0x74628000>; +def XVABSD_WU : LASX3R_XXX<0x74630000>; +def XVABSD_DU : LASX3R_XXX<0x74638000>; + +def XVADDA_B : LASX3R_XXX<0x745c0000>; +def XVADDA_H : LASX3R_XXX<0x745c8000>; +def XVADDA_W : LASX3R_XXX<0x745d0000>; +def XVADDA_D : LASX3R_XXX<0x745d8000>; + +def XVMAX_B : LASX3R_XXX<0x74700000>; +def XVMAX_H : LASX3R_XXX<0x74708000>; +def XVMAX_W : LASX3R_XXX<0x74710000>; +def XVMAX_D : LASX3R_XXX<0x74718000>; +def XVMAXI_B : LASX2RI5_XXI<0x76900000, simm5>; +def XVMAXI_H : LASX2RI5_XXI<0x76908000, simm5>; +def XVMAXI_W : LASX2RI5_XXI<0x76910000, simm5>; +def XVMAXI_D : LASX2RI5_XXI<0x76918000, simm5>; +def XVMAX_BU : LASX3R_XXX<0x74740000>; +def XVMAX_HU : LASX3R_XXX<0x74748000>; +def XVMAX_WU : LASX3R_XXX<0x74750000>; +def XVMAX_DU : LASX3R_XXX<0x74758000>; +def XVMAXI_BU : LASX2RI5_XXI<0x76940000>; +def XVMAXI_HU : LASX2RI5_XXI<0x76948000>; +def XVMAXI_WU : LASX2RI5_XXI<0x76950000>; +def XVMAXI_DU : LASX2RI5_XXI<0x76958000>; + +def XVMIN_B : LASX3R_XXX<0x74720000>; +def XVMIN_H : LASX3R_XXX<0x74728000>; +def XVMIN_W : LASX3R_XXX<0x74730000>; +def XVMIN_D : LASX3R_XXX<0x74738000>; +def XVMINI_B : LASX2RI5_XXI<0x76920000, simm5>; +def XVMINI_H : LASX2RI5_XXI<0x76928000, simm5>; +def XVMINI_W : LASX2RI5_XXI<0x76930000, simm5>; +def XVMINI_D : LASX2RI5_XXI<0x76938000, simm5>; +def XVMIN_BU : LASX3R_XXX<0x74760000>; +def XVMIN_HU : LASX3R_XXX<0x74768000>; +def XVMIN_WU : LASX3R_XXX<0x74770000>; +def XVMIN_DU : LASX3R_XXX<0x74778000>; +def XVMINI_BU : LASX2RI5_XXI<0x76960000>; +def XVMINI_HU : LASX2RI5_XXI<0x76968000>; +def XVMINI_WU : LASX2RI5_XXI<0x76970000>; +def XVMINI_DU : LASX2RI5_XXI<0x76978000>; + +def XVMUL_B : LASX3R_XXX<0x74840000>; +def XVMUL_H : LASX3R_XXX<0x74848000>; +def XVMUL_W : LASX3R_XXX<0x74850000>; +def XVMUL_D : LASX3R_XXX<0x74858000>; + +def XVMUH_B : LASX3R_XXX<0x74860000>; +def XVMUH_H : LASX3R_XXX<0x74868000>; +def XVMUH_W : LASX3R_XXX<0x74870000>; +def XVMUH_D : LASX3R_XXX<0x74878000>; +def XVMUH_BU : LASX3R_XXX<0x74880000>; +def XVMUH_HU : LASX3R_XXX<0x74888000>; +def XVMUH_WU : LASX3R_XXX<0x74890000>; +def XVMUH_DU : LASX3R_XXX<0x74898000>; + +def XVMULWEV_H_B : LASX3R_XXX<0x74900000>; +def XVMULWEV_W_H : LASX3R_XXX<0x74908000>; +def XVMULWEV_D_W : LASX3R_XXX<0x74910000>; +def XVMULWEV_Q_D : LASX3R_XXX<0x74918000>; +def XVMULWOD_H_B : LASX3R_XXX<0x74920000>; +def XVMULWOD_W_H : LASX3R_XXX<0x74928000>; +def XVMULWOD_D_W : LASX3R_XXX<0x74930000>; +def XVMULWOD_Q_D : LASX3R_XXX<0x74938000>; +def XVMULWEV_H_BU : LASX3R_XXX<0x74980000>; +def XVMULWEV_W_HU : LASX3R_XXX<0x74988000>; +def XVMULWEV_D_WU : LASX3R_XXX<0x74990000>; +def XVMULWEV_Q_DU : LASX3R_XXX<0x74998000>; +def XVMULWOD_H_BU : LASX3R_XXX<0x749a0000>; +def XVMULWOD_W_HU : LASX3R_XXX<0x749a8000>; +def XVMULWOD_D_WU : LASX3R_XXX<0x749b0000>; +def XVMULWOD_Q_DU : LASX3R_XXX<0x749b8000>; +def XVMULWEV_H_BU_B : LASX3R_XXX<0x74a00000>; +def XVMULWEV_W_HU_H : LASX3R_XXX<0x74a08000>; +def XVMULWEV_D_WU_W : LASX3R_XXX<0x74a10000>; +def XVMULWEV_Q_DU_D : LASX3R_XXX<0x74a18000>; +def XVMULWOD_H_BU_B : LASX3R_XXX<0x74a20000>; +def XVMULWOD_W_HU_H : LASX3R_XXX<0x74a28000>; +def XVMULWOD_D_WU_W : LASX3R_XXX<0x74a30000>; +def XVMULWOD_Q_DU_D : LASX3R_XXX<0x74a38000>; + +def XVMADD_B : LASX3R_XXXX<0x74a80000>; +def XVMADD_H : LASX3R_XXXX<0x74a88000>; +def XVMADD_W : LASX3R_XXXX<0x74a90000>; +def XVMADD_D : LASX3R_XXXX<0x74a98000>; + +def XVMSUB_B : LASX3R_XXXX<0x74aa0000>; +def XVMSUB_H : LASX3R_XXXX<0x74aa8000>; +def XVMSUB_W : LASX3R_XXXX<0x74ab0000>; +def XVMSUB_D : LASX3R_XXXX<0x74ab8000>; + +def XVMADDWEV_H_B : LASX3R_XXXX<0x74ac0000>; +def XVMADDWEV_W_H : LASX3R_XXXX<0x74ac8000>; +def XVMADDWEV_D_W : LASX3R_XXXX<0x74ad0000>; +def XVMADDWEV_Q_D : LASX3R_XXXX<0x74ad8000>; +def XVMADDWOD_H_B : LASX3R_XXXX<0x74ae0000>; +def XVMADDWOD_W_H : LASX3R_XXXX<0x74ae8000>; +def XVMADDWOD_D_W : LASX3R_XXXX<0x74af0000>; +def XVMADDWOD_Q_D : LASX3R_XXXX<0x74af8000>; +def XVMADDWEV_H_BU : LASX3R_XXXX<0x74b40000>; +def XVMADDWEV_W_HU : LASX3R_XXXX<0x74b48000>; +def XVMADDWEV_D_WU : LASX3R_XXXX<0x74b50000>; +def XVMADDWEV_Q_DU : LASX3R_XXXX<0x74b58000>; +def XVMADDWOD_H_BU : LASX3R_XXXX<0x74b60000>; +def XVMADDWOD_W_HU : LASX3R_XXXX<0x74b68000>; +def XVMADDWOD_D_WU : LASX3R_XXXX<0x74b70000>; +def XVMADDWOD_Q_DU : LASX3R_XXXX<0x74b78000>; +def XVMADDWEV_H_BU_B : LASX3R_XXXX<0x74bc0000>; +def XVMADDWEV_W_HU_H : LASX3R_XXXX<0x74bc8000>; +def XVMADDWEV_D_WU_W : LASX3R_XXXX<0x74bd0000>; +def XVMADDWEV_Q_DU_D : LASX3R_XXXX<0x74bd8000>; +def XVMADDWOD_H_BU_B : LASX3R_XXXX<0x74be0000>; +def XVMADDWOD_W_HU_H : LASX3R_XXXX<0x74be8000>; +def XVMADDWOD_D_WU_W : LASX3R_XXXX<0x74bf0000>; +def XVMADDWOD_Q_DU_D : LASX3R_XXXX<0x74bf8000>; + +def XVDIV_B : LASX3R_XXX<0x74e00000>; +def XVDIV_H : LASX3R_XXX<0x74e08000>; +def XVDIV_W : LASX3R_XXX<0x74e10000>; +def XVDIV_D : LASX3R_XXX<0x74e18000>; +def XVDIV_BU : LASX3R_XXX<0x74e40000>; +def XVDIV_HU : LASX3R_XXX<0x74e48000>; +def XVDIV_WU : LASX3R_XXX<0x74e50000>; +def XVDIV_DU : LASX3R_XXX<0x74e58000>; + +def XVMOD_B : LASX3R_XXX<0x74e20000>; +def XVMOD_H : LASX3R_XXX<0x74e28000>; +def XVMOD_W : LASX3R_XXX<0x74e30000>; +def XVMOD_D : LASX3R_XXX<0x74e38000>; +def XVMOD_BU : LASX3R_XXX<0x74e60000>; +def XVMOD_HU : LASX3R_XXX<0x74e68000>; +def XVMOD_WU : LASX3R_XXX<0x74e70000>; +def XVMOD_DU : LASX3R_XXX<0x74e78000>; + +def XVSAT_B : LASX2RI3_XXI<0x77242000>; +def XVSAT_H : LASX2RI4_XXI<0x77244000>; +def XVSAT_W : LASX2RI5_XXI<0x77248000>; +def XVSAT_D : LASX2RI6_XXI<0x77250000>; +def XVSAT_BU : LASX2RI3_XXI<0x77282000>; +def XVSAT_HU : LASX2RI4_XXI<0x77284000>; +def XVSAT_WU : LASX2RI5_XXI<0x77288000>; +def XVSAT_DU : LASX2RI6_XXI<0x77290000>; + +def XVEXTH_H_B : LASX2R_XX<0x769ee000>; +def XVEXTH_W_H : LASX2R_XX<0x769ee400>; +def XVEXTH_D_W : LASX2R_XX<0x769ee800>; +def XVEXTH_Q_D : LASX2R_XX<0x769eec00>; +def XVEXTH_HU_BU : LASX2R_XX<0x769ef000>; +def XVEXTH_WU_HU : LASX2R_XX<0x769ef400>; +def XVEXTH_DU_WU : LASX2R_XX<0x769ef800>; +def XVEXTH_QU_DU : LASX2R_XX<0x769efc00>; + +def VEXT2XV_H_B : LASX2R_XX<0x769f1000>; +def VEXT2XV_W_B : LASX2R_XX<0x769f1400>; +def VEXT2XV_D_B : LASX2R_XX<0x769f1800>; +def VEXT2XV_W_H : LASX2R_XX<0x769f1c00>; +def VEXT2XV_D_H : LASX2R_XX<0x769f2000>; +def VEXT2XV_D_W : LASX2R_XX<0x769f2400>; +def VEXT2XV_HU_BU : LASX2R_XX<0x769f2800>; +def VEXT2XV_WU_BU : LASX2R_XX<0x769f2c00>; +def VEXT2XV_DU_BU : LASX2R_XX<0x769f3000>; +def VEXT2XV_WU_HU : LASX2R_XX<0x769f3400>; +def VEXT2XV_DU_HU : LASX2R_XX<0x769f3800>; +def VEXT2XV_DU_WU : LASX2R_XX<0x769f3c00>; + +def XVHSELI_D : LASX2RI5_XXI<0x769f8000>; + +def XVSIGNCOV_B : LASX3R_XXX<0x752e0000>; +def XVSIGNCOV_H : LASX3R_XXX<0x752e8000>; +def XVSIGNCOV_W : LASX3R_XXX<0x752f0000>; +def XVSIGNCOV_D : LASX3R_XXX<0x752f8000>; + +def XVMSKLTZ_B : LASX2R_XX<0x769c4000>; +def XVMSKLTZ_H : LASX2R_XX<0x769c4400>; +def XVMSKLTZ_W : LASX2R_XX<0x769c4800>; +def XVMSKLTZ_D : LASX2R_XX<0x769c4c00>; + +def XVMSKGEZ_B : LASX2R_XX<0x769c5000>; + +def XVMSKNZ_B : LASX2R_XX<0x769c6000>; + +def XVLDI : LASX1RI13_XI<0x77e00000>; + +def XVAND_V : LASX3R_XXX<0x75260000>; +def XVOR_V : LASX3R_XXX<0x75268000>; +def XVXOR_V : LASX3R_XXX<0x75270000>; +def XVNOR_V : LASX3R_XXX<0x75278000>; +def XVANDN_V : LASX3R_XXX<0x75280000>; +def XVORN_V : LASX3R_XXX<0x75288000>; + +def XVANDI_B : LASX2RI8_XXI<0x77d00000>; +def XVORI_B : LASX2RI8_XXI<0x77d40000>; +def XVXORI_B : LASX2RI8_XXI<0x77d80000>; +def XVNORI_B : LASX2RI8_XXI<0x77dc0000>; + +def XVSLL_B : LASX3R_XXX<0x74e80000>; +def XVSLL_H : LASX3R_XXX<0x74e88000>; +def XVSLL_W : LASX3R_XXX<0x74e90000>; +def XVSLL_D : LASX3R_XXX<0x74e98000>; +def XVSLLI_B : LASX2RI3_XXI<0x772c2000>; +def XVSLLI_H : LASX2RI4_XXI<0x772c4000>; +def XVSLLI_W : LASX2RI5_XXI<0x772c8000>; +def XVSLLI_D : LASX2RI6_XXI<0x772d0000>; + +def XVSRL_B : LASX3R_XXX<0x74ea0000>; +def XVSRL_H : LASX3R_XXX<0x74ea8000>; +def XVSRL_W : LASX3R_XXX<0x74eb0000>; +def XVSRL_D : LASX3R_XXX<0x74eb8000>; +def XVSRLI_B : LASX2RI3_XXI<0x77302000>; +def XVSRLI_H : LASX2RI4_XXI<0x77304000>; +def XVSRLI_W : LASX2RI5_XXI<0x77308000>; +def XVSRLI_D : LASX2RI6_XXI<0x77310000>; + +def XVSRA_B : LASX3R_XXX<0x74ec0000>; +def XVSRA_H : LASX3R_XXX<0x74ec8000>; +def XVSRA_W : LASX3R_XXX<0x74ed0000>; +def XVSRA_D : LASX3R_XXX<0x74ed8000>; +def XVSRAI_B : LASX2RI3_XXI<0x77342000>; +def XVSRAI_H : LASX2RI4_XXI<0x77344000>; +def XVSRAI_W : LASX2RI5_XXI<0x77348000>; +def XVSRAI_D : LASX2RI6_XXI<0x77350000>; + +def XVROTR_B : LASX3R_XXX<0x74ee0000>; +def XVROTR_H : LASX3R_XXX<0x74ee8000>; +def XVROTR_W : LASX3R_XXX<0x74ef0000>; +def XVROTR_D : LASX3R_XXX<0x74ef8000>; +def XVROTRI_B : LASX2RI3_XXI<0x76a02000>; +def XVROTRI_H : LASX2RI4_XXI<0x76a04000>; +def XVROTRI_W : LASX2RI5_XXI<0x76a08000>; +def XVROTRI_D : LASX2RI6_XXI<0x76a10000>; + +def XVSLLWIL_H_B : LASX2RI3_XXI<0x77082000>; +def XVSLLWIL_W_H : LASX2RI4_XXI<0x77084000>; +def XVSLLWIL_D_W : LASX2RI5_XXI<0x77088000>; +def XVEXTL_Q_D : LASX2R_XX<0x77090000>; +def XVSLLWIL_HU_BU : LASX2RI3_XXI<0x770c2000>; +def XVSLLWIL_WU_HU : LASX2RI4_XXI<0x770c4000>; +def XVSLLWIL_DU_WU : LASX2RI5_XXI<0x770c8000>; +def XVEXTL_QU_DU : LASX2R_XX<0x770d0000>; + +def XVSRLR_B : LASX3R_XXX<0x74f00000>; +def XVSRLR_H : LASX3R_XXX<0x74f08000>; +def XVSRLR_W : LASX3R_XXX<0x74f10000>; +def XVSRLR_D : LASX3R_XXX<0x74f18000>; +def XVSRLRI_B : LASX2RI3_XXI<0x76a42000>; +def XVSRLRI_H : LASX2RI4_XXI<0x76a44000>; +def XVSRLRI_W : LASX2RI5_XXI<0x76a48000>; +def XVSRLRI_D : LASX2RI6_XXI<0x76a50000>; + +def XVSRAR_B : LASX3R_XXX<0x74f20000>; +def XVSRAR_H : LASX3R_XXX<0x74f28000>; +def XVSRAR_W : LASX3R_XXX<0x74f30000>; +def XVSRAR_D : LASX3R_XXX<0x74f38000>; +def XVSRARI_B : LASX2RI3_XXI<0x76a82000>; +def XVSRARI_H : LASX2RI4_XXI<0x76a84000>; +def XVSRARI_W : LASX2RI5_XXI<0x76a88000>; +def XVSRARI_D : LASX2RI6_XXI<0x76a90000>; + +def XVSRLN_B_H : LASX3R_XXX<0x74f48000>; +def XVSRLN_H_W : LASX3R_XXX<0x74f50000>; +def XVSRLN_W_D : LASX3R_XXX<0x74f58000>; +def XVSRAN_B_H : LASX3R_XXX<0x74f68000>; +def XVSRAN_H_W : LASX3R_XXX<0x74f70000>; +def XVSRAN_W_D : LASX3R_XXX<0x74f78000>; + +def XVSRLNI_B_H : LASX2RI4_XXXI<0x77404000>; +def XVSRLNI_H_W : LASX2RI5_XXXI<0x77408000>; +def XVSRLNI_W_D : LASX2RI6_XXXI<0x77410000>; +def XVSRLNI_D_Q : LASX2RI7_XXXI<0x77420000>; +def XVSRANI_B_H : LASX2RI4_XXXI<0x77584000>; +def XVSRANI_H_W : LASX2RI5_XXXI<0x77588000>; +def XVSRANI_W_D : LASX2RI6_XXXI<0x77590000>; +def XVSRANI_D_Q : LASX2RI7_XXXI<0x775a0000>; + +def XVSRLRN_B_H : LASX3R_XXX<0x74f88000>; +def XVSRLRN_H_W : LASX3R_XXX<0x74f90000>; +def XVSRLRN_W_D : LASX3R_XXX<0x74f98000>; +def XVSRARN_B_H : LASX3R_XXX<0x74fa8000>; +def XVSRARN_H_W : LASX3R_XXX<0x74fb0000>; +def XVSRARN_W_D : LASX3R_XXX<0x74fb8000>; + +def XVSRLRNI_B_H : LASX2RI4_XXXI<0x77444000>; +def XVSRLRNI_H_W : LASX2RI5_XXXI<0x77448000>; +def XVSRLRNI_W_D : LASX2RI6_XXXI<0x77450000>; +def XVSRLRNI_D_Q : LASX2RI7_XXXI<0x77460000>; +def XVSRARNI_B_H : LASX2RI4_XXXI<0x775c4000>; +def XVSRARNI_H_W : LASX2RI5_XXXI<0x775c8000>; +def XVSRARNI_W_D : LASX2RI6_XXXI<0x775d0000>; +def XVSRARNI_D_Q : LASX2RI7_XXXI<0x775e0000>; + +def XVSSRLN_B_H : LASX3R_XXX<0x74fc8000>; +def XVSSRLN_H_W : LASX3R_XXX<0x74fd0000>; +def XVSSRLN_W_D : LASX3R_XXX<0x74fd8000>; +def XVSSRAN_B_H : LASX3R_XXX<0x74fe8000>; +def XVSSRAN_H_W : LASX3R_XXX<0x74ff0000>; +def XVSSRAN_W_D : LASX3R_XXX<0x74ff8000>; +def XVSSRLN_BU_H : LASX3R_XXX<0x75048000>; +def XVSSRLN_HU_W : LASX3R_XXX<0x75050000>; +def XVSSRLN_WU_D : LASX3R_XXX<0x75058000>; +def XVSSRAN_BU_H : LASX3R_XXX<0x75068000>; +def XVSSRAN_HU_W : LASX3R_XXX<0x75070000>; +def XVSSRAN_WU_D : LASX3R_XXX<0x75078000>; + +def XVSSRLNI_B_H : LASX2RI4_XXXI<0x77484000>; +def XVSSRLNI_H_W : LASX2RI5_XXXI<0x77488000>; +def XVSSRLNI_W_D : LASX2RI6_XXXI<0x77490000>; +def XVSSRLNI_D_Q : LASX2RI7_XXXI<0x774a0000>; +def XVSSRANI_B_H : LASX2RI4_XXXI<0x77604000>; +def XVSSRANI_H_W : LASX2RI5_XXXI<0x77608000>; +def XVSSRANI_W_D : LASX2RI6_XXXI<0x77610000>; +def XVSSRANI_D_Q : LASX2RI7_XXXI<0x77620000>; +def XVSSRLNI_BU_H : LASX2RI4_XXXI<0x774c4000>; +def XVSSRLNI_HU_W : LASX2RI5_XXXI<0x774c8000>; +def XVSSRLNI_WU_D : LASX2RI6_XXXI<0x774d0000>; +def XVSSRLNI_DU_Q : LASX2RI7_XXXI<0x774e0000>; +def XVSSRANI_BU_H : LASX2RI4_XXXI<0x77644000>; +def XVSSRANI_HU_W : LASX2RI5_XXXI<0x77648000>; +def XVSSRANI_WU_D : LASX2RI6_XXXI<0x77650000>; +def XVSSRANI_DU_Q : LASX2RI7_XXXI<0x77660000>; + +def XVSSRLRN_B_H : LASX3R_XXX<0x75008000>; +def XVSSRLRN_H_W : LASX3R_XXX<0x75010000>; +def XVSSRLRN_W_D : LASX3R_XXX<0x75018000>; +def XVSSRARN_B_H : LASX3R_XXX<0x75028000>; +def XVSSRARN_H_W : LASX3R_XXX<0x75030000>; +def XVSSRARN_W_D : LASX3R_XXX<0x75038000>; +def XVSSRLRN_BU_H : LASX3R_XXX<0x75088000>; +def XVSSRLRN_HU_W : LASX3R_XXX<0x75090000>; +def XVSSRLRN_WU_D : LASX3R_XXX<0x75098000>; +def XVSSRARN_BU_H : LASX3R_XXX<0x750a8000>; +def XVSSRARN_HU_W : LASX3R_XXX<0x750b0000>; +def XVSSRARN_WU_D : LASX3R_XXX<0x750b8000>; + +def XVSSRLRNI_B_H : LASX2RI4_XXXI<0x77504000>; +def XVSSRLRNI_H_W : LASX2RI5_XXXI<0x77508000>; +def XVSSRLRNI_W_D : LASX2RI6_XXXI<0x77510000>; +def XVSSRLRNI_D_Q : LASX2RI7_XXXI<0x77520000>; +def XVSSRARNI_B_H : LASX2RI4_XXXI<0x77684000>; +def XVSSRARNI_H_W : LASX2RI5_XXXI<0x77688000>; +def XVSSRARNI_W_D : LASX2RI6_XXXI<0x77690000>; +def XVSSRARNI_D_Q : LASX2RI7_XXXI<0x776a0000>; +def XVSSRLRNI_BU_H : LASX2RI4_XXXI<0x77544000>; +def XVSSRLRNI_HU_W : LASX2RI5_XXXI<0x77548000>; +def XVSSRLRNI_WU_D : LASX2RI6_XXXI<0x77550000>; +def XVSSRLRNI_DU_Q : LASX2RI7_XXXI<0x77560000>; +def XVSSRARNI_BU_H : LASX2RI4_XXXI<0x776c4000>; +def XVSSRARNI_HU_W : LASX2RI5_XXXI<0x776c8000>; +def XVSSRARNI_WU_D : LASX2RI6_XXXI<0x776d0000>; +def XVSSRARNI_DU_Q : LASX2RI7_XXXI<0x776e0000>; + +def XVCLO_B : LASX2R_XX<0x769c0000>; +def XVCLO_H : LASX2R_XX<0x769c0400>; +def XVCLO_W : LASX2R_XX<0x769c0800>; +def XVCLO_D : LASX2R_XX<0x769c0c00>; +def XVCLZ_B : LASX2R_XX<0x769c1000>; +def XVCLZ_H : LASX2R_XX<0x769c1400>; +def XVCLZ_W : LASX2R_XX<0x769c1800>; +def XVCLZ_D : LASX2R_XX<0x769c1c00>; + +def XVPCNT_B : LASX2R_XX<0x769c2000>; +def XVPCNT_H : LASX2R_XX<0x769c2400>; +def XVPCNT_W : LASX2R_XX<0x769c2800>; +def XVPCNT_D : LASX2R_XX<0x769c2c00>; + +def XVBITCLR_B : LASX3R_XXX<0x750c0000>; +def XVBITCLR_H : LASX3R_XXX<0x750c8000>; +def XVBITCLR_W : LASX3R_XXX<0x750d0000>; +def XVBITCLR_D : LASX3R_XXX<0x750d8000>; +def XVBITCLRI_B : LASX2RI3_XXI<0x77102000>; +def XVBITCLRI_H : LASX2RI4_XXI<0x77104000>; +def XVBITCLRI_W : LASX2RI5_XXI<0x77108000>; +def XVBITCLRI_D : LASX2RI6_XXI<0x77110000>; + +def XVBITSET_B : LASX3R_XXX<0x750e0000>; +def XVBITSET_H : LASX3R_XXX<0x750e8000>; +def XVBITSET_W : LASX3R_XXX<0x750f0000>; +def XVBITSET_D : LASX3R_XXX<0x750f8000>; +def XVBITSETI_B : LASX2RI3_XXI<0x77142000>; +def XVBITSETI_H : LASX2RI4_XXI<0x77144000>; +def XVBITSETI_W : LASX2RI5_XXI<0x77148000>; +def XVBITSETI_D : LASX2RI6_XXI<0x77150000>; + +def XVBITREV_B : LASX3R_XXX<0x75100000>; +def XVBITREV_H : LASX3R_XXX<0x75108000>; +def XVBITREV_W : LASX3R_XXX<0x75110000>; +def XVBITREV_D : LASX3R_XXX<0x75118000>; +def XVBITREVI_B : LASX2RI3_XXI<0x77182000>; +def XVBITREVI_H : LASX2RI4_XXI<0x77184000>; +def XVBITREVI_W : LASX2RI5_XXI<0x77188000>; +def XVBITREVI_D : LASX2RI6_XXI<0x77190000>; + +def XVFRSTP_B : LASX3R_XXXX<0x752b0000>; +def XVFRSTP_H : LASX3R_XXXX<0x752b8000>; +def XVFRSTPI_B : LASX2RI5_XXXI<0x769a0000>; +def XVFRSTPI_H : LASX2RI5_XXXI<0x769a8000>; + +def XVFADD_S : LASX3R_XXX<0x75308000>; +def XVFADD_D : LASX3R_XXX<0x75310000>; +def XVFSUB_S : LASX3R_XXX<0x75328000>; +def XVFSUB_D : LASX3R_XXX<0x75330000>; +def XVFMUL_S : LASX3R_XXX<0x75388000>; +def XVFMUL_D : LASX3R_XXX<0x75390000>; +def XVFDIV_S : LASX3R_XXX<0x753a8000>; +def XVFDIV_D : LASX3R_XXX<0x753b0000>; + +def XVFMADD_S : LASX4R_XXXX<0x0a100000>; +def XVFMADD_D : LASX4R_XXXX<0x0a200000>; +def XVFMSUB_S : LASX4R_XXXX<0x0a500000>; +def XVFMSUB_D : LASX4R_XXXX<0x0a600000>; +def XVFNMADD_S : LASX4R_XXXX<0x0a900000>; +def XVFNMADD_D : LASX4R_XXXX<0x0aa00000>; +def XVFNMSUB_S : LASX4R_XXXX<0x0ad00000>; +def XVFNMSUB_D : LASX4R_XXXX<0x0ae00000>; + +def XVFMAX_S : LASX3R_XXX<0x753c8000>; +def XVFMAX_D : LASX3R_XXX<0x753d0000>; +def XVFMIN_S : LASX3R_XXX<0x753e8000>; +def XVFMIN_D : LASX3R_XXX<0x753f0000>; + +def XVFMAXA_S : LASX3R_XXX<0x75408000>; +def XVFMAXA_D : LASX3R_XXX<0x75410000>; +def XVFMINA_S : LASX3R_XXX<0x75428000>; +def XVFMINA_D : LASX3R_XXX<0x75430000>; + +def XVFLOGB_S : LASX2R_XX<0x769cc400>; +def XVFLOGB_D : LASX2R_XX<0x769cc800>; + +def XVFCLASS_S : LASX2R_XX<0x769cd400>; +def XVFCLASS_D : LASX2R_XX<0x769cd800>; + +def XVFSQRT_S : LASX2R_XX<0x769ce400>; +def XVFSQRT_D : LASX2R_XX<0x769ce800>; +def XVFRECIP_S : LASX2R_XX<0x769cf400>; +def XVFRECIP_D : LASX2R_XX<0x769cf800>; +def XVFRSQRT_S : LASX2R_XX<0x769d0400>; +def XVFRSQRT_D : LASX2R_XX<0x769d0800>; + +def XVFCVTL_S_H : LASX2R_XX<0x769de800>; +def XVFCVTH_S_H : LASX2R_XX<0x769dec00>; +def XVFCVTL_D_S : LASX2R_XX<0x769df000>; +def XVFCVTH_D_S : LASX2R_XX<0x769df400>; +def XVFCVT_H_S : LASX3R_XXX<0x75460000>; +def XVFCVT_S_D : LASX3R_XXX<0x75468000>; + +def XVFRINTRNE_S : LASX2R_XX<0x769d7400>; +def XVFRINTRNE_D : LASX2R_XX<0x769d7800>; +def XVFRINTRZ_S : LASX2R_XX<0x769d6400>; +def XVFRINTRZ_D : LASX2R_XX<0x769d6800>; +def XVFRINTRP_S : LASX2R_XX<0x769d5400>; +def XVFRINTRP_D : LASX2R_XX<0x769d5800>; +def XVFRINTRM_S : LASX2R_XX<0x769d4400>; +def XVFRINTRM_D : LASX2R_XX<0x769d4800>; +def XVFRINT_S : LASX2R_XX<0x769d3400>; +def XVFRINT_D : LASX2R_XX<0x769d3800>; + +def XVFTINTRNE_W_S : LASX2R_XX<0x769e5000>; +def XVFTINTRNE_L_D : LASX2R_XX<0x769e5400>; +def XVFTINTRZ_W_S : LASX2R_XX<0x769e4800>; +def XVFTINTRZ_L_D : LASX2R_XX<0x769e4c00>; +def XVFTINTRP_W_S : LASX2R_XX<0x769e4000>; +def XVFTINTRP_L_D : LASX2R_XX<0x769e4400>; +def XVFTINTRM_W_S : LASX2R_XX<0x769e3800>; +def XVFTINTRM_L_D : LASX2R_XX<0x769e3c00>; +def XVFTINT_W_S : LASX2R_XX<0x769e3000>; +def XVFTINT_L_D : LASX2R_XX<0x769e3400>; +def XVFTINTRZ_WU_S : LASX2R_XX<0x769e7000>; +def XVFTINTRZ_LU_D : LASX2R_XX<0x769e7400>; +def XVFTINT_WU_S : LASX2R_XX<0x769e5800>; +def XVFTINT_LU_D : LASX2R_XX<0x769e5c00>; + +def XVFTINTRNE_W_D : LASX3R_XXX<0x754b8000>; +def XVFTINTRZ_W_D : LASX3R_XXX<0x754b0000>; +def XVFTINTRP_W_D : LASX3R_XXX<0x754a8000>; +def XVFTINTRM_W_D : LASX3R_XXX<0x754a0000>; +def XVFTINT_W_D : LASX3R_XXX<0x75498000>; + +def XVFTINTRNEL_L_S : LASX2R_XX<0x769ea000>; +def XVFTINTRNEH_L_S : LASX2R_XX<0x769ea400>; +def XVFTINTRZL_L_S : LASX2R_XX<0x769e9800>; +def XVFTINTRZH_L_S : LASX2R_XX<0x769e9c00>; +def XVFTINTRPL_L_S : LASX2R_XX<0x769e9000>; +def XVFTINTRPH_L_S : LASX2R_XX<0x769e9400>; +def XVFTINTRML_L_S : LASX2R_XX<0x769e8800>; +def XVFTINTRMH_L_S : LASX2R_XX<0x769e8c00>; +def XVFTINTL_L_S : LASX2R_XX<0x769e8000>; +def XVFTINTH_L_S : LASX2R_XX<0x769e8400>; + +def XVFFINT_S_W : LASX2R_XX<0x769e0000>; +def XVFFINT_D_L : LASX2R_XX<0x769e0800>; +def XVFFINT_S_WU : LASX2R_XX<0x769e0400>; +def XVFFINT_D_LU : LASX2R_XX<0x769e0c00>; +def XVFFINTL_D_W : LASX2R_XX<0x769e1000>; +def XVFFINTH_D_W : LASX2R_XX<0x769e1400>; +def XVFFINT_S_L : LASX3R_XXX<0x75480000>; + +def XVSEQ_B : LASX3R_XXX<0x74000000>; +def XVSEQ_H : LASX3R_XXX<0x74008000>; +def XVSEQ_W : LASX3R_XXX<0x74010000>; +def XVSEQ_D : LASX3R_XXX<0x74018000>; +def XVSEQI_B : LASX2RI5_XXI<0x76800000, simm5>; +def XVSEQI_H : LASX2RI5_XXI<0x76808000, simm5>; +def XVSEQI_W : LASX2RI5_XXI<0x76810000, simm5>; +def XVSEQI_D : LASX2RI5_XXI<0x76818000, simm5>; + +def XVSLE_B : LASX3R_XXX<0x74020000>; +def XVSLE_H : LASX3R_XXX<0x74028000>; +def XVSLE_W : LASX3R_XXX<0x74030000>; +def XVSLE_D : LASX3R_XXX<0x74038000>; +def XVSLEI_B : LASX2RI5_XXI<0x76820000, simm5>; +def XVSLEI_H : LASX2RI5_XXI<0x76828000, simm5>; +def XVSLEI_W : LASX2RI5_XXI<0x76830000, simm5>; +def XVSLEI_D : LASX2RI5_XXI<0x76838000, simm5>; + +def XVSLE_BU : LASX3R_XXX<0x74040000>; +def XVSLE_HU : LASX3R_XXX<0x74048000>; +def XVSLE_WU : LASX3R_XXX<0x74050000>; +def XVSLE_DU : LASX3R_XXX<0x74058000>; +def XVSLEI_BU : LASX2RI5_XXI<0x76840000>; +def XVSLEI_HU : LASX2RI5_XXI<0x76848000>; +def XVSLEI_WU : LASX2RI5_XXI<0x76850000>; +def XVSLEI_DU : LASX2RI5_XXI<0x76858000>; + +def XVSLT_B : LASX3R_XXX<0x74060000>; +def XVSLT_H : LASX3R_XXX<0x74068000>; +def XVSLT_W : LASX3R_XXX<0x74070000>; +def XVSLT_D : LASX3R_XXX<0x74078000>; +def XVSLTI_B : LASX2RI5_XXI<0x76860000, simm5>; +def XVSLTI_H : LASX2RI5_XXI<0x76868000, simm5>; +def XVSLTI_W : LASX2RI5_XXI<0x76870000, simm5>; +def XVSLTI_D : LASX2RI5_XXI<0x76878000, simm5>; + +def XVSLT_BU : LASX3R_XXX<0x74080000>; +def XVSLT_HU : LASX3R_XXX<0x74088000>; +def XVSLT_WU : LASX3R_XXX<0x74090000>; +def XVSLT_DU : LASX3R_XXX<0x74098000>; +def XVSLTI_BU : LASX2RI5_XXI<0x76880000>; +def XVSLTI_HU : LASX2RI5_XXI<0x76888000>; +def XVSLTI_WU : LASX2RI5_XXI<0x76890000>; +def XVSLTI_DU : LASX2RI5_XXI<0x76898000>; + +def XVFCMP_CAF_S : LASX3R_XXX<0x0c900000>; +def XVFCMP_SAF_S : LASX3R_XXX<0x0c908000>; +def XVFCMP_CLT_S : LASX3R_XXX<0x0c910000>; +def XVFCMP_SLT_S : LASX3R_XXX<0x0c918000>; +def XVFCMP_CEQ_S : LASX3R_XXX<0x0c920000>; +def XVFCMP_SEQ_S : LASX3R_XXX<0x0c928000>; +def XVFCMP_CLE_S : LASX3R_XXX<0x0c930000>; +def XVFCMP_SLE_S : LASX3R_XXX<0x0c938000>; +def XVFCMP_CUN_S : LASX3R_XXX<0x0c940000>; +def XVFCMP_SUN_S : LASX3R_XXX<0x0c948000>; +def XVFCMP_CULT_S : LASX3R_XXX<0x0c950000>; +def XVFCMP_SULT_S : LASX3R_XXX<0x0c958000>; +def XVFCMP_CUEQ_S : LASX3R_XXX<0x0c960000>; +def XVFCMP_SUEQ_S : LASX3R_XXX<0x0c968000>; +def XVFCMP_CULE_S : LASX3R_XXX<0x0c970000>; +def XVFCMP_SULE_S : LASX3R_XXX<0x0c978000>; +def XVFCMP_CNE_S : LASX3R_XXX<0x0c980000>; +def XVFCMP_SNE_S : LASX3R_XXX<0x0c988000>; +def XVFCMP_COR_S : LASX3R_XXX<0x0c9a0000>; +def XVFCMP_SOR_S : LASX3R_XXX<0x0c9a8000>; +def XVFCMP_CUNE_S : LASX3R_XXX<0x0c9c0000>; +def XVFCMP_SUNE_S : LASX3R_XXX<0x0c9c8000>; + +def XVFCMP_CAF_D : LASX3R_XXX<0x0ca00000>; +def XVFCMP_SAF_D : LASX3R_XXX<0x0ca08000>; +def XVFCMP_CLT_D : LASX3R_XXX<0x0ca10000>; +def XVFCMP_SLT_D : LASX3R_XXX<0x0ca18000>; +def XVFCMP_CEQ_D : LASX3R_XXX<0x0ca20000>; +def XVFCMP_SEQ_D : LASX3R_XXX<0x0ca28000>; +def XVFCMP_CLE_D : LASX3R_XXX<0x0ca30000>; +def XVFCMP_SLE_D : LASX3R_XXX<0x0ca38000>; +def XVFCMP_CUN_D : LASX3R_XXX<0x0ca40000>; +def XVFCMP_SUN_D : LASX3R_XXX<0x0ca48000>; +def XVFCMP_CULT_D : LASX3R_XXX<0x0ca50000>; +def XVFCMP_SULT_D : LASX3R_XXX<0x0ca58000>; +def XVFCMP_CUEQ_D : LASX3R_XXX<0x0ca60000>; +def XVFCMP_SUEQ_D : LASX3R_XXX<0x0ca68000>; +def XVFCMP_CULE_D : LASX3R_XXX<0x0ca70000>; +def XVFCMP_SULE_D : LASX3R_XXX<0x0ca78000>; +def XVFCMP_CNE_D : LASX3R_XXX<0x0ca80000>; +def XVFCMP_SNE_D : LASX3R_XXX<0x0ca88000>; +def XVFCMP_COR_D : LASX3R_XXX<0x0caa0000>; +def XVFCMP_SOR_D : LASX3R_XXX<0x0caa8000>; +def XVFCMP_CUNE_D : LASX3R_XXX<0x0cac0000>; +def XVFCMP_SUNE_D : LASX3R_XXX<0x0cac8000>; + +def XVBITSEL_V : LASX4R_XXXX<0x0d200000>; + +def XVBITSELI_B : LASX2RI8_XXXI<0x77c40000>; + +def XVSETEQZ_V : LASX2R_CX<0x769c9800>; +def XVSETNEZ_V : LASX2R_CX<0x769c9c00>; +def XVSETANYEQZ_B : LASX2R_CX<0x769ca000>; +def XVSETANYEQZ_H : LASX2R_CX<0x769ca400>; +def XVSETANYEQZ_W : LASX2R_CX<0x769ca800>; +def XVSETANYEQZ_D : LASX2R_CX<0x769cac00>; +def XVSETALLNEZ_B : LASX2R_CX<0x769cb000>; +def XVSETALLNEZ_H : LASX2R_CX<0x769cb400>; +def XVSETALLNEZ_W : LASX2R_CX<0x769cb800>; +def XVSETALLNEZ_D : LASX2R_CX<0x769cbc00>; + +def XVINSGR2VR_W : LASX2RI3_XRI<0x76ebc000>; +def XVINSGR2VR_D : LASX2RI2_XRI<0x76ebe000>; +def XVPICKVE2GR_W : LASX2RI3_RXI<0x76efc000>; +def XVPICKVE2GR_D : LASX2RI2_RXI<0x76efe000>; +def XVPICKVE2GR_WU : LASX2RI3_RXI<0x76f3c000>; +def XVPICKVE2GR_DU : LASX2RI2_RXI<0x76f3e000>; + +def XVREPLGR2VR_B : LASX2R_XR<0x769f0000>; +def XVREPLGR2VR_H : LASX2R_XR<0x769f0400>; +def XVREPLGR2VR_W : LASX2R_XR<0x769f0800>; +def XVREPLGR2VR_D : LASX2R_XR<0x769f0c00>; + +def XVREPLVE_B : LASX3R_XXR<0x75220000>; +def XVREPLVE_H : LASX3R_XXR<0x75228000>; +def XVREPLVE_W : LASX3R_XXR<0x75230000>; +def XVREPLVE_D : LASX3R_XXR<0x75238000>; +def XVREPL128VEI_B : LASX2RI4_XXI<0x76f78000>; +def XVREPL128VEI_H : LASX2RI3_XXI<0x76f7c000>; +def XVREPL128VEI_W : LASX2RI2_XXI<0x76f7e000>; +def XVREPL128VEI_D : LASX2RI1_XXI<0x76f7f000>; + +def XVREPLVE0_B : LASX2R_XX<0x77070000>; +def XVREPLVE0_H : LASX2R_XX<0x77078000>; +def XVREPLVE0_W : LASX2R_XX<0x7707c000>; +def XVREPLVE0_D : LASX2R_XX<0x7707e000>; +def XVREPLVE0_Q : LASX2R_XX<0x7707f000>; + +def XVINSVE0_W : LASX2RI3_XXI<0x76ffc000>; +def XVINSVE0_D : LASX2RI2_XXI<0x76ffe000>; + +def XVPICKVE_W : LASX2RI3_XXI<0x7703c000>; +def XVPICKVE_D : LASX2RI2_XXI<0x7703e000>; + +def XVBSLL_V : LASX2RI5_XXI<0x768e0000>; +def XVBSRL_V : LASX2RI5_XXI<0x768e8000>; + +def XVPACKEV_B : LASX3R_XXX<0x75160000>; +def XVPACKEV_H : LASX3R_XXX<0x75168000>; +def XVPACKEV_W : LASX3R_XXX<0x75170000>; +def XVPACKEV_D : LASX3R_XXX<0x75178000>; +def XVPACKOD_B : LASX3R_XXX<0x75180000>; +def XVPACKOD_H : LASX3R_XXX<0x75188000>; +def XVPACKOD_W : LASX3R_XXX<0x75190000>; +def XVPACKOD_D : LASX3R_XXX<0x75198000>; + +def XVPICKEV_B : LASX3R_XXX<0x751e0000>; +def XVPICKEV_H : LASX3R_XXX<0x751e8000>; +def XVPICKEV_W : LASX3R_XXX<0x751f0000>; +def XVPICKEV_D : LASX3R_XXX<0x751f8000>; +def XVPICKOD_B : LASX3R_XXX<0x75200000>; +def XVPICKOD_H : LASX3R_XXX<0x75208000>; +def XVPICKOD_W : LASX3R_XXX<0x75210000>; +def XVPICKOD_D : LASX3R_XXX<0x75218000>; + +def XVILVL_B : LASX3R_XXX<0x751a0000>; +def XVILVL_H : LASX3R_XXX<0x751a8000>; +def XVILVL_W : LASX3R_XXX<0x751b0000>; +def XVILVL_D : LASX3R_XXX<0x751b8000>; +def XVILVH_B : LASX3R_XXX<0x751c0000>; +def XVILVH_H : LASX3R_XXX<0x751c8000>; +def XVILVH_W : LASX3R_XXX<0x751d0000>; +def XVILVH_D : LASX3R_XXX<0x751d8000>; + +def XVSHUF_B : LASX4R_XXXX<0x0d600000>; + +def XVSHUF_H : LASX3R_XXX<0x757a8000>; +def XVSHUF_W : LASX3R_XXX<0x757b0000>; +def XVSHUF_D : LASX3R_XXX<0x757b8000>; + +def XVPERM_W : LASX3R_XXX<0x757d0000>; + +def XVSHUF4I_B : LASX2RI8_XXI<0x77900000>; +def XVSHUF4I_H : LASX2RI8_XXI<0x77940000>; +def XVSHUF4I_W : LASX2RI8_XXI<0x77980000>; +def XVSHUF4I_D : LASX2RI8_XXI<0x779c0000>; + +def XVPERMI_W : LASX2RI8_XXI<0x77e40000>; +def XVPERMI_D : LASX2RI8_XXI<0x77e80000>; +def XVPERMI_Q : LASX2RI8_XXI<0x77ec0000>; + +def XVEXTRINS_D : LASX2RI8_XXI<0x77800000>; +def XVEXTRINS_W : LASX2RI8_XXI<0x77840000>; +def XVEXTRINS_H : LASX2RI8_XXI<0x77880000>; +def XVEXTRINS_B : LASX2RI8_XXI<0x778c0000>; + +let mayLoad = 1 in { +def XVLD : LASX2RI12_XRI<0x2c800000>; +def XVLDX : LASX3R_XRR<0x38480000>; + +def XVLDREPL_B : LASX2RI12_XRI<0x32800000>; +def XVLDREPL_H : LASX2RI11_XRI<0x32400000>; +def XVLDREPL_W : LASX2RI10_XRI<0x32200000>; +def XVLDREPL_D : LASX2RI9_XRI<0x32100000>; +} // mayLoad = 1 + +let mayStore = 1 in { +def XVST : LASX2RI12_XRI<0x2cc00000>; +def XVSTX : LASX3R_XRR<0x384c0000>; + +def XVSTELM_B : LASX2RI8I5_XRII<0x33800000>; +def XVSTELM_H : LASX2RI8I4_XRII<0x33400000, simm8_lsl1>; +def XVSTELM_W : LASX2RI8I3_XRII<0x33200000, simm8_lsl2>; +def XVSTELM_D : LASX2RI8I2_XRII<0x33100000, simm8_lsl3>; +} // mayStore = 1 + +} // Predicates = [HasExtLASX] + +// Pseudo-instructions + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, + isAsmParserOnly = 1 in { +def PseudoXVREPLI_B : Pseudo<(outs LASX256:$xd), (ins simm10:$imm), [], + "xvrepli.b", "$xd, $imm">; +def PseudoXVREPLI_H : Pseudo<(outs LASX256:$xd), (ins simm10:$imm), [], + "xvrepli.h", "$xd, $imm">; +def PseudoXVREPLI_W : Pseudo<(outs LASX256:$xd), (ins simm10:$imm), [], + "xvrepli.w", "$xd, $imm">; +def PseudoXVREPLI_D : Pseudo<(outs LASX256:$xd), (ins simm10:$imm), [], + "xvrepli.d", "$xd, $imm">; +} diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp @@ -279,14 +279,18 @@ int64_t Imm = MI.getOperand(1).getImm() & 0x3FF; switch (MI.getOpcode()) { case LoongArch::PseudoVREPLI_B: + case LoongArch::PseudoXVREPLI_B: break; case LoongArch::PseudoVREPLI_H: + case LoongArch::PseudoXVREPLI_H: Imm |= 0x400; break; case LoongArch::PseudoVREPLI_W: + case LoongArch::PseudoXVREPLI_W: Imm |= 0x800; break; case LoongArch::PseudoVREPLI_D: + case LoongArch::PseudoXVREPLI_D: Imm |= 0xC00; break; } @@ -310,6 +314,11 @@ case LoongArch::PseudoVREPLI_W: case LoongArch::PseudoVREPLI_D: return expandToVectorLDI(MI, CB, Fixups, STI); + case LoongArch::PseudoXVREPLI_B: + case LoongArch::PseudoXVREPLI_H: + case LoongArch::PseudoXVREPLI_W: + case LoongArch::PseudoXVREPLI_D: + return expandToVectorLDI(MI, OS, Fixups, STI); } switch (Size) {