diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
--- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
+++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
@@ -31,6 +31,7 @@
   uint16_t Pseudo;
   uint16_t BaseInstr;
   uint8_t VLMul;
+  uint8_t SEW;
 };
 
 #define GET_RISCVVInversePseudosTable_IMPL
@@ -100,7 +101,7 @@
     if (I->getDesc() == RISCVLMULInstrument::DESC_NAME) {
       uint8_t LMUL = static_cast<RISCVLMULInstrument *>(I)->getLMUL();
       const RISCVVInversePseudosTable::PseudoInfo *RVV =
-          RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL);
+          RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0);
       // Not a RVV instr
       if (!RVV) {
         LLVM_DEBUG(
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -504,9 +504,29 @@
   bits<8> V = val;
 }
 def InvalidIndex : CONST8b<0x80>;
+
+
+/// This class maps sew onto a bits<3> field so that SEW can be represented
+/// in as few bits as possible. This mapping does not come from the RVV spec
+/// and is an implementation defined mapping.
+class SEWTo3BitSEW<int sew> {
+  bits<3> s = !cond(
+    !eq(sew, 0) : 0b000,
+    !eq(sew, 8) : 0b001,
+    !eq(sew, 16) : 0b010,
+    !eq(sew, 32) : 0b011,
+    !eq(sew, 64) : 0b100
+  );
+}
+
 class RISCVVPseudo {
   Pseudo Pseudo = !cast<Pseudo>(NAME); // Used as a key.
   Instruction BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+
+  // SEW = 0 is used to denote that the RVInst is not SEW specific (Unknown).
+  // Unknown=0b000, E8 = 0b001, E16=0b010, E32=0b011, E64=0b100. This mapping
+  // does not come from the RVV spec and is an implementation defined mapping.
+  bits<3> SEW = 0;
 }
 
 // The actual table.
@@ -522,8 +542,8 @@
 def RISCVVInversePseudosTable : GenericTable {
   let FilterClass = "RISCVVPseudo";
   let CppTypeName = "PseudoInfo";
-  let Fields = [ "Pseudo", "BaseInstr", "VLMul" ];
-  let PrimaryKey = [ "BaseInstr", "VLMul" ];
+  let Fields = [ "Pseudo", "BaseInstr", "VLMul", "SEW"];
+  let PrimaryKey = [ "BaseInstr", "VLMul", "SEW"];
   let PrimaryKeyName = "getBaseInfo";
   let PrimaryKeyEarlyOut = true;
 }
@@ -750,10 +770,11 @@
                         1 : a#separator#b));
 }
 
-class VPseudo<Instruction instr, LMULInfo m, dag outs, dag ins> :
+class VPseudo<Instruction instr, LMULInfo m, dag outs, dag ins, int sew = 0> :
       Pseudo<outs, ins, []>, RISCVVPseudo {
   let BaseInstr = instr;
   let VLMul = m.value;
+  let SEW = SEWTo3BitSEW<sew>.s;
 }
 
 class GetVTypePredicates<VTypeInfo vti> {
@@ -1701,7 +1722,7 @@
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         def "E" # eew # "_V_" # LInfo :
           VPseudoUSLoadNoMask<vreg, eew>,
           VLESched<LInfo>;
@@ -1722,7 +1743,7 @@
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         def "E" # eew # "FF_V_" # LInfo:
           VPseudoUSLoadFFNoMask<vreg, eew>,
           VLFSched<LInfo>;
@@ -1754,7 +1775,7 @@
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         def "E" # eew # "_V_" # LInfo : VPseudoSLoadNoMask<vreg, eew>,
                                         VLSSched<eew, LInfo>;
         def "E" # eew # "_V_" # LInfo # "_TU": VPseudoSLoadNoMaskTU<vreg, eew>,
@@ -1807,7 +1828,7 @@
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         def "E" # eew # "_V_" # LInfo : VPseudoUSStoreNoMask<vreg, eew>,
                                         VSESched<LInfo>;
         def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSStoreMask<vreg, eew>,
@@ -1833,7 +1854,7 @@
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         def "E" # eew # "_V_" # LInfo : VPseudoSStoreNoMask<vreg, eew>,
                                         VSSSched<eew, LInfo>;
         def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSStoreMask<vreg, eew>,
@@ -1977,6 +1998,7 @@
         defvar WriteVCompressV_MX_E = !cast<SchedWrite>("WriteVCompressV" # suffix);
         defvar ReadVCompressV_MX_E = !cast<SchedRead>("ReadVCompressV" # suffix);
 
+        let SEW = SEWTo3BitSEW<e>.s in
         def _VM # suffix : VPseudoUnaryAnyMask<m.vrclass, m.vrclass>,
                            Sched<[WriteVCompressV_MX_E, ReadVCompressV_MX_E, ReadVCompressV_MX_E]>;
       }
@@ -1989,7 +2011,7 @@
                          LMULInfo MInfo,
                          string Constraint = "",
                          int sew = 0> {
-  let VLMul = MInfo.value in {
+  let VLMul = MInfo.value, SEW=SEWTo3BitSEW<sew>.s in {
     defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
     def suffix : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
                                      Constraint>;
@@ -2007,7 +2029,7 @@
                                      LMULInfo MInfo,
                                      string Constraint = "",
                                      int sew = 0> {
-  let VLMul = MInfo.value in {
+  let VLMul = MInfo.value, SEW=SEWTo3BitSEW<sew>.s in {
     defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
     def suffix : VPseudoBinaryNoMaskRoundingMode<RetClass, Op1Class, Op2Class,
                                                  Constraint>;
@@ -2044,7 +2066,7 @@
                              LMULInfo emul,
                              string Constraint = "",
                              int sew = 0> {
-  let VLMul = lmul.value in {
+  let VLMul = lmul.value, SEW=SEWTo3BitSEW<sew>.s in {
     defvar suffix = !if(sew, "_" # lmul.MX # "_E" # sew, "_" # lmul.MX);
     def suffix # "_" # emul.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
                                                             Constraint>;
@@ -2387,16 +2409,18 @@
         defvar WriteVFSqrtV_MX_E = !cast<SchedWrite>("WriteVFSqrtV" # suffix);
         defvar ReadVFSqrtV_MX_E = !cast<SchedRead>("ReadVFSqrtV" # suffix);
 
-        def "_V" # suffix : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
-                            Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
-                                   ReadVMask]>;
-        def "_V" # suffix # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.vrclass>,
-                                   Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
-                                          ReadVMask]>;
-        def "_V" # suffix # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
-                                      RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
-                                      Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
-                                             ReadVMask]>;
+        let SEW = SEWTo3BitSEW<e>.s in {
+          def "_V" # suffix : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
+                              Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
+                                     ReadVMask]>;
+          def "_V" # suffix # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.vrclass>,
+                                     Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
+                                            ReadVMask]>;
+          def "_V" # suffix # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
+                                        RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
+                                        Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
+                                               ReadVMask]>;
+        }
       }
   }
 }
@@ -3765,7 +3789,7 @@
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         foreach nf = NFSet<lmul>.L in {
           defvar vreg = SegRegClass<lmul, nf>.RC;
           def nf # "E" # eew # "_V_" # LInfo :
@@ -3784,7 +3808,7 @@
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         foreach nf = NFSet<lmul>.L in {
           defvar vreg = SegRegClass<lmul, nf>.RC;
           def nf # "E" # eew # "FF_V_" # LInfo :
@@ -3803,7 +3827,7 @@
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         foreach nf = NFSet<lmul>.L in {
           defvar vreg = SegRegClass<lmul, nf>.RC;
           def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegLoadNoMask<vreg, eew, nf>,
@@ -3859,7 +3883,7 @@
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         foreach nf = NFSet<lmul>.L in {
           defvar vreg = SegRegClass<lmul, nf>.RC;
           def nf # "E" # eew # "_V_" # LInfo : VPseudoUSSegStoreNoMask<vreg, eew, nf>,
@@ -3876,7 +3900,7 @@
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         foreach nf = NFSet<lmul>.L in {
           defvar vreg = SegRegClass<lmul, nf>.RC;
           def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegStoreNoMask<vreg, eew, nf>,