diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -858,9 +858,7 @@ return Kind == Expression; } - bool isSoppBrTarget() const { - return isExpr() || isImm(); - } + bool isSOPPBrTarget() const { return isExpr() || isImm(); } bool isSWaitCnt() const; bool isDepCtr() const; @@ -971,8 +969,6 @@ void addRegOrImmOperands(MCInst &Inst, unsigned N) const { if (isRegKind()) addRegOperands(Inst, N); - else if (isExpr()) - Inst.addOperand(MCOperand::createExpr(Expr)); else addImmOperands(Inst, N); } @@ -1014,15 +1010,6 @@ addRegWithInputModsOperands(Inst, N); } - void addSoppBrTargetOperands(MCInst &Inst, unsigned N) const { - if (isImm()) - addImmOperands(Inst, N); - else { - assert(isExpr()); - Inst.addOperand(MCOperand::createExpr(Expr)); - } - } - static void printImmTy(raw_ostream& OS, ImmTy Type) { switch (Type) { case ImmTyNone: OS << "None"; break; @@ -1726,7 +1713,7 @@ OperandMatchResultTy parseSendMsg(OperandVector &Operands); OperandMatchResultTy parseInterpSlot(OperandVector &Operands); OperandMatchResultTy parseInterpAttr(OperandVector &Operands); - OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands); + OperandMatchResultTy parseSOPPBrTarget(OperandVector &Operands); OperandMatchResultTy parseBoolReg(OperandVector &Operands); bool parseSwizzleOperand(int64_t &Op, @@ -2084,6 +2071,11 @@ } void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const { + if (isExpr()) { + Inst.addOperand(MCOperand::createExpr(Expr)); + return; + } + if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()), Inst.getNumOperands())) { addLiteralImmOperand(Inst, Imm.Val, @@ -7674,7 +7666,7 @@ //===----------------------------------------------------------------------===// OperandMatchResultTy -AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) { +AMDGPUAsmParser::parseSOPPBrTarget(OperandVector &Operands) { // Make sure we are not parsing something // that looks like a label or an expression but is not. @@ -9052,8 +9044,8 @@ return Operand.isSSrcB32() ? Match_Success : Match_InvalidOperand; case MCK_SSrcF32: return Operand.isSSrcF32() ? Match_Success : Match_InvalidOperand; - case MCK_SoppBrTarget: - return Operand.isSoppBrTarget() ? Match_Success : Match_InvalidOperand; + case MCK_SOPPBrTarget: + return Operand.isSOPPBrTarget() ? Match_Success : Match_InvalidOperand; case MCK_VReg32OrOff: return Operand.isVReg32OrOff() ? Match_Success : Match_InvalidOperand; case MCK_InterpSlot: diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -74,7 +74,7 @@ return OpIdx; } -static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, +static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -921,16 +921,11 @@ // Custom Operands //===----------------------------------------------------------------------===// -def SoppBrTarget : AsmOperandClass { - let Name = "SoppBrTarget"; - let ParserMethod = "parseSOppBrTarget"; -} - -def sopp_brtarget : Operand { +def SOPPBrTarget : CustomOperand { + let PrintMethod = "printOperand"; let EncoderMethod = "getSOPPBrEncoding"; - let DecoderMethod = "decodeSoppBrTarget"; + let DecoderMethod = "decodeSOPPBrTarget"; let OperandType = "OPERAND_PCREL"; - let ParserMatchClass = SoppBrTarget; } def si_ga : Operand; diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -500,7 +500,7 @@ // Branch on undef scc. Used to avoid intermediate copy from // IMPLICIT_DEF to SCC. -def SI_BR_UNDEF : SPseudoInstSI <(outs), (ins sopp_brtarget:$simm16)> { +def SI_BR_UNDEF : SPseudoInstSI <(outs), (ins SOPPBrTarget:$simm16)> { let isTerminator = 1; let usesCustomInserter = 1; let isBranch = 1; diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -784,7 +784,7 @@ class SOPK_32_BR pattern=[]> : SOPK_Pseudo < opName, (outs), - (ins sopp_brtarget:$simm16, SReg_32:$sdst), + (ins SOPPBrTarget:$simm16, SReg_32:$sdst), "$sdst, $simm16", pattern> { let Defs = [EXEC]; @@ -864,7 +864,7 @@ let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in def S_CBRANCH_I_FORK : SOPK_Pseudo < "s_cbranch_i_fork", - (outs), (ins SReg_64:$sdst, sopp_brtarget:$simm16), + (outs), (ins SReg_64:$sdst, SOPPBrTarget:$simm16), "$sdst, $simm16" >; @@ -942,7 +942,7 @@ def S_CALL_B64 : SOPK_Pseudo< "s_call_b64", (outs SReg_64:$sdst), - (ins sopp_brtarget:$simm16), + (ins SOPPBrTarget:$simm16), "$sdst, $simm16"> { let isCall = 1; } @@ -1195,60 +1195,60 @@ let isBranch = 1, SchedRW = [WriteBranch] in { let isBarrier = 1 in { defm S_BRANCH : SOPP_With_Relaxation< - "s_branch" , (ins sopp_brtarget:$simm16), "$simm16", + "s_branch" , (ins SOPPBrTarget:$simm16), "$simm16", [(br bb:$simm16)]>; } let Uses = [SCC] in { defm S_CBRANCH_SCC0 : SOPP_With_Relaxation< - "s_cbranch_scc0" , (ins sopp_brtarget:$simm16), + "s_cbranch_scc0" , (ins SOPPBrTarget:$simm16), "$simm16" >; defm S_CBRANCH_SCC1 : SOPP_With_Relaxation < - "s_cbranch_scc1" , (ins sopp_brtarget:$simm16), + "s_cbranch_scc1" , (ins SOPPBrTarget:$simm16), "$simm16" >; } // End Uses = [SCC] let Uses = [VCC] in { defm S_CBRANCH_VCCZ : SOPP_With_Relaxation < - "s_cbranch_vccz" , (ins sopp_brtarget:$simm16), + "s_cbranch_vccz" , (ins SOPPBrTarget:$simm16), "$simm16" >; defm S_CBRANCH_VCCNZ : SOPP_With_Relaxation < - "s_cbranch_vccnz" , (ins sopp_brtarget:$simm16), + "s_cbranch_vccnz" , (ins SOPPBrTarget:$simm16), "$simm16" >; } // End Uses = [VCC] let Uses = [EXEC] in { defm S_CBRANCH_EXECZ : SOPP_With_Relaxation < - "s_cbranch_execz" , (ins sopp_brtarget:$simm16), + "s_cbranch_execz" , (ins SOPPBrTarget:$simm16), "$simm16" >; defm S_CBRANCH_EXECNZ : SOPP_With_Relaxation < - "s_cbranch_execnz" , (ins sopp_brtarget:$simm16), + "s_cbranch_execnz" , (ins SOPPBrTarget:$simm16), "$simm16" >; } // End Uses = [EXEC] defm S_CBRANCH_CDBGSYS : SOPP_With_Relaxation < - "s_cbranch_cdbgsys" , (ins sopp_brtarget:$simm16), + "s_cbranch_cdbgsys" , (ins SOPPBrTarget:$simm16), "$simm16" >; defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_With_Relaxation < - "s_cbranch_cdbgsys_and_user" , (ins sopp_brtarget:$simm16), + "s_cbranch_cdbgsys_and_user" , (ins SOPPBrTarget:$simm16), "$simm16" >; defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_With_Relaxation < - "s_cbranch_cdbgsys_or_user" , (ins sopp_brtarget:$simm16), + "s_cbranch_cdbgsys_or_user" , (ins SOPPBrTarget:$simm16), "$simm16" >; defm S_CBRANCH_CDBGUSER : SOPP_With_Relaxation < - "s_cbranch_cdbguser" , (ins sopp_brtarget:$simm16), + "s_cbranch_cdbguser" , (ins SOPPBrTarget:$simm16), "$simm16" >;