diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -864,7 +864,7 @@ bool isSWaitCnt() const; bool isDepCtr() const; - bool isSDelayAlu() const; + bool isSDelayALU() const; bool isHwreg() const; bool isSendMsg() const; bool isSwizzle() const; @@ -1602,14 +1602,14 @@ void cvtExp(MCInst &Inst, const OperandVector &Operands); bool parseCnt(int64_t &IntVal); - OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands); + OperandMatchResultTy parseSWaitCnt(OperandVector &Operands); bool parseDepCtr(int64_t &IntVal, unsigned &Mask); void depCtrError(SMLoc Loc, int ErrorId, StringRef DepCtrName); - OperandMatchResultTy parseDepCtrOps(OperandVector &Operands); + OperandMatchResultTy parseDepCtr(OperandVector &Operands); bool parseDelay(int64_t &Delay); - OperandMatchResultTy parseSDelayAluOps(OperandVector &Operands); + OperandMatchResultTy parseSDelayALU(OperandVector &Operands); OperandMatchResultTy parseHwreg(OperandVector &Operands); @@ -1723,7 +1723,7 @@ unsigned MCK); OperandMatchResultTy parseExpTgt(OperandVector &Operands); - OperandMatchResultTy parseSendMsgOp(OperandVector &Operands); + OperandMatchResultTy parseSendMsg(OperandVector &Operands); OperandMatchResultTy parseInterpSlot(OperandVector &Operands); OperandMatchResultTy parseInterpAttr(OperandVector &Operands); OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands); @@ -1738,7 +1738,7 @@ const unsigned MinVal, const unsigned MaxVal, const StringRef ErrMsg); - OperandMatchResultTy parseSwizzleOp(OperandVector &Operands); + OperandMatchResultTy parseSwizzle(OperandVector &Operands); bool parseSwizzleOffset(int64_t &Imm); bool parseSwizzleMacro(int64_t &Imm); bool parseSwizzleQuadPerm(int64_t &Imm); @@ -6588,8 +6588,7 @@ return true; } -OperandMatchResultTy -AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) { +OperandMatchResultTy AMDGPUAsmParser::parseSWaitCnt(OperandVector &Operands) { AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); int64_t Waitcnt = getWaitcntBitMask(ISA); SMLoc S = getLoc(); @@ -6670,8 +6669,7 @@ return true; } -OperandMatchResultTy -AMDGPUAsmParser::parseSDelayAluOps(OperandVector &Operands) { +OperandMatchResultTy AMDGPUAsmParser::parseSDelayALU(OperandVector &Operands) { int64_t Delay = 0; SMLoc S = getLoc(); @@ -6694,7 +6692,7 @@ return isImm(); } -bool AMDGPUOperand::isSDelayAlu() const { return isImm(); } +bool AMDGPUOperand::isSDelayALU() const { return isImm(); } //===----------------------------------------------------------------------===// // DepCtr @@ -6758,7 +6756,7 @@ return true; } -OperandMatchResultTy AMDGPUAsmParser::parseDepCtrOps(OperandVector &Operands) { +OperandMatchResultTy AMDGPUAsmParser::parseDepCtr(OperandVector &Operands) { using namespace llvm::AMDGPU::DepCtr; int64_t DepCtr = getDefaultDepCtrEncoding(getSTI()); @@ -6972,8 +6970,7 @@ return true; } -OperandMatchResultTy -AMDGPUAsmParser::parseSendMsgOp(OperandVector &Operands) { +OperandMatchResultTy AMDGPUAsmParser::parseSendMsg(OperandVector &Operands) { using namespace llvm::AMDGPU::SendMsg; int64_t ImmVal = 0; @@ -7567,8 +7564,7 @@ return false; } -OperandMatchResultTy -AMDGPUAsmParser::parseSwizzleOp(OperandVector &Operands) { +OperandMatchResultTy AMDGPUAsmParser::parseSwizzle(OperandVector &Operands) { SMLoc S = getLoc(); int64_t Imm = 0; diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td --- a/llvm/lib/Target/AMDGPU/DSInstructions.td +++ b/llvm/lib/Target/AMDGPU/DSInstructions.td @@ -631,7 +631,7 @@ } // End SubtargetPredicate = HasDsSrc2Insts let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in { -def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>; +def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, Swizzle>; } let mayStore = 0 in { diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h @@ -165,8 +165,8 @@ void printInterpAttrChan(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printVGPRIndexMode(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); + void printGPRIdxMode(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); void printMemOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printBLGP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, @@ -240,11 +240,11 @@ raw_ostream &O); void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printWaitFlag(const MCInst *MI, unsigned OpNo, + void printSWaitCnt(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printDepCtr(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printDelayFlag(const MCInst *MI, unsigned OpNo, + void printSDelayALU(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -1277,9 +1277,9 @@ O << '.' << "xyzw"[Chan & 0x3]; } -void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { +void AMDGPUInstPrinter::printGPRIdxMode(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { using namespace llvm::AMDGPU::VGPRIndexMode; unsigned Val = MI->getOperand(OpNo).getImm(); @@ -1486,7 +1486,7 @@ } } -void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo, +void AMDGPUInstPrinter::printSWaitCnt(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU()); @@ -1548,7 +1548,7 @@ } } -void AMDGPUInstPrinter::printDelayFlag(const MCInst *MI, unsigned OpNo, +void AMDGPUInstPrinter::printSDelayALU(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { const char *BadInstId = "/* invalid instid value */"; diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -943,72 +943,22 @@ def InterpAttrChan : ImmOperand; -def SendMsgMatchClass : AsmOperandClass { - let Name = "SendMsg"; - let PredicateMethod = "isSendMsg"; - let ParserMethod = "parseSendMsgOp"; - let RenderMethod = "addImmOperands"; -} - -def SwizzleMatchClass : AsmOperandClass { - let Name = "Swizzle"; - let PredicateMethod = "isSwizzle"; - let ParserMethod = "parseSwizzleOp"; - let RenderMethod = "addImmOperands"; - let IsOptional = 1; -} - -def SWaitMatchClass : AsmOperandClass { - let Name = "SWaitCnt"; - let RenderMethod = "addImmOperands"; - let ParserMethod = "parseSWaitCntOps"; -} - -def DepCtrMatchClass : AsmOperandClass { - let Name = "DepCtr"; - let RenderMethod = "addImmOperands"; - let ParserMethod = "parseDepCtrOps"; -} - -def SDelayMatchClass : AsmOperandClass { - let Name = "SDelayAlu"; - let RenderMethod = "addImmOperands"; - let ParserMethod = "parseSDelayAluOps"; -} - def VReg32OrOffClass : AsmOperandClass { let Name = "VReg32OrOff"; let ParserMethod = "parseVReg32OrOff"; } -let OperandType = "OPERAND_IMMEDIATE" in { -def SendMsgImm : Operand { - let PrintMethod = "printSendMsg"; - let ParserMatchClass = SendMsgMatchClass; -} +def SendMsg : CustomOperand; -def SwizzleImm : Operand { - let PrintMethod = "printSwizzle"; - let ParserMatchClass = SwizzleMatchClass; -} +def Swizzle : CustomOperand; def Endpgm : CustomOperand; -def WAIT_FLAG : Operand { - let ParserMatchClass = SWaitMatchClass; - let PrintMethod = "printWaitFlag"; -} +def SWaitCnt : CustomOperand; -def DepCtrImm : Operand { - let ParserMatchClass = DepCtrMatchClass; - let PrintMethod = "printDepCtr"; -} +def DepCtr : CustomOperand; -def DELAY_FLAG : Operand { - let ParserMatchClass = SDelayMatchClass; - let PrintMethod = "printDelayFlag"; -} -} // End OperandType = "OPERAND_IMMEDIATE" +def SDelayALU : CustomOperand; include "SIInstrFormats.td" include "VIInstrFormats.td" diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -6,18 +6,7 @@ // //===----------------------------------------------------------------------===// -def GPRIdxModeMatchClass : AsmOperandClass { - let Name = "GPRIdxMode"; - let PredicateMethod = "isGPRIdxMode"; - let ParserMethod = "parseGPRIdxMode"; - let RenderMethod = "addImmOperands"; -} - -def GPRIdxMode : Operand { - let PrintMethod = "printVGPRIndexMode"; - let ParserMatchClass = GPRIdxModeMatchClass; - let OperandType = "OPERAND_IMMEDIATE"; -} +def GPRIdxMode : CustomOperand; class SOP_Pseudo pattern=[]> : @@ -402,11 +391,11 @@ // For s_sendmsg_rtn_* the src0 field encodes the message type directly; it // is not an SGPR number. def S_SENDMSG_RTN_B32 : SOP1_Pseudo< - "s_sendmsg_rtn_b32", (outs SReg_32:$sdst), (ins SendMsgImm:$src0), + "s_sendmsg_rtn_b32", (outs SReg_32:$sdst), (ins SendMsg:$src0), "$sdst, $src0", [(set i32:$sdst, (int_amdgcn_s_sendmsg_rtn timm:$src0))] >; def S_SENDMSG_RTN_B64 : SOP1_Pseudo< - "s_sendmsg_rtn_b64", (outs SReg_64:$sdst), (ins SendMsgImm:$src0), + "s_sendmsg_rtn_b64", (outs SReg_64:$sdst), (ins SendMsg:$src0), "$sdst, $src0", [(set i64:$sdst, (int_amdgcn_s_sendmsg_rtn timm:$src0))] >; } @@ -1284,7 +1273,7 @@ } let hasSideEffects = 1 in -def S_WAITCNT : SOPP_Pseudo <"s_waitcnt" , (ins WAIT_FLAG:$simm16), "$simm16", +def S_WAITCNT : SOPP_Pseudo <"s_waitcnt" , (ins SWaitCnt:$simm16), "$simm16", [(int_amdgcn_s_waitcnt timm:$simm16)]>; def S_SETHALT : SOPP_Pseudo <"s_sethalt" , (ins i32imm:$simm16), "$simm16", [(int_amdgcn_s_sethalt timm:$simm16)]>; @@ -1305,12 +1294,12 @@ } let Uses = [EXEC, M0] in { -def S_SENDMSG : SOPP_Pseudo <"s_sendmsg" , (ins SendMsgImm:$simm16), "$simm16", +def S_SENDMSG : SOPP_Pseudo <"s_sendmsg" , (ins SendMsg:$simm16), "$simm16", [(int_amdgcn_s_sendmsg (i32 timm:$simm16), M0)]> { let hasSideEffects = 1; } -def S_SENDMSGHALT : SOPP_Pseudo <"s_sendmsghalt" , (ins SendMsgImm:$simm16), "$simm16", +def S_SENDMSGHALT : SOPP_Pseudo <"s_sendmsghalt" , (ins SendMsg:$simm16), "$simm16", [(int_amdgcn_s_sendmsghalt (i32 timm:$simm16), M0)]> { let hasSideEffects = 1; } @@ -1367,7 +1356,7 @@ let fixed_imm = 1; } def S_WAITCNT_DEPCTR : - SOPP_Pseudo <"s_waitcnt_depctr" , (ins DepCtrImm:$simm16), "$simm16">; + SOPP_Pseudo <"s_waitcnt_depctr" , (ins DepCtr:$simm16), "$simm16">; let hasSideEffects = 0, Uses = [MODE], Defs = [MODE] in { def S_ROUND_MODE : @@ -1386,7 +1375,7 @@ "$simm16"> { let hasSideEffects = 1; } - def S_DELAY_ALU : SOPP_Pseudo<"s_delay_alu", (ins DELAY_FLAG:$simm16), + def S_DELAY_ALU : SOPP_Pseudo<"s_delay_alu", (ins SDelayALU:$simm16), "$simm16">; } // End SubtargetPredicate = isGFX11Plus