Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3956,6 +3956,16 @@
     }
     break;
   }
+  case ISD::GlobalAddress:
+  case ISD::TargetGlobalAddress: {
+    const auto *GlobalNode = cast<GlobalAddressSDNode>(Op);
+    if (std::optional<ConstantRange> CR = GlobalNode->getGlobal()->getAbsoluteSymbolRange())
+      Known = CR->toKnownBits();
+
+    if (const auto *GO = dyn_cast<GlobalObject>(GlobalNode->getGlobal()))
+      Known.Zero.setLowBits(Log2(GO->getAlign().valueOrOne()));
+    break;
+  }
   case ISD::FrameIndex:
   case ISD::TargetFrameIndex:
     TLI->computeKnownBitsForFrameIndex(cast<FrameIndexSDNode>(Op)->getIndex(),
Index: llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
+++ llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
@@ -9,7 +9,7 @@
 
 ; GCN-LABEL: {{^}}no_reorder_flat_load_local_store_local_load:
 ; GCN: flat_load_dwordx4
-; GCN: ds_write_b128 {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:512
+; GCN-DAG: ds_write2_b64 {{v[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:64 offset1:65
 ; GCN: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:129 offset1:130
 define amdgpu_kernel void @no_reorder_flat_load_local_store_local_load(ptr addrspace(3) %out, ptr %fptr) #0 {
   %ptr1 = getelementptr %struct.lds, ptr addrspace(3) @stored_lds_struct, i32 0, i32 1