Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5600,8 +5600,7 @@
     if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
       return getNode(OpOpcode, DL, VT, Operand.getOperand(0));
     if (OpOpcode == ISD::UNDEF)
-      // sext(undef) = 0, because the top bits will all be the same.
-      return getConstant(0, DL, VT);
+      return getUNDEF(VT);
     break;
   case ISD::ZERO_EXTEND:
     assert(VT.isInteger() && Operand.getValueType().isInteger() &&
Index: llvm/test/CodeGen/AArch64/abd-combine.ll
===================================================================
--- llvm/test/CodeGen/AArch64/abd-combine.ll
+++ llvm/test/CodeGen/AArch64/abd-combine.ll
@@ -260,7 +260,7 @@
 define <8 x i16> @abdu_i_const_onehigh() {
 ; CHECK-LABEL: abdu_i_const_onehigh:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #32765
+; CHECK-NEXT:    mov w8, #32765 // =0x7ffd
 ; CHECK-NEXT:    dup v0.8h, w8
 ; CHECK-NEXT:    ret
   %result = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
@@ -405,11 +405,7 @@
 define <8 x i16> @abds_undef(<8 x i16> %src1) {
 ; CHECK-LABEL: abds_undef:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sshll2 v1.4s, v0.8h, #0
-; CHECK-NEXT:    sshll v0.4s, v0.4h, #0
-; CHECK-NEXT:    abs v1.4s, v1.4s
-; CHECK-NEXT:    abs v0.4s, v0.4s
-; CHECK-NEXT:    uzp1 v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    movi v0.2d, #0000000000000000
 ; CHECK-NEXT:    ret
   %zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
   %zextsrc2 = sext <8 x i16> undef to <8 x i32>
@@ -480,7 +476,7 @@
 define <8 x i16> @abds_i_const_onehigh() {
 ; CHECK-LABEL: abds_i_const_onehigh:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #32765
+; CHECK-NEXT:    mov w8, #32765 // =0x7ffd
 ; CHECK-NEXT:    dup v0.8h, w8
 ; CHECK-NEXT:    ret
   %result = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
Index: llvm/test/CodeGen/AArch64/hadd-combine.ll
===================================================================
--- llvm/test/CodeGen/AArch64/hadd-combine.ll
+++ llvm/test/CodeGen/AArch64/hadd-combine.ll
@@ -248,10 +248,7 @@
 define <8 x i16> @hadds_undef(<8 x i16> %src1) {
 ; CHECK-LABEL: hadds_undef:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sshll v1.4s, v0.4h, #0
-; CHECK-NEXT:    sshll2 v2.4s, v0.8h, #0
-; CHECK-NEXT:    shrn v0.4h, v1.4s, #1
-; CHECK-NEXT:    shrn2 v0.8h, v2.4s, #1
+; CHECK-NEXT:    movi v0.2d, #0000000000000000
 ; CHECK-NEXT:    ret
   %zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
   %zextsrc2 = sext <8 x i16> undef to <8 x i32>
@@ -587,8 +584,7 @@
 define <8 x i16> @rhadds_undef(<8 x i16> %src1) {
 ; CHECK-LABEL: rhadds_undef:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    movi v1.8h, #1
-; CHECK-NEXT:    shadd v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    movi v0.2d, #0000000000000000
 ; CHECK-NEXT:    ret
   %zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
   %zextsrc2 = sext <8 x i16> undef to <8 x i32>
Index: llvm/test/CodeGen/AArch64/neon-dotreduce.ll
===================================================================
--- llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+++ llvm/test/CodeGen/AArch64/neon-dotreduce.ll
@@ -2073,9 +2073,9 @@
 ; CHECK-NEXT:    sshll v1.8h, v1.8b, #0
 ; CHECK-NEXT:    ld1 { v0.b }[7], [x10]
 ; CHECK-NEXT:    ld1 { v2.b }[7], [x9]
-; CHECK-NEXT:    add x9, sp, #552
+; CHECK-NEXT:    add x9, sp, #680
 ; CHECK-NEXT:    mov v3.b[7], w7
-; CHECK-NEXT:    add x10, sp, #680
+; CHECK-NEXT:    add x10, sp, #552
 ; CHECK-NEXT:    ld1 { v4.b }[6], [x8]
 ; CHECK-NEXT:    add x8, sp, #72
 ; CHECK-NEXT:    movi v6.2d, #0000000000000000
@@ -2097,54 +2097,54 @@
 ; CHECK-NEXT:    saddw v4.4s, v6.4s, v7.4h
 ; CHECK-NEXT:    ldr b6, [sp, #480]
 ; CHECK-NEXT:    add v5.4s, v16.4s, v5.4s
-; CHECK-NEXT:    ldr b7, [sp, #544]
-; CHECK-NEXT:    ldr b16, [sp, #672]
+; CHECK-NEXT:    ldr b7, [sp, #672]
+; CHECK-NEXT:    ldr b16, [sp, #544]
 ; CHECK-NEXT:    ld1 { v6.b }[1], [x8]
 ; CHECK-NEXT:    add x8, sp, #496
 ; CHECK-NEXT:    ld1 { v7.b }[1], [x9]
-; CHECK-NEXT:    add x9, sp, #560
+; CHECK-NEXT:    add x9, sp, #688
 ; CHECK-NEXT:    ld1 { v16.b }[1], [x10]
-; CHECK-NEXT:    add x10, sp, #688
+; CHECK-NEXT:    add x10, sp, #560
 ; CHECK-NEXT:    ld1 { v1.b }[3], [x11]
 ; CHECK-NEXT:    add x11, sp, #640
 ; CHECK-NEXT:    ld1 { v6.b }[2], [x8]
 ; CHECK-NEXT:    add x8, sp, #504
 ; CHECK-NEXT:    ld1 { v7.b }[2], [x9]
-; CHECK-NEXT:    add x9, sp, #568
+; CHECK-NEXT:    add x9, sp, #696
 ; CHECK-NEXT:    ld1 { v16.b }[2], [x10]
-; CHECK-NEXT:    add x10, sp, #696
+; CHECK-NEXT:    add x10, sp, #568
 ; CHECK-NEXT:    ld1 { v1.b }[4], [x11]
 ; CHECK-NEXT:    add x11, sp, #648
 ; CHECK-NEXT:    ld1 { v6.b }[3], [x8]
 ; CHECK-NEXT:    add x8, sp, #512
 ; CHECK-NEXT:    ld1 { v7.b }[3], [x9]
-; CHECK-NEXT:    add x9, sp, #576
+; CHECK-NEXT:    add x9, sp, #704
 ; CHECK-NEXT:    ld1 { v16.b }[3], [x10]
-; CHECK-NEXT:    add x10, sp, #704
+; CHECK-NEXT:    add x10, sp, #576
 ; CHECK-NEXT:    ld1 { v1.b }[5], [x11]
 ; CHECK-NEXT:    add x11, sp, #656
 ; CHECK-NEXT:    ld1 { v6.b }[4], [x8]
 ; CHECK-NEXT:    add x8, sp, #520
 ; CHECK-NEXT:    ld1 { v7.b }[4], [x9]
-; CHECK-NEXT:    add x9, sp, #584
+; CHECK-NEXT:    add x9, sp, #712
 ; CHECK-NEXT:    ld1 { v16.b }[4], [x10]
-; CHECK-NEXT:    add x10, sp, #712
+; CHECK-NEXT:    add x10, sp, #584
 ; CHECK-NEXT:    ld1 { v1.b }[6], [x11]
 ; CHECK-NEXT:    add x11, sp, #664
 ; CHECK-NEXT:    ld1 { v6.b }[5], [x8]
 ; CHECK-NEXT:    add x8, sp, #528
 ; CHECK-NEXT:    ld1 { v7.b }[5], [x9]
-; CHECK-NEXT:    add x9, sp, #592
+; CHECK-NEXT:    add x9, sp, #720
 ; CHECK-NEXT:    ld1 { v16.b }[5], [x10]
-; CHECK-NEXT:    add x10, sp, #720
+; CHECK-NEXT:    add x10, sp, #592
 ; CHECK-NEXT:    saddl v2.4s, v3.4h, v2.4h
 ; CHECK-NEXT:    ldr b3, [sp, #736]
 ; CHECK-NEXT:    ld1 { v6.b }[6], [x8]
-; CHECK-NEXT:    add x8, sp, #600
+; CHECK-NEXT:    add x8, sp, #728
 ; CHECK-NEXT:    saddw v0.4s, v4.4s, v0.4h
 ; CHECK-NEXT:    ld1 { v7.b }[6], [x9]
 ; CHECK-NEXT:    ld1 { v16.b }[6], [x10]
-; CHECK-NEXT:    add x9, sp, #728
+; CHECK-NEXT:    add x9, sp, #600
 ; CHECK-NEXT:    add x10, sp, #536
 ; CHECK-NEXT:    ld1 { v1.b }[7], [x11]
 ; CHECK-NEXT:    movi v4.2d, #0000000000000000
@@ -2160,7 +2160,7 @@
 ; CHECK-NEXT:    sshll v7.8h, v16.8b, #0
 ; CHECK-NEXT:    sshll v2.8h, v6.8b, #0
 ; CHECK-NEXT:    saddl2 v6.4s, v7.8h, v3.8h
-; CHECK-NEXT:    saddl2 v16.4s, v1.8h, v2.8h
+; CHECK-NEXT:    saddl2 v16.4s, v2.8h, v1.8h
 ; CHECK-NEXT:    saddw v2.4s, v4.4s, v2.4h
 ; CHECK-NEXT:    saddl v3.4s, v7.4h, v3.4h
 ; CHECK-NEXT:    add v4.4s, v16.4s, v6.4s
Index: llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
+++ llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
@@ -117,7 +117,6 @@
 ; CHECK-NEXT:  .LBB0_8: # %bb27
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    mr r3, r30
-; CHECK-NEXT:    li r4, 0
 ; CHECK-NEXT:    bl call_6@notoc
 ; CHECK-NEXT:    bc 4, 4*cr4+eq, .LBB0_18
 ; CHECK-NEXT:  # %bb.9: # %bb31
@@ -154,7 +153,6 @@
 ; CHECK-NEXT:    std r30, 104(r1)
 ; CHECK-NEXT:    std r29, 96(r1)
 ; CHECK-NEXT:    li r8, 0
-; CHECK-NEXT:    li r10, 0
 ; CHECK-NEXT:    xxlxor f1, f1, f1
 ; CHECK-NEXT:    std r4, 152(r1)
 ; CHECK-NEXT:    li r4, -1
@@ -274,7 +272,6 @@
 ; CHECK-BE-NEXT:  .LBB0_8: # %bb27
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    mr r3, r30
-; CHECK-BE-NEXT:    li r4, 0
 ; CHECK-BE-NEXT:    bl call_6
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:    bc 4, 4*cr4+eq, .LBB0_18
@@ -312,7 +309,6 @@
 ; CHECK-BE-NEXT:    std r30, 120(r1)
 ; CHECK-BE-NEXT:    std r29, 112(r1)
 ; CHECK-BE-NEXT:    li r8, 0
-; CHECK-BE-NEXT:    li r10, 0
 ; CHECK-BE-NEXT:    xxlxor f1, f1, f1
 ; CHECK-BE-NEXT:    std r4, 168(r1)
 ; CHECK-BE-NEXT:    li r4, -1
Index: llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
===================================================================
--- llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
+++ llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
@@ -26,14 +26,6 @@
 ; CHECK-NEXT:    .cfi_def_cfa s0, 0
 ; CHECK-NEXT:  .Ltmp0:
 ; CHECK-NEXT:    addi sp, sp, -32
-; CHECK-NEXT:    li a0, 0
-; CHECK-NEXT:    li a1, 0
-; CHECK-NEXT:    li a2, 0
-; CHECK-NEXT:    li a3, 0
-; CHECK-NEXT:    li a4, 0
-; CHECK-NEXT:    li a5, 0
-; CHECK-NEXT:    li a6, 0
-; CHECK-NEXT:    li a7, 0
 ; CHECK-NEXT:    call _Z3fooiiiiiiiiiiPi@plt
 ; CHECK-NEXT:    addi sp, sp, 32
 ; CHECK-NEXT:  .Ltmp1:
Index: llvm/test/CodeGen/RISCV/pr51206.ll
===================================================================
--- llvm/test/CodeGen/RISCV/pr51206.ll
+++ llvm/test/CodeGen/RISCV/pr51206.ll
@@ -35,7 +35,6 @@
 ; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:  .LBB0_2: # %bb12
-; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:    ret
 bb:
   %tmp = load i8, ptr @global, align 1
Index: llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
===================================================================
--- llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
+++ llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
@@ -556,3 +556,24 @@
   %dec = sub i64 %zext, 1
   ret i64 %dec
 }
+
+define dso_local signext i32 @ret_sext_i32undef_to_i64(i32 noundef signext %Int_1_Par_Val, i32 noundef signext %Int_2_Par_Val, ptr nocapture noundef writeonly %Int_Par_Ref) local_unnamed_addr align 8 {
+; RV32I-LABEL: ret_sext_i32undef_to_i64:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    addi a0, a0, 2
+; RV32I-NEXT:    sw a0, 0(a2)
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: ret_sext_i32undef_to_i64:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    addiw a0, a0, 2
+; RV64I-NEXT:    sw a0, 0(a2)
+; RV64I-NEXT:    ret
+entry:
+  %add = add nsw i32 %Int_1_Par_Val, 2
+  %add1 = add nsw i32 %add, %Int_2_Par_Val
+  store i32 %add1, ptr %Int_Par_Ref, align 4
+  ret i32 undef
+}
Index: llvm/test/CodeGen/X86/vector-shuffle-v1.ll
===================================================================
--- llvm/test/CodeGen/X86/vector-shuffle-v1.ll
+++ llvm/test/CodeGen/X86/vector-shuffle-v1.ll
@@ -48,7 +48,7 @@
 ; AVX512F-NEXT:    vpsllq $63, %xmm0, %xmm0
 ; AVX512F-NEXT:    vptestmq %zmm0, %zmm0, %k1
 ; AVX512F-NEXT:    vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
-; AVX512F-NEXT:    vmovdqa {{.*#+}} xmm1 = [18446744073709551615,0]
+; AVX512F-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
 ; AVX512F-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7]
 ; AVX512F-NEXT:    vptestmq %zmm0, %zmm0, %k1
 ; AVX512F-NEXT:    vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
@@ -62,8 +62,7 @@
 ; AVX512VL-NEXT:    vptestmq %xmm0, %xmm0, %k1
 ; AVX512VL-NEXT:    vpcmpeqd %xmm0, %xmm0, %xmm0
 ; AVX512VL-NEXT:    vmovdqa64 %xmm0, %xmm1 {%k1} {z}
-; AVX512VL-NEXT:    vmovdqa {{.*#+}} xmm2 = [18446744073709551615,0]
-; AVX512VL-NEXT:    vpalignr {{.*#+}} xmm1 = xmm1[8,9,10,11,12,13,14,15],xmm2[0,1,2,3,4,5,6,7]
+; AVX512VL-NEXT:    vpalignr {{.*#+}} xmm1 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
 ; AVX512VL-NEXT:    vptestmq %xmm1, %xmm1, %k1
 ; AVX512VL-NEXT:    vmovdqa64 %xmm0, %xmm0 {%k1} {z}
 ; AVX512VL-NEXT:    retq
@@ -73,7 +72,7 @@
 ; VL_BW_DQ-NEXT:    vpsllq $63, %xmm0, %xmm0
 ; VL_BW_DQ-NEXT:    vpmovq2m %xmm0, %k0
 ; VL_BW_DQ-NEXT:    vpmovm2q %k0, %xmm0
-; VL_BW_DQ-NEXT:    vmovdqa {{.*#+}} xmm1 = [18446744073709551615,0]
+; VL_BW_DQ-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
 ; VL_BW_DQ-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7]
 ; VL_BW_DQ-NEXT:    vpmovq2m %xmm0, %k0
 ; VL_BW_DQ-NEXT:    vpmovm2q %k0, %xmm0
@@ -735,7 +734,8 @@
 ; AVX512F-NEXT:    kmovw %edi, %k1
 ; AVX512F-NEXT:    vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
 ; AVX512F-NEXT:    vmovdqa64 {{.*#+}} zmm1 = [9,6,1,0,3,7,7,1]
-; AVX512F-NEXT:    vmovdqa64 {{.*#+}} zmm2 = [18446744073709551615,18446744073709551615,0,0,0,0,0,0]
+; AVX512F-NEXT:    vbroadcasti64x4 {{.*#+}} zmm2 = [18446744073709551615,18446744073709551615,0,0,18446744073709551615,18446744073709551615,0,0]
+; AVX512F-NEXT:    # zmm2 = mem[0,1,2,3,0,1,2,3]
 ; AVX512F-NEXT:    vpermt2q %zmm0, %zmm1, %zmm2
 ; AVX512F-NEXT:    vptestmq %zmm2, %zmm2, %k0
 ; AVX512F-NEXT:    kmovw %k0, %eax