diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -93,6 +93,7 @@
     {"zca", RISCVExtensionVersion{1, 0}},
     {"zcb", RISCVExtensionVersion{1, 0}},
     {"zcd", RISCVExtensionVersion{1, 0}},
+    {"zce", RISCVExtensionVersion{1, 0}},
     {"zcf", RISCVExtensionVersion{1, 0}},
     {"zcmp", RISCVExtensionVersion{1, 0}},
     {"zcmt", RISCVExtensionVersion{1, 0}},
@@ -946,6 +947,10 @@
         "' extension is incompatible with '" + (HasC ? "c" : "zcd") +
         "' extension when 'd' extension is enabled");
 
+  if (XLen != 32 && Exts.count("zcf"))
+    return createStringError(errc::invalid_argument,
+                             "'zcf' is only supported for 'rv32'");
+
   // Additional dependency checks.
   // TODO: The 'q' extension requires rv64.
   // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
@@ -959,6 +964,9 @@
 static const char *ImpliedExtsXTHeadVdot[] = {"v"};
 static const char *ImpliedExtsXsfvcp[] = {"zve32x"};
 static const char *ImpliedExtsZcb[] = {"zca"};
+static const char *ImpliedExtsZcd[] = {"zca"};
+static const char *ImpliedExtsZce[] = {"zcb", "zcmp", "zcmt"};
+static const char *ImpliedExtsZcf[] = {"zca"};
 static const char *ImpliedExtsZcmp[] = {"zca"};
 static const char *ImpliedExtsZcmt[] = {"zca"};
 static const char *ImpliedExtsZdinx[] = {"zfinx"};
@@ -1021,6 +1029,9 @@
     {{"xsfvcp"}, {ImpliedExtsXsfvcp}},
     {{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
     {{"zcb"}, {ImpliedExtsZcb}},
+    {{"zcd"}, {ImpliedExtsZcd}},
+    {{"zce"}, {ImpliedExtsZce}},
+    {{"zcf"}, {ImpliedExtsZcf}},
     {{"zcmp"}, {ImpliedExtsZcmp}},
     {{"zcmt"}, {ImpliedExtsZcmt}},
     {{"zdinx"}, {ImpliedExtsZdinx}},
@@ -1098,6 +1109,13 @@
       }
     }
   }
+
+  // Add Zcf if Zce and F are enabled on RV32.
+  if (XLen == 32 && Exts.count("zce") && Exts.count("f") &&
+      !Exts.count("zcf")) {
+    auto Version = findDefaultVersion("zcf");
+    addExtension("zcf", Version->Major, Version->Minor);
+  }
 }
 
 struct CombinedExtsEntry {
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -344,7 +344,8 @@
 
 def FeatureStdExtZcd
     : SubtargetFeature<"zcd", "HasStdExtZcd", "true",
-                       "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
+                       "'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
+                       [FeatureStdExtZca]>;
 
 def HasStdExtCOrZcd
     : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">,
@@ -354,7 +355,8 @@
 
 def FeatureStdExtZcf
     : SubtargetFeature<"zcf", "HasStdExtZcf", "true",
-                       "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
+                       "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
+                       [FeatureStdExtZca]>;
 
 def HasStdExtCOrZcf
     : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf()">,
@@ -364,7 +366,7 @@
 
 def FeatureStdExtZcmp
     : SubtargetFeature<"zcmp", "HasStdExtZcmp", "true",
-                       "'Zcmp' (sequenced instuctions for code-size reduction)", 
+                       "'Zcmp' (sequenced instuctions for code-size reduction)",
                        [FeatureStdExtZca]>;
 def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
                                AssemblerPredicate<(all_of FeatureStdExtZcmp, (not FeatureStdExtC)),
@@ -372,12 +374,18 @@
 
 def FeatureStdExtZcmt
     : SubtargetFeature<"zcmt", "HasStdExtZcmt", "true",
-                       "'Zcmt' (table jump instuctions for code-size reduction)", 
-                       [FeatureStdExtZca, FeatureStdExtZicsr]>; 
+                       "'Zcmt' (table jump instuctions for code-size reduction)",
+                       [FeatureStdExtZca, FeatureStdExtZicsr]>;
 def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
                            AssemblerPredicate<(all_of FeatureStdExtZcmt),
                            "'Zcmt' (table jump instuctions for code-size reduction)">;
 
+def FeatureStdExtZce
+    : SubtargetFeature<"zce", "HasStdExtZce", "true",
+                       "'Zce' (Compressed extensions for microcontrollers)",
+                       [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,
+                        FeatureStdExtZcmt]>;
+
 def FeatureNoRVCHints
     : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
                        "Disable RVC Hint Instructions.">;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -219,8 +219,8 @@
 ; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0"
 ; RV32ZCA: .attribute 5, "rv32i2p1_zca1p0"
 ; RV32ZCB: .attribute 5, "rv32i2p1_zca1p0_zcb1p0"
-; RV32ZCD: .attribute 5, "rv32i2p1_zcd1p0"
-; RV32ZCF: .attribute 5, "rv32i2p1_zcf1p0"
+; RV32ZCD: .attribute 5, "rv32i2p1_zca1p0_zcd1p0"
+; RV32ZCF: .attribute 5, "rv32i2p1_zca1p0_zcf1p0"
 ; RV32ZCMP: .attribute 5, "rv32i2p1_zca1p0_zcmp1p0"
 ; RV32ZCMT: .attribute 5, "rv32i2p1_zicsr2p0_zca1p0_zcmt1p0"
 ; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0"
@@ -306,7 +306,7 @@
 ; RV64ZTSO: .attribute 5, "rv64i2p1_ztso0p1"
 ; RV64ZCA: .attribute 5, "rv64i2p1_zca1p0"
 ; RV64ZCB: .attribute 5, "rv64i2p1_zca1p0_zcb1p0"
-; RV64ZCD: .attribute 5, "rv64i2p1_zcd1p0"
+; RV64ZCD: .attribute 5, "rv64i2p1_zca1p0_zcd1p0"
 ; RV64ZCMP: .attribute 5, "rv64i2p1_zca1p0_zcmp1p0"
 ; RV64ZCMT: .attribute 5, "rv64i2p1_zicsr2p0_zca1p0_zcmt1p0"
 ; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -229,10 +229,10 @@
 # CHECK: attribute      5, "rv32i2p1_zca1p0"
 
 .attribute arch, "rv32izcd1p0"
-# CHECK: attribute      5, "rv32i2p1_zcd1p0"
+# CHECK: attribute      5, "rv32i2p1_zca1p0_zcd1p0"
 
 .attribute arch, "rv32izcf1p0"
-# CHECK: attribute      5, "rv32i2p1_zcf1p0"
+# CHECK: attribute      5, "rv32i2p1_zca1p0_zcf1p0"
 
 .attribute arch, "rv32izcb1p0"
 # CHECK: attribute      5, "rv32i2p1_zca1p0_zcb1p0"
diff --git a/llvm/test/MC/RISCV/rv32fc-valid.s b/llvm/test/MC/RISCV/rv32fc-valid.s
--- a/llvm/test/MC/RISCV/rv32fc-valid.s
+++ b/llvm/test/MC/RISCV/rv32fc-valid.s
@@ -21,9 +21,6 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+c,+f \
 # RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
 # RUN:     | FileCheck -check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+zcf,+f \
-# RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
-# RUN:     | FileCheck -check-prefixes=CHECK-NO-RV32 %s
 
 # FIXME: error messages for rv64fc are misleading
 
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -471,6 +471,11 @@
               "'zcmt' extension is incompatible with 'zcd' extension when 'd' "
               "extension is enabled");
   }
+
+  for (StringRef Input : {"rv64if_zcf"}) {
+    EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+              "'zcf' is only supported for 'rv32'");
+  }
 }
 
 TEST(ToFeatureVector, IIsDroppedAndExperimentalExtensionsArePrefixed) {
@@ -509,3 +514,95 @@
               ElementsAre("i", "m", "l", "c", "y", "zicsr", "zmfoo", "zfinx",
                            "zzfoo", "sbar", "sfoo", "xbar", "xfoo"));
 }
+
+TEST(ParseArchString, ZceImplication) {
+  auto MaybeRV32IZce = RISCVISAInfo::parseArchString("rv32izce", true);
+  ASSERT_THAT_EXPECTED(MaybeRV32IZce, Succeeded());
+  RISCVISAInfo::OrderedExtensionMap ExtsRV32IZce =
+      (*MaybeRV32IZce)->getExtensions();
+  EXPECT_EQ(ExtsRV32IZce.size(), 6UL);
+  EXPECT_EQ(ExtsRV32IZce.count("i"), 1U);
+  EXPECT_EQ(ExtsRV32IZce.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV32IZce.count("zcb"), 1U);
+  EXPECT_EQ(ExtsRV32IZce.count("zce"), 1U);
+  EXPECT_EQ(ExtsRV32IZce.count("zcmp"), 1U);
+  EXPECT_EQ(ExtsRV32IZce.count("zcmt"), 1U);
+
+  auto MaybeRV32IFZce = RISCVISAInfo::parseArchString("rv32ifzce", true);
+  ASSERT_THAT_EXPECTED(MaybeRV32IFZce, Succeeded());
+  RISCVISAInfo::OrderedExtensionMap ExtsRV32IFZce =
+      (*MaybeRV32IFZce)->getExtensions();
+  EXPECT_EQ(ExtsRV32IFZce.size(), 9UL);
+  EXPECT_EQ(ExtsRV32IFZce.count("i"), 1U);
+  EXPECT_EQ(ExtsRV32IFZce.count("zicsr"), 1U);
+  EXPECT_EQ(ExtsRV32IFZce.count("f"), 1U);
+  EXPECT_EQ(ExtsRV32IFZce.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV32IFZce.count("zcb"), 1U);
+  EXPECT_EQ(ExtsRV32IFZce.count("zce"), 1U);
+  EXPECT_EQ(ExtsRV32IFZce.count("zcf"), 1U);
+  EXPECT_EQ(ExtsRV32IFZce.count("zcmp"), 1U);
+  EXPECT_EQ(ExtsRV32IFZce.count("zcmt"), 1U);
+
+  auto MaybeRV32IDZce = RISCVISAInfo::parseArchString("rv32idzce", true);
+  ASSERT_THAT_EXPECTED(MaybeRV32IDZce, Succeeded());
+  RISCVISAInfo::OrderedExtensionMap ExtsRV32IDZce =
+      (*MaybeRV32IDZce)->getExtensions();
+  EXPECT_EQ(ExtsRV32IDZce.size(), 10UL);
+  EXPECT_EQ(ExtsRV32IDZce.count("i"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("zicsr"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("f"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("d"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("zcb"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("zce"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("zcf"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("zcmp"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("zcmt"), 1U);
+
+  auto MaybeRV64IZce = RISCVISAInfo::parseArchString("rv64izce", true);
+  ASSERT_THAT_EXPECTED(MaybeRV64IZce, Succeeded());
+  RISCVISAInfo::OrderedExtensionMap ExtsRV64IZce =
+      (*MaybeRV64IZce)->getExtensions();
+  EXPECT_EQ(ExtsRV64IZce.size(), 6UL);
+  EXPECT_EQ(ExtsRV64IZce.count("i"), 1U);
+  EXPECT_EQ(ExtsRV64IZce.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV64IZce.count("zcb"), 1U);
+  EXPECT_EQ(ExtsRV64IZce.count("zce"), 1U);
+  EXPECT_EQ(ExtsRV64IZce.count("zcmp"), 1U);
+  EXPECT_EQ(ExtsRV64IZce.count("zcmt"), 1U);
+
+  auto MaybeRV64IFZce = RISCVISAInfo::parseArchString("rv64ifzce", true);
+  ASSERT_THAT_EXPECTED(MaybeRV64IFZce, Succeeded());
+  RISCVISAInfo::OrderedExtensionMap ExtsRV64IFZce =
+      (*MaybeRV64IFZce)->getExtensions();
+  EXPECT_EQ(ExtsRV64IFZce.size(), 8UL);
+  EXPECT_EQ(ExtsRV64IFZce.count("i"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zicsr"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("f"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zcb"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zce"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zcmp"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zcmt"), 1U);
+
+  EXPECT_EQ(ExtsRV64IFZce.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zcb"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zce"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zcmp"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zcmt"), 1U);
+
+  auto MaybeRV64IDZce = RISCVISAInfo::parseArchString("rv64idzce", true);
+  ASSERT_THAT_EXPECTED(MaybeRV64IDZce, Succeeded());
+  RISCVISAInfo::OrderedExtensionMap ExtsRV64IDZce =
+      (*MaybeRV64IDZce)->getExtensions();
+  EXPECT_EQ(ExtsRV64IDZce.size(), 9UL);
+  EXPECT_EQ(ExtsRV64IDZce.count("i"), 1U);
+  EXPECT_EQ(ExtsRV64IDZce.count("zicsr"), 1U);
+  EXPECT_EQ(ExtsRV64IDZce.count("f"), 1U);
+  EXPECT_EQ(ExtsRV64IDZce.count("d"), 1U);
+  EXPECT_EQ(ExtsRV64IDZce.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV64IDZce.count("zcb"), 1U);
+  EXPECT_EQ(ExtsRV64IDZce.count("zce"), 1U);
+  EXPECT_EQ(ExtsRV64IDZce.count("zcmp"), 1U);
+  EXPECT_EQ(ExtsRV64IDZce.count("zcmt"), 1U);
+}