diff --git a/llvm/lib/Target/Sparc/CMakeLists.txt b/llvm/lib/Target/Sparc/CMakeLists.txt --- a/llvm/lib/Target/Sparc/CMakeLists.txt +++ b/llvm/lib/Target/Sparc/CMakeLists.txt @@ -5,7 +5,7 @@ tablegen(LLVM SparcGenAsmMatcher.inc -gen-asm-matcher) tablegen(LLVM SparcGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM SparcGenCallingConv.inc -gen-callingconv) -tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel) +tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel -warn-on-unused-entities) tablegen(LLVM SparcGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info) tablegen(LLVM SparcGenMCCodeEmitter.inc -gen-emitter) diff --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/llvm/lib/Target/Sparc/SparcInstr64Bit.td --- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td +++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td @@ -367,13 +367,6 @@ "br$rcond,a,pn $rs1, $imm16", []>; } -multiclass bpr_alias { - def : InstAlias; - def : InstAlias; -} - let Predicates = [Is64Bit] in defm BP : BranchOnReg<[(SPbrreg bb:$imm16, imm:$rcond, i64:$rs1)]>; diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -847,10 +847,6 @@ // unconditional branch class. class BranchAlways pattern> : F2_2<0b010, 0, (outs), ins, asmstr, pattern>; - -// Same as BranchAlways but uses the new v9 encoding -class BranchPredictAlways pattern> - : F2_3<0b001, 0, 1, (outs), ins, asmstr, pattern>; } let cond = 8 in