diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt --- a/llvm/lib/Target/RISCV/CMakeLists.txt +++ b/llvm/lib/Target/RISCV/CMakeLists.txt @@ -7,7 +7,7 @@ tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter) tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel) tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler) -tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel) +tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel -warn-on-unused-entities) tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info) tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter) tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1722,15 +1722,6 @@ let Defs = Regs; } -class SwapSysReg Regs> - : Pseudo<(outs GPR:$rd), (ins GPR:$val), - [(set GPR:$rd, (riscv_swap_csr (XLenVT SR.Encoding), GPR:$val))]>, - PseudoInstExpansion<(CSRRW GPR:$rd, SR.Encoding, GPR:$val)> { - let hasSideEffects = 0; - let Uses = Regs; - let Defs = Regs; -} - class SwapSysRegImm Regs> : Pseudo<(outs GPR:$rd), (ins uimm5:$val), [(set GPR:$rd, (riscv_swap_csr (XLenVT SR.Encoding), uimm5:$val))]>, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -677,12 +677,6 @@ 1 : a#separator#b)); } -class VPseudo : - Pseudo, RISCVVPseudo { - let BaseInstr = instr; - let VLMul = m.value; -} - class GetVTypePredicates { list Predicates = !cond(!eq(vti.Scalar, f16) : [HasVInstructionsF16], !eq(vti.Scalar, f32) : [HasVInstructionsAnyF], @@ -1211,23 +1205,6 @@ let HasSEWOp = 1; } -class VPseudoBinaryMask : - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, - Op1Class:$rs2, Op2Class:$rs1, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, - RISCVVPseudo { - let mayLoad = 0; - let mayStore = 0; - let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; - let HasVLOp = 1; - let HasSEWOp = 1; -} - class VPseudoBinaryMaskPolicy : - Pseudo<(outs RetClass:$rd), - (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, - AVL:$vl, ixlenimm:$sew), - []>, - RISCVVPseudo { - let mayLoad = 0; - let mayStore = 0; - let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $rs3"], ",">.ret; - let HasVLOp = 1; - let HasSEWOp = 1; -} - class VPseudoTernaryNoMaskWithPolicy { - let VLMul = MInfo.value in { - def "_" # MInfo.MX : VPseudoTernaryNoMask; - def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMask; - } -} - -multiclass VPseudoTernaryNoMaskNoPolicy { - let VLMul = MInfo.value in { - def "_" # MInfo.MX : VPseudoTernaryNoMask; - def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy; - } -} - multiclass VPseudoTernaryWithTailPolicy; -} - multiclass VPseudoVWCVTI_V { defvar constraint = "@earlyclobber $rd"; foreach m = MxListFW in { @@ -3912,26 +3843,6 @@ (op2_type op2_reg_class:$rs2), GPR:$vl, log2sew)>; -class VPatUnaryMask : - Pat<(result_type (!cast(intrinsic_name#"_mask") - (result_type result_reg_class:$merge), - (op2_type op2_reg_class:$rs2), - (mask_type V0), - VLOpFrag)), - (!cast(inst#"_"#kind#"_"#vlmul.MX#"_MASK") - (result_type result_reg_class:$merge), - (op2_type op2_reg_class:$rs2), - (mask_type V0), GPR:$vl, sew)>; - class VPatUnaryMaskTA; -class VPatTernaryNoMask : - Pat<(result_type (!cast(intrinsic) - (result_type result_reg_class:$rs3), - (op1_type op1_reg_class:$rs1), - (op2_type op2_kind:$rs2), - VLOpFrag)), - (!cast(inst#"_"#kind#"_"#vlmul.MX) - result_reg_class:$rs3, - (op1_type op1_reg_class:$rs1), - op2_kind:$rs2, - GPR:$vl, sew)>; - class VPatTernaryNoMaskTA; -class VPatTernaryMask : - Pat<(result_type (!cast(intrinsic#"_mask") - (result_type result_reg_class:$rs3), - (op1_type op1_reg_class:$rs1), - (op2_type op2_kind:$rs2), - (mask_type V0), - VLOpFrag)), - (!cast(inst#"_"#kind#"_"#vlmul.MX # "_MASK") - result_reg_class:$rs3, - (op1_type op1_reg_class:$rs1), - op2_kind:$rs2, - (mask_type V0), - GPR:$vl, sew)>; - class VPatTernaryMaskPolicy, VPatBinaryV_X; -multiclass VPatTernary { - def : VPatTernaryNoMask; - def : VPatTernaryMask; -} - -multiclass VPatTernaryNoMaskNoPolicy { - def : VPatTernaryNoMask; - def : VPatTernaryMaskPolicy; -} - multiclass VPatTernaryWithPolicy(name # "_" # mx # "_E" # sew), val, writes>; } } -// Define classes to define list containing all SchedWrites for each (name, LMUL) -// pair for each LMUL in each of the SchedMxList variants above and name in -// argument `names`. These classes can be used to construct a list of existing -// definitions of writes corresponding to each (name, LMUL) pair, that are needed -// by the ReadAdvance. For example: -// ``` -// defm "" : LMULReadAdvance<"ReadVIALUX", 1, -// LMULSchedWriteList<["WriteVIMovVX"]>.value>; -// ``` -class LMULSchedWriteListImpl names, list MxList> { - list value = !foldl([], - !foreach(name, names, - !foreach(mx, MxList, !cast(name # "_" # mx))), - all, writes, !listconcat(all, writes)); -} multiclass LMULSchedWrites : LMULSchedWritesImpl; multiclass LMULSchedReads : LMULSchedReadsImpl; @@ -160,7 +145,6 @@ : LMULWriteResImpl; multiclass LMULReadAdvance writes = []> : LMULReadAdvanceImpl; -class LMULSchedWriteList names> : LMULSchedWriteListImpl; multiclass LMULSEWSchedWrites : LMULSEWSchedWritesImpl; multiclass LMULSEWSchedReads : LMULSEWSchedReadsImpl; @@ -192,7 +176,6 @@ : LMULWriteResImpl; multiclass LMULReadAdvanceW writes = []> : LMULReadAdvanceImpl; -class LMULSchedWriteListW names> : LMULSchedWriteListImpl; multiclass LMULSchedWritesFW : LMULSchedWritesImpl; multiclass LMULSchedReadsFW : LMULSchedReadsImpl; @@ -200,7 +183,6 @@ : LMULWriteResImpl; multiclass LMULReadAdvanceFW writes = []> : LMULReadAdvanceImpl; -class LMULSchedWriteListFW names> : LMULSchedWriteListImpl; // 3.6 Vector Byte Length vlenb def WriteRdVLENB : SchedWrite;