diff --git a/llvm/lib/Target/Mips/CMakeLists.txt b/llvm/lib/Target/Mips/CMakeLists.txt --- a/llvm/lib/Target/Mips/CMakeLists.txt +++ b/llvm/lib/Target/Mips/CMakeLists.txt @@ -8,7 +8,7 @@ tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel) tablegen(LLVM MipsGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM MipsGenFastISel.inc -gen-fast-isel) -tablegen(LLVM MipsGenGlobalISel.inc -gen-global-isel) +tablegen(LLVM MipsGenGlobalISel.inc -gen-global-isel -warn-on-unused-entities) tablegen(LLVM MipsGenPostLegalizeGICombiner.inc -gen-global-isel-combiner -combiners="MipsPostLegalizerCombinerHelper") tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info) diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td b/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td --- a/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -662,22 +662,6 @@ let Inst{5-0} = 0b111011; } -class POOL32F_ABS_FM_MMR6 fmt, bits<7> funct> - : MMR6Arch, MipsR6Inst { - bits<5> ft; - bits<5> fs; - - bits<32> Inst; - - let Inst{31-26} = 0b010101; - let Inst{25-21} = ft; - let Inst{20-16} = fs; - let Inst{15} = 0; - let Inst{14-13} = fmt; - let Inst{12-6} = funct; - let Inst{5-0} = 0b111011; -} - class POOL32F_MATH_FM_MMR6 fmt, bits<8> funct> : MMR6Arch, MipsR6Inst { bits<5> ft; diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td --- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -165,8 +165,6 @@ class SIGRIE_MMR6_ENC : SIGRIE_FM_MM, MMR6Arch<"sigrie">; class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>; class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>; -class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>; -class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>; class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>; class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>; class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>; @@ -678,20 +676,6 @@ InstrItinClass Itinerary = Itin; string BaseOpcode = opstr; } -class MTC1_64_MMR6_DESC_BASE< - string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, - InstrItinClass Itin = NoItinerary> : MipsR6Inst { - dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt); - dag OutOperandList = (outs DstRC:$fs); - string AsmString = !strconcat(opstr, "\t$rt, $fs"); - list Pattern = []; - Format f = FrmFR; - InstrItinClass Itinerary = Itin; - string BaseOpcode = opstr; - // $fs_in is part of a white lie to work around a widespread bug in the FPU - // implementation. See expandBuildPairF64 for details. - let Constraints = "$fs = $fs_in"; -} class MTC2_MMR6_DESC_BASE { dag InOperandList = (ins SrcRC:$rt); @@ -1047,10 +1031,6 @@ FGR32Opnd, II_TRUNC>; class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd, FGR64Opnd, II_TRUNC>; -class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd, - II_SQRT_S, fsqrt>; -class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, - AFGR64Opnd, II_SQRT_D, fsqrt>; class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>; class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd, diff --git a/llvm/lib/Target/Mips/Mips16InstrFormats.td b/llvm/lib/Target/Mips/Mips16InstrFormats.td --- a/llvm/lib/Target/Mips/Mips16InstrFormats.td +++ b/llvm/lib/Target/Mips/Mips16InstrFormats.td @@ -181,23 +181,6 @@ let Inst{4-0} = funct; } -// -// just used for breakpoint (hardware and software) instructions. -// -class FC16 _funct, dag outs, dag ins, string asmstr, - list pattern, InstrItinClass itin>: - MipsInst16 -{ - bits<6> _code; // code is a keyword in tablegen - bits<5> funct; - - let Opcode = 0b11101; // RR - let funct = _funct; - - let Inst{10-5} = _code; - let Inst{4-0} = funct; -} - // // J(AL)R(C) subformat // @@ -224,26 +207,6 @@ let Inst{4-0} = 0; } -//===----------------------------------------------------------------------===// -// Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|> -//===----------------------------------------------------------------------===// - -class FRRI16 op, dag outs, dag ins, string asmstr, - list pattern, InstrItinClass itin>: - MipsInst16 -{ - bits<3> rx; - bits<3> ry; - bits<5> imm5; - - let Opcode = op; - - - let Inst{10-8} = rx; - let Inst{7-5} = ry; - let Inst{4-0} = imm5; -} - //===----------------------------------------------------------------------===// // Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|> //===----------------------------------------------------------------------===// @@ -266,50 +229,6 @@ let Inst{1-0} = f; } -//===----------------------------------------------------------------------===// -// Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|> -//===----------------------------------------------------------------------===// - -class FRRI_A16 _f, dag outs, dag ins, string asmstr, - list pattern, InstrItinClass itin>: - MipsInst16 -{ - bits<3> rx; - bits<3> ry; - bits<1> f; - bits<4> imm4; - - let Opcode = 0b01000; - let f = _f; - - let Inst{10-8} = rx; - let Inst{7-5} = ry; - let Inst{4} = f; - let Inst{3-0} = imm4; -} - -//===----------------------------------------------------------------------===// -// Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|> -//===----------------------------------------------------------------------===// - -class FSHIFT16 _f, dag outs, dag ins, string asmstr, - list pattern, InstrItinClass itin>: - MipsInst16 -{ - bits<3> rx; - bits<3> ry; - bits<3> sa; - bits<2> f; - - let Opcode = 0b00110; - let f = _f; - - let Inst{10-8} = rx; - let Inst{7-5} = ry; - let Inst{4-2} = sa; - let Inst{1-0} = f; -} - //===----------------------------------------------------------------------===// // Format i8 instruction class in Mips : <|opcode|funct|imm8> //===----------------------------------------------------------------------===// @@ -445,35 +364,6 @@ } -//===----------------------------------------------------------------------===// -// Format ASMACRO instruction class in Mips16 : -// -//===----------------------------------------------------------------------===// - -class FASMACRO16 pattern, InstrItinClass itin>: - MipsInst16_EXTEND -{ - bits<3> select; - bits<3> p4; - bits<5> p3; - bits<5> RRR = 0b11100; - bits<3> p2; - bits<3> p1; - bits<5> p0; - - - let Inst{26-24} = select; - let Inst{23-21} = p4; - let Inst{20-16} = p3; - let Inst{15-11} = RRR; - let Inst{10-8} = p2; - let Inst{7-5} = p1; - let Inst{4-0} = p0; - -} - - //===----------------------------------------------------------------------===// // Format EXT-RI instruction class in Mips16 : // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0> @@ -600,40 +490,3 @@ let Inst{4-0} = imm16{4-0}; } - -//===----------------------------------------------------------------------===// -// Format EXT-I8_SVRS instruction class in Mips16 : -// <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0> -//===----------------------------------------------------------------------===// - -class FEXT_I8_SVRS16 s_, dag outs, dag ins, string asmstr, - list pattern, InstrItinClass itin>: - MipsInst16_EXTEND -{ - bits<3> xsregs =0; - bits<8> framesize =0; - bits<3> aregs =0; - bits<5> I8 = 0b01100; - bits<3> SVRS = 0b100; - bits<1> s; - bits<1> ra = 0; - bits<1> s0 = 0; - bits<1> s1 = 0; - - let s= s_; - - let Inst{26-24} = xsregs; - let Inst{23-20} = framesize{7-4}; - let Inst{19} = 0; - let Inst{18-16} = aregs; - let Inst{15-11} = I8; - let Inst{10-8} = SVRS; - let Inst{7} = s; - let Inst{6} = ra; - let Inst{5} = s0; - let Inst{4} = s1; - let Inst{3-0} = framesize{3-0}; - - -} - diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.td b/llvm/lib/Target/Mips/Mips16InstrInfo.td --- a/llvm/lib/Target/Mips/Mips16InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips16InstrInfo.td @@ -321,11 +321,6 @@ // RR-type instruction format // -class FRR16_ins f, string asmstr, InstrItinClass itin> : - FRR16 { -} - class FRRBreakNull16_ins : FRRBreak16<(outs), (ins), asmstr, [], itin> { let Code=0; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -373,10 +373,6 @@ list InsnPredicates = [HasMips32r6]; list EncodingPredicates = [InMicroMips]; } -class ISA_MICROMIPS64R6 { - list InsnPredicates = [HasMips64r6]; - list EncodingPredicates = [InMicroMips]; -} class ISA_MICROMIPS32_NOT_MIPS32R6 { list InsnPredicates = [NotMips32r6]; list EncodingPredicates = [InMicroMips]; @@ -402,12 +398,6 @@ list EncodingPredicates = [HasStdEnc]; } -// The portions of MIPS-IV that were also added to MIPS32. -class INSN_MIPS4_32 { - list InsnPredicates = [HasMips4_32]; - list EncodingPredicates = [HasStdEnc]; -} - // The portions of MIPS-IV that were also added to MIPS32 but were removed in // MIPS32r6 and MIPS64r6. class INSN_MIPS4_32_NOT_32R6_64R6 { @@ -447,10 +437,6 @@ list ASEPredicate = [HasCnMipsP]; } -class NOT_ASE_CNMIPSP { - list ASEPredicate = [NotCnMipsP]; -} - class ASE_MIPS64_CNMIPS { list ASEPredicate = [HasMips64, HasCnMips]; } @@ -483,13 +469,6 @@ list ASEPredicate = [HasGINV]; } -// Class used for separating microMIPSr6 and microMIPS (r3) instruction. -// It can be used only on instructions that doesn't inherit PredicateControl. -class ISA_MICROMIPS_NOT_32R6 : PredicateControl { - let InsnPredicates = [NotMips32r6]; - let EncodingPredicates = [InMicroMips]; -} - class ASE_NOT_DSP { list ASEPredicate = [NotDSP]; } @@ -528,26 +507,6 @@ bit isCTI = 1; } -class IsReturn { - bit isReturn = 1; - bit isCTI = 1; -} - -class IsCall { - bit isCall = 1; - bit isCTI = 1; -} - -class IsTailCall { - bit isCall = 1; - bit isTerminator = 1; - bit isReturn = 1; - bit isBarrier = 1; - bit hasExtraSrcRegAllocReq = 1; - bit isCodeGenOnly = 1; - bit isCTI = 1; -} - class IsAsCheapAsAMove { bit isAsCheapAsAMove = 1; } diff --git a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td --- a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td @@ -235,12 +235,6 @@ (MipsVSHF (vsplati64_splat_d node:$i), node:$v, node:$v)>; -class SplatPatLeaf - : PatLeaf { - Operand OpClass = opclass; -} - class SplatComplexPattern roots = [], list props = []> : diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.td b/llvm/lib/Target/Mips/MipsRegisterInfo.td --- a/llvm/lib/Target/Mips/MipsRegisterInfo.td +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.td @@ -75,9 +75,6 @@ let CoveredBySubRegs = 1; } -// Mips Hardware Registers -class HWR Enc, string n> : MipsReg; - //===----------------------------------------------------------------------===// // Registers //===----------------------------------------------------------------------===//