diff --git a/llvm/lib/Target/AVR/AVRInstrFormats.td b/llvm/lib/Target/AVR/AVRInstrFormats.td
--- a/llvm/lib/Target/AVR/AVRInstrFormats.td
+++ b/llvm/lib/Target/AVR/AVRInstrFormats.td
@@ -75,17 +75,6 @@
   let Inst{3 - 0} = rr{3 - 0};
 }
 
-class FTST<bits<4> opcode, bits<2> f, dag outs, dag ins, string asmstr,
-           list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern> {
-  bits<5> rd;
-
-  let Inst{15 - 12} = opcode;
-  let Inst{11 - 10} = f;
-  let Inst{9} = rd{4};
-  let Inst{8 - 4} = rd;
-  let Inst{3 - 0} = rd{3 - 0};
-}
-
 //===----------------------------------------------------------------------===//
 // Instruction of the format `<mnemonic> Z, Rd`
 // <|1001|001r|rrrr|0ttt>
@@ -445,11 +434,6 @@
   let Inst = opcode;
 }
 
-class F32<bits<32> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
-    : AVRInst32<outs, ins, asmstr, pattern> {
-  let Inst = opcode;
-}
-
 //===----------------------------------------------------------------------===//
 // Branching instructions with immediate12: <|110f|kkkk|kkkk|kkkk|>
 // f = secondary opcode = 1 bit
diff --git a/llvm/lib/Target/AVR/CMakeLists.txt b/llvm/lib/Target/AVR/CMakeLists.txt
--- a/llvm/lib/Target/AVR/CMakeLists.txt
+++ b/llvm/lib/Target/AVR/CMakeLists.txt
@@ -5,7 +5,7 @@
 tablegen(LLVM AVRGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel -warn-on-unused-entities)
 tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)