diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td
--- a/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -77,10 +77,6 @@
 // it doesn't have a Rn operand.
 class UnaryDP    { bit isUnaryDataProc = 1; }
 
-// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
-// a 16-bit Thumb instruction if certain conditions are met.
-class Xform16Bit { bit canXformTo16Bit = 1; }
-
 //===----------------------------------------------------------------------===//
 // ARM Instruction flags.  These need to match ARMBaseInstrInfo.h.
 //
@@ -485,12 +481,6 @@
   : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb]>;
 class t2AsmPseudo<string asm, dag iops, dag oops = (outs)>
   : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>;
-class VFP2AsmPseudo<string asm, dag iops, dag oops = (outs)>
-  : AsmPseudoInst<asm, iops, oops>, Requires<[HasVFP2]>;
-class NEONAsmPseudo<string asm, dag iops, dag oops = (outs)>
-  : AsmPseudoInst<asm, iops, oops>, Requires<[HasNEON]>;
-class MVEAsmPseudo<string asm, dag iops, dag oops = (outs)>
-  : AsmPseudoInst<asm, iops, oops>, Requires<[HasMVEInt]>;
 
 // Pseudo instructions for the code generator.
 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
@@ -618,10 +608,6 @@
          string opc, string asm, list<dag> pattern>
   : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
       opc, asm, "", pattern>;
-class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
-          string opc, string asm, list<dag> pattern>
-  : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
-       opc, asm, "", pattern>;
 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
           string asm, list<dag> pattern>
   : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
@@ -650,11 +636,6 @@
 }
 
 // BR_JT instructions
-class JTI<dag oops, dag iops, InstrItinClass itin,
-          string asm, list<dag> pattern>
-  : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin,
-       asm, "", pattern>;
-
 class AIldr_ex_or_acq<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin,
               string opc, string asm, list<dag> pattern>
   : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
@@ -756,13 +737,6 @@
   let Inst{24-21} = opcod;
   let Inst{27-26} = 0b00;
 }
-class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
-           string asm, list<dag> pattern>
-  : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
-       asm, "", pattern> {
-  let Inst{24-21} = opcod;
-  let Inst{27-26} = 0b00;
-}
 
 // loads
 
@@ -793,60 +767,8 @@
   let Inst{20}    = isLd; // L bit
   let Inst{15-12} = Rt;
 }
-class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
-                IndexMode im, Format f, InstrItinClass itin, string opc,
-                string asm, string cstr, list<dag> pattern>
-  : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
-               pattern> {
-  // AM2 store w/ two operands: (GPR, am2offset)
-  // {12}     isAdd
-  // {11-0}   imm12/Rm
-  bits<14> offset;
-  bits<4> Rn;
-  let Inst{25} = 1;
-  let Inst{23} = offset{12};
-  let Inst{19-16} = Rn;
-  let Inst{11-5} = offset{11-5};
-  let Inst{4} = 0;
-  let Inst{3-0} = offset{3-0};
-}
-
-class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
-                IndexMode im, Format f, InstrItinClass itin, string opc,
-                string asm, string cstr, list<dag> pattern>
-  : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
-               pattern> {
-  // AM2 store w/ two operands: (GPR, am2offset)
-  // {12}     isAdd
-  // {11-0}   imm12/Rm
-  bits<14> offset;
-  bits<4> Rn;
-  let Inst{25} = 0;
-  let Inst{23} = offset{12};
-  let Inst{19-16} = Rn;
-  let Inst{11-0} = offset{11-0};
-}
 
 
-// FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
-// but for now use this class for STRT and STRBT.
-class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
-                IndexMode im, Format f, InstrItinClass itin, string opc,
-                string asm, string cstr, list<dag> pattern>
-  : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
-               pattern> {
-  // AM2 store w/ two operands: (GPR, am2offset)
-  // {17-14}  Rn
-  // {13}     1 == Rm, 0 == imm12
-  // {12}     isAdd
-  // {11-0}   imm12/Rm
-  bits<18> addr;
-  let Inst{25} = addr{13};
-  let Inst{23} = addr{12};
-  let Inst{19-16} = addr{17-14};
-  let Inst{11-0} = addr{11-0};
-}
-
 // addrmode3 instructions
 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
             InstrItinClass itin, string opc, string asm, list<dag> pattern>
@@ -1178,11 +1100,6 @@
   let Inst{12}    = opcod3;
 }
 
-// BR_JT instructions
-class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
-           list<dag> pattern>
-  : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
-
 // Thumb1 only
 class Thumb1I<dag oops, dag iops, AddrMode am, int sz,
               InstrItinClass itin, string asm, string cstr, list<dag> pattern>
@@ -1197,15 +1114,6 @@
 class T1I<dag oops, dag iops, InstrItinClass itin,
           string asm, list<dag> pattern>
   : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
-class T1Ix2<dag oops, dag iops, InstrItinClass itin,
-            string asm, list<dag> pattern>
-  : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
-
-// Two-address instructions
-class T1It<dag oops, dag iops, InstrItinClass itin,
-           string asm, string cstr, list<dag> pattern>
-  : Thumb1I<oops, iops, AddrModeNone, 2, itin,
-            asm, cstr, pattern>;
 
 // Thumb1 instruction that can either be predicated or set CPSR.
 class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
@@ -1453,9 +1361,6 @@
 class T2XI<dag oops, dag iops, InstrItinClass itin,
            string asm, list<dag> pattern>
   : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
-class T2JTI<dag oops, dag iops, InstrItinClass itin,
-            string asm, list<dag> pattern>
-  : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
 
 // Move to/from coprocessor instructions
 class T2Cop<bits<4> opc, dag oops, dag iops, string opcstr, string asm,
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td
--- a/llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -554,21 +554,6 @@
 
 // Classes for VLD* pseudo-instructions with multi-register operands.
 // These are expanded to real instructions after register allocation.
-class VLDQPseudo<InstrItinClass itin>
-  : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
-class VLDQWBPseudo<InstrItinClass itin>
-  : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
-                (ins addrmode6:$addr, am6offset:$offset), itin,
-                "$addr.addr = $wb">;
-class VLDQWBfixedPseudo<InstrItinClass itin>
-  : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
-                (ins addrmode6:$addr), itin,
-                "$addr.addr = $wb">;
-class VLDQWBregisterPseudo<InstrItinClass itin>
-  : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
-                (ins addrmode6:$addr, rGPR:$offset), itin,
-                "$addr.addr = $wb">;
-
 class VLDQQPseudo<InstrItinClass itin>
   : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
 class VLDQQWBPseudo<InstrItinClass itin>
@@ -1662,20 +1647,6 @@
 
 // Classes for VST* pseudo-instructions with multi-register operands.
 // These are expanded to real instructions after register allocation.
-class VSTQPseudo<InstrItinClass itin>
-  : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
-class VSTQWBPseudo<InstrItinClass itin>
-  : PseudoNLdSt<(outs GPR:$wb),
-                (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
-                "$addr.addr = $wb">;
-class VSTQWBfixedPseudo<InstrItinClass itin>
-  : PseudoNLdSt<(outs GPR:$wb),
-                (ins addrmode6:$addr, QPR:$src), itin,
-                "$addr.addr = $wb">;
-class VSTQWBregisterPseudo<InstrItinClass itin>
-  : PseudoNLdSt<(outs GPR:$wb),
-                (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
-                "$addr.addr = $wb">;
 class VSTQQPseudo<InstrItinClass itin>
   : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
 class VSTQQWBPseudo<InstrItinClass itin>
@@ -3753,18 +3724,6 @@
                         OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
 }
 
-// ....then also with element size of 8 bits:
-multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
-                       InstrItinClass itin16, InstrItinClass itin32,
-                       string OpcodeStr, string Dt,
-                       SDPatternOperator IntOp, bit Commutable = 0>
-  : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
-               IntOp, Commutable> {
-  def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
-                      OpcodeStr, !strconcat(Dt, "8"),
-                      v8i16, v8i8, IntOp, Commutable>;
-}
-
 // ....with explicit extend (VABDL).
 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
                        InstrItinClass itin, string OpcodeStr, string Dt,
@@ -3879,21 +3838,6 @@
                        OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
 }
 
-//   element sizes of 8, 16 and 32 bits:
-multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
-                       InstrItinClass itinD16, InstrItinClass itinD32,
-                       InstrItinClass itinQ16, InstrItinClass itinQ32,
-                       string OpcodeStr, string Dt, SDPatternOperator IntOp>
-           :N3VInt3_HS <op24, op23, op11_8, op4, itinD16, itinD32,
-                        itinQ16, itinQ32, OpcodeStr, Dt, IntOp>{
-  // 64-bit vector types.
-  def v8i8  : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD16,
-                       OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
-  // 128-bit vector types.
-  def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ16,
-                       OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
-}
-
 // Neon Long Multiply-Op vector operations,
 //   element sizes of 8, 16 and 32 bits:
 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
@@ -3937,15 +3881,6 @@
                          OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
 }
 
-// ....then also with element size of 8 bits:
-multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
-                        InstrItinClass itin16, InstrItinClass itin32,
-                        string OpcodeStr, string Dt, SDPatternOperator IntOp>
-  : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
-  def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
-                       OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
-}
-
 // ....with explicit extend (VABAL).
 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
                             InstrItinClass itin, string OpcodeStr, string Dt,
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -438,20 +438,6 @@
 // Multiclass helpers...
 //
 
-
-class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
-           string opc, string asm, list<dag> pattern>
-  : T2I<oops, iops, itin, opc, asm, pattern> {
-  bits<4> Rd;
-  bits<12> imm;
-
-  let Inst{11-8}  = Rd;
-  let Inst{26}    = imm{11};
-  let Inst{14-12} = imm{10-8};
-  let Inst{7-0}   = imm{7-0};
-}
-
-
 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
            string opc, string asm, list<dag> pattern>
   : T2sI<oops, iops, itin, opc, asm, pattern> {
@@ -478,19 +464,6 @@
 }
 
 
-class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
-           string opc, string asm, list<dag> pattern>
-  : T2I<oops, iops, itin, opc, asm, pattern> {
-  bits<4> Rd;
-  bits<12> ShiftedRm;
-
-  let Inst{11-8}  = Rd;
-  let Inst{3-0}   = ShiftedRm{3-0};
-  let Inst{5-4}   = ShiftedRm{6-5};
-  let Inst{14-12} = ShiftedRm{11-9};
-  let Inst{7-6}   = ShiftedRm{8-7};
-}
-
 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
            string opc, string asm, list<dag> pattern>
   : T2sI<oops, iops, itin, opc, asm, pattern> {
@@ -548,20 +521,6 @@
 }
 
 
-class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
-           string opc, string asm, list<dag> pattern>
-  : T2I<oops, iops, itin, opc, asm, pattern> {
-  bits<4> Rd;
-  bits<4> Rn;
-  bits<12> imm;
-
-  let Inst{11-8}  = Rd;
-  let Inst{19-16} = Rn;
-  let Inst{26}    = imm{11};
-  let Inst{14-12} = imm{10-8};
-  let Inst{7-0}   = imm{7-0};
-}
-
 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
            string opc, string asm, list<dag> pattern>
   : T2sI<oops, iops, itin, opc, asm, pattern> {
@@ -638,21 +597,6 @@
   let Inst{3-0}   = Rm;
 }
 
-class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
-           string opc, string asm, list<dag> pattern>
-  : T2I<oops, iops, itin, opc, asm, pattern> {
-  bits<4> Rd;
-  bits<4> Rn;
-  bits<12> ShiftedRm;
-
-  let Inst{11-8}  = Rd;
-  let Inst{19-16} = Rn;
-  let Inst{3-0}   = ShiftedRm{3-0};
-  let Inst{5-4}   = ShiftedRm{6-5};
-  let Inst{14-12} = ShiftedRm{11-9};
-  let Inst{7-6}   = ShiftedRm{8-7};
-}
-
 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
            string opc, string asm, list<dag> pattern>
   : T2sI<oops, iops, itin, opc, asm, pattern> {
diff --git a/llvm/lib/Target/ARM/CMakeLists.txt b/llvm/lib/Target/ARM/CMakeLists.txt
--- a/llvm/lib/Target/ARM/CMakeLists.txt
+++ b/llvm/lib/Target/ARM/CMakeLists.txt
@@ -8,7 +8,7 @@
 tablegen(LLVM ARMGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM ARMGenFastISel.inc -gen-fast-isel)
-tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel -warn-on-unused-entities)
 tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM ARMGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM ARMGenMCPseudoLowering.inc -gen-pseudo-lowering)