diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -6241,13 +6241,15 @@
 SDValue DAGTypeLegalizer::WidenVecOp_INSERT_SUBVECTOR(SDNode *N) {
   EVT VT = N->getValueType(0);
   SDValue SubVec = N->getOperand(1);
+  EVT SubVT = SubVec.getValueType();
   SDValue InVec = N->getOperand(0);
 
   if (getTypeAction(SubVec.getValueType()) == TargetLowering::TypeWidenVector)
     SubVec = GetWidenedVector(SubVec);
 
-  if (SubVec.getValueType().knownBitsLE(VT) && InVec.isUndef() &&
-      N->getConstantOperandVal(2) == 0)
+  bool IndicesValid = SubVT.knownBitsLE(VT) ||
+                      (VT.isScalableVector() && SubVT.isFixedLengthVector());
+  if (IndicesValid && InVec.isUndef() && N->getConstantOperandVal(2) == 0)
     return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, InVec, SubVec,
                        N->getOperand(2));
 
diff --git a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
--- a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
@@ -495,6 +495,14 @@
   ret void
 }
 
+define <vscale x 4 x i64> @insert_nxv4i64_nxv3i64(<3 x i64> %sv) {
+; CHECK-LABEL: insert_nxv4i64_nxv3i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ret
+  %vec = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.v3i64(<vscale x 4 x i64> undef, <3 x i64> %sv, i64 0)
+  ret <vscale x 4 x i64> %vec
+}
+
 declare <vscale x 4 x i1> @llvm.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1>, <vscale x 1 x i1>, i64)
 declare <vscale x 32 x i1> @llvm.vector.insert.nxv8i1.nxv32i1(<vscale x 32 x i1>, <vscale x 8 x i1>, i64)
 
@@ -512,3 +520,5 @@
 declare <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32>, <vscale x 2 x i32>, i64 %idx)
 declare <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32>, <vscale x 4 x i32>, i64 %idx)
 declare <vscale x 16 x i32> @llvm.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32>, <vscale x 8 x i32>, i64 %idx)
+
+declare <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.v3i64(<vscale x 4 x i64>, <3 x i64>, i64 %idx)