Index: llvm/lib/Target/CSKY/CSKYInstrInfo.td =================================================================== --- llvm/lib/Target/CSKY/CSKYInstrInfo.td +++ llvm/lib/Target/CSKY/CSKYInstrInfo.td @@ -112,6 +112,13 @@ let DecoderMethod = "decodeUImmOperand<"#num#", "#shift#">"; } +def uimm_neg_XFORM : SDNodeXFormgetTargetConstant(-N->getSExtValue(), SDLoc(N), MVT::i32); +}]>; +class uimm_neg : Operand, + ImmLeaf(-Imm);"> { +} + class simm : Operand, ImmLeaf(Imm);"> { let EncoderMethod = "getImmOpValue<"#shift#">"; @@ -371,6 +378,8 @@ def uimm24 : uimm<24>; def uimm24_8 : uimm<24, 8>; +def uimm5_neg : uimm_neg<5>; + def simm8_2 : simm<8, 2>; class RegSeqAsmOperand : AsmOperandClass { @@ -1235,8 +1244,14 @@ (INCT32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>; def : Pat<(select (i32 (seteq GPR:$rs1, uimm16:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$false), (INCF32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>; - -multiclass INCTF32Pat0 { +def : Pat<(select (i32 (setne GPR:$rs1, uimm16:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$false), + (DECT32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$false, GPR:$rx, + (uimm_neg_XFORM uimm5_neg:$imm))>; +def : Pat<(select (i32 (seteq GPR:$rs1, uimm16:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$false), + (DECF32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$false, GPR:$rx, + (uimm_neg_XFORM uimm5:$imm))>; + +multiclass INCDECPat { def : Pat<(select (i32 (cond0 GPR:$rs1, oimm16:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$other), (INCT32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>; def : Pat<(select (i32 (cond1 GPR:$rs1, oimm16:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$other), @@ -1245,19 +1260,40 @@ (INCF32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>; def : Pat<(select (i32 (cond1 GPR:$rs1, oimm16:$rs2)), GPR:$other, (add GPR:$rx, uimm5:$imm)), (INCT32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>; -} - -defm : INCTF32Pat0; -defm : INCTF32Pat0; - -def : Pat<(select CARRY:$ca, (add GPR:$rx, uimm5:$imm), GPR:$false), - (INCT32 CARRY:$ca, GPR:$false, GPR:$rx, uimm5:$imm)>; -def : Pat<(select CARRY:$ca, GPR:$true, (add GPR:$rx, uimm5:$imm)), - (INCF32 CARRY:$ca, GPR:$true, GPR:$rx, uimm5:$imm)>; -def : Pat<(select (and CARRY:$ca, 1), (add GPR:$rx, uimm5:$imm), GPR:$false), - (INCT32 CARRY:$ca, GPR:$false, GPR:$rx, uimm5:$imm)>; -def : Pat<(select (and CARRY:$ca, 1), GPR:$true, (add GPR:$rx, uimm5:$imm)), - (INCF32 CARRY:$ca, GPR:$true, GPR:$rx, uimm5:$imm)>; + def : Pat<(select (i32 (cond0 GPR:$rs1, oimm16:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$other), + (DECT32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, + (uimm_neg_XFORM uimm5_neg:$imm))>; + def : Pat<(select (i32 (cond1 GPR:$rs1, oimm16:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$other), + (DECF32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, + (uimm_neg_XFORM uimm5_neg:$imm))>; + def : Pat<(select (i32 (cond0 GPR:$rs1, oimm16:$rs2)), GPR:$other, (add GPR:$rx, uimm5_neg:$imm)), + (DECF32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, + (uimm_neg_XFORM uimm5_neg:$imm))>; + def : Pat<(select (i32 (cond1 GPR:$rs1, oimm16:$rs2)), GPR:$other, (add GPR:$rx, uimm5_neg:$imm)), + (DECT32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, + (uimm_neg_XFORM uimm5_neg:$imm))>; +} + +defm : INCDECPat; +defm : INCDECPat; + +def : Pat<(select CARRY:$ca, (add GPR:$rx, uimm5:$imm), GPR:$other), + (INCT32 CARRY:$ca, GPR:$other, GPR:$rx, uimm5:$imm)>; +def : Pat<(select CARRY:$ca, GPR:$other, (add GPR:$rx, uimm5:$imm)), + (INCF32 CARRY:$ca, GPR:$other, GPR:$rx, uimm5:$imm)>; +def : Pat<(select (and CARRY:$ca, 1), (add GPR:$rx, uimm5:$imm), GPR:$other), + (INCT32 CARRY:$ca, GPR:$other, GPR:$rx, uimm5:$imm)>; +def : Pat<(select (and CARRY:$ca, 1), GPR:$other, (add GPR:$rx, uimm5:$imm)), + (INCF32 CARRY:$ca, GPR:$other, GPR:$rx, uimm5:$imm)>; + +def : Pat<(select CARRY:$ca, (add GPR:$rx, uimm5_neg:$imm), GPR:$other), + (DECT32 CARRY:$ca, GPR:$other, GPR:$rx, (uimm_neg_XFORM uimm5_neg:$imm))>; +def : Pat<(select CARRY:$ca, GPR:$other, (add GPR:$rx, uimm5_neg:$imm)), + (DECF32 CARRY:$ca, GPR:$other, GPR:$rx, (uimm_neg_XFORM uimm5_neg:$imm))>; +def : Pat<(select (and CARRY:$ca, 1), (add GPR:$rx, uimm5_neg:$imm), GPR:$other), + (DECT32 CARRY:$ca, GPR:$other, GPR:$rx, (uimm_neg_XFORM uimm5_neg:$imm))>; +def : Pat<(select (and CARRY:$ca, 1), GPR:$other, (add GPR:$rx, uimm5_neg:$imm)), + (DECF32 CARRY:$ca, GPR:$other, GPR:$rx, (uimm_neg_XFORM uimm5_neg:$imm))>; def : Pat<(select CARRY:$ca, GPR:$rx, GPR:$false), (MOVT32 CARRY:$ca, GPR:$rx, GPR:$false)>; @@ -1291,23 +1327,48 @@ (INCT32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>; def : Pat<(select (i32 (seteq GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$false), (INCF32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>; - -multiclass INCTF32Pat1 { +def : Pat<(select (i32 (setne GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$false), + (DECT32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx, + (uimm_neg_XFORM uimm5_neg:$imm))>; +def : Pat<(select (i32 (seteq GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$false), + (DECF32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx, + (uimm_neg_XFORM uimm5_neg:$imm))>; + +multiclass INCPat { def : Pat<(select (i32 (cond0 GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$other), - (incdec0 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>; + (inc0 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>; def : Pat<(select (i32 (cond0 GPR:$rs1, GPR:$rs2)), GPR:$other, (add GPR:$rx, uimm5:$imm)), - (incdec1 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>; + (inc1 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>; def : Pat<(select (i32 (cond1 GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$other), - (incdec0 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx, uimm5:$imm)>; + (inc0 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx, uimm5:$imm)>; def : Pat<(select (i32 (cond1 GPR:$rs1, GPR:$rs2)), GPR:$other, (add GPR:$rx, uimm5:$imm)), - (incdec1 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx, uimm5:$imm)>; -} - -defm : INCTF32Pat1; -defm : INCTF32Pat1; -defm : INCTF32Pat1; -defm : INCTF32Pat1; + (inc1 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx, uimm5:$imm)>; +} + +defm : INCPat; +defm : INCPat; +defm : INCPat; +defm : INCPat; + +multiclass DECPat { + def : Pat<(select (i32 (cond0 GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$other), + (dec0 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx, + (uimm_neg_XFORM uimm5_neg:$imm))>; + def : Pat<(select (i32 (cond0 GPR:$rs1, GPR:$rs2)), GPR:$other, (add GPR:$rx, uimm5_neg:$imm)), + (dec1 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx, + (uimm_neg_XFORM uimm5_neg:$imm))>; + def : Pat<(select (i32 (cond1 GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$other), + (dec0 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx, + (uimm_neg_XFORM uimm5_neg:$imm))>; + def : Pat<(select (i32 (cond1 GPR:$rs1, GPR:$rs2)), GPR:$other, (add GPR:$rx, uimm5_neg:$imm)), + (dec1 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx, + (uimm_neg_XFORM uimm5_neg:$imm))>; +} + +defm : DECPat; +defm : DECPat; +defm : DECPat; +defm : DECPat; def : Pat<(select (i32 (setne GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false), (MOVT32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>; Index: llvm/test/CodeGen/CSKY/dect-decf.ll =================================================================== --- llvm/test/CodeGen/CSKY/dect-decf.ll +++ llvm/test/CodeGen/CSKY/dect-decf.ll @@ -4,11 +4,8 @@ define i32 @select_by_icmp_ugt(i32 %t0, i32 %t1, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_ugt: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 t0, 65535 -; CHECK-NEXT: ori32 t0, t0, 65526 -; CHECK-NEXT: addu16 a2, t0 ; CHECK-NEXT: cmphs16 a1, a0 -; CHECK-NEXT: movf32 a3, a2 +; CHECK-NEXT: decf32 a3, a2, 10 ; CHECK-NEXT: mov16 a0, a3 ; CHECK-NEXT: rts16 %t4 = icmp ugt i32 %t0, %t1 @@ -20,11 +17,8 @@ define i32 @select_by_icmp_sgt(i32 %t0, i32 %t1, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_sgt: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 t0, 65535 -; CHECK-NEXT: ori32 t0, t0, 65526 -; CHECK-NEXT: addu16 a2, t0 ; CHECK-NEXT: cmplt16 a1, a0 -; CHECK-NEXT: movt32 a3, a2 +; CHECK-NEXT: dect32 a3, a2, 10 ; CHECK-NEXT: mov16 a0, a3 ; CHECK-NEXT: rts16 %t4 = icmp sgt i32 %t0, %t1 @@ -36,11 +30,8 @@ define i32 @select_by_icmp_uge(i32 %t0, i32 %t1, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_uge: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 t0, 65535 -; CHECK-NEXT: ori32 t0, t0, 65526 -; CHECK-NEXT: addu16 a2, t0 ; CHECK-NEXT: cmphs16 a0, a1 -; CHECK-NEXT: movt32 a3, a2 +; CHECK-NEXT: dect32 a3, a2, 10 ; CHECK-NEXT: mov16 a0, a3 ; CHECK-NEXT: rts16 %t4 = icmp uge i32 %t0, %t1 @@ -52,11 +43,8 @@ define i32 @select_by_icmp_sge(i32 %t0, i32 %t1, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_sge: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 t0, 65535 -; CHECK-NEXT: ori32 t0, t0, 65526 -; CHECK-NEXT: addu16 a2, t0 ; CHECK-NEXT: cmplt16 a0, a1 -; CHECK-NEXT: movf32 a3, a2 +; CHECK-NEXT: decf32 a3, a2, 10 ; CHECK-NEXT: mov16 a0, a3 ; CHECK-NEXT: rts16 %t4 = icmp sge i32 %t0, %t1 @@ -68,11 +56,8 @@ define i32 @select_by_icmp_ult(i32 %t0, i32 %t1, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_ult: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 t0, 65535 -; CHECK-NEXT: ori32 t0, t0, 65526 -; CHECK-NEXT: addu16 a2, t0 ; CHECK-NEXT: cmphs16 a0, a1 -; CHECK-NEXT: movf32 a3, a2 +; CHECK-NEXT: decf32 a3, a2, 10 ; CHECK-NEXT: mov16 a0, a3 ; CHECK-NEXT: rts16 %t4 = icmp ult i32 %t0, %t1 @@ -84,11 +69,8 @@ define i32 @select_by_icmp_slt(i32 %t0, i32 %t1, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_slt: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 t0, 65535 -; CHECK-NEXT: ori32 t0, t0, 65526 -; CHECK-NEXT: addu16 a2, t0 ; CHECK-NEXT: cmplt16 a0, a1 -; CHECK-NEXT: movt32 a3, a2 +; CHECK-NEXT: dect32 a3, a2, 10 ; CHECK-NEXT: mov16 a0, a3 ; CHECK-NEXT: rts16 %t4 = icmp slt i32 %t0, %t1 @@ -100,11 +82,8 @@ define i32 @select_by_icmp_ule(i32 %t0, i32 %t1, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_ule: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 t0, 65535 -; CHECK-NEXT: ori32 t0, t0, 65526 -; CHECK-NEXT: addu16 a2, t0 ; CHECK-NEXT: cmphs16 a1, a0 -; CHECK-NEXT: movt32 a3, a2 +; CHECK-NEXT: dect32 a3, a2, 10 ; CHECK-NEXT: mov16 a0, a3 ; CHECK-NEXT: rts16 %t4 = icmp ule i32 %t0, %t1 @@ -116,11 +95,8 @@ define i32 @select_by_icmp_sle(i32 %t0, i32 %t1, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_sle: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 t0, 65535 -; CHECK-NEXT: ori32 t0, t0, 65526 -; CHECK-NEXT: addu16 a2, t0 ; CHECK-NEXT: cmplt16 a1, a0 -; CHECK-NEXT: movf32 a3, a2 +; CHECK-NEXT: decf32 a3, a2, 10 ; CHECK-NEXT: mov16 a0, a3 ; CHECK-NEXT: rts16 %t4 = icmp sle i32 %t0, %t1 @@ -132,11 +108,8 @@ define i32 @select_by_icmp_ne(i32 %t0, i32 %t1, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_ne: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 t0, 65535 -; CHECK-NEXT: ori32 t0, t0, 65526 -; CHECK-NEXT: addu16 a2, t0 ; CHECK-NEXT: cmpne16 a0, a1 -; CHECK-NEXT: movt32 a3, a2 +; CHECK-NEXT: dect32 a3, a2, 10 ; CHECK-NEXT: mov16 a0, a3 ; CHECK-NEXT: rts16 %t4 = icmp ne i32 %t0, %t1 @@ -148,11 +121,8 @@ define i32 @select_by_icmp_eq(i32 %t0, i32 %t1, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_eq: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 t0, 65535 -; CHECK-NEXT: ori32 t0, t0, 65526 -; CHECK-NEXT: addu16 a2, t0 ; CHECK-NEXT: cmpne16 a0, a1 -; CHECK-NEXT: movf32 a3, a2 +; CHECK-NEXT: decf32 a3, a2, 10 ; CHECK-NEXT: mov16 a0, a3 ; CHECK-NEXT: rts16 %t4 = icmp eq i32 %t0, %t1 @@ -164,12 +134,9 @@ define i32 @select_by_icmp_ugt_imm(i32 %t0, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_ugt_imm: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 a3, 65535 -; CHECK-NEXT: ori32 a3, a3, 65526 -; CHECK-NEXT: addu16 a1, a3 ; CHECK-NEXT: movi16 a3, 128 ; CHECK-NEXT: cmphs16 a3, a0 -; CHECK-NEXT: movf32 a2, a1 +; CHECK-NEXT: decf32 a2, a1, 10 ; CHECK-NEXT: mov16 a0, a2 ; CHECK-NEXT: rts16 %t4 = icmp ugt i32 %t0, 128 @@ -181,12 +148,9 @@ define i32 @select_by_icmp_sgt_imm(i32 %t0, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_sgt_imm: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 a3, 65535 -; CHECK-NEXT: ori32 a3, a3, 65526 -; CHECK-NEXT: addu16 a1, a3 ; CHECK-NEXT: movi16 a3, 128 ; CHECK-NEXT: cmplt16 a3, a0 -; CHECK-NEXT: movt32 a2, a1 +; CHECK-NEXT: dect32 a2, a1, 10 ; CHECK-NEXT: mov16 a0, a2 ; CHECK-NEXT: rts16 %t4 = icmp sgt i32 %t0, 128 @@ -198,12 +162,9 @@ define i32 @select_by_icmp_uge_imm(i32 %t0, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_uge_imm: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 a3, 65535 -; CHECK-NEXT: ori32 a3, a3, 65526 -; CHECK-NEXT: addu16 a1, a3 ; CHECK-NEXT: movi16 a3, 127 ; CHECK-NEXT: cmphs16 a3, a0 -; CHECK-NEXT: movf32 a2, a1 +; CHECK-NEXT: decf32 a2, a1, 10 ; CHECK-NEXT: mov16 a0, a2 ; CHECK-NEXT: rts16 %t4 = icmp uge i32 %t0, 128 @@ -215,12 +176,9 @@ define i32 @select_by_icmp_sge_imm(i32 %t0, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_sge_imm: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 a3, 65535 -; CHECK-NEXT: ori32 a3, a3, 65526 -; CHECK-NEXT: addu16 a1, a3 ; CHECK-NEXT: movi16 a3, 127 ; CHECK-NEXT: cmplt16 a3, a0 -; CHECK-NEXT: movt32 a2, a1 +; CHECK-NEXT: dect32 a2, a1, 10 ; CHECK-NEXT: mov16 a0, a2 ; CHECK-NEXT: rts16 %t4 = icmp sge i32 %t0, 128 @@ -232,11 +190,8 @@ define i32 @select_by_icmp_ult_imm(i32 %t0, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_ult_imm: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 a3, 65535 -; CHECK-NEXT: ori32 a3, a3, 65526 -; CHECK-NEXT: addu16 a1, a3 ; CHECK-NEXT: cmphsi32 a0, 128 -; CHECK-NEXT: movf32 a2, a1 +; CHECK-NEXT: decf32 a2, a1, 10 ; CHECK-NEXT: mov16 a0, a2 ; CHECK-NEXT: rts16 %t4 = icmp ult i32 %t0, 128 @@ -248,11 +203,8 @@ define i32 @select_by_icmp_slt_imm(i32 %t0, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_slt_imm: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 a3, 65535 -; CHECK-NEXT: ori32 a3, a3, 65526 -; CHECK-NEXT: addu16 a1, a3 ; CHECK-NEXT: cmplti32 a0, 128 -; CHECK-NEXT: movt32 a2, a1 +; CHECK-NEXT: dect32 a2, a1, 10 ; CHECK-NEXT: mov16 a0, a2 ; CHECK-NEXT: rts16 %t4 = icmp slt i32 %t0, 128 @@ -264,11 +216,8 @@ define i32 @select_by_icmp_ule_imm(i32 %t0, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_ule_imm: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 a3, 65535 -; CHECK-NEXT: ori32 a3, a3, 65526 -; CHECK-NEXT: addu16 a1, a3 ; CHECK-NEXT: cmphsi32 a0, 129 -; CHECK-NEXT: movf32 a2, a1 +; CHECK-NEXT: decf32 a2, a1, 10 ; CHECK-NEXT: mov16 a0, a2 ; CHECK-NEXT: rts16 %t4 = icmp ule i32 %t0, 128 @@ -280,11 +229,8 @@ define i32 @select_by_icmp_sle_imm(i32 %t0, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_sle_imm: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 a3, 65535 -; CHECK-NEXT: ori32 a3, a3, 65526 -; CHECK-NEXT: addu16 a1, a3 ; CHECK-NEXT: cmplti32 a0, 129 -; CHECK-NEXT: movt32 a2, a1 +; CHECK-NEXT: dect32 a2, a1, 10 ; CHECK-NEXT: mov16 a0, a2 ; CHECK-NEXT: rts16 %t4 = icmp sle i32 %t0, 128 @@ -296,11 +242,8 @@ define i32 @select_by_icmp_ne_imm(i32 %t0, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_ne_imm: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 a3, 65535 -; CHECK-NEXT: ori32 a3, a3, 65526 -; CHECK-NEXT: addu16 a1, a3 ; CHECK-NEXT: cmpnei32 a0, 128 -; CHECK-NEXT: movt32 a2, a1 +; CHECK-NEXT: dect32 a2, a1, 10 ; CHECK-NEXT: mov16 a0, a2 ; CHECK-NEXT: rts16 %t4 = icmp ne i32 %t0, 128 @@ -312,11 +255,8 @@ define i32 @select_by_icmp_eq_imm(i32 %t0, i32 %t2, i32 %t3) { ; CHECK-LABEL: select_by_icmp_eq_imm: ; CHECK: # %bb.0: -; CHECK-NEXT: movih32 a3, 65535 -; CHECK-NEXT: ori32 a3, a3, 65526 -; CHECK-NEXT: addu16 a1, a3 ; CHECK-NEXT: cmpnei32 a0, 128 -; CHECK-NEXT: movf32 a2, a1 +; CHECK-NEXT: decf32 a2, a1, 10 ; CHECK-NEXT: mov16 a0, a2 ; CHECK-NEXT: rts16 %t4 = icmp eq i32 %t0, 128 @@ -340,11 +280,8 @@ ; CHECK-NEXT: mov16 l0, a2 ; CHECK-NEXT: mov16 l1, a1 ; CHECK-NEXT: jsri32 [.LCPI20_0] -; CHECK-NEXT: movih32 a1, 65535 -; CHECK-NEXT: ori32 a1, a1, 65526 -; CHECK-NEXT: addu16 a1, l1 ; CHECK-NEXT: btsti16 a0, 0 -; CHECK-NEXT: movt32 l0, a1 +; CHECK-NEXT: dect32 l0, l1, 10 ; CHECK-NEXT: mov16 a0, l0 ; CHECK-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload ; CHECK-NEXT: ld16.w l0, (sp, 4) # 4-byte Folded Reload @@ -377,12 +314,9 @@ ; CHECK-NEXT: mov16 l0, a2 ; CHECK-NEXT: mov16 l1, a1 ; CHECK-NEXT: jsri32 [.LCPI21_0] -; CHECK-NEXT: movih32 a1, 65535 -; CHECK-NEXT: ori32 a1, a1, 65526 -; CHECK-NEXT: addu16 a1, l1 ; CHECK-NEXT: btsti16 a0, 0 -; CHECK-NEXT: movt32 a1, l0 -; CHECK-NEXT: mov16 a0, a1 +; CHECK-NEXT: decf32 l0, l1, 10 +; CHECK-NEXT: mov16 a0, l0 ; CHECK-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload ; CHECK-NEXT: ld16.w l0, (sp, 4) # 4-byte Folded Reload ; CHECK-NEXT: ld16.w l1, (sp, 8) # 4-byte Folded Reload