diff --git a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll @@ -0,0 +1,1049 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck %s + +; The tests check the following optimization of DAGCombiner: +; CMP(A,C)||CMP(B,C) => CMP(MIN/MAX(A,B), C) +; CMP(A,C)&&CMP(B,C) => CMP(MIN/MAX(A,B), C) + +define i1 @test1(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test1: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0 +; CHECK-NEXT: v_cmp_gt_i32_e64 s0, 0x3e8, v1 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp slt i32 %arg1, 1000 + %cmp2 = icmp slt i32 %arg2, 1000 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test2(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test2: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x3e8, v0 +; CHECK-NEXT: v_cmp_gt_u32_e64 s0, 0x3e8, v1 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ult i32 %arg1, 1000 + %cmp2 = icmp ult i32 %arg2, 1000 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test3(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test3: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0x3e9, v0 +; CHECK-NEXT: v_cmp_gt_i32_e64 s0, 0x3e9, v1 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sle i32 %arg1, 1000 + %cmp2 = icmp sle i32 %arg2, 1000 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test4(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test4: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x3e9, v0 +; CHECK-NEXT: v_cmp_gt_u32_e64 s0, 0x3e9, v1 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ule i32 %arg1, 1000 + %cmp2 = icmp ule i32 %arg2, 1000 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test5(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test5: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0x3e8, v0 +; CHECK-NEXT: v_cmp_lt_i32_e64 s0, 0x3e8, v1 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sgt i32 %arg1, 1000 + %cmp2 = icmp sgt i32 %arg2, 1000 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test6(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test6: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3e8, v0 +; CHECK-NEXT: v_cmp_lt_u32_e64 s0, 0x3e8, v1 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ugt i32 %arg1, 1000 + %cmp2 = icmp ugt i32 %arg2, 1000 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test7(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test7: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v0 +; CHECK-NEXT: v_cmp_lt_i32_e64 s0, 0x3e7, v1 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sge i32 %arg1, 1000 + %cmp2 = icmp sge i32 %arg2, 1000 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test8(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test8: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3e7, v0 +; CHECK-NEXT: v_cmp_lt_u32_e64 s0, 0x3e7, v1 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp uge i32 %arg1, 1000 + %cmp2 = icmp uge i32 %arg2, 1000 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test9(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test9: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_lt_i32_e64 s0, v1, v2 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp slt i32 %arg1, %arg3 + %cmp2 = icmp slt i32 %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test10(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test10: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_lt_u32_e64 s0, v1, v2 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ult i32 %arg1, %arg3 + %cmp2 = icmp ult i32 %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test11(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test11: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_le_i32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_le_i32_e64 s0, v1, v2 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sle i32 %arg1, %arg3 + %cmp2 = icmp sle i32 %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test12(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test12: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_le_u32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_le_u32_e64 s0, v1, v2 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ule i32 %arg1, %arg3 + %cmp2 = icmp ule i32 %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test13(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test13: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_gt_i32_e64 s0, v1, v2 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sgt i32 %arg1, %arg3 + %cmp2 = icmp sgt i32 %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test14(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test14: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_gt_u32_e64 s0, v1, v2 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ugt i32 %arg1, %arg3 + %cmp2 = icmp ugt i32 %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test15(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test15: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_ge_i32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_ge_i32_e64 s0, v1, v2 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sge i32 %arg1, %arg3 + %cmp2 = icmp sge i32 %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test16(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test16: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_ge_u32_e64 s0, v1, v2 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp uge i32 %arg1, %arg3 + %cmp2 = icmp uge i32 %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test17(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test17: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0 +; CHECK-NEXT: v_cmp_gt_i32_e64 s0, 0x3e8, v1 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp slt i32 %arg1, 1000 + %cmp2 = icmp slt i32 %arg2, 1000 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test18(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test18: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x3e8, v0 +; CHECK-NEXT: v_cmp_gt_u32_e64 s0, 0x3e8, v1 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ult i32 %arg1, 1000 + %cmp2 = icmp ult i32 %arg2, 1000 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test19(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test19: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0x3e9, v0 +; CHECK-NEXT: v_cmp_gt_i32_e64 s0, 0x3e9, v1 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sle i32 %arg1, 1000 + %cmp2 = icmp sle i32 %arg2, 1000 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test20(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test20: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x3e9, v0 +; CHECK-NEXT: v_cmp_gt_u32_e64 s0, 0x3e9, v1 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ule i32 %arg1, 1000 + %cmp2 = icmp ule i32 %arg2, 1000 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test21(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test21: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0x3e8, v0 +; CHECK-NEXT: v_cmp_lt_i32_e64 s0, 0x3e8, v1 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sgt i32 %arg1, 1000 + %cmp2 = icmp sgt i32 %arg2, 1000 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test22(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test22: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3e8, v0 +; CHECK-NEXT: v_cmp_lt_u32_e64 s0, 0x3e8, v1 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ugt i32 %arg1, 1000 + %cmp2 = icmp ugt i32 %arg2, 1000 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test23(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test23: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v0 +; CHECK-NEXT: v_cmp_lt_i32_e64 s0, 0x3e7, v1 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sge i32 %arg1, 1000 + %cmp2 = icmp sge i32 %arg2, 1000 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test24(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test24: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3e7, v0 +; CHECK-NEXT: v_cmp_lt_u32_e64 s0, 0x3e7, v1 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp uge i32 %arg1, 1000 + %cmp2 = icmp uge i32 %arg2, 1000 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test25(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test25: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_lt_i32_e64 s0, v1, v2 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp slt i32 %arg1, %arg3 + %cmp2 = icmp slt i32 %arg2, %arg3 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test26(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test26: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_lt_u32_e64 s0, v1, v2 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ult i32 %arg1, %arg3 + %cmp2 = icmp ult i32 %arg2, %arg3 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test27(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test27: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_le_i32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_le_i32_e64 s0, v1, v2 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sle i32 %arg1, %arg3 + %cmp2 = icmp sle i32 %arg2, %arg3 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test28(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test28: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_le_u32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_le_u32_e64 s0, v1, v2 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ule i32 %arg1, %arg3 + %cmp2 = icmp ule i32 %arg2, %arg3 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test29(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test29: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_gt_i32_e64 s0, v1, v2 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sgt i32 %arg1, %arg3 + %cmp2 = icmp sgt i32 %arg2, %arg3 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test30(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test30: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_gt_u32_e64 s0, v1, v2 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ugt i32 %arg1, %arg3 + %cmp2 = icmp ugt i32 %arg2, %arg3 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test31(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test31: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_ge_i32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_ge_i32_e64 s0, v1, v2 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sge i32 %arg1, %arg3 + %cmp2 = icmp sge i32 %arg2, %arg3 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test32(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_ge_u32_e64 s0, v1, v2 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp uge i32 %arg1, %arg3 + %cmp2 = icmp uge i32 %arg2, %arg3 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test33(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test33: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v1 +; CHECK-NEXT: v_cmp_gt_i32_e64 s0, 0x3e8, v0 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp slt i32 %arg1, %arg2 + %cmp2 = icmp slt i32 %arg1, 1000 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test34(i32 %arg1, i64 %arg2) { +; CHECK-LABEL: test34: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_mov_b64 s[0:1], 0x3e8 +; CHECK-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[1:2] +; CHECK-NEXT: v_cmp_gt_i32_e64 s0, 0x3e8, v0 +; CHECK-NEXT: s_or_b32 s0, s0, vcc_lo +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp slt i32 %arg1, 1000 + %cmp2 = icmp slt i64 %arg2, 1000 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test35(i32 %arg1, i64 %arg2) { +; CHECK-LABEL: test35: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_mov_b64 s[0:1], 0x3e8 +; CHECK-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[0:1], v[1:2] +; CHECK-NEXT: v_cmp_eq_u32_e64 s0, 0x3e8, v0 +; CHECK-NEXT: s_or_b32 s0, s0, vcc_lo +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp eq i32 %arg1, 1000 + %cmp2 = icmp eq i64 %arg2, 1000 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test36(i32 %arg1, i64 %arg2) { +; CHECK-LABEL: test36: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_mov_b64 s[0:1], 0x3e8 +; CHECK-NEXT: v_cmp_ne_u64_e32 vcc_lo, s[0:1], v[1:2] +; CHECK-NEXT: v_cmp_ne_u32_e64 s0, 0x3e8, v0 +; CHECK-NEXT: s_or_b32 s0, s0, vcc_lo +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ne i32 %arg1, 1000 + %cmp2 = icmp ne i64 %arg2, 1000 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define amdgpu_gfx void @test37(i32 inreg %arg1, i32 inreg %arg2) { +; CHECK-LABEL: test37: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_cmpk_lt_i32 s4, 0x3e9 +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: s_cselect_b32 s0, -1, 0 +; CHECK-NEXT: s_cmpk_lt_i32 s5, 0x3e9 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: s_cselect_b32 s1, -1, 0 +; CHECK-NEXT: s_or_b32 s0, s0, s1 +; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 +; CHECK-NEXT: global_store_b8 v[0:1], v2, off dlc +; CHECK-NEXT: s_waitcnt_vscnt null, 0x0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sle i32 %arg1, 1000 + %cmp2 = icmp sle i32 %arg2, 1000 + %or = or i1 %cmp1, %cmp2 + store volatile i1 %or, ptr addrspace(1) null + ret void +} + +define amdgpu_gfx void @test38(i32 inreg %arg1, i32 inreg %arg2) { +; CHECK-LABEL: test38: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_cmpk_gt_i32 s4, 0x3e8 +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: s_cselect_b32 s0, -1, 0 +; CHECK-NEXT: s_cmpk_gt_i32 s5, 0x3e8 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: s_cselect_b32 s1, -1, 0 +; CHECK-NEXT: s_or_b32 s0, s0, s1 +; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 +; CHECK-NEXT: global_store_b8 v[0:1], v2, off dlc +; CHECK-NEXT: s_waitcnt_vscnt null, 0x0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sgt i32 %arg1, 1000 + %cmp2 = icmp sgt i32 %arg2, 1000 + %or = or i1 %cmp1, %cmp2 + store volatile i1 %or, ptr addrspace(1) null + ret void +} + +define amdgpu_gfx void @test39(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) { +; CHECK-LABEL: test39: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_cmp_lt_u32 s4, s6 +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: s_cselect_b32 s0, -1, 0 +; CHECK-NEXT: s_cmp_lt_u32 s5, s6 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: s_cselect_b32 s1, -1, 0 +; CHECK-NEXT: s_or_b32 s0, s0, s1 +; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 +; CHECK-NEXT: global_store_b8 v[0:1], v2, off dlc +; CHECK-NEXT: s_waitcnt_vscnt null, 0x0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ult i32 %arg1, %arg3 + %cmp2 = icmp ult i32 %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + store volatile i1 %or, ptr addrspace(1) null + ret void +} + +define amdgpu_gfx void @test40(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) { +; CHECK-LABEL: test40: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_cmp_ge_i32 s4, s6 +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: s_cselect_b32 s0, -1, 0 +; CHECK-NEXT: s_cmp_ge_i32 s5, s6 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: s_cselect_b32 s1, -1, 0 +; CHECK-NEXT: s_or_b32 s0, s0, s1 +; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 +; CHECK-NEXT: global_store_b8 v[0:1], v2, off dlc +; CHECK-NEXT: s_waitcnt_vscnt null, 0x0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sge i32 %arg1, %arg3 + %cmp2 = icmp sge i32 %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + store volatile i1 %or, ptr addrspace(1) null + ret void +} + +define amdgpu_gfx void @test41(i32 inreg %arg1, i32 inreg %arg2) { +; CHECK-LABEL: test41: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_cmpk_lt_u32 s4, 0x3e9 +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: s_cselect_b32 s0, -1, 0 +; CHECK-NEXT: s_cmpk_lt_u32 s5, 0x3e9 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: s_cselect_b32 s1, -1, 0 +; CHECK-NEXT: s_and_b32 s0, s0, s1 +; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 +; CHECK-NEXT: global_store_b8 v[0:1], v2, off dlc +; CHECK-NEXT: s_waitcnt_vscnt null, 0x0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ule i32 %arg1, 1000 + %cmp2 = icmp ule i32 %arg2, 1000 + %and = and i1 %cmp1, %cmp2 + store volatile i1 %and, ptr addrspace(1) null + ret void +} + +define amdgpu_gfx void @test42(i32 inreg %arg1, i32 inreg %arg2) { +; CHECK-LABEL: test42: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_cmpk_gt_i32 s4, 0x3e7 +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: s_cselect_b32 s0, -1, 0 +; CHECK-NEXT: s_cmpk_gt_i32 s5, 0x3e7 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: s_cselect_b32 s1, -1, 0 +; CHECK-NEXT: s_and_b32 s0, s0, s1 +; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 +; CHECK-NEXT: global_store_b8 v[0:1], v2, off dlc +; CHECK-NEXT: s_waitcnt_vscnt null, 0x0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sge i32 %arg1, 1000 + %cmp2 = icmp sge i32 %arg2, 1000 + %and = and i1 %cmp1, %cmp2 + store volatile i1 %and, ptr addrspace(1) null + ret void +} + +define amdgpu_gfx void @test43(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) { +; CHECK-LABEL: test43: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_cmp_le_i32 s4, s6 +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: s_cselect_b32 s0, -1, 0 +; CHECK-NEXT: s_cmp_le_i32 s5, s6 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: s_cselect_b32 s1, -1, 0 +; CHECK-NEXT: s_and_b32 s0, s0, s1 +; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 +; CHECK-NEXT: global_store_b8 v[0:1], v2, off dlc +; CHECK-NEXT: s_waitcnt_vscnt null, 0x0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sle i32 %arg1, %arg3 + %cmp2 = icmp sle i32 %arg2, %arg3 + %and = and i1 %cmp1, %cmp2 + store volatile i1 %and, ptr addrspace(1) null + ret void +} + +define amdgpu_gfx void @test44(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) { +; CHECK-LABEL: test44: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_cmp_ge_u32 s4, s6 +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: s_cselect_b32 s0, -1, 0 +; CHECK-NEXT: s_cmp_ge_u32 s5, s6 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: s_cselect_b32 s1, -1, 0 +; CHECK-NEXT: s_and_b32 s0, s0, s1 +; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 +; CHECK-NEXT: global_store_b8 v[0:1], v2, off dlc +; CHECK-NEXT: s_waitcnt_vscnt null, 0x0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp uge i32 %arg1, %arg3 + %cmp2 = icmp uge i32 %arg2, %arg3 + %and = and i1 %cmp1, %cmp2 + store volatile i1 %and, ptr addrspace(1) null + ret void +} + +define i1 @test45(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test45: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v2, v0 +; CHECK-NEXT: v_cmp_lt_u32_e64 s0, v2, v1 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ult i32 %arg3, %arg1 + %cmp2 = icmp ult i32 %arg3, %arg2 + %or = and i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test46(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test46: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v2, v0 +; CHECK-NEXT: v_cmp_lt_u32_e64 s0, v2, v1 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ult i32 %arg3, %arg1 + %cmp2 = icmp ult i32 %arg3, %arg2 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + + +define i1 @test47(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test47: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, v2, v0 +; CHECK-NEXT: v_cmp_gt_u32_e64 s0, v2, v1 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ugt i32 %arg3, %arg1 + %cmp2 = icmp ugt i32 %arg3, %arg2 + %or = and i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test48(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test48: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, v2, v0 +; CHECK-NEXT: v_cmp_gt_u32_e64 s0, v2, v1 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ugt i32 %arg3, %arg1 + %cmp2 = icmp ugt i32 %arg3, %arg2 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test49(i64 %arg1, i64 %arg2, i64 %arg3) { +; CHECK-LABEL: test49: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5] +; CHECK-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[4:5] +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ult i64 %arg1, %arg3 + %cmp2 = icmp ult i64 %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test50(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test50: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, v2, v0 +; CHECK-NEXT: v_cmp_gt_i32_e64 s0, v1, v2 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp slt i32 %arg3, %arg1 + %cmp2 = icmp sgt i32 %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test51(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test51: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_lt_i32_e64 s0, v2, v1 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sgt i32 %arg1, %arg3 + %cmp2 = icmp slt i32 %arg3, %arg2 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test52(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test52: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_gt_i32_e64 s0, v2, v1 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp slt i32 %arg1, %arg3 + %cmp2 = icmp sgt i32 %arg3, %arg2 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test53(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test53: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, v2, v0 +; CHECK-NEXT: v_cmp_lt_i32_e64 s0, v1, v2 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sgt i32 %arg3, %arg1 + %cmp2 = icmp slt i32 %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test54(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test54: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, v2, v0 +; CHECK-NEXT: v_cmp_gt_i32_e64 s0, v1, v2 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp slt i32 %arg3, %arg1 + %cmp2 = icmp sgt i32 %arg2, %arg3 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test55(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test55: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_lt_i32_e64 s0, v2, v1 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sgt i32 %arg1, %arg3 + %cmp2 = icmp slt i32 %arg3, %arg2 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test56(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test56: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_gt_i32_e64 s0, v2, v1 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp slt i32 %arg1, %arg3 + %cmp2 = icmp sgt i32 %arg3, %arg2 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +define i1 @test57(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test57: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, v2, v0 +; CHECK-NEXT: v_cmp_lt_i32_e64 s0, v1, v2 +; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp sgt i32 %arg3, %arg1 + %cmp2 = icmp slt i32 %arg2, %arg3 + %and = and i1 %cmp1, %cmp2 + ret i1 %and +} + +; The optimization does not apply to the following tests. + +define i1 @test58(float %arg1, float %arg2, float %arg3) { +; CHECK-LABEL: test58: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_nge_f32_e64 s0, v1, v2 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp ult float %arg1, %arg3 + %cmp2 = fcmp ult float %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test59(double %arg1, double %arg2, double %arg3) { +; CHECK-LABEL: test59: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5] +; CHECK-NEXT: v_cmp_nge_f64_e64 s0, v[2:3], v[4:5] +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp ult double %arg1, %arg3 + %cmp2 = fcmp ult double %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test60(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test60: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_lt_u32_e64 s0, v2, v1 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ult i32 %arg1, %arg3 + %cmp2 = icmp ult i32 %arg3, %arg2 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test61(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test61: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_le_u32_e64 s0, v1, v2 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ult i32 %arg1, %arg3 + %cmp2 = icmp ule i32 %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test62(i32 %arg1, i32 %arg2, i32 %arg3) { +; CHECK-LABEL: test62: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_le_u32_e32 vcc_lo, v2, v0 +; CHECK-NEXT: v_cmp_gt_u32_e64 s0, v1, v2 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ule i32 %arg3, %arg1 + %cmp2 = icmp ugt i32 %arg2, %arg3 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test63(i16 %arg1, i32 %arg2) { +; CHECK-LABEL: test63: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_u16_e32 vcc_lo, 10, v0 +; CHECK-NEXT: v_cmp_gt_u32_e64 s0, 10, v1 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ult i16 %arg1, 10 + %cmp2 = icmp ult i32 %arg2, 10 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +} + +define i1 @test64(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) { +; CHECK-LABEL: test64: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2 +; CHECK-NEXT: v_cmp_lt_u32_e64 s0, v1, v2 +; CHECK-NEXT: v_cmp_lt_u32_e64 s1, v0, v3 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: s_or_b32 s1, s1, vcc_lo +; CHECK-NEXT: s_or_b32 s0, s0, s1 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ult i32 %arg1, %arg3 + %cmp2 = icmp ult i32 %arg2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + %cmp3 = icmp ult i32 %arg1, %arg4 + %or2 = or i1 %cmp3, %cmp1 + %or3 = or i1 %or1, %or2 + ret i1 %or3 +} + +define i1 @test65(i32 %arg1, i32 %arg2) { +; CHECK-LABEL: test65: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x64, v0 +; CHECK-NEXT: v_cmp_gt_u32_e64 s0, 0x3e8, v1 +; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %cmp1 = icmp ult i32 %arg1, 100 + %cmp2 = icmp ult i32 %arg2, 1000 + %or = or i1 %cmp1, %cmp2 + ret i1 %or +}