diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -738,6 +738,12 @@ ReadVMask]>; } +multiclass VREDMINMAX_FV_V funct6> { + def _VS : VALUVV, + Sched<[WriteVFRedMinMaxV_From_WorstCase, ReadVFRedV, ReadVFRedV0, + ReadVMask]>; +} + multiclass VREDO_FV_V funct6> { def _VS : VALUVV, Sched<[WriteVFRedOV_From_WorstCase, ReadVFRedOV, ReadVFRedOV0, @@ -1514,8 +1520,8 @@ defm VFREDUSUM : VRED_FV_V<"vfredusum", 0b000001>; } let mayRaiseFPException = true in { -defm VFREDMAX : VRED_FV_V<"vfredmax", 0b000111>; -defm VFREDMIN : VRED_FV_V<"vfredmin", 0b000101>; +defm VFREDMAX : VREDMINMAX_FV_V<"vfredmax", 0b000111>; +defm VFREDMIN : VREDMINMAX_FV_V<"vfredmin", 0b000101>; } } // RVVConstraint = NoConstraint diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -3456,6 +3456,18 @@ } } +multiclass VPseudoVFREDMINMAX_VS { + foreach m = MxListF in { + defvar mx = m.MX; + foreach e = SchedSEWSet.val in { + defvar WriteVFRedMinMaxV_From_MX_E = !cast("WriteVFRedMinMaxV_From_" # mx # "_E" # e); + defm _VS : VPseudoTernaryWithTailPolicy, + Sched<[WriteVFRedMinMaxV_From_MX_E, ReadVFRedV, ReadVFRedV, ReadVFRedV, + ReadVMask]>; + } + } +} + multiclass VPseudoVFREDO_VS { foreach m = MxListF in { defvar mx = m.MX; @@ -6152,8 +6164,8 @@ defm PseudoVFREDUSUM : VPseudoVFRED_VS; } let mayRaiseFPException = true in { -defm PseudoVFREDMIN : VPseudoVFRED_VS; -defm PseudoVFREDMAX : VPseudoVFRED_VS; +defm PseudoVFREDMIN : VPseudoVFREDMINMAX_VS; +defm PseudoVFREDMAX : VPseudoVFREDMINMAX_VS; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -628,6 +628,7 @@ defm "" : LMULSEWWriteRes<"WriteVIWRedV_From", [SiFive7VA]>; defm "" : LMULSEWWriteRes<"WriteVFRedV_From", [SiFive7VA]>; defm "" : LMULSEWWriteRes<"WriteVFRedOV_From", [SiFive7VA]>; +defm "" : LMULSEWWriteResF<"WriteVFRedMinMaxV_From", [SiFive7VA]>; defm "" : LMULSEWWriteResFWRed<"WriteVFWRedV_From", [SiFive7VA]>; defm "" : LMULSEWWriteResFWRed<"WriteVFWRedOV_From", [SiFive7VA]>; } diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td --- a/llvm/lib/Target/RISCV/RISCVScheduleV.td +++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td @@ -409,6 +409,7 @@ // 14.3. Vector Single-Width Floating-Point Reduction Instructions defm "" : LMULSEWSchedWritesF<"WriteVFRedV_From">; defm "" : LMULSEWSchedWritesF<"WriteVFRedOV_From">; +defm "" : LMULSEWSchedWritesF<"WriteVFRedMinMaxV_From">; // 14.4. Vector Widening Floating-Point Reduction Instructions defm "" : LMULSEWSchedWritesFWRed<"WriteVFWRedV_From">; defm "" : LMULSEWSchedWritesFWRed<"WriteVFWRedOV_From">; @@ -633,6 +634,7 @@ def ReadVFRedV0 : SchedRead; def ReadVFRedOV : SchedRead; def ReadVFRedOV0 : SchedRead; +def ReadVFRedMinMaxV : SchedRead; // 14.4. Vector Widening Floating-Point Reduction Instructions def ReadVFWRedV : SchedRead; def ReadVFWRedV0 : SchedRead; @@ -847,6 +849,7 @@ defm "" : LMULSEWWriteResWRed<"WriteVIWRedV_From", []>; defm "" : LMULSEWWriteResF<"WriteVFRedV_From", []>; defm "" : LMULSEWWriteResF<"WriteVFRedOV_From", []>; +defm "" : LMULSEWWriteResF<"WriteVFRedMinMaxV_From", []>; defm "" : LMULSEWWriteResFWRed<"WriteVFWRedV_From", []>; defm "" : LMULSEWWriteResFWRed<"WriteVFWRedOV_From", []>; @@ -1006,6 +1009,7 @@ def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; +def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance;