Index: llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -399,7 +399,8 @@
             ExtendOp = TargetOpcode::G_ZEXT;
 
           LLT NewLLT(NewVT);
-          LLT OldLLT(MVT::getVT(CurArgInfo.Ty));
+          MVT OldVT = MVT::getVT(CurArgInfo.Ty);
+          LLT OldLLT(OldVT);
           CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx);
           // Instead of an extend, we might have a vector type which needs
           // padding with more elements, e.g. <2 x half> -> <4 x half>.
@@ -416,10 +417,13 @@
                 CurVReg =
                     MIRBuilder.buildMergeLikeInstr({NewLLT}, {CurVReg, Undef})
                         .getReg(0);
-              } else {
+              } else if (OldVT.isInteger() && NewVT.isInteger()) {
                 // Just do a vector extend.
                 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
                               .getReg(0);
+              } else {
+                LLVM_DEBUG(dbgs() << "Could not handle float type\n");
+                return false;
               }
             } else if (NewLLT.getNumElements() == 2) {
               // We need to pad a <1 x S> type to <2 x S>. Since we don't have
Index: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
===================================================================
--- llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -3199,14 +3199,17 @@
     const Register SrcReg = I.getOperand(1).getReg();
 
     const RegisterBank &RBDst = *RBI.getRegBank(DstReg, MRI, TRI);
-    if (RBDst.getID() != AArch64::GPRRegBankID) {
+    // The integer vector can be extend
+    if (RBDst.getID() != AArch64::GPRRegBankID &&
+        !MRI.getType(DstReg).isVector()) {
       LLVM_DEBUG(dbgs() << "G_ANYEXT on bank: " << RBDst
                         << ", expected: GPR\n");
       return false;
     }
 
     const RegisterBank &RBSrc = *RBI.getRegBank(SrcReg, MRI, TRI);
-    if (RBSrc.getID() != AArch64::GPRRegBankID) {
+    if (RBSrc.getID() != AArch64::GPRRegBankID &&
+        !MRI.getType(SrcReg).isVector()) {
       LLVM_DEBUG(dbgs() << "G_ANYEXT on bank: " << RBSrc
                         << ", expected: GPR\n");
       return false;
Index: llvm/test/CodeGen/AArch64/extract-sext-zext.ll
===================================================================
--- llvm/test/CodeGen/AArch64/extract-sext-zext.ll
+++ llvm/test/CodeGen/AArch64/extract-sext-zext.ll
@@ -494,3 +494,19 @@
   %u = xor i64 %s, %t
   ret i64 %u
 }
+
+define <2 x i16> @extend_v2i16() {
+; CHECK-ISEL-LABEL: extend_v2i16:
+; CHECK-ISEL:       // %bb.0:
+; CHECK-ISEL-NEXT:    movi v0.2d, #0000000000000000
+; CHECK-ISEL-NEXT:    ret
+;
+; CHECK-GLOBAL-LABEL: extend_v2i16:
+; CHECK-GLOBAL:       // %bb.0:
+; CHECK-GLOBAL-NEXT:    adrp x8, .LCPI42_0
+; CHECK-GLOBAL-NEXT:    ldr s0, [x8, :lo12:.LCPI42_0]
+; CHECK-GLOBAL-NEXT:    fmov w0, s0
+; CHECK-GLOBAL-NEXT:    fmov d0, x0
+; CHECK-GLOBAL-NEXT:    ret
+  ret <2 x i16> <i16 0, i16 0>
+}