diff --git a/llvm/lib/Passes/PassBuilderPipelines.cpp b/llvm/lib/Passes/PassBuilderPipelines.cpp
--- a/llvm/lib/Passes/PassBuilderPipelines.cpp
+++ b/llvm/lib/Passes/PassBuilderPipelines.cpp
@@ -1014,7 +1014,7 @@
     // Compare/branch metadata may alter the behavior of passes like
     // SimplifyCFG.
     EarlyFPM.addPass(LowerExpectIntrinsicPass());
-    EarlyFPM.addPass(SimplifyCFGPass());
+    EarlyFPM.addPass(SimplifyCFGPass(SimplifyCFGOptions().speculateBlocks(false)));
     EarlyFPM.addPass(SROAPass(SROAOptions::ModifyCFG));
     EarlyFPM.addPass(EarlyCSEPass());
     if (Level == OptimizationLevel::O3)
@@ -1082,7 +1082,7 @@
   GlobalCleanupPM.addPass(InstCombinePass());
   invokePeepholeEPCallbacks(GlobalCleanupPM, Level);
   GlobalCleanupPM.addPass(
-      SimplifyCFGPass(SimplifyCFGOptions().convertSwitchRangeToICmp(true)));
+      SimplifyCFGPass(SimplifyCFGOptions().convertSwitchRangeToICmp(true).speculateBlocks(false)));
   MPM.addPass(createModuleToFunctionPassAdaptor(std::move(GlobalCleanupPM),
                                                 PTO.EagerlyInvalidateAnalyses));
 
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll
--- a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll
@@ -409,7 +409,7 @@
 ; CHECK-NEXT:    [[TMP5:%.*]] = bitcast <8 x i1> [[TMP4]] to i8
 ; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i8 [[TMP5]], 0
 ; CHECK-NEXT:    [[SHIFT:%.*]] = shufflevector <4 x i32> [[T]], <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT:    [[TMP6:%.*]] = add nsw <4 x i32> [[SHIFT]], [[T]]
+; CHECK-NEXT:    [[TMP6:%.*]] = add nuw nsw <4 x i32> [[SHIFT]], [[T]]
 ; CHECK-NEXT:    [[ADD:%.*]] = extractelement <4 x i32> [[TMP6]], i64 0
 ; CHECK-NEXT:    [[CONV:%.*]] = sitofp i32 [[ADD]] to float
 ; CHECK-NEXT:    [[RETVAL_0:%.*]] = select i1 [[DOTNOT]], float [[CONV]], float 0.000000e+00
diff --git a/llvm/test/Transforms/PhaseOrdering/simplifycfg-jump-threading.ll b/llvm/test/Transforms/PhaseOrdering/simplifycfg-jump-threading.ll
--- a/llvm/test/Transforms/PhaseOrdering/simplifycfg-jump-threading.ll
+++ b/llvm/test/Transforms/PhaseOrdering/simplifycfg-jump-threading.ll
@@ -36,26 +36,7 @@
 ; CHECK-LABEL: define i32 @f
 ; CHECK-SAME: () local_unnamed_addr #[[ATTR0:[0-9]+]] {
 ; CHECK-NEXT:  bb:
-; CHECK-NEXT:    [[ALLOCA:%.*]] = alloca [3 x i32], align 4
-; CHECK-NEXT:    store i32 1, ptr [[ALLOCA]], align 4
-; CHECK-NEXT:    [[GETELEMENTPTR:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 1
-; CHECK-NEXT:    store i32 2, ptr [[GETELEMENTPTR]], align 4
-; CHECK-NEXT:    [[GETELEMENTPTR1:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 2
-; CHECK-NEXT:    store i32 3, ptr [[GETELEMENTPTR1]], align 4
-; CHECK-NEXT:    [[GETELEMENTPTR2:%.*]] = getelementptr inbounds i32, ptr [[ALLOCA]], i64 3
-; CHECK-NEXT:    br label [[BB11_I:%.*]]
-; CHECK:       bb11.i:
-; CHECK-NEXT:    [[PHI37_I:%.*]] = phi i32 [ [[ADD_I:%.*]], [[BB11_I]] ], [ 0, [[BB:%.*]] ]
-; CHECK-NEXT:    [[PHI6_I:%.*]] = phi ptr [ [[SPEC_SELECT_I:%.*]], [[BB11_I]] ], [ [[ALLOCA]], [[BB]] ]
-; CHECK-NEXT:    [[SPEC_SELECT_I]] = getelementptr i32, ptr [[PHI6_I]], i64 1
-; CHECK-NEXT:    [[LOAD_I:%.*]] = load i32, ptr [[PHI6_I]], align 4
-; CHECK-NEXT:    [[ADD_I]] = add i32 [[LOAD_I]], [[PHI37_I]]
-; CHECK-NEXT:    [[ICMP4_I:%.*]] = icmp ne ptr [[SPEC_SELECT_I]], [[GETELEMENTPTR2]]
-; CHECK-NEXT:    [[ICMP102_I:%.*]] = icmp ne ptr [[SPEC_SELECT_I]], null
-; CHECK-NEXT:    [[ICMP10_NOT_I:%.*]] = and i1 [[ICMP102_I]], [[ICMP4_I]]
-; CHECK-NEXT:    br i1 [[ICMP10_NOT_I]], label [[BB11_I]], label [[ZOT_EXIT:%.*]]
-; CHECK:       zot.exit:
-; CHECK-NEXT:    ret i32 [[ADD_I]]
+; CHECK-NEXT:    ret i32 6
 ;
 bb:
   %alloca = alloca [3 x i32], align 4