diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -112,7 +112,8 @@ // MCPU-SIFIVE-S76: "-nostdsysteminc" "-target-cpu" "sifive-s76" // MCPU-SIFIVE-S76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" // MCPU-SIFIVE-S76: "-target-feature" "+c" -// MCPU-SIFIVE-S76: "-target-feature" "+zicsr" "-target-feature" "+zifencei" +// MCPU-SIFIVE-S76: "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintpause" +// MCPU-SIFIVE-S76: "-target-feature" "+xsfcie" // MCPU-SIFIVE-S76: "-target-abi" "lp64d" // mcpu with default march diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -285,3 +285,6 @@ ``XCVmac`` LLVM implements `version 1.3.1 of the Core-V Multiply-Accumulate (MAC) custom instructions specification `_ by Core-V. All instructions are prefixed with `cv.mac.` as described in the specification. These instructions are only available for riscv32 at this time. + +``XSfcie`` + LLVM implements `version 1.0.0 of the SiFive Custom Instruction Extension (CIE) Software Specification `_ by SiFive. All custom instruction are added as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for S76 processor at this time. diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -206,6 +206,8 @@ extension disassembler/assembler. * Added support for the vendor-defined Xsfvcp (SiFive VCIX) extension disassembler/assembler. +* Added support for the vendor-defined Xsfcie (SiFive SCIE) extension + disassembler/assembler. * Support for the now-ratified Zawrs extension is no longer experimental. * Adds support for the vendor-defined XTHeadCmo (cache management operations) extension. * Adds support for the vendor-defined XTHeadSync (multi-core synchronization instructions) extension. diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -119,6 +119,7 @@ {"svinval", RISCVExtensionVersion{1, 0}}, // vendor-defined ('X') extensions + {"xsfcie", RISCVExtensionVersion{1, 0}}, {"xsfvcp", RISCVExtensionVersion{1, 0}}, {"xtheadba", RISCVExtensionVersion{1, 0}}, {"xtheadbb", RISCVExtensionVersion{1, 0}}, diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -558,6 +558,8 @@ "XTHeadVdot custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32, "SiFive VCIX custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32, + "SCIE custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip, DecoderTableXCVbitmanip32, "CORE-V Bit Manipulation custom opcode table"); diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -752,6 +752,12 @@ AssemblerPredicate<(all_of FeatureVendorXSfvcp), "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">; +def FeatureVendorXSfcie + : SubtargetFeature<"xsfcie", "HasVendorXSfcie", "true", + "'XSfcie' (SiFive Custom Instruction Extension SCIE.)">; +def HasVendorXSfcie : Predicate<"Subtarget->hasVendorXSfcie()">, + AssemblerPredicate<(all_of FeatureVendorXSfcie), + "'XSfcie' (SiFive Custom Instruction Extension SCIE.)">; def FeatureVendorXCVbitmanip : SubtargetFeature<"xcvbitmanip", "HasVendorXCVbitmanip", "true", diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td @@ -504,3 +504,27 @@ } } } + +let Predicates = [HasVendorXSfcie] in { +let hasSideEffects = 1, mayLoad = 0, mayStore = 0, DecoderNamespace = "XSfcie" in { +def SF_CFLUSH_D_L1 : RVInstI<0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), "cflush.d.l1","$rs1">, + Sched<[]> { + let rd = 0; + let imm12 = {0b1111,0b1100,0b0000}; +} + +def SF_CDISCARD_D_L1 : RVInstI<0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), "cdiscard.d.l1","$rs1">, + Sched<[]> { + let rd = 0; + let imm12 = {0b1111,0b1100,0b0010}; +} + +def SF_CEASE : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "cease","">, Sched<[]> { + let rs1 = 0; + let rd = 0; + let imm12 = {0b0011,0b0000,0b0101}; +} +} +def : InstAlias<"cflush.d.l1", (SF_CFLUSH_D_L1 X0)>; +def : InstAlias<"cdiscard.d.l1", (SF_CDISCARD_D_L1 X0)>; +} // Predicates = [HasVendorXScie] diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -142,7 +142,9 @@ FeatureStdExtA, FeatureStdExtF, FeatureStdExtD, - FeatureStdExtC], + FeatureStdExtC, + FeatureStdExtZihintpause, + FeatureVendorXSfcie], [TuneSiFive7]>; def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54", diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -278,3 +278,6 @@ .attribute arch, "rv32i_zvfbfwma0p6" # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0" + +.attribute arch, "rv64i_xsfcie" +# CHECK: attribute 5, "rv64i2p1_xsfcie1p0" diff --git a/llvm/test/MC/RISCV/xsfcie-invalid.s b/llvm/test/MC/RISCV/xsfcie-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/xsfcie-invalid.s @@ -0,0 +1,25 @@ +# SCIE - SiFive Custom Instructions Extension. +# RUN: not llvm-mc -triple riscv32 -mattr=-xsfcie < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv64 -mattr=-xsfcie < %s 2>&1 | FileCheck %s + +cflush.d.l1 0x10 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + +cdiscard.d.l1 0x10 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction + +cflush.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.) + +cdiscard.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.) + +cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.) + +cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.) + +cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.) + +cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.) + +cease x1 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction + +cease 0x10 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction + +cease # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.) diff --git a/llvm/test/MC/RISCV/xsfcie-valid.s b/llvm/test/MC/RISCV/xsfcie-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/xsfcie-valid.s @@ -0,0 +1,42 @@ +# SCIE - SiFive Custom Instructions Extension. +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xsfcie -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xsfcie < %s \ +# RUN: | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xsfcie < %s \ +# RUN: | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv64 -mcpu=sifive-s76 -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mcpu=sifive-s76 < %s \ +# RUN: | llvm-objdump --mcpu=sifive-s76 -M no-aliases -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s + +# CHECK-INST: cflush.d.l1 zero +# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc] +# CHECK-INST: cflush.d.l1 zero +# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc] +cflush.d.l1 x0 +cflush.d.l1 + +# CHECK-INST: cflush.d.l1 t2 +# CHECK-ENC: encoding: [0x73,0x80,0x03,0xfc] +cflush.d.l1 x7 + +# CHECK-INST: cdiscard.d.l1 zero +# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc] +# CHECK-INST: cdiscard.d.l1 zero +# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc] +cdiscard.d.l1 x0 +cdiscard.d.l1 + +# CHECK-INST: cdiscard.d.l1 t2 +# CHECK-ENC: encoding: [0x73,0x80,0x23,0xfc] +cdiscard.d.l1 x7 + +# CHECK-INST: cease +# CHECK-ENC: encoding: [0x73,0x00,0x50,0x30] +cease