Index: lib/Target/AArch64/AArch64InstrInfo.td =================================================================== --- lib/Target/AArch64/AArch64InstrInfo.td +++ lib/Target/AArch64/AArch64InstrInfo.td @@ -3811,6 +3811,11 @@ (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (i64 FPR64:$Rn), dsub))>; +def : Pat<(v4f16 (scalar_to_vector (f16 FPR16:$Rn))), + (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; +def : Pat<(v8f16 (scalar_to_vector (f16 FPR16:$Rn))), + (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; + def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))), (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>; def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))), Index: test/CodeGen/AArch64/fp16-v4-instructions.ll =================================================================== --- test/CodeGen/AArch64/fp16-v4-instructions.ll +++ test/CodeGen/AArch64/fp16-v4-instructions.ll @@ -218,4 +218,13 @@ ret <4 x half> %1 } +define void @test_insert_at_zero(half %a, <4 x half>* %b) #0 { +; CHECK-LABEL: test_insert_at_zero: +; CHECK-NEXT: str d0, [x0] +; CHECK-NEXT: ret + %1 = insertelement <4 x half> undef, half %a, i64 0 + store <4 x half> %1, <4 x half>* %b, align 4 + ret void +} + attributes #0 = { nounwind } Index: test/CodeGen/AArch64/fp16-v8-instructions.ll =================================================================== --- test/CodeGen/AArch64/fp16-v8-instructions.ll +++ test/CodeGen/AArch64/fp16-v8-instructions.ll @@ -358,4 +358,13 @@ ret <8 x half> %1 } +define void @test_insert_at_zero(half %a, <8 x half>* %b) #0 { +; CHECK-LABEL: test_insert_at_zero: +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ret + %1 = insertelement <8 x half> undef, half %a, i64 0 + store <8 x half> %1, <8 x half>* %b, align 4 + ret void +} + attributes #0 = { nounwind }