diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -1893,14 +1893,16 @@ VReg Op1Class, DAGOperand Op2Class, LMULInfo MInfo, - string Constraint = ""> { + string Constraint = "", + int sew = 0> { let VLMul = MInfo.value in { - def "_" # MInfo.MX : VPseudoBinaryNoMask; + defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); + def suffix : VPseudoBinaryNoMask; let ForceTailAgnostic = true in - def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask, - RISCVMaskedPseudo; + def suffix # "_MASK" : VPseudoBinaryMOutMask, + RISCVMaskedPseudo; } } @@ -1926,11 +1928,13 @@ multiclass VPseudoTiedBinary { + string Constraint = "", + int sew = 0> { let VLMul = MInfo.value in { - def "_" # MInfo.MX # "_TIED": VPseudoTiedBinaryNoMask; - def "_" # MInfo.MX # "_MASK_TIED" : VPseudoTiedBinaryMask; } } @@ -2027,9 +2031,9 @@ // * The destination EEW is greater than the source EEW, the source EMUL is // at least 1, and the overlap is in the highest-numbered part of the // destination register group is legal. Otherwise, it is illegal. -multiclass VPseudoBinaryW_VV { +multiclass VPseudoBinaryW_VV { defm _VV : VPseudoBinary; + "@earlyclobber $rd", sew>; } multiclass VPseudoBinaryW_VX { @@ -2037,26 +2041,26 @@ "@earlyclobber $rd">; } -multiclass VPseudoBinaryW_VF { +multiclass VPseudoBinaryW_VF { defm "_V" # f.FX : VPseudoBinary; + "@earlyclobber $rd", sew>; } -multiclass VPseudoBinaryW_WV { +multiclass VPseudoBinaryW_WV { defm _WV : VPseudoBinary; + "@earlyclobber $rd", sew>; defm _WV : VPseudoTiedBinary; + "@earlyclobber $rd", sew>; } multiclass VPseudoBinaryW_WX { defm "_WX" : VPseudoBinary; } -multiclass VPseudoBinaryW_WF { +multiclass VPseudoBinaryW_WF { defm "_W" # f.FX : VPseudoBinary; + f.fprclass, m, "", sew>; } // Narrowing instructions like vnsrl/vnsra/vnclip(u) don't need @earlyclobber @@ -2250,17 +2254,21 @@ multiclass VPseudoVRCP_V { foreach m = MxListF in { defvar mx = m.MX; - defvar WriteVFRecpV_MX = !cast("WriteVFRecpV_" # mx); - defvar ReadVFRecpV_MX = !cast("ReadVFRecpV_" # mx); + defvar sews = SchedSEWSet.val; + foreach e = sews in { + defvar WriteVFRecpV_MX_E = !cast("WriteVFRecpV_" # mx # "_E" # e); + defvar ReadVFRecpV_MX_E = !cast("ReadVFRecpV_" # mx # "_E" # e); - let VLMul = m.value in { - def "_V_" # mx : VPseudoUnaryNoMask, - Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>; - def "_V_" # mx # "_TU": VPseudoUnaryNoMaskTU, - Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>; - def "_V_" # mx # "_MASK" : VPseudoUnaryMaskTA, - RISCVMaskedPseudo, - Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>; + let VLMul = m.value in { + defvar suffix = "_V_" # mx # "_E" # e; + def suffix : VPseudoUnaryNoMask, + Sched<[WriteVFRecpV_MX_E, ReadVFRecpV_MX_E, ReadVMask]>; + def suffix # "_TU": VPseudoUnaryNoMaskTU, + Sched<[WriteVFRecpV_MX_E, ReadVFRecpV_MX_E, ReadVMask]>; + def suffix # "_MASK" : VPseudoUnaryMaskTA, + RISCVMaskedPseudo, + Sched<[WriteVFRecpV_MX_E, ReadVFRecpV_MX_E, ReadVMask]>; + } } } } @@ -2557,22 +2565,25 @@ multiclass VPseudoVFMUL_VV_VF { foreach m = MxListF in { defvar mx = m.MX; - defvar WriteVFMulV_MX = !cast("WriteVFMulV_" # mx); - defvar ReadVFMulV_MX = !cast("ReadVFMulV_" # mx); + defvar sews = SchedSEWSet.val; + foreach e = sews in { + defvar WriteVFMulV_MX_E = !cast("WriteVFMulV_" # mx # "_E" # e); + defvar ReadVFMulV_MX_E = !cast("ReadVFMulV_" # mx # "_E" # e); - defm "" : VPseudoBinaryFV_VV, - Sched<[WriteVFMulV_MX, ReadVFMulV_MX, ReadVFMulV_MX, ReadVMask]>; + defm "" : VPseudoBinaryFV_VV, + Sched<[WriteVFMulV_MX_E, ReadVFMulV_MX_E, ReadVFMulV_MX_E, ReadVMask]>; + } } foreach f = FPList in { foreach m = f.MxList in { defvar mx = m.MX; - defvar WriteVFMulF_MX = !cast("WriteVFMulF_" # mx); - defvar ReadVFMulV_MX = !cast("ReadVFMulV_" # mx); - defvar ReadVFMulF_MX = !cast("ReadVFMulF_" # mx); + defvar WriteVFMulF_MX_E = !cast("WriteVFMulF_" # mx # "_E" # f.SEW); + defvar ReadVFMulV_MX_E = !cast("ReadVFMulV_" # mx # "_E" # f.SEW); + defvar ReadVFMulF_MX_E = !cast("ReadVFMulF_" # mx # "_E" # f.SEW); - defm "" : VPseudoBinaryV_VF, - Sched<[WriteVFMulF_MX, ReadVFMulV_MX, ReadVFMulF_MX, ReadVMask]>; + defm "" : VPseudoBinaryV_VF, + Sched<[WriteVFMulF_MX_E, ReadVFMulV_MX_E, ReadVFMulF_MX_E, ReadVMask]>; } } } @@ -2681,21 +2692,25 @@ multiclass VPseudoVALU_VV_VF { foreach m = MxListF in { defvar mx = m.MX; - defvar WriteVFALUV_MX = !cast("WriteVFALUV_" # mx); - defvar ReadVFALUV_MX = !cast("ReadVFALUV_" # mx); + defvar sews = SchedSEWSet.val; + foreach e = sews in { + defvar suffix = "_" # mx # "_E" # e; + defvar WriteVFALUV_MX_E = !cast("WriteVFALUV" # suffix); + defvar ReadVFALUV_MX_E = !cast("ReadVFALUV" # suffix); - defm "" : VPseudoBinaryFV_VV, - Sched<[WriteVFALUV_MX, ReadVFALUV_MX, ReadVFALUV_MX, ReadVMask]>; + defm "" : VPseudoBinaryFV_VV, + Sched<[WriteVFALUV_MX_E, ReadVFALUV_MX_E, ReadVFALUV_MX_E, ReadVMask]>; + } } foreach f = FPList in { foreach m = f.MxList in { defvar mx = m.MX; - defvar WriteVFALUF_MX = !cast("WriteVFALUF_" # mx); - defvar ReadVFALUV_MX = !cast("ReadVFALUV_" # mx); - defvar ReadVFALUF_MX = !cast("ReadVFALUF_" # mx); - defm "" : VPseudoBinaryV_VF, - Sched<[WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX, ReadVMask]>; + defvar WriteVFALUF_MX_E = !cast("WriteVFALUF_" # mx # "_E" # f.SEW); + defvar ReadVFALUV_MX_E = !cast("ReadVFALUV_" # mx # "_E" # f.SEW); + defvar ReadVFALUF_MX_E = !cast("ReadVFALUF_" # mx # "_E" # f.SEW); + defm "" : VPseudoBinaryV_VF, + Sched<[WriteVFALUF_MX_E, ReadVFALUV_MX_E, ReadVFALUF_MX_E, ReadVMask]>; } } } @@ -2704,12 +2719,12 @@ foreach f = FPList in { foreach m = f.MxList in { defvar mx = m.MX; - defvar WriteVFALUF_MX = !cast("WriteVFALUF_" # mx); - defvar ReadVFALUV_MX = !cast("ReadVFALUV_" # mx); - defvar ReadVFALUF_MX = !cast("ReadVFALUF_" # mx); + defvar WriteVFALUF_MX_E = !cast("WriteVFALUF_" # mx # "_E" # f.SEW); + defvar ReadVFALUV_MX_E = !cast("ReadVFALUV_" # mx # "_E" # f.SEW); + defvar ReadVFALUF_MX_E = !cast("ReadVFALUF_" # mx # "_E" # f.SEW); - defm "" : VPseudoBinaryV_VF, - Sched<[WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX, ReadVMask]>; + defm "" : VPseudoBinaryV_VF, + Sched<[WriteVFALUF_MX_E, ReadVFALUV_MX_E, ReadVFALUF_MX_E, ReadVMask]>; } } } @@ -2762,22 +2777,28 @@ multiclass VPseudoVWMUL_VV_VF { foreach m = MxListFW in { defvar mx = m.MX; - defvar WriteVFWMulV_MX = !cast("WriteVFWMulV_" # mx); - defvar ReadVFWMulV_MX = !cast("ReadVFWMulV_" # mx); + defvar sews = SchedSEWSet.val; + foreach e = sews in { + defvar WriteVFWMulV_MX_E = !cast("WriteVFWMulV_" # mx # "_E" # e); + defvar ReadVFWMulV_MX_E = !cast("ReadVFWMulV_" # mx # "_E" # e); - defm "" : VPseudoBinaryW_VV, - Sched<[WriteVFWMulV_MX, ReadVFWMulV_MX, ReadVFWMulV_MX, ReadVMask]>; + defm "" : VPseudoBinaryW_VV, + Sched<[WriteVFWMulV_MX_E, ReadVFWMulV_MX_E, ReadVFWMulV_MX_E, ReadVMask]>; + } } foreach f = FPListW in { foreach m = f.MxListFW in { defvar mx = m.MX; - defvar WriteVFWMulF_MX = !cast("WriteVFWMulF_" # mx); - defvar ReadVFWMulV_MX = !cast("ReadVFWMulV_" # mx); - defvar ReadVFWMulF_MX = !cast("ReadVFWMulF_" # mx); + defvar sews = SchedSEWSet.val; + foreach e = sews in { + defvar WriteVFWMulF_MX_E = !cast("WriteVFWMulF_" # mx # "_E" # e); + defvar ReadVFWMulV_MX_E = !cast("ReadVFWMulV_" # mx # "_E" # e); + defvar ReadVFWMulF_MX_E = !cast("ReadVFWMulF_" # mx # "_E" # e); - defm "" : VPseudoBinaryW_VF, - Sched<[WriteVFWMulF_MX, ReadVFWMulV_MX, ReadVFWMulF_MX, ReadVMask]>; + defm "" : VPseudoBinaryW_VF, + Sched<[WriteVFWMulF_MX_E, ReadVFWMulV_MX_E, ReadVFWMulF_MX_E, ReadVMask]>; + } } } } @@ -2800,22 +2821,28 @@ multiclass VPseudoVFWALU_VV_VF { foreach m = MxListFW in { defvar mx = m.MX; - defvar WriteVFWALUV_MX = !cast("WriteVFWALUV_" # mx); - defvar ReadVFWALUV_MX = !cast("ReadVFWALUV_" # mx); + defvar sews = SchedSEWSet.val; + foreach e = sews in { + defvar WriteVFWALUV_MX_E = !cast("WriteVFWALUV_" # mx # "_E" # e); + defvar ReadVFWALUV_MX_E = !cast("ReadVFWALUV_" # mx # "_E" # e); - defm "" : VPseudoBinaryW_VV, - Sched<[WriteVFWALUV_MX, ReadVFWALUV_MX, ReadVFWALUV_MX, ReadVMask]>; + defm "" : VPseudoBinaryW_VV, + Sched<[WriteVFWALUV_MX_E, ReadVFWALUV_MX_E, ReadVFWALUV_MX_E, ReadVMask]>; + } } foreach f = FPListW in { foreach m = f.MxListFW in { defvar mx = m.MX; - defvar WriteVFWALUF_MX = !cast("WriteVFWALUF_" # mx); - defvar ReadVFWALUV_MX = !cast("ReadVFWALUV_" # mx); - defvar ReadVFWALUF_MX = !cast("ReadVFWALUF_" # mx); + defvar sews = SchedSEWSet.val; + foreach e = sews in { + defvar WriteVFWALUF_MX_E = !cast("WriteVFWALUF_" # mx # "_E" # e); + defvar ReadVFWALUV_MX_E = !cast("ReadVFWALUV_" # mx # "_E" # e); + defvar ReadVFWALUF_MX_E = !cast("ReadVFWALUF_" # mx # "_E" # e); - defm "" : VPseudoBinaryW_VF, - Sched<[WriteVFWALUF_MX, ReadVFWALUV_MX, ReadVFWALUF_MX, ReadVMask]>; + defm "" : VPseudoBinaryW_VF, + Sched<[WriteVFWALUF_MX_E, ReadVFWALUV_MX_E, ReadVFWALUF_MX_E, ReadVMask]>; + } } } } @@ -2823,21 +2850,27 @@ multiclass VPseudoVFWALU_WV_WF { foreach m = MxListFW in { defvar mx = m.MX; - defvar WriteVFWALUV_MX = !cast("WriteVFWALUV_" # mx); - defvar ReadVFWALUV_MX = !cast("ReadVFWALUV_" # mx); + defvar sews = SchedSEWSet.val; + foreach e = sews in { + defvar WriteVFWALUV_MX_E = !cast("WriteVFWALUV_" # mx # "_E" # e); + defvar ReadVFWALUV_MX_E = !cast("ReadVFWALUV_" # mx # "_E" # e); - defm "" : VPseudoBinaryW_WV, - Sched<[WriteVFWALUV_MX, ReadVFWALUV_MX, ReadVFWALUV_MX, ReadVMask]>; + defm "" : VPseudoBinaryW_WV, + Sched<[WriteVFWALUV_MX_E, ReadVFWALUV_MX_E, ReadVFWALUV_MX_E, ReadVMask]>; + } } foreach f = FPListW in { foreach m = f.MxListFW in { defvar mx = m.MX; - defvar WriteVFWALUF_MX = !cast("WriteVFWALUF_" # mx); - defvar ReadVFWALUV_MX = !cast("ReadVFWALUV_" # mx); - defvar ReadVFWALUF_MX = !cast("ReadVFWALUF_" # mx); + defvar sews = SchedSEWSet.val; + foreach e = sews in { + defvar WriteVFWALUF_MX_E = !cast("WriteVFWALUF_" # mx # "_E" # e); + defvar ReadVFWALUV_MX_E = !cast("ReadVFWALUV_" # mx # "_E" # e); + defvar ReadVFWALUF_MX_E = !cast("ReadVFWALUF_" # mx # "_E" # e); - defm "" : VPseudoBinaryW_WF, - Sched<[WriteVFWALUF_MX, ReadVFWALUV_MX, ReadVFWALUF_MX, ReadVMask]>; + defm "" : VPseudoBinaryW_WF, + Sched<[WriteVFWALUF_MX_E, ReadVFWALUV_MX_E, ReadVFWALUF_MX_E, ReadVMask]>; + } } } } @@ -3057,35 +3090,37 @@ DAGOperand Op2Class, LMULInfo MInfo, string Constraint = "", - bit Commutable = 0> { + bit Commutable = 0, + int sew = 0> { let VLMul = MInfo.value in { + defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); let isCommutable = Commutable in - def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy; - def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy, + def suffix : VPseudoTernaryNoMaskWithPolicy; + def suffix # "_MASK" : VPseudoBinaryMaskPolicy, RISCVMaskedPseudo; } } -multiclass VPseudoTernaryV_VV_AAXA { +multiclass VPseudoTernaryV_VV_AAXA { defm _VV : VPseudoTernaryWithPolicy; + Constraint, /*Commutable*/1, sew>; } -multiclass VPseudoTernaryV_VX_AAXA { +multiclass VPseudoTernaryV_VX_AAXA { defm "_VX" : VPseudoTernaryWithPolicy; + Constraint, /*Commutable*/1, sew>; } -multiclass VPseudoTernaryV_VF_AAXA { +multiclass VPseudoTernaryV_VF_AAXA { defm "_V" # f.FX : VPseudoTernaryWithPolicy; + /*Commutable*/1, sew>; } -multiclass VPseudoTernaryW_VV { +multiclass VPseudoTernaryW_VV { defvar constraint = "@earlyclobber $rd"; defm _VV : VPseudoTernaryWithPolicy; + constraint, /*Commutable*/0, sew>; } multiclass VPseudoTernaryW_VX { @@ -3094,10 +3129,11 @@ constraint>; } -multiclass VPseudoTernaryW_VF { +multiclass VPseudoTernaryW_VF { defvar constraint = "@earlyclobber $rd"; defm "_V" # f.FX : VPseudoTernaryWithPolicy; + m.vrclass, m, constraint, + /*Commutable*/0, sew>; } multiclass VPseudoVSLDVWithPolicy { foreach m = MxListF in { defvar mx = m.MX; - defvar WriteVFMulAddV_MX = !cast("WriteVFMulAddV_" # mx); - defvar ReadVFMulAddV_MX = !cast("ReadVFMulAddV_" # mx); + defvar sews = SchedSEWSet.val; + foreach e = sews in { + defvar WriteVFMulAddV_MX_E = !cast("WriteVFMulAddV_" # mx # "_E" # e); + defvar ReadVFMulAddV_MX_E = !cast("ReadVFMulAddV_" # mx # "_E" # e); - defm "" : VPseudoTernaryV_VV_AAXA, - Sched<[WriteVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVMask]>; + defm "" : VPseudoTernaryV_VV_AAXA, + Sched<[WriteVFMulAddV_MX_E, ReadVFMulAddV_MX_E, ReadVFMulAddV_MX_E, ReadVFMulAddV_MX_E, ReadVMask]>; + } } foreach f = FPList in { foreach m = f.MxList in { defvar mx = m.MX; - defvar WriteVFMulAddF_MX = !cast("WriteVFMulAddF_" # mx); - defvar ReadVFMulAddV_MX = !cast("ReadVFMulAddV_" # mx); - defvar ReadVFMulAddF_MX = !cast("ReadVFMulAddF_" # mx); + defvar WriteVFMulAddF_MX_E = !cast("WriteVFMulAddF_" # mx # "_E" # f.SEW); + defvar ReadVFMulAddV_MX_E = !cast("ReadVFMulAddV_" # mx # "_E" # f.SEW); + defvar ReadVFMulAddF_MX_E = !cast("ReadVFMulAddF_" # mx # "_E" # f.SEW); - defm "" : VPseudoTernaryV_VF_AAXA, - Sched<[WriteVFMulAddF_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddF_MX, ReadVMask]>; + defm "" : VPseudoTernaryV_VF_AAXA, + Sched<[WriteVFMulAddF_MX_E, ReadVFMulAddV_MX_E, ReadVFMulAddV_MX_E, ReadVFMulAddF_MX_E, ReadVMask]>; } } } @@ -3208,24 +3247,30 @@ multiclass VPseudoVWMAC_VV_VF { foreach m = MxListFW in { defvar mx = m.MX; - defvar WriteVFWMulAddV_MX = !cast("WriteVFWMulAddV_" # mx); - defvar ReadVFWMulAddV_MX = !cast("ReadVFWMulAddV_" # mx); + defvar sews = SchedSEWSet.val; + foreach e = sews in { + defvar WriteVFWMulAddV_MX_E = !cast("WriteVFWMulAddV_" # mx # "_E" # e); + defvar ReadVFWMulAddV_MX_E = !cast("ReadVFWMulAddV_" # mx # "_E" # e); - defm "" : VPseudoTernaryW_VV, - Sched<[WriteVFWMulAddV_MX, ReadVFWMulAddV_MX, - ReadVFWMulAddV_MX, ReadVFWMulAddV_MX, ReadVMask]>; + defm "" : VPseudoTernaryW_VV, + Sched<[WriteVFWMulAddV_MX_E, ReadVFWMulAddV_MX_E, + ReadVFWMulAddV_MX_E, ReadVFWMulAddV_MX_E, ReadVMask]>; + } } foreach f = FPListW in { foreach m = f.MxListFW in { defvar mx = m.MX; - defvar WriteVFWMulAddF_MX = !cast("WriteVFWMulAddF_" # mx); - defvar ReadVFWMulAddV_MX = !cast("ReadVFWMulAddV_" # mx); - defvar ReadVFWMulAddF_MX = !cast("ReadVFWMulAddF_" # mx); + defvar sews = SchedSEWSet.val; + foreach e = sews in { + defvar WriteVFWMulAddF_MX_E = !cast("WriteVFWMulAddF_" # mx # "_E" # e); + defvar ReadVFWMulAddV_MX_E = !cast("ReadVFWMulAddV_" # mx # "_E" # e); + defvar ReadVFWMulAddF_MX_E = !cast("ReadVFWMulAddF_" # mx # "_E" # e); - defm "" : VPseudoTernaryW_VF, - Sched<[WriteVFWMulAddF_MX, ReadVFWMulAddV_MX, - ReadVFWMulAddV_MX, ReadVFWMulAddF_MX, ReadVMask]>; + defm "" : VPseudoTernaryW_VF, + Sched<[WriteVFWMulAddF_MX_E, ReadVFWMulAddV_MX_E, + ReadVFWMulAddV_MX_E, ReadVFWMulAddF_MX_E, ReadVMask]>; + } } } } @@ -4126,21 +4171,25 @@ ValueType result_type, ValueType op1_type, ValueType op2_type, - int sew, + int log2sew, LMULInfo vlmul, VReg result_reg_class, RegisterClass op1_reg_class, - DAGOperand op2_kind> : + DAGOperand op2_kind, + bit isSEWAware = 0> : Pat<(result_type (!cast(intrinsic) (result_type result_reg_class:$rs3), (op1_type op1_reg_class:$rs1), (op2_type op2_kind:$rs2), VLOpFrag, (XLenVT timm:$policy))), - (!cast(inst#"_"#kind#"_"#vlmul.MX) + (!cast( + !if(isSEWAware, + inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew), + inst#"_"#kind#"_"#vlmul.MX)) result_reg_class:$rs3, (op1_type op1_reg_class:$rs1), op2_kind:$rs2, - GPR:$vl, sew, (XLenVT timm:$policy))>; + GPR:$vl, log2sew, (XLenVT timm:$policy))>; class VPatTernaryMask : + DAGOperand op2_kind, + bit isSEWAware = 0> : Pat<(result_type (!cast(intrinsic#"_mask") (result_type result_reg_class:$rs3), (op1_type op1_reg_class:$rs1), (op2_type op2_kind:$rs2), (mask_type V0), VLOpFrag, (XLenVT timm:$policy))), - (!cast(inst#"_"#kind#"_"#vlmul.MX # "_MASK") + (!cast( + !if(isSEWAware, + inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew) # "_MASK", + inst#"_"#kind#"_"#vlmul.MX # "_MASK")) result_reg_class:$rs3, (op1_type op1_reg_class:$rs1), op2_kind:$rs2, (mask_type V0), - GPR:$vl, sew, (XLenVT timm:$policy))>; + GPR:$vl, log2sew, (XLenVT timm:$policy))>; class VPatTernaryMaskTA vtilist> { + list vtilist, bit isSEWAware = 0> { foreach VtiToWti = vtilist in { defvar Vti = VtiToWti.Vti; defvar Wti = VtiToWti.Wti; + defvar name = !if(isSEWAware, + instruction # "_VV_" # Vti.LMul.MX # "_E" # Vti.SEW, + instruction # "_VV_" # Vti.LMul.MX); let Predicates = !listconcat(GetVTypePredicates.Predicates, GetVTypePredicates.Predicates) in - defm : VPatBinaryTA; @@ -4596,14 +4652,17 @@ } multiclass VPatBinaryW_VX vtilist> { + list vtilist, bit isSEWAware = 0> { foreach VtiToWti = vtilist in { defvar Vti = VtiToWti.Vti; defvar Wti = VtiToWti.Wti; defvar kind = "V"#Vti.ScalarSuffix; + defvar name = !if(isSEWAware, + instruction#"_"#kind#"_"#Vti.LMul.MX#"_E"#Vti.SEW, + instruction#"_"#kind#"_"#Vti.LMul.MX); let Predicates = !listconcat(GetVTypePredicates.Predicates, GetVTypePredicates.Predicates) in - defm : VPatBinaryTA; @@ -4611,27 +4670,30 @@ } multiclass VPatBinaryW_WV vtilist> { + list vtilist, bit isSEWAware = 0> { foreach VtiToWti = vtilist in { defvar Vti = VtiToWti.Vti; defvar Wti = VtiToWti.Wti; + defvar name = !if(isSEWAware, + instruction # "_WV_" # Vti.LMul.MX # "_E" # Vti.SEW, + instruction # "_WV_" # Vti.LMul.MX); let Predicates = !listconcat(GetVTypePredicates.Predicates, GetVTypePredicates.Predicates) in { - def : VPatTiedBinaryNoMask; - def : VPatBinaryNoMaskTU; let AddedComplexity = 1 in { - def : VPatTiedBinaryNoMaskTU; - def : VPatTiedBinaryMask; } - def : VPatBinaryMaskTA; @@ -4640,14 +4702,17 @@ } multiclass VPatBinaryW_WX vtilist> { + list vtilist, bit isSEWAware = 0> { foreach VtiToWti = vtilist in { defvar Vti = VtiToWti.Vti; defvar Wti = VtiToWti.Wti; defvar kind = "W"#Vti.ScalarSuffix; + defvar name = !if(isSEWAware, + instruction#"_"#kind#"_"#Vti.LMul.MX#"_E"#Vti.SEW, + instruction#"_"#kind#"_"#Vti.LMul.MX); let Predicates = !listconcat(GetVTypePredicates.Predicates, GetVTypePredicates.Predicates) in - defm : VPatBinaryTA; @@ -4855,14 +4920,14 @@ VPatBinaryV_VI; multiclass VPatBinaryW_VV_VX vtilist> - : VPatBinaryW_VV, - VPatBinaryW_VX; + list vtilist, bit isSEWAware = 0> + : VPatBinaryW_VV, + VPatBinaryW_VX; multiclass VPatBinaryW_WV_WX vtilist> - : VPatBinaryW_WV, - VPatBinaryW_WX; + list vtilist, bit isSEWAware = 0> + : VPatBinaryW_WV, + VPatBinaryW_WX; multiclass VPatBinaryV_WV_WX_WI vtilist> @@ -4948,13 +5013,14 @@ LMULInfo vlmul, VReg result_reg_class, RegisterClass op1_reg_class, - DAGOperand op2_kind> { + DAGOperand op2_kind, + bit isSEWAware = 0> { def : VPatTernaryNoMaskWithPolicy; + op1_reg_class, op2_kind, isSEWAware>; def : VPatTernaryMaskPolicy; + op2_kind, isSEWAware>; } multiclass VPatTernaryTA vtilist> { + list vtilist, bit isSEWAware = 0> { foreach vti = vtilist in let Predicates = GetVTypePredicates.Predicates in defm : VPatTernaryWithPolicy; + vti.RegClass, vti.RegClass, isSEWAware>; } multiclass VPatTernaryV_VX vtilist> { + list vtilist, bit isSEWAware = 0> { foreach vti = vtilist in let Predicates = GetVTypePredicates.Predicates in defm : VPatTernaryWithPolicy; + vti.ScalarRegClass, vti.RegClass, isSEWAware>; } multiclass VPatTernaryV_VI vtilist> { + list vtilist, bit isSEWAware = 0> { foreach vtiToWti = vtilist in { defvar vti = vtiToWti.Vti; defvar wti = vtiToWti.Wti; @@ -5028,12 +5094,13 @@ defm : VPatTernaryWithPolicy; + wti.RegClass, vti.RegClass, + vti.RegClass, isSEWAware>; } } multiclass VPatTernaryW_VX vtilist> { + list vtilist, bit isSEWAware = 0> { foreach vtiToWti = vtilist in { defvar vti = vtiToWti.Vti; defvar wti = vtiToWti.Wti; @@ -5043,14 +5110,15 @@ "V"#vti.ScalarSuffix, wti.Vector, vti.Scalar, vti.Vector, vti.Mask, vti.Log2SEW, vti.LMul, - wti.RegClass, vti.ScalarRegClass, vti.RegClass>; + wti.RegClass, vti.ScalarRegClass, + vti.RegClass, isSEWAware>; } } multiclass VPatTernaryV_VV_VX_AAXA vtilist> - : VPatTernaryV_VV_AAXA, - VPatTernaryV_VX_AAXA; + list vtilist, bit isSEWAware = 0> + : VPatTernaryV_VV_AAXA, + VPatTernaryV_VX_AAXA; multiclass VPatTernaryV_VX_VI vtilist, Operand Imm_type = simm5> @@ -5065,9 +5133,9 @@ VPatBinaryM_VI; multiclass VPatTernaryW_VV_VX vtilist> - : VPatTernaryW_VV, - VPatTernaryW_VX; + list vtilist, bit isSEWAware = 0> + : VPatTernaryW_VV, + VPatTernaryW_VX; multiclass VPatBinaryM_VV_VX vtilist> @@ -6294,49 +6362,49 @@ //===----------------------------------------------------------------------===// // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions //===----------------------------------------------------------------------===// -defm : VPatBinaryV_VV_VX<"int_riscv_vfadd", "PseudoVFADD", AllFloatVectors>; -defm : VPatBinaryV_VV_VX<"int_riscv_vfsub", "PseudoVFSUB", AllFloatVectors>; -defm : VPatBinaryV_VX<"int_riscv_vfrsub", "PseudoVFRSUB", AllFloatVectors>; +defm : VPatBinaryV_VV_VX<"int_riscv_vfadd", "PseudoVFADD", AllFloatVectors, /*isSEWAware*/ 1>; +defm : VPatBinaryV_VV_VX<"int_riscv_vfsub", "PseudoVFSUB", AllFloatVectors, /*isSEWAware*/ 1>; +defm : VPatBinaryV_VX<"int_riscv_vfrsub", "PseudoVFRSUB", AllFloatVectors, /*isSEWAware*/ 1>; //===----------------------------------------------------------------------===// // 13.3. Vector Widening Floating-Point Add/Subtract Instructions //===----------------------------------------------------------------------===// -defm : VPatBinaryW_VV_VX<"int_riscv_vfwadd", "PseudoVFWADD", AllWidenableFloatVectors>; -defm : VPatBinaryW_VV_VX<"int_riscv_vfwsub", "PseudoVFWSUB", AllWidenableFloatVectors>; -defm : VPatBinaryW_WV_WX<"int_riscv_vfwadd_w", "PseudoVFWADD", AllWidenableFloatVectors>; -defm : VPatBinaryW_WV_WX<"int_riscv_vfwsub_w", "PseudoVFWSUB", AllWidenableFloatVectors>; +defm : VPatBinaryW_VV_VX<"int_riscv_vfwadd", "PseudoVFWADD", AllWidenableFloatVectors, /*isSEWAware*/ 1>; +defm : VPatBinaryW_VV_VX<"int_riscv_vfwsub", "PseudoVFWSUB", AllWidenableFloatVectors, /*isSEWAware*/ 1>; +defm : VPatBinaryW_WV_WX<"int_riscv_vfwadd_w", "PseudoVFWADD", AllWidenableFloatVectors, /*isSEWAware*/ 1>; +defm : VPatBinaryW_WV_WX<"int_riscv_vfwsub_w", "PseudoVFWSUB", AllWidenableFloatVectors, /*isSEWAware*/ 1>; //===----------------------------------------------------------------------===// // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions //===----------------------------------------------------------------------===// -defm : VPatBinaryV_VV_VX<"int_riscv_vfmul", "PseudoVFMUL", AllFloatVectors>; +defm : VPatBinaryV_VV_VX<"int_riscv_vfmul", "PseudoVFMUL", AllFloatVectors, /*isSEWAware*/ 1>; defm : VPatBinaryV_VV_VX<"int_riscv_vfdiv", "PseudoVFDIV", AllFloatVectors, /*isSEWAware*/ 1>; defm : VPatBinaryV_VX<"int_riscv_vfrdiv", "PseudoVFRDIV", AllFloatVectors, /*isSEWAware*/ 1>; //===----------------------------------------------------------------------===// // 13.5. Vector Widening Floating-Point Multiply //===----------------------------------------------------------------------===// -defm : VPatBinaryW_VV_VX<"int_riscv_vfwmul", "PseudoVFWMUL", AllWidenableFloatVectors>; +defm : VPatBinaryW_VV_VX<"int_riscv_vfwmul", "PseudoVFWMUL", AllWidenableFloatVectors, /*isSEWAware*/ 1>; //===----------------------------------------------------------------------===// // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions //===----------------------------------------------------------------------===// -defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmacc", "PseudoVFMACC", AllFloatVectors>; -defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmacc", "PseudoVFNMACC", AllFloatVectors>; -defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmsac", "PseudoVFMSAC", AllFloatVectors>; -defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmsac", "PseudoVFNMSAC", AllFloatVectors>; -defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmadd", "PseudoVFMADD", AllFloatVectors>; -defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmadd", "PseudoVFNMADD", AllFloatVectors>; -defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmsub", "PseudoVFMSUB", AllFloatVectors>; -defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmsub", "PseudoVFNMSUB", AllFloatVectors>; +defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmacc", "PseudoVFMACC", AllFloatVectors, /*isSEWAware*/ 1>; +defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmacc", "PseudoVFNMACC", AllFloatVectors, /*isSEWAware*/ 1>; +defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmsac", "PseudoVFMSAC", AllFloatVectors, /*isSEWAware*/ 1>; +defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmsac", "PseudoVFNMSAC", AllFloatVectors, /*isSEWAware*/ 1>; +defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmadd", "PseudoVFMADD", AllFloatVectors, /*isSEWAware*/ 1>; +defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmadd", "PseudoVFNMADD", AllFloatVectors, /*isSEWAware*/ 1>; +defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmsub", "PseudoVFMSUB", AllFloatVectors, /*isSEWAware*/ 1>; +defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmsub", "PseudoVFNMSUB", AllFloatVectors, /*isSEWAware*/ 1>; //===----------------------------------------------------------------------===// // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions //===----------------------------------------------------------------------===// -defm : VPatTernaryW_VV_VX<"int_riscv_vfwmacc", "PseudoVFWMACC", AllWidenableFloatVectors>; -defm : VPatTernaryW_VV_VX<"int_riscv_vfwnmacc", "PseudoVFWNMACC", AllWidenableFloatVectors>; -defm : VPatTernaryW_VV_VX<"int_riscv_vfwmsac", "PseudoVFWMSAC", AllWidenableFloatVectors>; -defm : VPatTernaryW_VV_VX<"int_riscv_vfwnmsac", "PseudoVFWNMSAC", AllWidenableFloatVectors>; +defm : VPatTernaryW_VV_VX<"int_riscv_vfwmacc", "PseudoVFWMACC", AllWidenableFloatVectors, /*isSEWAware*/ 1>; +defm : VPatTernaryW_VV_VX<"int_riscv_vfwnmacc", "PseudoVFWNMACC", AllWidenableFloatVectors, /*isSEWAware*/ 1>; +defm : VPatTernaryW_VV_VX<"int_riscv_vfwmsac", "PseudoVFWMSAC", AllWidenableFloatVectors, /*isSEWAware*/ 1>; +defm : VPatTernaryW_VV_VX<"int_riscv_vfwnmsac", "PseudoVFWNMSAC", AllWidenableFloatVectors, /*isSEWAware*/ 1>; //===----------------------------------------------------------------------===// // 13.8. Vector Floating-Point Square-Root Instruction @@ -6346,12 +6414,12 @@ //===----------------------------------------------------------------------===// // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction //===----------------------------------------------------------------------===// -defm : VPatUnaryV_V<"int_riscv_vfrsqrt7", "PseudoVFRSQRT7", AllFloatVectors>; +defm : VPatUnaryV_V<"int_riscv_vfrsqrt7", "PseudoVFRSQRT7", AllFloatVectors, /*isSEWAware*/ 1>; //===----------------------------------------------------------------------===// // 13.10. Vector Floating-Point Reciprocal Estimate Instruction //===----------------------------------------------------------------------===// -defm : VPatUnaryV_V<"int_riscv_vfrec7", "PseudoVFREC7", AllFloatVectors>; +defm : VPatUnaryV_V<"int_riscv_vfrec7", "PseudoVFREC7", AllFloatVectors, /*isSEWAware*/ 1>; //===----------------------------------------------------------------------===// // 13.11. Vector Floating-Point Min/Max Instructions diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -481,7 +481,7 @@ (wti.Vector (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), (XLenVT srcvalue)))), - (!cast(instruction_name#"_VV_"#vti.LMul.MX) + (!cast(instruction_name#"_VV_"#vti.LMul.MX#"_E"#vti.SEW) vti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), @@ -489,13 +489,13 @@ (wti.Vector (riscv_fpextend_vl_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), (vti.Mask true_mask), (XLenVT srcvalue)))), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW) vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), (XLenVT srcvalue))), (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW) vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; } } @@ -511,18 +511,18 @@ (wti.Vector (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), (XLenVT srcvalue)))), - (!cast(instruction_name#"_WV_"#vti.LMul.MX#"_TIED") + (!cast(instruction_name#"_WV_"#vti.LMul.MX#"_E"#vti.SEW#"_TIED") wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; def : Pat<(op (wti.Vector wti.RegClass:$rs2), (wti.Vector (riscv_fpextend_vl_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), (vti.Mask true_mask), (XLenVT srcvalue)))), - (!cast(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX) + (!cast(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW) wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; def : Pat<(op (wti.Vector wti.RegClass:$rs2), (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))), - (!cast(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX) + (!cast(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW) wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; } } @@ -546,7 +546,7 @@ (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), (XLenVT srcvalue))), (wti.Vector wti.RegClass:$rd)), - (!cast(instruction_name#"_VV_"#vti.LMul.MX) + (!cast(instruction_name#"_VV_"#vti.LMul.MX#"_E"#vti.SEW) wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; def : Pat<(fma (wti.Vector (SplatFPOp @@ -555,7 +555,7 @@ (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), (XLenVT srcvalue))), (wti.Vector wti.RegClass:$rd)), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW) wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; } @@ -574,7 +574,7 @@ (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), (XLenVT srcvalue)), (fneg wti.RegClass:$rd)), - (!cast(instruction_name#"_VV_"#vti.LMul.MX) + (!cast(instruction_name#"_VV_"#vti.LMul.MX#"_E"#vti.SEW) wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; def : Pat<(fma (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)), @@ -582,14 +582,14 @@ (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), (XLenVT srcvalue)))), (fneg wti.RegClass:$rd)), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW) wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; def : Pat<(fma (fneg (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))), (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), (XLenVT srcvalue)), (fneg wti.RegClass:$rd)), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW) wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; } @@ -608,14 +608,14 @@ (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), (XLenVT srcvalue)), (fneg wti.RegClass:$rd)), - (!cast(instruction_name#"_VV_"#vti.LMul.MX) + (!cast(instruction_name#"_VV_"#vti.LMul.MX#"_E"#vti.SEW) wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; def : Pat<(fma (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1))), (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), (XLenVT srcvalue)), (fneg wti.RegClass:$rd)), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW) wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; } @@ -634,7 +634,7 @@ (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), (XLenVT srcvalue)), wti.RegClass:$rd), - (!cast(instruction_name#"_VV_"#vti.LMul.MX) + (!cast(instruction_name#"_VV_"#vti.LMul.MX#"_E"#vti.SEW) wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; def : Pat<(fma (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1))), @@ -642,14 +642,14 @@ (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), (XLenVT srcvalue)))), wti.RegClass:$rd), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW) wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; def : Pat<(fma (fneg (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))), (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), (XLenVT srcvalue)), wti.RegClass:$rd), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW) wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; } @@ -922,16 +922,16 @@ // 13. Vector Floating-Point Instructions // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions -defm : VPatBinaryFPSDNode_VV_VF; -defm : VPatBinaryFPSDNode_VV_VF; -defm : VPatBinaryFPSDNode_R_VF; +defm : VPatBinaryFPSDNode_VV_VF; +defm : VPatBinaryFPSDNode_VV_VF; +defm : VPatBinaryFPSDNode_R_VF; // 13.3. Vector Widening Floating-Point Add/Subtract Instructions defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF; defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF; // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions -defm : VPatBinaryFPSDNode_VV_VF; +defm : VPatBinaryFPSDNode_VV_VF; defm : VPatBinaryFPSDNode_VV_VF; defm : VPatBinaryFPSDNode_R_VF; @@ -942,7 +942,7 @@ foreach fvti = AllFloatVectors in { // NOTE: We choose VFMADD because it has the most commuting freedom. So it // works best with how TwoAddressInstructionPass tries commuting. - defvar suffix = fvti.LMul.MX; + defvar suffix = fvti.LMul.MX # "_E" # fvti.SEW; let Predicates = GetVTypePredicates.Predicates in { def : Pat<(fvti.Vector (any_fma fvti.RegClass:$rs1, fvti.RegClass:$rd, fvti.RegClass:$rs2)), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -594,20 +594,24 @@ string suffix, ValueType result_type, ValueType op2_type, - int sew, + int log2sew, LMULInfo vlmul, VReg result_reg_class, - VReg op2_reg_class> { + VReg op2_reg_class, + bit isSEWAware = 0> { + defvar name = !if(isSEWAware, + instruction_name#"_"#suffix#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_TIED", + instruction_name#"_"#suffix#"_"#vlmul.MX#"_TIED"); def : Pat<(result_type (vop (result_type result_reg_class:$rs1), (op2_type op2_reg_class:$rs2), srcvalue, true_mask, VLOpFrag)), - (!cast(instruction_name#"_"#suffix#"_"# vlmul.MX#"_TIED") + (!cast(name) result_reg_class:$rs1, op2_reg_class:$rs2, - GPR:$vl, sew, TAIL_AGNOSTIC)>; + GPR:$vl, log2sew, TAIL_AGNOSTIC)>; // Tail undisturbed def : Pat<(riscv_vp_merge_vl true_mask, (result_type (vop @@ -617,10 +621,10 @@ true_mask, VLOpFrag)), result_reg_class:$rs1, VLOpFrag), - (!cast(instruction_name#"_"#suffix#"_"# vlmul.MX#"_TIED") + (!cast(name) result_reg_class:$rs1, op2_reg_class:$rs2, - GPR:$vl, sew, TAIL_UNDISTURBED_MASK_UNDISTURBED)>; + GPR:$vl, log2sew, TAIL_UNDISTURBED_MASK_UNDISTURBED)>; } class VPatBinaryVL_XI; + vti.RegClass, /*isSEWAware*/ 1>; def : VPatBinaryVL_VF; + vti.ScalarRegClass, /*isSEWAware*/ 1>; } } } @@ -1301,15 +1305,16 @@ GetVTypePredicates.Predicates) in { defm : VPatTiedBinaryNoMaskVL_V; + vti.LMul, wti.RegClass, vti.RegClass, + /*isSEWAware*/ 1>; def : VPatBinaryVL_V; + vti.RegClass, /*isSEWAware*/ 1>; def : VPatBinaryVL_VF; + vti.ScalarRegClass, /*isSEWAware*/ 1>; } } } @@ -1457,7 +1462,7 @@ multiclass VPatFPMulAddVL_VV_VF { foreach vti = AllFloatVectors in { - defvar suffix = vti.LMul.MX; + defvar suffix = vti.LMul.MX # "_E" # vti.SEW; let Predicates = GetVTypePredicates.Predicates in { def : Pat<(vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rd, vti.RegClass:$rs2, (vti.Mask V0), @@ -1479,7 +1484,7 @@ multiclass VPatFPMulAccVL_VV_VF { foreach vti = AllFloatVectors in { - defvar suffix = vti.LMul.MX; + defvar suffix = vti.LMul.MX # "_E" # vti.SEW; let Predicates = GetVTypePredicates.Predicates in { def : Pat<(riscv_vp_merge_vl (vti.Mask V0), (vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rs2, @@ -1523,14 +1528,14 @@ (vti.Vector vti.RegClass:$rs2), (wti.Vector wti.RegClass:$rd), (vti.Mask V0), VLOpFrag), - (!cast(instruction_name#"_VV_"#vti.LMul.MX #"_MASK") + (!cast(instruction_name#"_VV_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK") wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; def : Pat<(vop (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), (vti.Vector vti.RegClass:$rs2), (wti.Vector wti.RegClass:$rd), (vti.Mask V0), VLOpFrag), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX #"_MASK") + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK") wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; } @@ -1822,16 +1827,16 @@ // 13. Vector Floating-Point Instructions // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions -defm : VPatBinaryFPVL_VV_VF; -defm : VPatBinaryFPVL_VV_VF; -defm : VPatBinaryFPVL_R_VF; +defm : VPatBinaryFPVL_VV_VF; +defm : VPatBinaryFPVL_VV_VF; +defm : VPatBinaryFPVL_R_VF; // 13.3. Vector Widening Floating-Point Add/Subtract Instructions defm : VPatBinaryFPWVL_VV_VF_WV_WF; defm : VPatBinaryFPWVL_VV_VF_WV_WF; // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions -defm : VPatBinaryFPVL_VV_VF; +defm : VPatBinaryFPVL_VV_VF; defm : VPatBinaryFPVL_VV_VF; defm : VPatBinaryFPVL_R_VF; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -541,17 +541,26 @@ } // 13. Vector Floating-Point Instructions +foreach mx = SchedMxListF in { + defvar Cycles = SiFive7GetCyclesDefault.c; + foreach sew = SchedSEWSet.val in { + defvar IsWorstCase = SiFive7IsWorstCaseMXSEW.c; + let Latency = 8, ResourceCycles = [Cycles] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [SiFive7VA], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [SiFive7VA], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [SiFive7VA], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [SiFive7VA], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [SiFive7VA], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [SiFive7VA], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [SiFive7VA], mx, sew, IsWorstCase>; + } + } +} + foreach mx = SchedMxList in { defvar Cycles = SiFive7GetCyclesDefault.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; let Latency = 8, ResourceCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVFALUV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFALUF", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFMulV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFMulF", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFMulAddV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFMulAddF", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFRecpV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVFCvtIToFV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFive7VA], mx, IsWorstCase>; } @@ -595,16 +604,26 @@ defvar Cycles = SiFive7GetCyclesWidening.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; let Latency = 8, ResourceCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVFWALUV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFWMulV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFWMulAddV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVFWCvtFToFV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFWMulAddF", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFWMulF", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFWALUF", [SiFive7VA], mx, IsWorstCase>; } } + +foreach mx = SchedMxListFW in { + defvar Cycles = SiFive7GetCyclesWidening.c; + foreach sew = SchedSEWSet.val in { + defvar IsWorstCase = SiFive7IsWorstCaseMXSEW.c; + let Latency = 8, ResourceCycles = [Cycles] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [SiFive7VA], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [SiFive7VA], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [SiFive7VA], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [SiFive7VA], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [SiFive7VA], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [SiFive7VA], mx, sew, IsWorstCase>; + } + } +} + // Narrowing foreach mx = SchedMxListW in { defvar Cycles = SiFive7GetCyclesNarrowing.c; @@ -890,22 +909,22 @@ defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>; // 14. Vector Floating-Point Instructions -defm "" : LMULReadAdvance<"ReadVFALUV", 0>; -defm "" : LMULReadAdvance<"ReadVFALUF", 0>; -defm "" : LMULReadAdvanceFW<"ReadVFWALUV", 0>; -defm "" : LMULReadAdvanceFW<"ReadVFWALUF", 0>; -defm "" : LMULReadAdvance<"ReadVFMulV", 0>; -defm "" : LMULReadAdvance<"ReadVFMulF", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>; defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>; defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>; -defm "" : LMULReadAdvanceFW<"ReadVFWMulV", 0>; -defm "" : LMULReadAdvanceFW<"ReadVFWMulF", 0>; -defm "" : LMULReadAdvance<"ReadVFMulAddV", 0>; -defm "" : LMULReadAdvance<"ReadVFMulAddF", 0>; -defm "" : LMULReadAdvanceFW<"ReadVFWMulAddV", 0>; -defm "" : LMULReadAdvanceFW<"ReadVFWMulAddF", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>; defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>; -defm "" : LMULReadAdvance<"ReadVFRecpV", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>; defm "" : LMULReadAdvance<"ReadVFMinMaxV", 0>; defm "" : LMULReadAdvance<"ReadVFMinMaxF", 0>; defm "" : LMULReadAdvance<"ReadVFSgnjV", 0>; diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td --- a/llvm/lib/Target/RISCV/RISCVScheduleV.td +++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td @@ -186,6 +186,20 @@ multiclass LMULSEWReadAdvanceF writes = []> : LMULSEWReadAdvanceImpl; +multiclass LMULSEWSchedWritesW : LMULSEWSchedWritesImpl; +multiclass LMULSEWSchedReadsW : LMULSEWSchedReadsImpl; +multiclass LMULSEWWriteResW resources> + : LMULSEWWriteResImpl; +multiclass LMULSEWReadAdvanceW writes = []> + : LMULSEWReadAdvanceImpl; + +multiclass LMULSEWSchedWritesFW : LMULSEWSchedWritesImpl; +multiclass LMULSEWSchedReadsFW : LMULSEWSchedReadsImpl; +multiclass LMULSEWWriteResFW resources> + : LMULSEWWriteResImpl; +multiclass LMULSEWReadAdvanceFW writes = []> + : LMULSEWReadAdvanceImpl; + multiclass LMULSchedWritesW : LMULSchedWritesImpl; multiclass LMULSchedReadsW : LMULSchedReadsImpl; multiclass LMULWriteResW resources> @@ -346,30 +360,30 @@ // 13. Vector Floating-Point Instructions // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions -defm "" : LMULSchedWrites<"WriteVFALUV">; -defm "" : LMULSchedWrites<"WriteVFALUF">; +defm "" : LMULSEWSchedWritesF<"WriteVFALUV">; +defm "" : LMULSEWSchedWritesF<"WriteVFALUF">; // 13.3. Vector Widening Floating-Point Add/Subtract Instructions -defm "" : LMULSchedWritesFW<"WriteVFWALUV">; -defm "" : LMULSchedWritesFW<"WriteVFWALUF">; +defm "" : LMULSEWSchedWritesFW<"WriteVFWALUV">; +defm "" : LMULSEWSchedWritesFW<"WriteVFWALUF">; // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions -defm "" : LMULSchedWrites<"WriteVFMulV">; -defm "" : LMULSchedWrites<"WriteVFMulF">; +defm "" : LMULSEWSchedWritesF<"WriteVFMulV">; +defm "" : LMULSEWSchedWritesF<"WriteVFMulF">; defm "" : LMULSEWSchedWritesF<"WriteVFDivV">; defm "" : LMULSEWSchedWritesF<"WriteVFDivF">; // 13.5. Vector Widening Floating-Point Multiply -defm "" : LMULSchedWritesFW<"WriteVFWMulV">; -defm "" : LMULSchedWritesFW<"WriteVFWMulF">; +defm "" : LMULSEWSchedWritesFW<"WriteVFWMulV">; +defm "" : LMULSEWSchedWritesFW<"WriteVFWMulF">; // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions -defm "" : LMULSchedWrites<"WriteVFMulAddV">; -defm "" : LMULSchedWrites<"WriteVFMulAddF">; +defm "" : LMULSEWSchedWritesF<"WriteVFMulAddV">; +defm "" : LMULSEWSchedWritesF<"WriteVFMulAddF">; // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions -defm "" : LMULSchedWritesFW<"WriteVFWMulAddV">; -defm "" : LMULSchedWritesFW<"WriteVFWMulAddF">; +defm "" : LMULSEWSchedWritesFW<"WriteVFWMulAddV">; +defm "" : LMULSEWSchedWritesFW<"WriteVFWMulAddF">; // 13.8. Vector Floating-Point Square-Root Instruction defm "" : LMULSEWSchedWritesF<"WriteVFSqrtV">; // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction // 13.10. Vector Floating-Point Reciprocal Estimate Instruction -defm "" : LMULSchedWrites<"WriteVFRecpV">; +defm "" : LMULSEWSchedWritesF<"WriteVFRecpV">; // 13.11. Vector Floating-Point MIN/MAX Instructions defm "" : LMULSchedWrites<"WriteVFMinMaxV">; defm "" : LMULSchedWrites<"WriteVFMinMaxF">; @@ -569,30 +583,30 @@ // 13. Vector Floating-Point Instructions // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions -defm "" : LMULSchedReads<"ReadVFALUV">; -defm "" : LMULSchedReads<"ReadVFALUF">; +defm "" : LMULSEWSchedReadsF<"ReadVFALUV">; +defm "" : LMULSEWSchedReadsF<"ReadVFALUF">; // 13.3. Vector Widening Floating-Point Add/Subtract Instructions -defm "" : LMULSchedReadsFW<"ReadVFWALUV">; -defm "" : LMULSchedReadsFW<"ReadVFWALUF">; +defm "" : LMULSEWSchedReadsFW<"ReadVFWALUV">; +defm "" : LMULSEWSchedReadsFW<"ReadVFWALUF">; // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions -defm "" : LMULSchedReads<"ReadVFMulV">; -defm "" : LMULSchedReads<"ReadVFMulF">; +defm "" : LMULSEWSchedReadsF<"ReadVFMulV">; +defm "" : LMULSEWSchedReadsF<"ReadVFMulF">; defm "" : LMULSEWSchedReadsF<"ReadVFDivV">; defm "" : LMULSEWSchedReadsF<"ReadVFDivF">; // 13.5. Vector Widening Floating-Point Multiply -defm "" : LMULSchedReadsFW<"ReadVFWMulV">; -defm "" : LMULSchedReadsFW<"ReadVFWMulF">; +defm "" : LMULSEWSchedReadsFW<"ReadVFWMulV">; +defm "" : LMULSEWSchedReadsFW<"ReadVFWMulF">; // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions -defm "" : LMULSchedReads<"ReadVFMulAddV">; -defm "" : LMULSchedReads<"ReadVFMulAddF">; +defm "" : LMULSEWSchedReadsF<"ReadVFMulAddV">; +defm "" : LMULSEWSchedReadsF<"ReadVFMulAddF">; // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions -defm "" : LMULSchedReadsFW<"ReadVFWMulAddV">; -defm "" : LMULSchedReadsFW<"ReadVFWMulAddF">; +defm "" : LMULSEWSchedReadsFW<"ReadVFWMulAddV">; +defm "" : LMULSEWSchedReadsFW<"ReadVFWMulAddF">; // 13.8. Vector Floating-Point Square-Root Instruction defm "" : LMULSEWSchedReadsF<"ReadVFSqrtV">; // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction // 13.10. Vector Floating-Point Reciprocal Estimate Instruction -defm "" : LMULSchedReads<"ReadVFRecpV">; +defm "" : LMULSEWSchedReadsF<"ReadVFRecpV">; // 13.11. Vector Floating-Point MIN/MAX Instructions defm "" : LMULSchedReads<"ReadVFMinMaxV">; defm "" : LMULSchedReads<"ReadVFMinMaxF">; @@ -808,22 +822,22 @@ defm "" : LMULWriteResW<"WriteVNClipI", []>; // 13. Vector Floating-Point Instructions -defm "" : LMULWriteRes<"WriteVFALUV", []>; -defm "" : LMULWriteRes<"WriteVFALUF", []>; -defm "" : LMULWriteResFW<"WriteVFWALUV", []>; -defm "" : LMULWriteResFW<"WriteVFWALUF", []>; -defm "" : LMULWriteRes<"WriteVFMulV", []>; -defm "" : LMULWriteRes<"WriteVFMulF", []>; +defm "" : LMULSEWWriteResF<"WriteVFALUV", []>; +defm "" : LMULSEWWriteResF<"WriteVFALUF", []>; +defm "" : LMULSEWWriteResFW<"WriteVFWALUV", []>; +defm "" : LMULSEWWriteResFW<"WriteVFWALUF", []>; +defm "" : LMULSEWWriteResF<"WriteVFMulV", []>; +defm "" : LMULSEWWriteResF<"WriteVFMulF", []>; defm "" : LMULSEWWriteResF<"WriteVFDivV", []>; defm "" : LMULSEWWriteResF<"WriteVFDivF", []>; -defm "" : LMULWriteResFW<"WriteVFWMulV", []>; -defm "" : LMULWriteResFW<"WriteVFWMulF", []>; -defm "" : LMULWriteRes<"WriteVFMulAddV", []>; -defm "" : LMULWriteRes<"WriteVFMulAddF", []>; -defm "" : LMULWriteResFW<"WriteVFWMulAddV", []>; -defm "" : LMULWriteResFW<"WriteVFWMulAddF", []>; +defm "" : LMULSEWWriteResFW<"WriteVFWMulV", []>; +defm "" : LMULSEWWriteResFW<"WriteVFWMulF", []>; +defm "" : LMULSEWWriteResF<"WriteVFMulAddV", []>; +defm "" : LMULSEWWriteResF<"WriteVFMulAddF", []>; +defm "" : LMULSEWWriteResFW<"WriteVFWMulAddV", []>; +defm "" : LMULSEWWriteResFW<"WriteVFWMulAddF", []>; defm "" : LMULSEWWriteResF<"WriteVFSqrtV", []>; -defm "" : LMULWriteRes<"WriteVFRecpV", []>; +defm "" : LMULSEWWriteResF<"WriteVFRecpV", []>; defm "" : LMULWriteRes<"WriteVFMinMaxV", []>; defm "" : LMULWriteRes<"WriteVFMinMaxF", []>; defm "" : LMULWriteRes<"WriteVFSgnjV", []>; @@ -962,22 +976,22 @@ defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>; // 13. Vector Floating-Point Instructions -defm "" : LMULReadAdvance<"ReadVFALUV", 0>; -defm "" : LMULReadAdvance<"ReadVFALUF", 0>; -defm "" : LMULReadAdvanceFW<"ReadVFWALUV", 0>; -defm "" : LMULReadAdvanceFW<"ReadVFWALUF", 0>; -defm "" : LMULReadAdvance<"ReadVFMulV", 0>; -defm "" : LMULReadAdvance<"ReadVFMulF", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>; defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>; defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>; -defm "" : LMULReadAdvanceFW<"ReadVFWMulV", 0>; -defm "" : LMULReadAdvanceFW<"ReadVFWMulF", 0>; -defm "" : LMULReadAdvance<"ReadVFMulAddV", 0>; -defm "" : LMULReadAdvance<"ReadVFMulAddF", 0>; -defm "" : LMULReadAdvanceFW<"ReadVFWMulAddV", 0>; -defm "" : LMULReadAdvanceFW<"ReadVFWMulAddF", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>; defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>; -defm "" : LMULReadAdvance<"ReadVFRecpV", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>; defm "" : LMULReadAdvance<"ReadVFMinMaxV", 0>; defm "" : LMULReadAdvance<"ReadVFMinMaxF", 0>; defm "" : LMULReadAdvance<"ReadVFSgnjV", 0>;