Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -255,13 +255,6 @@
   uint16_t Pseudo;
 };
 
-struct RISCVMaskedPseudoInfo {
-  uint16_t MaskedPseudo;
-  uint16_t UnmaskedPseudo;
-  uint16_t UnmaskedTUPseudo;
-  uint8_t MaskOpIdx;
-};
-
 #define GET_RISCVVSSEGTable_DECL
 #define GET_RISCVVLSEGTable_DECL
 #define GET_RISCVVLXSEGTable_DECL
@@ -270,7 +263,6 @@
 #define GET_RISCVVSETable_DECL
 #define GET_RISCVVLXTable_DECL
 #define GET_RISCVVSXTable_DECL
-#define GET_RISCVMaskedPseudosTable_DECL
 #include "RISCVGenSearchableTables.inc"
 } // namespace RISCV
 
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -37,7 +37,6 @@
 #define GET_RISCVVSETable_IMPL
 #define GET_RISCVVLXTable_IMPL
 #define GET_RISCVVSXTable_IMPL
-#define GET_RISCVMaskedPseudosTable_IMPL
 #include "RISCVGenSearchableTables.inc"
 } // namespace llvm::RISCV
 
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -276,6 +276,66 @@
 static constexpr unsigned FPMASK_Positive_Infinity = 0x080;
 static constexpr unsigned FPMASK_Signaling_NaN = 0x100;
 static constexpr unsigned FPMASK_Quiet_NaN = 0x200;
+
+/*
+  Overview of our vector instruction psuedos.  Many of the instructions
+  have behavior which depends on the value of VTYPE.  Several core aspects of
+  the compiler - e.g. register allocation - depend on fields in this
+  configuration register.  The details of which fields matter differ by the
+  specific instruction, but the common dimensions are:
+
+  LMUL/EMUL - Most instructions can write to differently sized register groups
+  depending on LMUL.
+
+  Masked vs Unmasked - Many instructions which allow a mask disallow register
+  overlap.  As a result, masked vs unmasked require different register
+  allocation constraints.
+
+  Policy - For each of mask and tail policy, there are three options:
+  * "Undisturbed" - As defined in the specification, required to preserve the
+  exact bit pattern of inactive lanes.
+  * "Agnostic" - As defined in the specification, required to either preserve
+  the exact bit pattern of inactive lanes, or produce the bit pattern -1 for
+  those lanes.
+  * "Undefined" - The bit pattern of the inactive lanes is unspecified, and
+  can be changed without impacting the semantics of the program.  Note that
+  this concept does not exist in the specification, and requires source
+  knownledge to be preserved.
+
+  SEW - Some instructions have semantics which depend on SEW.  This is
+  relatively rare, and mostly impacts scheduling and cost estimation.
+
+  We have two techniques we use to represent the impact of these fields:
+  1) For fields which don't impact register classes, we largely use
+  dummy operands on the psuedo instructions which convey information
+  about the value of VTYPE.
+  * For fields which do impact register classes (and a few bits of
+  legacy - see policy discussion below), we define a family of pseudo
+  instructions for each actual instruction.  Said differently, we encode
+  each of the preceding fields which are relevant for a given instruction
+  in the opcode space.
+
+  Currently, the policy is represented via the following instrinic families:
+  * (Unsuffixed) -- Does not have a passthrough operand, and thus represents
+  the "undefined" state.  Note that terminology in code frequently refers to
+  these as "TA" which is confusing.  We're in the process of migrating away
+  from this representation.
+  * _TU - Can represent all three policy states.  If passthrough is
+  IMPLICIT_DEF, then represents "undefined".  Otherwise, policy operand
+  and tablegen flags drive the interpretation.
+  * _MASK - See _TU, differs in the existance of a mask operand and the
+  overlap constraint mentioned above.
+ */
+struct RISCVMaskedPseudoInfo {
+  uint16_t MaskedPseudo;
+  uint16_t UnmaskedPseudo;
+  uint16_t UnmaskedTUPseudo;
+  uint8_t MaskOpIdx;
+};
+
+#define GET_RISCVMaskedPseudosTable_DECL
+#include "RISCVGenSearchableTables.inc"
+
 } // namespace RISCV
 
 namespace RISCVVPseudosTable {
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -55,6 +55,11 @@
                clEnumValN(MachineTraceStrategy::TS_MinInstrCount, "min-instr",
                           "MinInstrCount strategy.")));
 
+namespace llvm::RISCV {
+#define GET_RISCVMaskedPseudosTable_IMPL
+#include "RISCVGenSearchableTables.inc"
+} // namespace llvm::RISCV
+
 namespace llvm::RISCVVPseudosTable {
 
 using namespace RISCV;