diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
--- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
@@ -260,81 +260,6 @@
 def : GINodeEquiv<G_FPTRUNC_ROUND_UPWARD, SIfptrunc_round_upward>;
 def : GINodeEquiv<G_FPTRUNC_ROUND_DOWNWARD, SIfptrunc_round_downward>;
 
-class GISelSop2Pat <
-  SDPatternOperator node,
-  Instruction inst,
-  ValueType dst_vt,
-  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
-
-  (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),
-  (inst src0_vt:$src0, src1_vt:$src1)
->;
-
-class GISelVop2Pat <
-  SDPatternOperator node,
-  Instruction inst,
-  ValueType dst_vt,
-  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
-
-  (dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))),
-  (inst src0_vt:$src0, src1_vt:$src1)
->;
-
-class GISelVop2CommutePat <
-  SDPatternOperator node,
-  Instruction inst,
-  ValueType dst_vt,
-  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
-
-  (dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))),
-  (inst src0_vt:$src0, src1_vt:$src1)
->;
-
-class GISelVop3Pat2 <
-  SDPatternOperator node,
-  Instruction inst,
-  ValueType dst_vt,
-  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
-
-  (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
-  (inst src0_vt:$src0, src1_vt:$src1)
->;
-
-class GISelVop3Pat2CommutePat <
-  SDPatternOperator node,
-  Instruction inst,
-  ValueType dst_vt,
-  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
-
-  (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
-  (inst src0_vt:$src1, src1_vt:$src0)
->;
-
-class GISelVop3Pat2ModsPat <
-  SDPatternOperator node,
-  Instruction inst,
-  ValueType dst_vt,
-  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
-
-  (dst_vt (node (src0_vt (VOP3Mods0 src0_vt:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omods)),
-                (src1_vt (VOP3Mods src1_vt:$src1, i32:$src1_modifiers)))),
-  (inst i32:$src0_modifiers, src0_vt:$src0,
-        i32:$src1_modifiers, src1_vt:$src1, $clamp, $omods)
->;
-
-multiclass GISelVop2IntrPat <
-  SDPatternOperator node, Instruction inst,
-  ValueType dst_vt, ValueType src_vt = dst_vt> {
-
-  def : GISelVop2Pat <node, inst, dst_vt, src_vt>;
-
-  // FIXME: Intrinsics aren't marked as commutable, so we need to add an explicit
-  // pattern to handle commuting.  This is another reason why legalizing to a
-  // generic machine instruction may be better that matching the intrinsic
-  // directly.
-  def : GISelVop2CommutePat <node, inst, dst_vt, src_vt>;
-}
-
 // Since GlobalISel is more flexible then SelectionDAG, I think we can get
 // away with adding patterns for integer types and not legalizing all
 // loads and stores to vector types.  This should help simplify the load/store
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -48,34 +48,10 @@
   let TSFlags{62} = isRegisterStore;
 }
 
-class AMDGPUShaderInst <dag outs, dag ins, string asm = "",
-  list<dag> pattern = []> : AMDGPUInst<outs, ins, asm, pattern> {
-
-  field bits<32> Inst = 0xffffffff;
-}
-
 //===---------------------------------------------------------------------===//
 // Return instruction
 //===---------------------------------------------------------------------===//
 
-class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
-: Instruction {
-
-     let Namespace = "AMDGPU";
-     dag OutOperandList = outs;
-     dag InOperandList = ins;
-     let Pattern = pattern;
-     let AsmString = !strconcat(asmstr, "\n");
-     let isPseudo = 1;
-     let Itinerary = NullALU;
-     bit hasIEEEFlag = 0;
-     bit hasZeroOpFlag = 0;
-     let mayLoad = 0;
-     let mayStore = 0;
-     let hasSideEffects = 0;
-     let isCodeGenOnly = 1;
-}
-
 def TruePredicate : Predicate<"">;
 
 // FIXME: Tablegen should specially supports this
@@ -86,11 +62,6 @@
   list<Predicate> ret = !listconcat(lst, !listremove([pred], lst));
 }
 
-// Get the union of two Register lists
-class RegListUnion<list<Register> lstA, list<Register> lstB> {
-  list<Register> ret = !listconcat(lstA, !listremove(lstB, lstA));
-}
-
 class PredicateControl {
   Predicate SubtargetPredicate = TruePredicate;
   Predicate AssemblerPredicate = TruePredicate;
@@ -106,9 +77,6 @@
 class AMDGPUPat<dag pattern, dag result> : Pat<pattern, result>,
       PredicateControl, GISelFlags;
 
-let GIIgnoreCopies = 1 in
-class AMDGPUPatIgnoreCopies<dag pattern, dag result> : AMDGPUPat<pattern, result>;
-
 let RecomputePerFunction = 1 in {
 def FP16Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().allFP64FP16Denormals()">;
 def FP32Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().allFP32Denormals()">;
@@ -198,27 +166,6 @@
   }];
 }
 
-class is_canonicalized<SDPatternOperator op> : PatFrag<
-  (ops node:$src0, node:$src1),
-  (op $src0, $src1),
-  [{
-    const SITargetLowering &Lowering =
-              *static_cast<const SITargetLowering *>(getTargetLowering());
-
-    return Lowering.isCanonicalized(*CurDAG, N->getOperand(0)) &&
-      Lowering.isCanonicalized(*CurDAG, N->getOperand(1));
-   }]> {
-
-  // TODO: Improve the Legalizer for g_build_vector in Global Isel to match this class
-  let GISelPredicateCode = [{
-    const SITargetLowering *TLI = static_cast<const SITargetLowering *>(
-      MF.getSubtarget().getTargetLowering());
-
-    return TLI->isCanonicalized(MI.getOperand(1).getReg(), const_cast<MachineFunction&>(MF)) &&
-      TLI->isCanonicalized(MI.getOperand(2).getReg(), const_cast<MachineFunction&>(MF));
-  }];
-}
-
 class FoldTernaryOpPat<SDPatternOperator op1, SDPatternOperator op2> : PatFrag<
   (ops node:$src0, node:$src1, node:$src2),
   (op2 (op1 node:$src0, node:$src1), node:$src2)
@@ -725,15 +672,6 @@
   [{return N->isExactlyValue(0.5);}]
 >;
 
-/* Generic helper patterns for intrinsics */
-/* -------------------------------------- */
-
-class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
-  : AMDGPUPat <
-  (fpow f32:$src0, f32:$src1),
-  (exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
->;
-
 /* Other helper patterns */
 /* --------------------- */
 
@@ -761,13 +699,6 @@
   (dt rc:$src0)
 >;
 
-// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
-// can handle COPY instructions.
-class DwordAddrPat<ValueType vt, RegisterClass rc> : AMDGPUPat <
-  (vt (AMDGPUdwordaddr (vt rc:$addr))),
-  (vt rc:$addr)
->;
-
 // rotr pattern
 class ROTRPattern <Instruction BIT_ALIGN> : AMDGPUPat <
   (rotr i32:$src0, i32:$src1),
@@ -802,11 +733,6 @@
 >;
 } // AddedComplexity.
 
-class RcpPat<Instruction RcpInst, ValueType vt> : AMDGPUPat <
-  (fdiv FP_ONE, vt:$src),
-  (RcpInst $src)
->;
-
 // Instructions which select to the same v_min_f*
 def fminnum_like : PatFrags<(ops node:$src0, node:$src1),
   [(fminnum_ieee node:$src0, node:$src1),
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -1411,10 +1411,6 @@
   } // end foreach RtnMode
 }
 
-multiclass BufferAtomicIntrPat<string OpPrefix, ValueType vt, string Inst> {
-  defm : BufferAtomicPat<OpPrefix, vt, Inst, /* isIntr */ 1>;
-}
-
 multiclass BufferAtomicCmpSwapPat<ValueType vt, ValueType data_vt, string Inst> {
   foreach RtnMode = ["ret", "noret"] in {
 
@@ -1558,49 +1554,6 @@
   defm : SIBufferAtomicPat<"SIbuffer_atomic_fmax", f64, "BUFFER_ATOMIC_FMAX_X2">;
 }
 
-class NoUseBufferAtomic<SDPatternOperator Op, ValueType vt> : PatFrag <
-  (ops node:$src0, node:$src1, node:$src2, node:$src3, node:$src4, node:$src5, node:$src6, node:$src7),
-  (vt (Op $src0, $src1, $src2, $src3, $src4, $src5, $src6, $src7))> {
-  let HasNoUse = true;
-}
-
-multiclass BufferAtomicPatterns_NO_RTN<SDPatternOperator name, ValueType vt,
-                                       string opcode> {
-  def : GCNPat<
-    (NoUseBufferAtomic<name, vt> vt:$vdata_in, v4i32:$rsrc, 0,
-                                 0, i32:$soffset, timm:$offset,
-                                 timm:$cachepolicy, 0),
-    (!cast<MUBUF_Pseudo>(opcode # _OFFSET) getVregSrcForVT<vt>.ret:$vdata_in, SReg_128:$rsrc, SCSrc_b32:$soffset,
-                                          timm:$offset, timm:$cachepolicy)
-  >;
-
-  def : GCNPat<
-    (NoUseBufferAtomic<name, vt> vt:$vdata_in, v4i32:$rsrc, i32:$vindex,
-                                 0, i32:$soffset, timm:$offset,
-                                 timm:$cachepolicy, timm),
-    (!cast<MUBUF_Pseudo>(opcode # _IDXEN) getVregSrcForVT<vt>.ret:$vdata_in, VGPR_32:$vindex, SReg_128:$rsrc, SCSrc_b32:$soffset,
-                                          timm:$offset, timm:$cachepolicy)
-  >;
-
-  def : GCNPat<
-    (NoUseBufferAtomic<name, vt> vt:$vdata_in, v4i32:$rsrc, 0,
-                                 i32:$voffset, i32:$soffset, timm:$offset,
-                                 timm:$cachepolicy, 0),
-    (!cast<MUBUF_Pseudo>(opcode # _OFFEN) getVregSrcForVT<vt>.ret:$vdata_in, VGPR_32:$voffset, SReg_128:$rsrc, SCSrc_b32:$soffset,
-                                          timm:$offset, timm:$cachepolicy)
-  >;
-
-  def : GCNPat<
-    (NoUseBufferAtomic<name, vt> vt:$vdata_in, v4i32:$rsrc, i32:$vindex,
-                                 i32:$voffset, i32:$soffset, timm:$offset,
-                                 timm:$cachepolicy, timm),
-    (!cast<MUBUF_Pseudo>(opcode # _BOTHEN)
-      getVregSrcForVT<vt>.ret:$vdata_in,
-      (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
-      SReg_128:$rsrc, SCSrc_b32:$soffset, timm:$offset, timm:$cachepolicy)
-  >;
-}
-
 let SubtargetPredicate = HasAtomicFaddNoRtnInsts in
 defm : SIBufferAtomicPat<"SIbuffer_atomic_fadd", f32, "BUFFER_ATOMIC_ADD_F32", ["noret"]>;
 
diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt
--- a/llvm/lib/Target/AMDGPU/CMakeLists.txt
+++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt
@@ -5,7 +5,8 @@
 tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel
+              -warn-on-unused-entities)
 tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
@@ -16,7 +17,8 @@
 tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
 
 set(LLVM_TARGET_DEFINITIONS AMDGPUGISel.td)
-tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel
+              -warn-on-unused-entities)
 tablegen(LLVM AMDGPUGenPreLegalizeGICombiner.inc -gen-global-isel-combiner
               -combiners="AMDGPUPreLegalizerCombinerHelper")
 tablegen(LLVM AMDGPUGenPostLegalizeGICombiner.inc -gen-global-isel-combiner
@@ -27,7 +29,8 @@
 set(LLVM_TARGET_DEFINITIONS R600.td)
 tablegen(LLVM R600GenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM R600GenCallingConv.inc -gen-callingconv)
-tablegen(LLVM R600GenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM R600GenDAGISel.inc -gen-dag-isel
+              -warn-on-unused-entities)
 tablegen(LLVM R600GenDFAPacketizer.inc -gen-dfa-packetizer)
 tablegen(LLVM R600GenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM R600GenMCCodeEmitter.inc -gen-emitter)
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -374,15 +374,6 @@
   let has_data1 = 0;
 }
 
-multiclass DS_1A_mc <string opName> {
-  def "" : DS_1A<opName>;
-
-  let has_m0_read = 0 in {
-    def _gfx9 : DS_1A<opName>;
-  }
-}
-
-
 class DS_GWS <string opName, dag ins, string asmOps>
 : DS_Pseudo<opName, (outs), ins, asmOps> {
 
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -1008,12 +1008,6 @@
   (inst $voffset, getVregSrcForVT<data_vt>.ret:$data, $saddr, $offset)
 >;
 
-class GlobalAtomicNoRtnSaddrPat <FLAT_Pseudo inst, SDPatternOperator node,
-                                 ValueType vt> : GCNPat <
-  (node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i32:$offset), vt:$data),
-  (inst $voffset, getVregSrcForVT<vt>.ret:$data, $saddr, $offset)
->;
-
 class FlatStorePat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
   (node vt:$data, (FlatOffset i64:$vaddr, i32:$offset)),
   (inst $vaddr, getVregSrcForVT<vt>.ret:$data, $offset)
diff --git a/llvm/lib/Target/AMDGPU/R600Instructions.td b/llvm/lib/Target/AMDGPU/R600Instructions.td
--- a/llvm/lib/Target/AMDGPU/R600Instructions.td
+++ b/llvm/lib/Target/AMDGPU/R600Instructions.td
@@ -79,6 +79,23 @@
 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
 
+class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
+: Instruction {
+
+     let Namespace = "AMDGPU";
+     dag OutOperandList = outs;
+     dag InOperandList = ins;
+     let Pattern = pattern;
+     let AsmString = !strconcat(asmstr, "\n");
+     let isPseudo = 1;
+     let Itinerary = NullALU;
+     bit hasIEEEFlag = 0;
+     bit hasZeroOpFlag = 0;
+     let mayLoad = 0;
+     let mayStore = 0;
+     let hasSideEffects = 0;
+     let isCodeGenOnly = 1;
+}
 
 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
                                      (ops PRED_SEL_OFF)>;
@@ -365,6 +382,12 @@
 // R600 SDNodes
 //===----------------------------------------------------------------------===//
 
+class AMDGPUShaderInst <dag outs, dag ins, string asm = "",
+  list<dag> pattern = []> : AMDGPUInst<outs, ins, asm, pattern> {
+
+  field bits<32> Inst = 0xffffffff;
+}
+
 let Namespace = "R600" in {
 
 def INTERP_PAIR_XY :  AMDGPUShaderInst <
@@ -1218,7 +1241,10 @@
   (MUL_IEEE $src0, (recip_ieee $src1))
 >;
 
-def : RcpPat<recip_ieee, f32>;
+def : AMDGPUPat <
+  (fdiv FP_ONE, f32:$src),
+  (recip_ieee $src)
+>;
 }
 
 class SqrtPat<Instruction RsqInst, Instruction RecipInst> : R600Pat <
@@ -1226,6 +1252,12 @@
   (RecipInst (RsqInst $src))
 >;
 
+class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
+  : AMDGPUPat <
+  (fpow f32:$src0, f32:$src1),
+  (exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
+>;
+
 //===----------------------------------------------------------------------===//
 // R600 / R700 Instructions
 //===----------------------------------------------------------------------===//
@@ -1776,7 +1808,12 @@
 def : BitConvert <v4i32, v4f32, R600_Reg128>;
 
 // DWORDADDR pattern
-def : DwordAddrPat  <i32, R600_Reg32>;
+// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
+// can handle COPY instructions.
+def : AMDGPUPat <
+  (i32 (AMDGPUdwordaddr (i32 R600_Reg32:$addr))),
+  (i32 R600_Reg32:$addr)
+>;
 
 } // End SubtargetPredicate = isR600toCayman
 
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -238,13 +238,6 @@
   let HasNoUse = true;
 }
 
-class SDGlobalAtomicNoRtn<string opcode, ValueType ty> : SDNode <opcode,
-  SDTypeProfile<0, 2,
-      [SDTCisPtrTy<0>,     // vaddr
-       SDTCisVT<1, ty>]>,  // vdata
-  [SDNPMemOperand, SDNPHasChain, SDNPMayLoad, SDNPMayStore]
->;
-
 def SIpc_add_rel_offset : SDNode<"AMDGPUISD::PC_ADD_REL_OFFSET",
   SDTypeProfile<1, 2, [SDTCisVT<0, iPTR>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>
 >;
@@ -819,12 +812,6 @@
   N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
 }]>;
 
-class bitextract_imm<int bitnum> : SDNodeXForm<imm, [{
-  uint64_t Imm = N->getZExtValue();
-  unsigned Bit = (Imm >> }] # bitnum # [{ ) & 1;
-  return CurDAG->getTargetConstant(Bit, SDLoc(N), MVT::i1);
-}]>;
-
 def SIMM16bit : ImmLeaf <i32,
   [{return isInt<16>(Imm);}]
 >;
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2006,6 +2006,8 @@
   }]
 >;
 
+let GIIgnoreCopies = 1 in
+class AMDGPUPatIgnoreCopies<dag pattern, dag result> : AMDGPUPat<pattern, result>;
 
 // Definition from ISA doc:
 // (y & x) | (z & ~x)
@@ -2869,6 +2871,27 @@
 >;
 }
 
+class is_canonicalized<SDPatternOperator op> : PatFrag<
+  (ops node:$src0, node:$src1),
+  (op $src0, $src1),
+  [{
+    const SITargetLowering &Lowering =
+              *static_cast<const SITargetLowering *>(getTargetLowering());
+
+    return Lowering.isCanonicalized(*CurDAG, N->getOperand(0)) &&
+      Lowering.isCanonicalized(*CurDAG, N->getOperand(1));
+   }]> {
+
+  // TODO: Improve the Legalizer for g_build_vector in Global Isel to match this class
+  let GISelPredicateCode = [{
+    const SITargetLowering *TLI = static_cast<const SITargetLowering *>(
+      MF.getSubtarget().getTargetLowering());
+
+    return TLI->isCanonicalized(MI.getOperand(1).getReg(), const_cast<MachineFunction&>(MF)) &&
+      TLI->isCanonicalized(MI.getOperand(2).getReg(), const_cast<MachineFunction&>(MF));
+  }];
+}
+
 let SubtargetPredicate = HasVOP3PInsts in {
 def : GCNPat <
   (v2i16 (UniformBinFrag<build_vector> (i16 SReg_32:$src0), (i16 SReg_32:$src1))),
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -2056,18 +2056,12 @@
                SOPPRelaxTable<1, ps.KeyName, "_gfx10">;
 }
 
-multiclass SOPP_Real_64_gfx8_gfx9_gfx10<bits<7> op> :
-  SOPP_Real_64_gfx8_gfx9<op>, SOPP_Real_64_gfx10<op>;
-
 multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9<bits<7> op> :
   SOPP_Real_64_gfx6_gfx7<op>, SOPP_Real_64_gfx8_gfx9<op>;
 
 multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10<bits<7> op> :
   SOPP_Real_64_gfx6_gfx7_gfx8_gfx9<op>, SOPP_Real_64_gfx10<op>;
 
-multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11<bits<7> op> :
-  SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10<op>, SOPP_Real_64_gfx11<op>;
-
 //relaxation for insts with no operands not implemented
 multiclass SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<bits<7> op> {
   defm "" : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<op>;
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -118,18 +118,6 @@
   VOP_DPP_Pseudo <OpName, P, pattern> {
 }
 
-
-class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {
-  list<dag> ret = !if(P.HasModifiers,
-    [(set P.DstVT:$vdst,
-      (node (P.Src0VT
-              !if(P.HasOMod,
-                  (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
-                  (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
-            (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
-    [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
-}
-
 multiclass VOP2Inst_e32<string opName,
                         VOPProfile P,
                         SDPatternOperator node = null_frag,
@@ -1261,11 +1249,6 @@
     let IsSingle = 1 in
       defm NAME: VOP2_Real_e32_gfx11<op>;
   }
-  multiclass VOP2_Real_e64_gfx11<bits<6> op> {
-    def _e64_gfx11 :
-      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX11>,
-      VOP3e_gfx11<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
-  }
   multiclass VOP2_Real_dpp_gfx11<bits<6> op> {
     if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then
     def _dpp_gfx11 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX11> {
@@ -1433,9 +1416,6 @@
 multiclass VOP2_Real_FULL_t16_gfx11<bits<6> op, string asmName, string opName = NAME>
     : VOP2_Real_FULL_with_name_gfx11<op, opName, asmName>;
 
-multiclass VOP2_Real_NO_DPP_gfx11<bits<6> op> :
-  VOP2_Real_e32_gfx11<op>, VOP2_Real_e64_gfx11<op>;
-
 multiclass VOP2_Real_NO_DPP_with_name_gfx11<bits<6> op, string opName,
                                            string asmName> {
   defm NAME : VOP2_Real_e32_with_name_gfx11<op, opName, asmName>,
@@ -1514,15 +1494,6 @@
       VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>,
       VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
   }
-  multiclass VOP2Only_Real_MADK_gfx10_with_name<bits<6> op, string opName,
-                                                string asmName> {
-    def _gfx10 :
-        VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX10>,
-        VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> {
-      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName);
-      let AsmString = asmName # ps.AsmOperands;
-    }
-  }
   multiclass VOP2_Real_e32_gfx10<bits<6> op> {
     def _e32_gfx10 :
       VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -1262,14 +1262,6 @@
             }
 }
 
-multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> {
-  def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
-              VOP3e_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl> {
-              VOP_Pseudo ps = !cast<VOP_Pseudo>(NAME#"_e64");
-              let AsmString = AsmName # ps.AsmOperands;
-            }
-}
-
 } // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9"
 
 defm V_MAD_U64_U32      : VOP3be_Real_vi <0x1E8>;
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -1954,9 +1954,6 @@
 multiclass VOPC_Real_gfx6_gfx7_gfx10_gfx11<bits<9> op> :
   VOPC_Real_gfx6_gfx7_gfx10<op>, VOPC_Real_gfx11<op>;
 
-multiclass VOPCX_Real_gfx6_gfx7_gfx10_gfx11<bits<9> op> :
-  VOPCX_Real_gfx6_gfx7_gfx10<op>, VOPCX_Real_gfx11<op>;
-
 defm V_CMP_F_F32      : VOPC_Real_gfx6_gfx7_gfx10<0x000>;
 defm V_CMP_LT_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x001>;
 defm V_CMP_EQ_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x002>;
diff --git a/llvm/lib/Target/AMDGPU/VOPDInstructions.td b/llvm/lib/Target/AMDGPU/VOPDInstructions.td
--- a/llvm/lib/Target/AMDGPU/VOPDInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPDInstructions.td
@@ -54,6 +54,11 @@
 // VOPD classes
 //===----------------------------------------------------------------------===//
 
+// Get the union of two Register lists
+class RegListUnion<list<Register> lstA, list<Register> lstB> {
+  list<Register> ret = !listconcat(lstA, !listremove(lstB, lstA));
+}
+
 class VOPD_Base<dag outs, dag ins, string asm, VOP_Pseudo VDX, VOP_Pseudo VDY,
                 VOPD_Component XasVC, VOPD_Component YasVC>
     : VOPAnyCommon<outs, ins, asm, []>,
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -313,8 +313,6 @@
   let Inst{62}    = !if(p.HasSrc0Mods, src0_modifiers{0}, 0);
 }
 
-class VOP3Interp_gfx11<bits<10> op, VOPProfile p> : VOP3Interp_gfx10<op, p>;
-
 class VOP3be <VOPProfile P> : Enc64 {
   bits<8> vdst;
   bits<2> src0_modifiers;