diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -279,3 +279,6 @@ ``XSfvcp`` LLVM implements `version 1.0.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification `_ by SiFive. All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above. + +``XCVbitmanip`` + LLVM implements `version 1.3.1 of the Core-V bit manipulation custom instructions specification `_ by Core-V. All instructions are prefixed with `cv.` as described in the specification. diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -558,6 +558,9 @@ "XTHeadVdot custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32, "SiFive VCIX custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip, + DecoderTableXCVbitmanip32, + "CORE-V Bit Manipulation custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -752,6 +752,14 @@ AssemblerPredicate<(all_of FeatureVendorXSfvcp), "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">; + +def FeatureVendorXCVbitmanip + : SubtargetFeature<"xcvbitmanip", "HasVendorXCVbitmanip", "true", + "'XCVbitmanip' (Bit Manipulation)">; +def HasVendorXCVbitmanip : Predicate<"Subtarget->hasVendorXCVbitmanip()">, + AssemblerPredicate<(all_of FeatureVendorXCVbitmanip), + "'XCVbitmanip' (Bit Manipulation)">; + //===----------------------------------------------------------------------===// // LLVM specific features and extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1919,3 +1919,4 @@ include "RISCVInstrInfoXVentana.td" include "RISCVInstrInfoXTHead.td" include "RISCVInstrInfoXSf.td" +include "RISCVInstrInfoXCVbitmanip.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCVbitmanip.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCVbitmanip.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCVbitmanip.td @@ -0,0 +1,109 @@ +//===-- RISCVInstrInfoXCVbitmanip.td - CORE-V instructions -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the vendor extensions defined by Core-V bit-manipulation +// extension. +// +//===----------------------------------------------------------------------===// + +class RVInstBitManipRII funct2, bits<3> funct3, dag outs, dag ins, + string opcodestr, string argstr, list pattern> + : RVInst { + bits<5> is3; + bits<5> is2; + bits<5> rs1; + bits<5> rd; + + let Inst{31-30} = funct2; + let Inst{29-25} = is3; + let Inst{24-20} = is2; + let Inst{19-15} = rs1; + let Inst{14-12} = funct3; + let Inst{11-7} = rd; + let Opcode = OPC_CUSTOM_2.Value; + let DecoderNamespace = "XCVbitmanip"; +} + + +class RVInstBitManipRR funct7, bits<3> funct3, dag outs, dag ins, + string opcodestr, string argstr, list pattern> + : RVInst { + bits<5> rs2; + bits<5> rs1; + bits<5> rd; + + let Inst{31-25} = funct7; + let Inst{24-20} = rs2; + let Inst{19-15} = rs1; + let Inst{14-12} = funct3; + let Inst{11-7} = rd; + let Opcode = OPC_CUSTOM_1.Value; + let DecoderNamespace = "XCVbitmanip"; +} + + +class RVInstBitManipR funct7, bits<3> funct3, dag outs, dag ins, + string opcodestr, string argstr, list pattern> + : RVInst { + bits<5> rs1; + bits<5> rd; + + let Inst{31-25} = funct7; + let Inst{24-20} = 0b00000; + let Inst{19-15} = rs1; + let Inst{14-12} = funct3; + let Inst{11-7} = rd; + let Opcode = OPC_CUSTOM_1.Value; + let DecoderNamespace = "XCVbitmanip"; +} + +class CVBitManipRII funct2, bits<3> funct3, string opcodestr> + : RVInstBitManipRII; + +class CVBitManipRR funct7, string opcodestr> + : RVInstBitManipRR; + +class CVBitManipR funct7, string opcodestr> + : RVInstBitManipR; + +let Predicates = [HasVendorXCVbitmanip, IsRV32], + hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { + def CV_EXTRACT : CVBitManipRII<0b00, 0b000, "cv.extract">; + def CV_EXTRACTU : CVBitManipRII<0b01, 0b000, "cv.extractu">; + + def CV_BCLR : CVBitManipRII<0b00, 0b001, "cv.bclr">; + def CV_BSET : CVBitManipRII<0b01, 0b001, "cv.bset">; + def CV_BITREV : RVInstBitManipRII<0b11, 0b001, (outs GPR:$rd), + (ins GPR:$rs1, uimm2:$is3, uimm5:$is2), + "cv.bitrev", "$rd, $rs1, $is3, $is2", []>; + + def CV_EXTRACTR : CVBitManipRR<0b0011000, "cv.extractr">; + def CV_EXTRACTUR : CVBitManipRR<0b0011001, "cv.extractur">; + + let Constraints = "$rd = $rd_wb" in { + def CV_INSERT : RVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb), + (ins GPR:$rs1, uimm5:$is3, uimm5:$is2, GPR:$rd), + "cv.insert", "$rd, $rs1, $is3, $is2", []>; + def CV_INSERTR : RVInstBitManipRR<0b0011010, 0b011, (outs GPR:$rd_wb), + (ins GPR:$rs1, GPR:$rs2, GPR:$rd), + "cv.insertr", "$rd, $rs1, $rs2", []>; + } + + def CV_BCLRR : CVBitManipRR<0b0011100, "cv.bclrr">; + def CV_BSETR : CVBitManipRR<0b0011101, "cv.bsetr">; + + def CV_ROR : CVBitManipRR<0b0100000, "cv.ror">; + def CV_FF1 : CVBitManipR<0b0100001, "cv.ff1">; + def CV_FL1 : CVBitManipR<0b0100010, "cv.fl1">; + def CV_CLB : CVBitManipR<0b0100011, "cv.clb">; + def CV_CNT : CVBitManipR<0b0100100, "cv.cnt">; +} diff --git a/llvm/test/MC/RISCV/corev/XCVbitmanip-invalid.s b/llvm/test/MC/RISCV/corev/XCVbitmanip-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/corev/XCVbitmanip-invalid.s @@ -0,0 +1,267 @@ +# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvbitmanip %s 2>&1 \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR + +cv.extract t0, t1 +# CHECK-ERROR: too few operands for instruction + +cv.extract t0, t1, 0 +# CHECK-ERROR: too few operands for instruction + +cv.extract t0, t1, t2 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.extract t0, t1, t2, t3 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.extract t0, t1, 0, 32 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.extract t0, t1, 0, -1 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.extract t0, t1, 32, 0 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.extract t0, t1, -1, 0 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.extractu t0, t1 +# CHECK-ERROR: too few operands for instruction + +cv.extractu t0, t1, 0 +# CHECK-ERROR: too few operands for instruction + +cv.extractu t0, t1, t2 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.extractu t0, t1, t2, t3 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.extractu t0, t1, 0, 32 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.extractu t0, t1, 0, -1 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.extractu t0, t1, 32, 0 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.extractu t0, t1, -1, 0 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.insert t0, t1 +# CHECK-ERROR: too few operands for instruction + +cv.insert t0, t1, 0 +# CHECK-ERROR: too few operands for instruction + +cv.insert t0, t1, t2 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.insert t0, t1, t2, t3 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.insert t0, t1, 0, 32 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.insert t0, t1, 0, -1 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.insert t0, t1, 32, 0 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.insert t0, t1, -1, 0 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.bclr t0, t1 +# CHECK-ERROR: too few operands for instruction + +cv.bclr t0, t1, 0 +# CHECK-ERROR: too few operands for instruction + +cv.bclr t0, t1, t2 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.bclr t0, t1, t2, t3 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.bclr t0, t1, 0, 32 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.bclr t0, t1, 0, -1 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.bclr t0, t1, 32, 0 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.bclr t0, t1, -1, 0 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.bset t0, t1 +# CHECK-ERROR: too few operands for instruction + +cv.bset t0, t1, 0 +# CHECK-ERROR: too few operands for instruction + +cv.bset t0, t1, t2 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.bset t0, t1, t2, t3 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.bset t0, t1, 0, 32 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.bset t0, t1, 0, -1 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.bset t0, t1, 32, 0 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.bset t0, t1, -1, 0 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.bitrev t0, t1 +# CHECK-ERROR: too few operands for instruction + +cv.bitrev t0, t1, 0 +# CHECK-ERROR: too few operands for instruction + +cv.bitrev t0, t1, t2 +# CHECK-ERROR: immediate must be an integer in the range [0, 3] + +cv.bitrev t0, t1, t2, t3 +# CHECK-ERROR: immediate must be an integer in the range [0, 3] + +cv.bitrev t0, t1, 0, 32 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.bitrev t0, t1, 0, -1 +# CHECK-ERROR: immediate must be an integer in the range [0, 31] + +cv.bitrev t0, t1, 32, 0 +# CHECK-ERROR: immediate must be an integer in the range [0, 3] + +cv.bitrev t0, t1, -1, 0 +# CHECK-ERROR: immediate must be an integer in the range [0, 3] + +cv.extractr t0 +# CHECK-ERROR: too few operands for instruction + +cv.extractr t0, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.extractr t0, t1, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.extractr t0, t1 +# CHECK-ERROR: too few operands for instruction + +cv.extractur t0 +# CHECK-ERROR: too few operands for instruction + +cv.extractur t0, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.extractur t0, t1, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.extractur t0, t1 +# CHECK-ERROR: too few operands for instruction + +cv.insertr t0 +# CHECK-ERROR: too few operands for instruction + +cv.insertr t0, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.insertr t0, t1, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.insertr t0, t1 +# CHECK-ERROR: too few operands for instruction + +cv.bclrr t0 +# CHECK-ERROR: too few operands for instruction + +cv.bclrr t0, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.bclrr t0, t1, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.bclrr t0, t1 +# CHECK-ERROR: too few operands for instruction + +cv.bsetr t0 +# CHECK-ERROR: too few operands for instruction + +cv.bsetr t0, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.bsetr t0, t1, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.bsetr t0, t1 +# CHECK-ERROR: too few operands for instruction + +cv.ror t0 +# CHECK-ERROR: too few operands for instruction + +cv.ror t0, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.ror t0, t1, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.ror t0, t1 +# CHECK-ERROR: too few operands for instruction + +cv.ff1 t0 +# CHECK-ERROR: too few operands for instruction + +cv.ff1 t0, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.ff1 t0, t1, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.ff1 t0, t1, t2 +# CHECK-ERROR: invalid operand for instruction + +cv.fl1 t0 +# CHECK-ERROR: too few operands for instruction + +cv.fl1 t0, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.fl1 t0, t1, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.fl1 t0, t1, t2 +# CHECK-ERROR: invalid operand for instruction + +cv.clb t0 +# CHECK-ERROR: too few operands for instruction + +cv.clb t0, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.clb t0, t1, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.clb t0, t1, t2 +# CHECK-ERROR: invalid operand for instruction + +cv.cnt t0 +# CHECK-ERROR: too few operands for instruction + +cv.cnt t0, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.cnt t0, t1, 0 +# CHECK-ERROR: invalid operand for instruction + +cv.cnt t0, t1, t2 +# CHECK-ERROR: invalid operand for instruction + diff --git a/llvm/test/MC/RISCV/corev/XCVbitmanip.s b/llvm/test/MC/RISCV/corev/XCVbitmanip.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/corev/XCVbitmanip.s @@ -0,0 +1,246 @@ +# RUN: llvm-mc -triple=riscv32 --mattr=+xcvbitmanip -show-encoding %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR +# +# RUN: not llvm-mc -triple riscv32 %s 2>&1 \ +# RUN: | FileCheck -check-prefix=CHECK-NO-EXT %s + +cv.extract t0, t1, 0, 1 +# CHECK-INSTR: cv.extract t0, t1, 0, 1 +# CHECK-ENCODING: [0xdb,0x02,0x13,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.extract a0, a1, 17, 18 +# CHECK-INSTR: cv.extract a0, a1, 17, 18 +# CHECK-ENCODING: [0x5b,0x85,0x25,0x23] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.extract s0, s1, 30, 31 +# CHECK-INSTR: cv.extract s0, s1, 30, 31 +# CHECK-ENCODING: [0x5b,0x84,0xf4,0x3d] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.extractu t0, t1, 0, 1 +# CHECK-INSTR: cv.extractu t0, t1, 0, 1 +# CHECK-ENCODING: [0xdb,0x02,0x13,0x40] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.extractu a0, a1, 17, 18 +# CHECK-INSTR: cv.extractu a0, a1, 17, 18 +# CHECK-ENCODING: [0x5b,0x85,0x25,0x63] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.extractu s0, s1, 30, 31 +# CHECK-INSTR: cv.extractu s0, s1, 30, 31 +# CHECK-ENCODING: [0x5b,0x84,0xf4,0x7d] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.insert t0, t1, 0, 1 +# CHECK-INSTR: cv.insert t0, t1, 0, 1 +# CHECK-ENCODING: [0xdb,0x02,0x13,0x80] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.insert a0, a1, 17, 18 +# CHECK-INSTR: cv.insert a0, a1, 17, 18 +# CHECK-ENCODING: [0x5b,0x85,0x25,0xa3] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.insert s0, s1, 30, 31 +# CHECK-INSTR: cv.insert s0, s1, 30, 31 +# CHECK-ENCODING: [0x5b,0x84,0xf4,0xbd] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.bclr t0, t1, 0, 1 +# CHECK-INSTR: cv.bclr t0, t1, 0, 1 +# CHECK-ENCODING: [0xdb,0x12,0x13,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.bclr a0, a1, 17, 18 +# CHECK-INSTR: cv.bclr a0, a1, 17, 18 +# CHECK-ENCODING: [0x5b,0x95,0x25,0x23] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.bclr s0, s1, 30, 31 +# CHECK-INSTR: cv.bclr s0, s1, 30, 31 +# CHECK-ENCODING: [0x5b,0x94,0xf4,0x3d] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.bset t0, t1, 0, 1 +# CHECK-INSTR: cv.bset t0, t1, 0, 1 +# CHECK-ENCODING: [0xdb,0x12,0x13,0x40] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.bset a0, a1, 17, 18 +# CHECK-INSTR: cv.bset a0, a1, 17, 18 +# CHECK-ENCODING: [0x5b,0x95,0x25,0x63] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.bset s0, s1, 30, 31 +# CHECK-INSTR: cv.bset s0, s1, 30, 31 +# CHECK-ENCODING: [0x5b,0x94,0xf4,0x7d] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.bitrev t0, t1, 0, 1 +# CHECK-INSTR: cv.bitrev t0, t1, 0, 1 +# CHECK-ENCODING: [0xdb,0x12,0x13,0xc0] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.bitrev a0, a1, 1, 18 +# CHECK-INSTR: cv.bitrev a0, a1, 1, 18 +# CHECK-ENCODING: [0x5b,0x95,0x25,0xc3] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.bitrev s0, s1, 2, 31 +# CHECK-INSTR: cv.bitrev s0, s1, 2, 31 +# CHECK-ENCODING: [0x5b,0x94,0xf4,0xc5] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.extractr t0, t1, t2 +# CHECK-INSTR: cv.extractr t0, t1, t2 +# CHECK-ENCODING: [0xab,0x32,0x73,0x30] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.extractr a0, a1, a2 +# CHECK-INSTR: cv.extractr a0, a1, a2 +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x30] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.extractr s0, s1, s2 +# CHECK-INSTR: cv.extractr s0, s1, s2 +# CHECK-ENCODING: [0x2b,0xb4,0x24,0x31] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.extractur t0, t1, t2 +# CHECK-INSTR: cv.extractur t0, t1, t2 +# CHECK-ENCODING: [0xab,0x32,0x73,0x32] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.extractur a0, a1, a2 +# CHECK-INSTR: cv.extractur a0, a1, a2 +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x32] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.extractur s0, s1, s2 +# CHECK-INSTR: cv.extractur s0, s1, s2 +# CHECK-ENCODING: [0x2b,0xb4,0x24,0x33] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.insertr t0, t1, t2 +# CHECK-INSTR: cv.insertr t0, t1, t2 +# CHECK-ENCODING: [0xab,0x32,0x73,0x34] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.insertr a0, a1, a2 +# CHECK-INSTR: cv.insertr a0, a1, a2 +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x34] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.insertr s0, s1, s2 +# CHECK-INSTR: cv.insertr s0, s1, s2 +# CHECK-ENCODING: [0x2b,0xb4,0x24,0x35] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.bclrr t0, t1, t2 +# CHECK-INSTR: cv.bclrr t0, t1, t2 +# CHECK-ENCODING: [0xab,0x32,0x73,0x38] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.bclrr a0, a1, a2 +# CHECK-INSTR: cv.bclrr a0, a1, a2 +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x38] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.bclrr s0, s1, s2 +# CHECK-INSTR: cv.bclrr s0, s1, s2 +# CHECK-ENCODING: [0x2b,0xb4,0x24,0x39] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.bsetr t0, t1, t2 +# CHECK-INSTR: cv.bsetr t0, t1, t2 +# CHECK-ENCODING: [0xab,0x32,0x73,0x3a] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.bsetr a0, a1, a2 +# CHECK-INSTR: cv.bsetr a0, a1, a2 +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x3a] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.bsetr s0, s1, s2 +# CHECK-INSTR: cv.bsetr s0, s1, s2 +# CHECK-ENCODING: [0x2b,0xb4,0x24,0x3b] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.ror t0, t1, t2 +# CHECK-INSTR: cv.ror t0, t1, t2 +# CHECK-ENCODING: [0xab,0x32,0x73,0x40] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.ror a0, a1, a2 +# CHECK-INSTR: cv.ror a0, a1, a2 +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x40] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.ror s0, s1, s2 +# CHECK-INSTR: cv.ror s0, s1, s2 +# CHECK-ENCODING: [0x2b,0xb4,0x24,0x41] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.ff1 t0, t1 +# CHECK-INSTR: cv.ff1 t0, t1 +# CHECK-ENCODING: [0xab,0x32,0x03,0x42] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.ff1 a0, a1 +# CHECK-INSTR: cv.ff1 a0, a1 +# CHECK-ENCODING: [0x2b,0xb5,0x05,0x42] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.ff1 s0, s1 +# CHECK-INSTR: cv.ff1 s0, s1 +# CHECK-ENCODING: [0x2b,0xb4,0x04,0x42] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.fl1 t0, t1 +# CHECK-INSTR: cv.fl1 t0, t1 +# CHECK-ENCODING: [0xab,0x32,0x03,0x44] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.fl1 a0, a1 +# CHECK-INSTR: cv.fl1 a0, a1 +# CHECK-ENCODING: [0x2b,0xb5,0x05,0x44] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.fl1 s0, s1 +# CHECK-INSTR: cv.fl1 s0, s1 +# CHECK-ENCODING: [0x2b,0xb4,0x04,0x44] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.clb t0, t1 +# CHECK-INSTR: cv.clb t0, t1 +# CHECK-ENCODING: [0xab,0x32,0x03,0x46] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.clb a0, a1 +# CHECK-INSTR: cv.clb a0, a1 +# CHECK-ENCODING: [0x2b,0xb5,0x05,0x46] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.clb s0, s1 +# CHECK-INSTR: cv.clb s0, s1 +# CHECK-ENCODING: [0x2b,0xb4,0x04,0x46] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.cnt t0, t1 +# CHECK-INSTR: cv.cnt t0, t1 +# CHECK-ENCODING: [0xab,0x32,0x03,0x48] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.cnt a0, a1 +# CHECK-INSTR: cv.cnt a0, a1 +# CHECK-ENCODING: [0x2b,0xb5,0x05,0x48] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} + +cv.cnt s0, s1 +# CHECK-INSTR: cv.cnt s0, s1 +# CHECK-ENCODING: [0x2b,0xb4,0x04,0x48] +# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}} +