Index: llvm/lib/Target/AArch64/AArch64.td =================================================================== --- llvm/lib/Target/AArch64/AArch64.td +++ llvm/lib/Target/AArch64/AArch64.td @@ -811,6 +811,7 @@ def TuneA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", "Cortex-A76 ARM processors", [ + FeatureCustomCheapAsMoveHandling, FeatureFuseAES, FeatureFuseAdrpAdd, FeatureLSLFast, @@ -818,6 +819,7 @@ def TuneA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", "Cortex-A77 ARM processors", [ + FeatureCustomCheapAsMoveHandling, FeatureCmpBccFusion, FeatureFuseAES, FeatureFuseAdrpAdd, @@ -826,6 +828,7 @@ def TuneA78 : SubtargetFeature<"a78", "ARMProcFamily", "CortexA78", "Cortex-A78 ARM processors", [ + FeatureCustomCheapAsMoveHandling, FeatureCmpBccFusion, FeatureFuseAES, FeatureFuseAdrpAdd, @@ -836,6 +839,7 @@ def TuneA78C : SubtargetFeature<"a78c", "ARMProcFamily", "CortexA78C", "Cortex-A78C ARM processors", [ + FeatureCustomCheapAsMoveHandling, FeatureCmpBccFusion, FeatureFuseAES, FeatureFuseAdrpAdd, @@ -845,6 +849,7 @@ def TuneA710 : SubtargetFeature<"a710", "ARMProcFamily", "CortexA710", "Cortex-A710 ARM processors", [ + FeatureCustomCheapAsMoveHandling, FeatureCmpBccFusion, FeatureFuseAES, FeatureFuseAdrpAdd, @@ -854,6 +859,7 @@ def TuneA715 : SubtargetFeature<"a715", "ARMProcFamily", "CortexA715", "Cortex-A715 ARM processors", [ + FeatureCustomCheapAsMoveHandling, FeatureFuseAES, FeaturePostRAScheduler, FeatureCmpBccFusion, @@ -868,6 +874,7 @@ def TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", "Cortex-X1 ARM processors", [ + FeatureCustomCheapAsMoveHandling, FeatureCmpBccFusion, FeatureFuseAES, FeatureFuseAdrpAdd, @@ -877,6 +884,7 @@ def TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2", "Cortex-X2 ARM processors", [ + FeatureCustomCheapAsMoveHandling, FeatureCmpBccFusion, FeatureFuseAES, FeatureFuseAdrpAdd, @@ -886,6 +894,7 @@ def TuneX3 : SubtargetFeature<"cortex-x3", "ARMProcFamily", "CortexX3", "Cortex-X3 ARM processors", [ + FeatureCustomCheapAsMoveHandling, FeatureLSLFast, FeatureFuseAdrpAdd, FeatureFuseAES, @@ -1017,6 +1026,7 @@ def TuneExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", "Samsung Exynos-M3 processors", [FeatureExynosCheapAsMoveHandling, + FeatureCustomCheapAsMoveHandling, FeatureForce32BitJumpTables, FeatureFuseAddress, FeatureFuseAES, @@ -1071,6 +1081,7 @@ def TuneNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", "NeoverseN1", "Neoverse N1 ARM processors", [ + FeatureCustomCheapAsMoveHandling, FeatureFuseAES, FeatureFuseAdrpAdd, FeatureLSLFast, @@ -1079,6 +1090,7 @@ def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2", "Neoverse N2 ARM processors", [ + FeatureCustomCheapAsMoveHandling, FeatureFuseAES, FeatureFuseAdrpAdd, FeatureLSLFast, @@ -1087,6 +1099,7 @@ def TuneNeoverse512TVB : SubtargetFeature<"neoverse512tvb", "ARMProcFamily", "Neoverse512TVB", "Neoverse 512-TVB ARM processors", [ + FeatureCustomCheapAsMoveHandling, FeatureFuseAES, FeatureFuseAdrpAdd, FeatureLSLFast, @@ -1095,6 +1108,7 @@ def TuneNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", "NeoverseV1", "Neoverse V1 ARM processors", [ + FeatureCustomCheapAsMoveHandling, FeatureFuseAES, FeatureFuseAdrpAdd, FeatureLSLFast, @@ -1103,6 +1117,7 @@ def TuneNeoverseV2 : SubtargetFeature<"neoversev2", "ARMProcFamily", "NeoverseV2", "Neoverse V2 ARM processors", [ + FeatureCustomCheapAsMoveHandling, FeatureFuseAES, FeatureLSLFast, FeaturePostRAScheduler, @@ -1164,6 +1179,7 @@ def TuneAmpere1 : SubtargetFeature<"ampere1", "ARMProcFamily", "Ampere1", "Ampere Computing Ampere-1 processors", [ + FeatureCustomCheapAsMoveHandling, FeaturePostRAScheduler, FeatureFuseAES, FeatureLSLFast, @@ -1175,6 +1191,7 @@ def TuneAmpere1A : SubtargetFeature<"ampere1a", "ARMProcFamily", "Ampere1A", "Ampere Computing Ampere-1A processors", [ + FeatureCustomCheapAsMoveHandling, FeaturePostRAScheduler, FeatureFuseAES, FeatureLSLFast, Index: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -822,6 +822,13 @@ return true; } + if (Subtarget.hasLSLFast()) { + if ((Opcode == AArch64::ADDWrs || Opcode == AArch64::ADDXrs || + Opcode == AArch64::SUBWrs || Opcode == AArch64::SUBXrs) && + MI.getOperand(3).getImm() <= 4) + return true; + } + // Secondly, check cases specific to sub-targets. if (Subtarget.hasExynosCheapAsMoveHandling()) {