[ARMv8-M] [7/9] Add ARMv8-M security extension instructions to ARMv8-M Baseline/Mainline

[bsmith]

Summary

This patch forms part of the ARMv8-M Baseline/Mainline support, adding support for ARMv8-M security extension instructions in ARMv8-M Baseline/Mainline.

[bsmith]

Rebase patch against latest trunk changes.

[t.p.northover]

Some minor points here, though again I'm having to trust you on matching the specification.

Cheers.

Tim.

lib/Target/ARM/ARMInstrThumb2.td

4342–4345

Does this need hasSideEffects or similar? Otherwise (with no inputs or outputs) if it ever gets to CodeGen the compiler is going to nuke it out of hand.

lib/Target/ARM/ARMInstrVFP.td

207

These look unrelated to the security extensions. Probably also need mayLoad/mayStore.

test/MC/ARM/thumbv8m.s

168

Written like this, it becomes just a count of "invalid operand for instruction" errors. It's easier to track down future regressions if the problematic input line gets checked too (as in other error tests).

[bsmith]

lib/Target/ARM/ARMInstrVFP.td

207

These are infact part of the security extensions, they are used for loading/storing floating point state to the specified register, however you are correct about the missing mayLoad/mayStore.

[bsmith]

Add missing mayLoad/mayStore/hasSideEffects flags to added intructions

[t.p.northover]

lib/Target/ARM/ARMInstrVFP.td

207

So don't they need to be marked Has8MSecExt too?

[bsmith]

lib/Target/ARM/ARMInstrVFP.td

207

Sorry yes, I missed this.

[bsmith]

Add missing HasV8SecExt to VLLDM/VLSTM instructions.

[t.p.northover]

Thanks Bradley, this looks fine now.

Tim.

[bsmith]

Thanks, committed as r257883.

lib/Target/ARM/ARM.td

 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
                                          "FP compare + branch is slow">;
 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
                           "Floating point unit supports single precision only">;
 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
                            "Enable support for Performance Monitor extensions">;
 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
                           "Enable support for TrustZone security extensions">;
+def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
+                          "Enable support for ARMv8-M Security Extensions">;
 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
                           "Enable support for Cryptography extensions",
                           [FeatureNEON]>;
 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
                           "Enable support for CRC instructions">;
 
 // Cyclone has preferred instructions for zeroing VFP registers, which can
 // execute in 0 cycles.
def ARMv82a   : Architecture<"armv8.2-a", "ARMv82a",  [HasV8_2aOps,
                                                        FeatureCRC]>;
 
 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
                                                       [HasV8MBaselineOps,
                                                        FeatureNoARM,
                                                        FeatureDB,
                                                        FeatureHWDiv,
                                                        FeatureV7Clrex,
+                                                       Feature8MSecExt,
                                                        FeatureAcquireRelease,
                                                        FeatureMClass]>;
 
 def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
                                                       [HasV8MMainlineOps,
                                                        FeatureNoARM,
                                                        FeatureDB,
                                                        FeatureHWDiv,
+                                                       Feature8MSecExt,
                                                        FeatureAcquireRelease,
                                                        FeatureMClass]>;
 
 // Aliases
 def IWMMXT   : Architecture<"iwmmxt",      "ARMv5te",  [ARMv5te]>;
 def IWMMXT2  : Architecture<"iwmmxt2",     "ARMv5te",  [ARMv5te]>;
 def XScale   : Architecture<"xscale",      "ARMv5te",  [ARMv5te]>;
 def ARMv6j   : Architecture<"armv6j",      "ARMv7a",   [ARMv6]>;

lib/Target/ARM/ARMInstrInfo.td

def HasMP            : Predicate<"Subtarget->hasMPExtension()">,
                                  AssemblerPredicate<"FeatureMP",
                                                     "mp-extensions">;
 def HasVirtualization: Predicate<"false">,
                                  AssemblerPredicate<"FeatureVirtualization",
                                                    "virtualization-extensions">;
 def HasTrustZone     : Predicate<"Subtarget->hasTrustZone()">,
                                  AssemblerPredicate<"FeatureTrustZone",
                                                     "TrustZone">;
+def Has8MSecExt      : Predicate<"Subtarget->has8MSecExt()">,
+                                 AssemblerPredicate<"Feature8MSecExt",
+                                                    "ARMv8-M Security Extensions">;
 def HasZCZ           : Predicate<"Subtarget->hasZeroCycleZeroing()">;
 def UseNEONForFP     : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
 def IsThumb          : Predicate<"Subtarget->isThumb()">,
                                  AssemblerPredicate<"ModeThumb", "thumb">;
 def IsThumb1Only     : Predicate<"Subtarget->isThumb1Only()">;
 def IsThumb2         : Predicate<"Subtarget->isThumb2()">,
                                  AssemblerPredicate<"ModeThumb,FeatureThumb2",

lib/Target/ARM/ARMInstrThumb.td

let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
   def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
             T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
     // A6.2.3 & A8.6.25
     bits<4> Rm;
     let Inst{6-3} = Rm;
     let Inst{2-0} = 0b000;
     let Unpredictable{2-0} = 0b111;
   }
+  def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>,
+              Requires<[IsThumb, Has8MSecExt]>,
+              T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
+    bits<4> Rm;
+    let Inst{6-3} = Rm;
+    let Inst{2-0} = 0b100;
+    let Unpredictable{1-0} = 0b11;
+  }
 }
 
 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
   def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
                    [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
 
   // Alternative return instruction used by vararg functions.
   def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
                   [(ARMtcall GPR:$func)]>,
               Requires<[IsThumb, HasV5T]>,
               T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
     bits<4> func;
     let Inst{6-3} = func;
     let Inst{2-0} = 0b000;
   }
 
+  // ARMv8-M Security Extensions
+  def tBLXNSr : TI<(outs), (ins pred:$p, GPRnopc:$func), IIC_Br,
+                   "blxns${p}\t$func", []>,
+                Requires<[IsThumb, Has8MSecExt]>,
+                T1Special<{1,1,1,?}>, Sched<[WriteBrL]> {
+    bits<4> func;
+    let Inst{6-3} = func;
+    let Inst{2-0} = 0b100;
+    let Unpredictable{1-0} = 0b11;
+  }
+
   // ARMv4T
   def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func),
                   4, IIC_Br,
                   [(ARMcall_nolink tGPR:$func)]>,
             Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>;
 }
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {

lib/Target/ARM/ARMInstrThumb2.td

def t2SETPAN : T1I<(outs), (ins imm0_1:$imm), NoItinerary, "setpan\t$imm", []>,
   let Inst{3} = imm;
   let Inst{2-0} = 0b000;
 
   let Unpredictable{4} = 0b1;
   let Unpredictable{2-0} = 0b111;
 }
 
 //===----------------------------------------------------------------------===//
+// ARMv8-M Security Extensions instructions
+//
+
+let hasSideEffects = 1 in
+def t2SG : T2I<(outs), (ins), NoItinerary, "sg", "", []>,
+           Requires<[Has8MSecExt]> {
+  let Inst = 0xe97fe97f;
+}
+
+class T2TT<bits<2> at, string asm, list<dag> pattern>
+  : T2I<(outs rGPR:$Rt), (ins GPRnopc:$Rn), NoItinerary, asm, "\t$Rt, $Rn",
+        pattern> {
+  bits<4> Rn;
+  bits<4> Rt;
+
+  let Inst{31-20} = 0b111010000100;
+  let Inst{19-16} = Rn;
+  let Inst{15-12} = 0b1111;
+  let Inst{11-8} = Rt;
+  let Inst{7-6} = at;
+  let Inst{5-0} = 0b000000;
+
+  let Unpredictable{5-0} = 0b111111;
+}
+
+def t2TT   : T2TT<0b00, "tt",   []>, Requires<[IsThumb,Has8MSecExt]>;
+def t2TTT  : T2TT<0b01, "ttt",  []>, Requires<[IsThumb,Has8MSecExt]>;
+def t2TTA  : T2TT<0b10, "tta",  []>, Requires<[IsThumb,Has8MSecExt]>;
+def t2TTAT : T2TT<0b11, "ttat", []>, Requires<[IsThumb,Has8MSecExt]>;
+
+//===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //
 
 // SXT/UXT with no rotate
 let AddedComplexity = 16 in {
 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
            Requires<[IsThumb2]>;
 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,

lib/Target/ARM/ARMInstrVFP.td

 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>;
 
 } // hasSideEffects
 
 def : MnemonicAlias<"vldm", "vldmia">;
 def : MnemonicAlias<"vstm", "vstmia">;
 
+
+//===----------------------------------------------------------------------===//
+//  Lazy load / store multiple Instructions
+//
+let mayLoad = 1 in
+def VLLDM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone,
+                  IIC_fpLoad_m, "vlldm${p}\t$Rn", "", []>,
+            Requires<[HasV8MMainline, Has8MSecExt]> {
+    let Inst{24-23} = 0b00;
+    let Inst{22}    = 0;
+    let Inst{21}    = 1;
+    let Inst{20}    = 1;
+    let Inst{15-12} = 0;
+    let Inst{7-0}   = 0;
+    let mayLoad     = 1;
+}
+
+let mayStore = 1 in
+def VLSTM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone,
+                  IIC_fpStore_m, "vlstm${p}\t$Rn", "", []>,
+            Requires<[HasV8MMainline, Has8MSecExt]> {
+    let Inst{24-23} = 0b00;
+    let Inst{22}    = 0;
+    let Inst{21}    = 1;
+    let Inst{20}    = 0;
+    let Inst{15-12} = 0;
+    let Inst{7-0}   = 0;
+    let mayStore    = 1;
+}
+
+
 // FLDM/FSTM - Load / Store multiple single / double precision registers for
 // pre-ARMv6 cores.
 // These instructions are deprecated!
 def : VFP2MnemonicAlias<"fldmias", "vldmia">;
 def : VFP2MnemonicAlias<"fldmdbs", "vldmdb">;
 def : VFP2MnemonicAlias<"fldmeas", "vldmdb">;
 def : VFP2MnemonicAlias<"fldmfds", "vldmia">;
 def : VFP2MnemonicAlias<"fldmiad", "vldmia">;

lib/Target/ARM/ARMSubtarget.h

protected:
   /// If true, the processor supports the Performance Monitor Extensions. These
   /// include a generic cycle-counter as well as more fine-grained (often
   /// implementation-specific) events.
   bool HasPerfMon;
 
   /// HasTrustZone - if true, processor supports TrustZone security extensions
   bool HasTrustZone;
 
+  /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
+  bool Has8MSecExt;
+
   /// HasCrypto - if true, processor supports Cryptography extensions
   bool HasCrypto;
 
   /// HasCRC - if true, processor supports CRC instructions
   bool HasCRC;
 
   /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
   /// particularly effective at zeroing a VFP register.
public:
   }
   bool useMulOps() const { return UseMulOps; }
   bool useFPVMLx() const { return !SlowFPVMLx; }
   bool hasVMLxForwarding() const { return HasVMLxForwarding; }
   bool isFPBrccSlow() const { return SlowFPBrcc; }
   bool isFPOnlySP() const { return FPOnlySP; }
   bool hasPerfMon() const { return HasPerfMon; }
   bool hasTrustZone() const { return HasTrustZone; }
+  bool has8MSecExt() const { return Has8MSecExt; }
   bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
   bool prefers32BitThumb() const { return Pref32BitThumb; }
   bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
   bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
   bool hasRAS() const { return HasRAS; }
   bool hasMPExtension() const { return HasMPExtension; }
   bool hasDSP() const { return HasDSP; }
   bool useNaClTrap() const { return UseNaClTrap; }

lib/Target/ARM/ARMSubtarget.cpp

void ARMSubtarget::initializeEnvironment() {
   AvoidCPSRPartialUpdate = false;
   AvoidMOVsShifterOperand = false;
   HasRAS = false;
   HasMPExtension = false;
   HasVirtualization = false;
   FPOnlySP = false;
   HasPerfMon = false;
   HasTrustZone = false;
+  Has8MSecExt = false;
   HasCrypto = false;
   HasCRC = false;
   HasZeroCycleZeroing = false;
   StrictAlign = false;
   HasDSP = false;
   UseNaClTrap = false;
   GenLongCalls = false;
   UnsafeFPMath = false;

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

if ((Mnemonic == "movs" && isThumb()) ||
       Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
-      Mnemonic.startswith("vsel"))
+      Mnemonic == "bxns"  || Mnemonic == "blxns" || Mnemonic.startswith("vsel"))
     return Mnemonic;
 
   // First, split out any predication code. Ignore mnemonics we know aren't
   // predicated but do have a carry-set and so weren't caught above.
   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
       Mnemonic != "sbcs" && Mnemonic != "rscs") {

test/MC/ARM/thumbv8m.s

 // RUN: not llvm-mc -triple=thumbv8m.base -show-encoding < %s 2>%t \
-// RUN:   | FileCheck --check-prefix=CHECK %s
+// RUN:   | FileCheck --check-prefix=CHECK-BASELINE --check-prefix=CHECK %s
 // RUN:     FileCheck --check-prefix=UNDEF-BASELINE --check-prefix=UNDEF < %t %s
 // RUN: not llvm-mc -triple=thumbv8m.main -show-encoding < %s 2>%t \
-// RUN:   | FileCheck --check-prefix=CHECK %s
+// RUN:   | FileCheck --check-prefix=CHECK-MAINLINE --check-prefix=CHECK %s
 // RUN:     FileCheck --check-prefix=UNDEF-MAINLINE --check-prefix=UNDEF < %t %s
 
 // Simple check that baseline is v6M and mainline is v7M
 // UNDEF-BASELINE: error: instruction requires: thumb2
 // UNDEF-MAINLINE-NOT: error: instruction requires:
 mov.w r0, r0
 
 // Check that .arm is invalid

 // CHECK: stlexb  r1, r2, [r3]            @ encoding: [0xc3,0xe8,0xc1,0x2f]
 stlexb r1, r2, [r3]
 
 // CHECK: stlexh  r1, r2, [r3]            @ encoding: [0xc3,0xe8,0xd1,0x2f]
 stlexh r1, r2, [r3]
 
 // UNDEF: error: instruction requires: !armv*m
 stlexd r0, r1, r2, [r2]
+
+// ARMv8-M Security Extensions
+
+// CHECK: sg                         @ encoding: [0x7f,0xe9,0x7f,0xe9]
+sg
+
+// CHECK: bxns r0                    @ encoding: [0x04,0x47]
+bxns r0
+
+// CHECK: bxns lr                    @ encoding: [0x74,0x47]
+bxns lr
+
+// CHECK: blxns r0                   @ encoding: [0x84,0x47]
+blxns r0
+
+// CHECK: tt r0, r1                  @ encoding: [0x41,0xe8,0x00,0xf0]
+tt r0, r1
+
+// CHECK: tt r0, sp                  @ encoding: [0x4d,0xe8,0x00,0xf0]
+tt r0, sp
+
+// CHECK: tta r0, r1                 @ encoding: [0x41,0xe8,0x80,0xf0]
+tta r0, r1
+
+// CHECK: ttt r0, r1                 @ encoding: [0x41,0xe8,0x40,0xf0]
+ttt r0, r1
+
+// CHECK: ttat r0, r1                @ encoding: [0x41,0xe8,0xc0,0xf0]
+ttat r0, r1
+
+// 'Lazy Load/Store Multiple'
+
+// UNDEF-BASELINE: error: instruction requires: armv8m.main
+// CHECK-MAINLINE: vlldm r5          @ encoding: [0x35,0xec,0x00,0x0a]
+vlldm r5
+
+// UNDEF-BASELINE: error: instruction requires: armv8m.main
+// CHECK-MAINLINE: vlstm r10         @ encoding: [0x2a,0xec,0x00,0x0a]
+vlstm r10
+
+
+// Invalid operand tests
+// UNDEF: error: invalid operand for instruction
+// UNDEF:     sg #0
+sg #0
+// UNDEF: error: invalid operand for instruction
+// UNDEF:     sg r0
+sg r0
+// UNDEF: error: invalid operand for instruction
+// UNDEF:     bxns r0, r1
+bxns r0, r1
+// UNDEF: error: invalid operand for instruction
+// UNDEF:     blxns r0, #0
+blxns r0, #0
+// UNDEF: error: invalid operand for instruction
+// UNDEF:     blxns label
+blxns label
+// UNDEF: error: invalid operand for instruction
+// UNDEF:     tt r0, r1, r2
+tt r0, r1, r2
+// UNDEF: error: invalid operand for instruction
+// UNDEF:     tt r0, [r1]
+tt r0, [r1]
+// UNDEF: error: invalid operand for instruction
+// UNDEF:     tt r0, r1, #4
+tt r0, r1, #4
+// UNDEF: error: invalid operand for instruction
+// UNDEF:     tt r0, #4
+tt r0, #4
+
+// Unpredictable operands
+// UNDEF: error: invalid operand for instruction
+// UNDEF:     blxns pc
+blxns pc
+// UNDEF: error: invalid operand for instruction
+// UNDEF:     tt sp, r0
+tt sp, r0
+// UNDEF: error: invalid operand for instruction
+// UNDEF:     tt pc, r0
+tt pc, r0
+// UNDEF: error: invalid operand for instruction
+// UNDEF:     tt r0, pc
+tt r0, pc
+
+// UNDEF: error: invalid operand for instruction
+// UNDEF:     vlldm pc
+vlldm pc
+
+// UNDEF: error: invalid operand for instruction
+// UNDEF:     vlstm pc
+vlstm pc