diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -6400,6 +6400,23 @@
       case Intrinsic::minimum:
       case Intrinsic::maximum:
       case Intrinsic::is_fpclass:
+      case Intrinsic::amdgcn_fmed3:
+      case Intrinsic::amdgcn_fmul_legacy:
+      case Intrinsic::amdgcn_fract:
+      case Intrinsic::amdgcn_icmp:
+      case Intrinsic::amdgcn_interp_p1:
+      case Intrinsic::amdgcn_interp_p1_f16:
+      case Intrinsic::amdgcn_interp_p2:
+      case Intrinsic::amdgcn_interp_p2_f16:
+      case Intrinsic::amdgcn_mbcnt_hi:
+      case Intrinsic::amdgcn_mbcnt_lo:
+      case Intrinsic::amdgcn_rcp:
+      case Intrinsic::amdgcn_readfirstlane:
+      case Intrinsic::amdgcn_readlane:
+      case Intrinsic::amdgcn_rsq:
+      case Intrinsic::amdgcn_softwqm:
+      case Intrinsic::amdgcn_wqm:
+      case Intrinsic::amdgcn_wwm:
         return false;
       case Intrinsic::lround:
       case Intrinsic::llround:
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/freeze.ll b/llvm/test/Transforms/InstCombine/AMDGPU/freeze.ll
--- a/llvm/test/Transforms/InstCombine/AMDGPU/freeze.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/freeze.ll
@@ -5,8 +5,7 @@
 ; CHECK-LABEL: define float @fmed3
 ; CHECK-SAME: (float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[X]], float [[Y]], float [[Z]])
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze float [[VAL]]
-; CHECK-NEXT:    ret float [[FRZ]]
+; CHECK-NEXT:    ret float [[VAL]]
 ;
   %val = call float @llvm.amdgcn.fmed3.f32(float %x, float %y, float %z)
   %frz = freeze float %val
@@ -17,8 +16,7 @@
 ; CHECK-LABEL: define float @fmul.legacy
 ; CHECK-SAME: (float noundef [[X:%.*]], float noundef [[Y:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call float @llvm.amdgcn.fmul.legacy(float [[X]], float [[Y]])
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze float [[VAL]]
-; CHECK-NEXT:    ret float [[FRZ]]
+; CHECK-NEXT:    ret float [[VAL]]
 ;
   %val = call float @llvm.amdgcn.fmul.legacy(float %x, float %y)
   %frz = freeze float %val
@@ -29,8 +27,7 @@
 ; CHECK-LABEL: define float @fract
 ; CHECK-SAME: (float noundef [[X:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze float [[VAL]]
-; CHECK-NEXT:    ret float [[FRZ]]
+; CHECK-NEXT:    ret float [[VAL]]
 ;
   %val = call float @llvm.amdgcn.fract.f32(float %x)
   %frz = freeze float %val
@@ -41,8 +38,7 @@
 ; CHECK-LABEL: define i32 @icmp
 ; CHECK-SAME: (i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.amdgcn.icmp.i32.i32(i32 [[X]], i32 [[Y]], i32 0)
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze i32 [[VAL]]
-; CHECK-NEXT:    ret i32 [[FRZ]]
+; CHECK-NEXT:    ret i32 [[VAL]]
 ;
   %val = call i32 @llvm.amdgcn.icmp.i32(i32 %x, i32 %y, i32 0)
   %frz = freeze i32 %val
@@ -53,8 +49,7 @@
 ; CHECK-LABEL: define float @interp.p1
 ; CHECK-SAME: (float noundef [[X:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call float @llvm.amdgcn.interp.p1(float [[X]], i32 0, i32 0, i32 0)
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze float [[VAL]]
-; CHECK-NEXT:    ret float [[FRZ]]
+; CHECK-NEXT:    ret float [[VAL]]
 ;
   %val = call float @llvm.amdgcn.interp.p1(float %x, i32 0, i32 0, i32 0)
   %frz = freeze float %val
@@ -65,8 +60,7 @@
 ; CHECK-LABEL: define float @interp.p1.f16
 ; CHECK-SAME: (float noundef [[X:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call float @llvm.amdgcn.interp.p1.f16(float [[X]], i32 0, i32 0, i1 false, i32 0)
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze float [[VAL]]
-; CHECK-NEXT:    ret float [[FRZ]]
+; CHECK-NEXT:    ret float [[VAL]]
 ;
   %val = call float @llvm.amdgcn.interp.p1.f16(float %x, i32 0, i32 0, i1 false, i32 0)
   %frz = freeze float %val
@@ -77,8 +71,7 @@
 ; CHECK-LABEL: define float @interp.p2
 ; CHECK-SAME: (float noundef [[X:%.*]], float noundef [[Y:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call float @llvm.amdgcn.interp.p2(float [[X]], float [[Y]], i32 0, i32 0, i32 0)
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze float [[VAL]]
-; CHECK-NEXT:    ret float [[FRZ]]
+; CHECK-NEXT:    ret float [[VAL]]
 ;
   %val = call float @llvm.amdgcn.interp.p2(float %x, float %y, i32 0, i32 0, i32 0)
   %frz = freeze float %val
@@ -89,8 +82,7 @@
 ; CHECK-LABEL: define half @interp.p2.f16
 ; CHECK-SAME: (float noundef [[X:%.*]], float noundef [[Y:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call half @llvm.amdgcn.interp.p2.f16(float [[X]], float [[Y]], i32 0, i32 0, i1 false, i32 0)
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze half [[VAL]]
-; CHECK-NEXT:    ret half [[FRZ]]
+; CHECK-NEXT:    ret half [[VAL]]
 ;
   %val = call half @llvm.amdgcn.interp.p2.f16(float %x, float %y, i32 0, i32 0, i1 false, i32 0)
   %frz = freeze half %val
@@ -101,8 +93,7 @@
 ; CHECK-LABEL: define i32 @mbcnt.hi
 ; CHECK-SAME: (i32 noundef [[X:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[X]], i32 0)
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze i32 [[VAL]]
-; CHECK-NEXT:    ret i32 [[FRZ]]
+; CHECK-NEXT:    ret i32 [[VAL]]
 ;
   %val = call i32 @llvm.amdgcn.mbcnt.hi(i32 %x, i32 0)
   %frz = freeze i32 %val
@@ -113,8 +104,7 @@
 ; CHECK-LABEL: define i32 @mbcnt.lo
 ; CHECK-SAME: (i32 noundef [[X:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[X]], i32 0)
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze i32 [[VAL]]
-; CHECK-NEXT:    ret i32 [[FRZ]]
+; CHECK-NEXT:    ret i32 [[VAL]]
 ;
   %val = call i32 @llvm.amdgcn.mbcnt.hi(i32 %x, i32 0)
   %frz = freeze i32 %val
@@ -125,8 +115,7 @@
 ; CHECK-LABEL: define float @rcp
 ; CHECK-SAME: (float noundef [[X:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[X]])
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze float [[VAL]]
-; CHECK-NEXT:    ret float [[FRZ]]
+; CHECK-NEXT:    ret float [[VAL]]
 ;
   %val = call float @llvm.amdgcn.rcp.f32(float %x)
   %frz = freeze float %val
@@ -137,8 +126,7 @@
 ; CHECK-LABEL: define i32 @readfirstlane
 ; CHECK-SAME: (i32 noundef [[X:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.amdgcn.readfirstlane(i32 [[X]])
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze i32 [[VAL]]
-; CHECK-NEXT:    ret i32 [[FRZ]]
+; CHECK-NEXT:    ret i32 [[VAL]]
 ;
   %val = call i32 @llvm.amdgcn.readfirstlane(i32 %x)
   %frz = freeze i32 %val
@@ -149,8 +137,7 @@
 ; CHECK-LABEL: define i32 @readlane
 ; CHECK-SAME: (i32 noundef [[X:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[X]], i32 7)
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze i32 [[VAL]]
-; CHECK-NEXT:    ret i32 [[FRZ]]
+; CHECK-NEXT:    ret i32 [[VAL]]
 ;
   %val = call i32 @llvm.amdgcn.readlane(i32 %x, i32 7)
   %frz = freeze i32 %val
@@ -161,8 +148,7 @@
 ; CHECK-LABEL: define float @rsq
 ; CHECK-SAME: (float noundef [[X:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call float @llvm.amdgcn.rsq.f32(float [[X]])
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze float [[VAL]]
-; CHECK-NEXT:    ret float [[FRZ]]
+; CHECK-NEXT:    ret float [[VAL]]
 ;
   %val = call float @llvm.amdgcn.rsq.f32(float %x)
   %frz = freeze float %val
@@ -173,8 +159,7 @@
 ; CHECK-LABEL: define i32 @softwqm
 ; CHECK-SAME: (i32 noundef [[X:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.amdgcn.softwqm.i32(i32 [[X]])
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze i32 [[VAL]]
-; CHECK-NEXT:    ret i32 [[FRZ]]
+; CHECK-NEXT:    ret i32 [[VAL]]
 ;
   %val = call i32 @llvm.amdgcn.softwqm.i32(i32 %x)
   %frz = freeze i32 %val
@@ -185,8 +170,7 @@
 ; CHECK-LABEL: define i32 @wqm
 ; CHECK-SAME: (i32 noundef [[X:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.amdgcn.wqm.i32(i32 [[X]])
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze i32 [[VAL]]
-; CHECK-NEXT:    ret i32 [[FRZ]]
+; CHECK-NEXT:    ret i32 [[VAL]]
 ;
   %val = call i32 @llvm.amdgcn.wqm.i32(i32 %x)
   %frz = freeze i32 %val
@@ -197,8 +181,7 @@
 ; CHECK-LABEL: define i32 @wwm
 ; CHECK-SAME: (i32 noundef [[X:%.*]]) {
 ; CHECK-NEXT:    [[VAL:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[X]])
-; CHECK-NEXT:    [[FRZ:%.*]] = freeze i32 [[VAL]]
-; CHECK-NEXT:    ret i32 [[FRZ]]
+; CHECK-NEXT:    ret i32 [[VAL]]
 ;
   %val = call i32 @llvm.amdgcn.wwm.i32(i32 %x)
   %frz = freeze i32 %val