Index: llvm/docs/AMDGPUUsage.rst =================================================================== --- llvm/docs/AMDGPUUsage.rst +++ llvm/docs/AMDGPUUsage.rst @@ -958,6 +958,14 @@ mask. On gfx9+, bit 23 is FP16_OVFL. Bitfields not relevant to floating-point instructions are 0s. + :ref:`llvm.log2 ` Implemented for float and half (and vectors of float or + half). Not implemented for double. Hardware provides + 1ULP accuracy for float, and 0.51ULP for half. Float + instruction does not natively support denormal + inputs. Backend will optimize out denormal scaling if + marked with the :ref:`afn ` flag. + + ========================================= ========================================================== Index: llvm/docs/LangRef.rst =================================================================== --- llvm/docs/LangRef.rst +++ llvm/docs/LangRef.rst @@ -3431,6 +3431,8 @@ to form arbitrary contractions. For example, ``(a*b) + (c*d) + e`` can not be transformed into ``(a*b) + ((c*d) + e)`` to create two fma operations. +.. _fastmath_afn: + ``afn`` Approximate functions - Allow substitution of approximate calculations for functions (sin, log, sqrt, etc). See floating-point intrinsic definitions @@ -14830,6 +14832,9 @@ When specified with the fast-math-flag 'afn', the result may be approximated using a less accurate calculation. + +.. _int_log2: + '``llvm.log2.*``' Intrinsic ^^^^^^^^^^^^^^^^^^^^^^^^^^^ Index: llvm/docs/ReleaseNotes.rst =================================================================== --- llvm/docs/ReleaseNotes.rst +++ llvm/docs/ReleaseNotes.rst @@ -136,6 +136,9 @@ * Added llvm.amdgcn.log.f32 intrinsic. This provides direct access to v_log_f32. +* llvm.log2.f32 is now lowered accurately. Use llvm.amdgcn.log.f32 to + access the old behavior. + Changes to the ARM Backend -------------------------- Index: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -60,6 +60,7 @@ SDValue LowerFROUNDEVEN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerFLOG2(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFLOG(SDValue Op, SelectionDAG &DAG, double Log2BaseInverted) const; SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const; Index: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -328,11 +328,11 @@ // Library functions. These default to Expand, but we have instructions // for them. - setOperationAction({ISD::FCEIL, ISD::FEXP2, ISD::FPOW, ISD::FLOG2, ISD::FABS, - ISD::FFLOOR, ISD::FRINT, ISD::FTRUNC, ISD::FMINNUM, - ISD::FMAXNUM}, + setOperationAction({ISD::FCEIL, ISD::FEXP2, ISD::FPOW, ISD::FABS, ISD::FFLOOR, + ISD::FRINT, ISD::FTRUNC, ISD::FMINNUM, ISD::FMAXNUM}, MVT::f32, Legal); + setOperationAction(ISD::FLOG2, MVT::f32, Custom); setOperationAction(ISD::FROUND, {MVT::f32, MVT::f64}, Custom); setOperationAction({ISD::FLOG, ISD::FLOG10, ISD::FEXP}, MVT::f32, Custom); @@ -345,8 +345,10 @@ if (Subtarget->has16BitInsts()) setOperationAction(ISD::IS_FPCLASS, {MVT::f16, MVT::f32, MVT::f64}, Legal); - else + else { setOperationAction(ISD::IS_FPCLASS, {MVT::f32, MVT::f64}, Legal); + setOperationAction(ISD::FLOG2, MVT::f16, Custom); + } // FIXME: These IS_FPCLASS vector fp types are marked custom so it reaches // scalarization code. Can be removed when IS_FPCLASS expand isn't called by @@ -1304,6 +1306,8 @@ return LowerFROUNDEVEN(Op, DAG); case ISD::FROUND: return LowerFROUND(Op, DAG); case ISD::FFLOOR: return LowerFFLOOR(Op, DAG); + case ISD::FLOG2: + return LowerFLOG2(Op, DAG); case ISD::FLOG: return LowerFLOG(Op, DAG, numbers::ln2); case ISD::FLOG10: @@ -1338,6 +1342,10 @@ // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do // nothing here and let the illegal result integer be handled normally. return; + case ISD::FLOG2: + if (SDValue Lowered = LowerFLOG2(SDValue(N, 0), DAG)) + Results.push_back(Lowered); + return; default: return; } @@ -2425,6 +2433,76 @@ return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); } +/// Return true if it's known that \p Src can never be an f32 denormal value. +static bool valueIsKnownNeverF32Denorm(SDValue Src) { + switch (Src.getOpcode()) { + case ISD::FP_EXTEND: + return Src.getOperand(0).getValueType() == MVT::f16; + case ISD::FP16_TO_FP: + return true; + default: + return false; + } + + llvm_unreachable("covered opcode switch"); +} + +SDValue AMDGPUTargetLowering::LowerFLOG2(SDValue Op, SelectionDAG &DAG) const { + // v_log_f32 is good enough for OpenCL, except it doesn't handle denormals. + // If we have to handle denormals, scale up the input and adjust the result. + + // scaled = x * (is_denormal ? 0x1.0p+32 : 1.0) + // log2 = amdgpu_log2 - (is_denormal ? 32.0 : 0.0) + + SDLoc SL(Op); + EVT VT = Op.getValueType(); + SDValue Src = Op.getOperand(0); + SDNodeFlags Flags = Op->getFlags(); + + if (VT == MVT::f16) { + // Nothing in half is a denormal when promoted to f32. + assert(!Subtarget->has16BitInsts()); + SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src, Flags); + SDValue Log = DAG.getNode(AMDGPUISD::LOG, SL, MVT::f32, Ext, Flags); + return DAG.getNode(ISD::FP_ROUND, SL, VT, Log, + DAG.getTargetConstant(0, SL, MVT::i32), Flags); + } + + bool NeedDenormHandling = + !Flags.hasApproximateFuncs() && !DAG.getTarget().Options.UnsafeFPMath && + !DAG.getTarget().Options.ApproxFuncFPMath && + !valueIsKnownNeverF32Denorm(Src) && + DAG.getDenormalMode(VT).Input != DenormalMode::PreserveSign; + + if (!NeedDenormHandling) + return DAG.getNode(AMDGPUISD::LOG, SL, VT, Src, Flags); + + const fltSemantics &Semantics = APFloat::IEEEsingle(); + SDValue SmallestNormal = + DAG.getConstantFP(APFloat::getSmallestNormalized(Semantics), SL, VT); + + // Want to scale denormals up, but negatives and 0 work just as well on the + // scaled path. + SDValue IsLtSmallestNormal = DAG.getSetCC( + SL, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), Src, + SmallestNormal, ISD::SETOLT); + + SDValue Scale32 = DAG.getConstantFP(0x1.0p+32, SL, VT); + SDValue One = DAG.getConstantFP(1.0, SL, VT); + SDValue ScaleFactor = + DAG.getNode(ISD::SELECT, SL, VT, IsLtSmallestNormal, Scale32, One, Flags); + + SDValue ScaledInput = DAG.getNode(ISD::FMUL, SL, VT, Src, ScaleFactor, Flags); + + SDValue Log2 = DAG.getNode(AMDGPUISD::LOG, SL, VT, ScaledInput, Flags); + + SDValue ThirtyTwo = DAG.getConstantFP(32.0, SL, VT); + SDValue Zero = DAG.getConstantFP(0.0, SL, VT); + SDValue ResultOffset = + DAG.getNode(ISD::SELECT, SL, VT, IsLtSmallestNormal, ThirtyTwo, Zero); + return DAG.getNode(ISD::FSUB, SL, VT, Log2, ResultOffset, Flags); +} + SDValue AMDGPUTargetLowering::LowerFLOG(SDValue Op, SelectionDAG &DAG, double Log2BaseInverted) const { EVT VT = Op.getValueType(); Index: llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td +++ llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td @@ -389,8 +389,7 @@ def AMDGPUfract : PatFrags<(ops node:$src), [(int_amdgcn_fract node:$src), (AMDGPUfract_impl node:$src)]>; def AMDGPUlog : PatFrags<(ops node:$src), [(int_amdgcn_log node:$src), - (AMDGPUlog_impl node:$src), - (flog2 node:$src)]>; + (AMDGPUlog_impl node:$src)]>; def AMDGPUlogf16 : PatFrags<(ops node:$src), [(int_amdgcn_log node:$src), (flog2 node:$src)]>; Index: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h +++ llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h @@ -78,6 +78,7 @@ bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const; + bool legalizeFlog2(MachineInstr &MI, MachineIRBuilder &B) const; bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B, double Log2BaseInverted) const; bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const; Index: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -1110,7 +1110,7 @@ .scalarize(0); // FIXME: fpow has a selection pattern that should move to custom lowering. - auto &Exp2Ops = getActionDefinitionsBuilder({G_FEXP2, G_FLOG2}); + auto &Exp2Ops = getActionDefinitionsBuilder(G_FEXP2); if (ST.has16BitInsts()) Exp2Ops.legalFor({S32, S16}); else @@ -1130,6 +1130,15 @@ .clampScalar(0, MinScalarFPTy, S32) .lower(); + auto &Log2Ops = getActionDefinitionsBuilder(G_FLOG2); + Log2Ops.customFor({S32}); + if (ST.has16BitInsts()) + Log2Ops.legalFor({S16}); + else + Log2Ops.customFor({S16}); + Log2Ops.scalarize(0) + .lower(); + // The 64-bit versions produce 32-bit results, but only on the SALU. getActionDefinitionsBuilder(G_CTPOP) .legalFor({{S32, S32}, {S32, S64}}) @@ -1986,6 +1995,8 @@ return legalizeSignedDIV_REM(MI, MRI, B); case TargetOpcode::G_ATOMIC_CMPXCHG: return legalizeAtomicCmpXChg(MI, MRI, B); + case TargetOpcode::G_FLOG2: + return legalizeFlog2(MI, B); case TargetOpcode::G_FLOG: return legalizeFlog(MI, B, numbers::ln2); case TargetOpcode::G_FLOG10: @@ -2978,6 +2989,83 @@ return true; } +/// Return true if it's known that \p Src can never be an f32 denormal value. +static bool valueIsKnownNeverF32Denorm(const MachineRegisterInfo &MRI, + Register Src) { + Register ExtSrc; + if (mi_match(Src, MRI, m_GFPExt(m_Reg(ExtSrc)))) + return MRI.getType(ExtSrc) == LLT::scalar(16); + return false; +} + +bool AMDGPULegalizerInfo::legalizeFlog2(MachineInstr &MI, + MachineIRBuilder &B) const { + // v_log_f32 is good enough for OpenCL, except it doesn't handle denormals. + // If we have to handle denormals, scale up the input and adjust the result. + + // scaled = x * (is_denormal ? 0x1.0p+32 : 1.0) + // log2 = amdgpu_log2 - (is_denormal ? 32.0 : 0.0) + + Register Dst = MI.getOperand(0).getReg(); + Register Src = MI.getOperand(1).getReg(); + LLT Ty = B.getMRI()->getType(Dst); + unsigned Flags = MI.getFlags(); + + const MachineFunction &MF = B.getMF(); + + if (Ty == LLT::scalar(16)) { + const LLT F32 = LLT::scalar(32); + // Nothing in half is a denormal when promoted to f32. + auto Ext = B.buildFPExt(F32, Src, Flags); + auto Log2 = B.buildIntrinsic(Intrinsic::amdgcn_log, {F32}, false) + .addUse(Ext.getReg(0)) + .setMIFlags(Flags); + B.buildFPTrunc(Dst, Log2, Flags); + MI.eraseFromParent(); + return true; + } + + assert(Ty == LLT::scalar(32)); + + const fltSemantics &Flt = APFloat::IEEEsingle(); + + bool NeedDenormHandling = + !MI.getFlag(MachineInstr::FmAfn) && + !MF.getTarget().Options.UnsafeFPMath && + !MF.getTarget().Options.ApproxFuncFPMath && + !valueIsKnownNeverF32Denorm(*B.getMRI(), Src) && + MF.getDenormalMode(Flt).Input != DenormalMode::PreserveSign; + + if (!NeedDenormHandling) { + B.buildIntrinsic(Intrinsic::amdgcn_log, ArrayRef{Dst}, false) + .addUse(Src) + .setMIFlags(Flags); + MI.eraseFromParent(); + return true; + } + + auto SmallestNormal = + B.buildFConstant(Ty, APFloat::getSmallestNormalized(Flt)); + auto IsDenormOrZero = + B.buildFCmp(CmpInst::FCMP_OLT, LLT::scalar(1), Src, SmallestNormal); + + auto Scale32 = B.buildFConstant(Ty, 0x1.0p+32); + auto One = B.buildFConstant(Ty, 1.0); + auto ScaleFactor = B.buildSelect(Ty, IsDenormOrZero, Scale32, One, Flags); + auto ScaledInput = B.buildFMul(Ty, Src, ScaleFactor, Flags); + auto Log2 = B.buildIntrinsic(Intrinsic::amdgcn_log, {Ty}, false) + .addUse(ScaledInput.getReg(0)) + .setMIFlags(Flags); + + auto ThirtyTwo = B.buildFConstant(Ty, 32.0); + auto Zero = B.buildFConstant(Ty, 0.0); + auto ResultOffset = B.buildSelect(Ty, IsDenormOrZero, ThirtyTwo, Zero, Flags); + B.buildFSub(Dst, Log2, ResultOffset, Flags); + + MI.eraseFromParent(); + return true; +} + bool AMDGPULegalizerInfo::legalizeFlog( MachineInstr &MI, MachineIRBuilder &B, double Log2BaseInverted) const { Register Dst = MI.getOperand(0).getReg(); Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp =================================================================== --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5263,6 +5263,7 @@ return; } default: + AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG); break; } } @@ -10452,6 +10453,7 @@ case AMDGPUISD::RSQ_CLAMP: case AMDGPUISD::RCP_LEGACY: case AMDGPUISD::RCP_IFLAG: + case AMDGPUISD::LOG: case AMDGPUISD::DIV_SCALE: case AMDGPUISD::DIV_FMAS: case AMDGPUISD::DIV_FIXUP: Index: llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll @@ -9,7 +9,15 @@ ; GFX6-LABEL: v_pow_f32: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX6-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX6-NEXT: v_mul_f32_e32 v0, v0, v2 ; GFX6-NEXT: v_log_f32_e32 v0, v0 +; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 ; GFX6-NEXT: s_setpc_b64 s[30:31] @@ -17,7 +25,15 @@ ; GFX8-LABEL: v_pow_f32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX8-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2 ; GFX8-NEXT: v_log_f32_e32 v0, v0 +; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] @@ -25,7 +41,15 @@ ; GFX9-LABEL: v_pow_f32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX9-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2 ; GFX9-NEXT: v_log_f32_e32 v0, v0 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -34,7 +58,12 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| +; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s4 +; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4 ; GFX10-NEXT: v_log_f32_e32 v0, v0 +; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] @@ -43,8 +72,15 @@ ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0 +; GFX11-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_exp_f32_e32 v0, v0 @@ -57,9 +93,22 @@ ; GFX6-LABEL: v_pow_v2f32: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: s_mov_b32 s4, 0x800000 +; GFX6-NEXT: v_mov_b32_e32 v4, 0x4f800000 +; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4 +; GFX6-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc +; GFX6-NEXT: v_mul_f32_e32 v0, v0, v5 +; GFX6-NEXT: v_mov_b32_e32 v5, 0x42000000 +; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc +; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4 ; GFX6-NEXT: v_log_f32_e32 v0, v0 +; GFX6-NEXT: v_cndmask_b32_e32 v4, 1.0, v4, vcc +; GFX6-NEXT: v_mul_f32_e32 v1, v1, v4 ; GFX6-NEXT: v_log_f32_e32 v1, v1 +; GFX6-NEXT: v_sub_f32_e32 v0, v0, v6 ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc +; GFX6-NEXT: v_sub_f32_e32 v1, v1, v2 ; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 ; GFX6-NEXT: v_exp_f32_e32 v1, v1 @@ -68,9 +117,22 @@ ; GFX8-LABEL: v_pow_v2f32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: s_mov_b32 s4, 0x800000 +; GFX8-NEXT: v_mov_b32_e32 v4, 0x4f800000 +; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4 +; GFX8-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc +; GFX8-NEXT: v_mul_f32_e32 v0, v0, v5 +; GFX8-NEXT: v_mov_b32_e32 v5, 0x42000000 +; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc +; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4 ; GFX8-NEXT: v_log_f32_e32 v0, v0 +; GFX8-NEXT: v_cndmask_b32_e32 v4, 1.0, v4, vcc +; GFX8-NEXT: v_mul_f32_e32 v1, v1, v4 ; GFX8-NEXT: v_log_f32_e32 v1, v1 +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v6 ; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc +; GFX8-NEXT: v_sub_f32_e32 v1, v1, v2 ; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 ; GFX8-NEXT: v_exp_f32_e32 v1, v1 @@ -79,9 +141,22 @@ ; GFX9-LABEL: v_pow_v2f32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_mov_b32 s4, 0x800000 +; GFX9-NEXT: v_mov_b32_e32 v4, 0x4f800000 +; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4 +; GFX9-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc +; GFX9-NEXT: v_mul_f32_e32 v0, v0, v5 +; GFX9-NEXT: v_mov_b32_e32 v5, 0x42000000 +; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc +; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4 ; GFX9-NEXT: v_log_f32_e32 v0, v0 +; GFX9-NEXT: v_cndmask_b32_e32 v4, 1.0, v4, vcc +; GFX9-NEXT: v_mul_f32_e32 v1, v1, v4 ; GFX9-NEXT: v_log_f32_e32 v1, v1 +; GFX9-NEXT: v_sub_f32_e32 v0, v0, v6 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc +; GFX9-NEXT: v_sub_f32_e32 v1, v1, v2 ; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: v_exp_f32_e32 v1, v1 @@ -91,8 +166,18 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| +; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v1| +; GFX10-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x4f800000, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v5, 1.0, 0x4f800000, s5 +; GFX10-NEXT: v_mul_f32_e32 v0, v0, v4 +; GFX10-NEXT: v_mul_f32_e32 v1, v1, v5 +; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s5 ; GFX10-NEXT: v_log_f32_e32 v0, v0 ; GFX10-NEXT: v_log_f32_e32 v1, v1 +; GFX10-NEXT: v_sub_f32_e32 v0, v0, v4 +; GFX10-NEXT: v_sub_f32_e32 v1, v1, v5 ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 ; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 ; GFX10-NEXT: v_exp_f32_e32 v0, v0 @@ -103,9 +188,20 @@ ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| +; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v1| +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x4f800000, s0 +; GFX11-NEXT: v_cndmask_b32_e64 v5, 1.0, 0x4f800000, s1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_dual_mul_f32 v0, v0, v4 :: v_dual_mul_f32 v1, v1, v5 +; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0 +; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s1 ; GFX11-NEXT: v_log_f32_e32 v0, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_log_f32_e32 v1, v1 ; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_sub_f32 v1, v1, v5 ; GFX11-NEXT: v_dual_mul_dx9_zero_f32 v0, v0, v2 :: v_dual_mul_dx9_zero_f32 v1, v1, v3 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_exp_f32_e32 v0, v0 @@ -647,7 +743,15 @@ ; GFX6-LABEL: v_pow_f32_fabs_lhs: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: v_log_f32_e64 v0, |v0| +; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX6-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX6-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX6-NEXT: v_log_f32_e32 v0, v0 +; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 ; GFX6-NEXT: s_setpc_b64 s[30:31] @@ -655,7 +759,15 @@ ; GFX8-LABEL: v_pow_f32_fabs_lhs: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_log_f32_e64 v0, |v0| +; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX8-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX8-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX8-NEXT: v_log_f32_e32 v0, v0 +; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] @@ -663,7 +775,15 @@ ; GFX9-LABEL: v_pow_f32_fabs_lhs: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_log_f32_e64 v0, |v0| +; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX9-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX9-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX9-NEXT: v_log_f32_e32 v0, v0 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -672,7 +792,12 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_log_f32_e64 v0, |v0| +; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| +; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s4 +; GFX10-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4 +; GFX10-NEXT: v_log_f32_e32 v0, v0 +; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] @@ -681,8 +806,15 @@ ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_log_f32_e64 v0, |v0| +; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0 +; GFX11-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_exp_f32_e32 v0, v0 @@ -696,7 +828,15 @@ ; GFX6-LABEL: v_pow_f32_fabs_rhs: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX6-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX6-NEXT: v_mul_f32_e32 v0, v0, v2 ; GFX6-NEXT: v_log_f32_e32 v0, v0 +; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| ; GFX6-NEXT: v_exp_f32_e32 v0, v0 ; GFX6-NEXT: s_setpc_b64 s[30:31] @@ -704,7 +844,15 @@ ; GFX8-LABEL: v_pow_f32_fabs_rhs: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX8-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2 ; GFX8-NEXT: v_log_f32_e32 v0, v0 +; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| ; GFX8-NEXT: v_exp_f32_e32 v0, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] @@ -712,7 +860,15 @@ ; GFX9-LABEL: v_pow_f32_fabs_rhs: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX9-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2 ; GFX9-NEXT: v_log_f32_e32 v0, v0 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| ; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -721,7 +877,12 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| +; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s4 +; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4 ; GFX10-NEXT: v_log_f32_e32 v0, v0 +; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| ; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] @@ -730,8 +891,15 @@ ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0 +; GFX11-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, |v1| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_exp_f32_e32 v0, v0 @@ -745,7 +913,15 @@ ; GFX6-LABEL: v_pow_f32_fabs_lhs_rhs: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: v_log_f32_e64 v0, |v0| +; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX6-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX6-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX6-NEXT: v_log_f32_e32 v0, v0 +; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| ; GFX6-NEXT: v_exp_f32_e32 v0, v0 ; GFX6-NEXT: s_setpc_b64 s[30:31] @@ -753,7 +929,15 @@ ; GFX8-LABEL: v_pow_f32_fabs_lhs_rhs: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_log_f32_e64 v0, |v0| +; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX8-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX8-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX8-NEXT: v_log_f32_e32 v0, v0 +; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| ; GFX8-NEXT: v_exp_f32_e32 v0, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] @@ -761,7 +945,15 @@ ; GFX9-LABEL: v_pow_f32_fabs_lhs_rhs: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_log_f32_e64 v0, |v0| +; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX9-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX9-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX9-NEXT: v_log_f32_e32 v0, v0 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| ; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -770,7 +962,12 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_log_f32_e64 v0, |v0| +; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| +; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s4 +; GFX10-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4 +; GFX10-NEXT: v_log_f32_e32 v0, v0 +; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| ; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] @@ -779,8 +976,15 @@ ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_log_f32_e64 v0, |v0| +; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0 +; GFX11-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, |v1| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_exp_f32_e32 v0, v0 @@ -794,36 +998,72 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) { ; GFX6-LABEL: v_pow_f32_sgpr_vgpr: ; GFX6: ; %bb.0: -; GFX6-NEXT: v_log_f32_e32 v1, s0 +; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX6-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v1 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GFX6-NEXT: v_mul_f32_e32 v1, s0, v1 +; GFX6-NEXT: v_log_f32_e32 v1, v1 +; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX6-NEXT: v_sub_f32_e32 v1, v1, v2 ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: v_pow_f32_sgpr_vgpr: ; GFX8: ; %bb.0: -; GFX8-NEXT: v_log_f32_e32 v1, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX8-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v1 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GFX8-NEXT: v_mul_f32_e32 v1, s0, v1 +; GFX8-NEXT: v_log_f32_e32 v1, v1 +; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX8-NEXT: v_sub_f32_e32 v1, v1, v2 ; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: v_pow_f32_sgpr_vgpr: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_log_f32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GFX9-NEXT: v_mul_f32_e32 v1, s0, v1 +; GFX9-NEXT: v_log_f32_e32 v1, v1 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9-NEXT: v_sub_f32_e32 v1, v1, v2 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: v_pow_f32_sgpr_vgpr: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_log_f32_e32 v1, s0 +; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |s0| +; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s1 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s1 +; GFX10-NEXT: v_mul_f32_e32 v1, s0, v1 +; GFX10-NEXT: v_log_f32_e32 v1, v1 +; GFX10-NEXT: v_sub_f32_e32 v1, v1, v2 ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: v_pow_f32_sgpr_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_log_f32_e32 v1, s0 +; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |s0| +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s1 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s1 +; GFX11-NEXT: v_mul_f32_e32 v1, s0, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_log_f32_e32 v1, v1 ; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_sub_f32_e32 v1, v1, v2 ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_exp_f32_e32 v0, v0 @@ -835,36 +1075,72 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) { ; GFX6-LABEL: v_pow_f32_vgpr_sgpr: ; GFX6: ; %bb.0: +; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX6-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_log_f32_e32 v0, v0 +; GFX6-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: v_pow_f32_vgpr_sgpr: ; GFX8: ; %bb.0: +; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX8-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GFX8-NEXT: v_mul_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_log_f32_e32 v0, v0 +; GFX8-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: v_pow_f32_vgpr_sgpr: ; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_log_f32_e32 v0, v0 +; GFX9-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: v_pow_f32_vgpr_sgpr: ; GFX10: ; %bb.0: +; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0| +; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s1 +; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s1 ; GFX10-NEXT: v_log_f32_e32 v0, v0 +; GFX10-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 ; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: v_pow_f32_vgpr_sgpr: ; GFX11: ; %bb.0: +; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0| +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s1 +; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_exp_f32_e32 v0, v0 @@ -876,36 +1152,72 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) { ; GFX6-LABEL: v_pow_f32_sgpr_sgpr: ; GFX6: ; %bb.0: -; GFX6-NEXT: v_log_f32_e32 v0, s0 +; GFX6-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX6-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v0 +; GFX6-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; GFX6-NEXT: v_mul_f32_e32 v0, s0, v0 +; GFX6-NEXT: v_log_f32_e32 v0, v0 +; GFX6-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: v_pow_f32_sgpr_sgpr: ; GFX8: ; %bb.0: -; GFX8-NEXT: v_log_f32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX8-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v0 +; GFX8-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; GFX8-NEXT: v_mul_f32_e32 v0, s0, v0 +; GFX8-NEXT: v_log_f32_e32 v0, v0 +; GFX8-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: v_pow_f32_sgpr_sgpr: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_log_f32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v0 +; GFX9-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; GFX9-NEXT: v_mul_f32_e32 v0, s0, v0 +; GFX9-NEXT: v_log_f32_e32 v0, v0 +; GFX9-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: v_pow_f32_sgpr_sgpr: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_log_f32_e32 v0, s0 +; GFX10-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, |s0| +; GFX10-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s2 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s2 +; GFX10-NEXT: v_mul_f32_e32 v0, s0, v0 +; GFX10-NEXT: v_log_f32_e32 v0, v0 +; GFX10-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 ; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: v_pow_f32_sgpr_sgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_log_f32_e32 v0, s0 +; GFX11-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, |s0| +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s2 +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s2 +; GFX11-NEXT: v_mul_f32_e32 v0, s0, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s1, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_exp_f32_e32 v0, v0 @@ -918,7 +1230,15 @@ ; GFX6-LABEL: v_pow_f32_fneg_lhs: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: v_log_f32_e64 v0, -v0 +; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX6-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX6-NEXT: v_mul_f32_e64 v0, -v0, v2 +; GFX6-NEXT: v_log_f32_e32 v0, v0 +; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 ; GFX6-NEXT: s_setpc_b64 s[30:31] @@ -926,7 +1246,15 @@ ; GFX8-LABEL: v_pow_f32_fneg_lhs: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_log_f32_e64 v0, -v0 +; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX8-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX8-NEXT: v_mul_f32_e64 v0, -v0, v2 +; GFX8-NEXT: v_log_f32_e32 v0, v0 +; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] @@ -934,7 +1262,15 @@ ; GFX9-LABEL: v_pow_f32_fneg_lhs: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_log_f32_e64 v0, -v0 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX9-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX9-NEXT: v_mul_f32_e64 v0, -v0, v2 +; GFX9-NEXT: v_log_f32_e32 v0, v0 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -943,7 +1279,12 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_log_f32_e64 v0, -v0 +; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| +; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s4 +; GFX10-NEXT: v_mul_f32_e64 v0, -v0, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4 +; GFX10-NEXT: v_log_f32_e32 v0, v0 +; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] @@ -952,8 +1293,15 @@ ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_log_f32_e64 v0, -v0 +; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0 +; GFX11-NEXT: v_mul_f32_e64 v0, -v0, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_exp_f32_e32 v0, v0 @@ -967,7 +1315,15 @@ ; GFX6-LABEL: v_pow_f32_fneg_rhs: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX6-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX6-NEXT: v_mul_f32_e32 v0, v0, v2 ; GFX6-NEXT: v_log_f32_e32 v0, v0 +; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 ; GFX6-NEXT: s_setpc_b64 s[30:31] @@ -975,7 +1331,15 @@ ; GFX8-LABEL: v_pow_f32_fneg_rhs: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX8-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2 ; GFX8-NEXT: v_log_f32_e32 v0, v0 +; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] @@ -983,7 +1347,15 @@ ; GFX9-LABEL: v_pow_f32_fneg_rhs: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX9-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2 ; GFX9-NEXT: v_log_f32_e32 v0, v0 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -992,7 +1364,12 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| +; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s4 +; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4 ; GFX10-NEXT: v_log_f32_e32 v0, v0 +; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 ; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] @@ -1001,8 +1378,15 @@ ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0 +; GFX11-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, -v1 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_exp_f32_e32 v0, v0 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir @@ -11,10 +11,21 @@ ; CHECK: liveins: $vgpr0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[COPY]] - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000 - ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C]] - ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]] + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[SELECT]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000 + ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C5]] + ; CHECK-NEXT: $vgpr0 = COPY [[FMUL1]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = G_FLOG %0 $vgpr0 = COPY %1 @@ -30,10 +41,21 @@ ; CHECK: liveins: $vgpr0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = nnan G_FLOG2 [[COPY]] - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000 - ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[FLOG2_]], [[C]] - ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = nnan G_FABS [[COPY]] + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[SELECT]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[INT]], [[SELECT1]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000 + ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[FSUB]], [[C5]] + ; CHECK-NEXT: $vgpr0 = COPY [[FMUL1]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = nnan G_FLOG %0 $vgpr0 = COPY %1 @@ -50,12 +72,29 @@ ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) - ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]] - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000 - ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C]] - ; CHECK-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]] - ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_1]], [[C]] - ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[UV]] + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000 + ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C5]] + ; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]] + ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]] + ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](s32) + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT1]], [[SELECT3]] + ; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[FSUB1]], [[C5]] + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL1]](s32), [[FMUL3]](s32) ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %1:_(<2 x s32>) = G_FLOG %0 @@ -73,14 +112,37 @@ ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>) - ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]] - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000 - ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C]] - ; CHECK-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]] - ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_1]], [[C]] - ; CHECK-NEXT: [[FLOG2_2:%[0-9]+]]:_(s32) = G_FLOG2 [[UV2]] - ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_2]], [[C]] - ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32), [[FMUL2]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[UV]] + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000 + ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C5]] + ; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]] + ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]] + ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](s32) + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT1]], [[SELECT3]] + ; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[FSUB1]], [[C5]] + ; CHECK-NEXT: [[FABS2:%[0-9]+]]:_(s32) = G_FABS [[UV2]] + ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](s32), [[C]] + ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[SELECT4]] + ; CHECK-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL4]](s32) + ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[INT2]], [[SELECT5]] + ; CHECK-NEXT: [[FMUL5:%[0-9]+]]:_(s32) = G_FMUL [[FSUB2]], [[C5]] + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMUL1]](s32), [[FMUL3]](s32), [[FMUL5]](s32) ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>) %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 %1:_(<3 x s32>) = G_FLOG %0 @@ -99,9 +161,9 @@ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) - ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000 - ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C]] + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C]] ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32) ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16) ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) @@ -129,13 +191,13 @@ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) - ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000 - ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C1]] + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C1]] ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32) ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16) - ; CHECK-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT1]] - ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_1]], [[C1]] + ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT1]](s32) + ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[C1]] ; CHECK-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL1]](s32) ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16) ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16) Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir @@ -11,10 +11,20 @@ ; CHECK: liveins: $vgpr0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[COPY]] - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000 - ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C]] - ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[SELECT]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000 + ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C5]] + ; CHECK-NEXT: $vgpr0 = COPY [[FMUL1]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = G_FLOG10 %0 $vgpr0 = COPY %1 @@ -30,10 +40,20 @@ ; CHECK: liveins: $vgpr0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = nnan G_FLOG2 [[COPY]] - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000 - ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[FLOG2_]], [[C]] - ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[SELECT]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[INT]], [[SELECT1]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000 + ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[FSUB]], [[C5]] + ; CHECK-NEXT: $vgpr0 = COPY [[FMUL1]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = nnan G_FLOG10 %0 $vgpr0 = COPY %1 @@ -50,12 +70,27 @@ ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) - ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]] - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000 - ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C]] - ; CHECK-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]] - ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_1]], [[C]] - ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000 + ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C5]] + ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]] + ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](s32) + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT1]], [[SELECT3]] + ; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[FSUB1]], [[C5]] + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL1]](s32), [[FMUL3]](s32) ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %1:_(<2 x s32>) = G_FLOG10 %0 @@ -73,14 +108,34 @@ ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>) - ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]] - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000 - ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C]] - ; CHECK-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]] - ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_1]], [[C]] - ; CHECK-NEXT: [[FLOG2_2:%[0-9]+]]:_(s32) = G_FLOG2 [[UV2]] - ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_2]], [[C]] - ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32), [[FMUL2]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000 + ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C5]] + ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]] + ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](s32) + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT1]], [[SELECT3]] + ; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[FSUB1]], [[C5]] + ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](s32), [[C]] + ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[SELECT4]] + ; CHECK-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL4]](s32) + ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[INT2]], [[SELECT5]] + ; CHECK-NEXT: [[FMUL5:%[0-9]+]]:_(s32) = G_FMUL [[FSUB2]], [[C5]] + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMUL1]](s32), [[FMUL3]](s32), [[FMUL5]](s32) ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>) %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 %1:_(<3 x s32>) = G_FLOG10 %0 @@ -99,9 +154,9 @@ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) - ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000 - ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C]] + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C]] ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32) ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16) ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) @@ -129,13 +184,13 @@ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) - ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000 - ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C1]] + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C1]] ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32) ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16) - ; CHECK-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT1]] - ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_1]], [[C1]] + ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT1]](s32) + ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[C1]] ; CHECK-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL1]](s32) ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16) ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16) Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir @@ -11,8 +11,19 @@ ; CHECK: liveins: $vgpr0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[COPY]] - ; CHECK-NEXT: $vgpr0 = COPY [[FLOG2_]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]] + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[SELECT]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]] + ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = G_FLOG2 %0 $vgpr0 = COPY %1 @@ -29,9 +40,26 @@ ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) - ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]] - ; CHECK-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]] - ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FLOG2_]](s32), [[FLOG2_1]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[UV]] + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]] + ; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]] + ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]] + ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL1]](s32) + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT1]], [[SELECT3]] + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32) ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %1:_(<2 x s32>) = G_FLOG2 %0 @@ -49,10 +77,33 @@ ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>) - ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]] - ; CHECK-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]] - ; CHECK-NEXT: [[FLOG2_2:%[0-9]+]]:_(s32) = G_FLOG2 [[UV2]] - ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FLOG2_]](s32), [[FLOG2_1]](s32), [[FLOG2_2]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[UV]] + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]] + ; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]] + ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]] + ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL1]](s32) + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT1]], [[SELECT3]] + ; CHECK-NEXT: [[FABS2:%[0-9]+]]:_(s32) = G_FABS [[UV2]] + ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](s32), [[C]] + ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]] + ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[SELECT4]] + ; CHECK-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](s32) + ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]] + ; CHECK-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[INT2]], [[SELECT5]] + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32), [[FSUB2]](s32) ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>) %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 %1:_(<3 x s32>) = G_FLOG2 %0 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir @@ -15,18 +15,40 @@ ; GFX6-NEXT: {{ $}} ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[COPY]] - ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[COPY1]](s32) - ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]] + ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]] + ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[SELECT]] + ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]] + ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[COPY1]](s32) + ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] ; GFX6-NEXT: $vgpr0 = COPY [[FEXP2_]](s32) ; GFX9-LABEL: name: test_fpow_s32 ; GFX9: liveins: $vgpr0, $vgpr1 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX9-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[COPY]] - ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[COPY1]](s32) - ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]] + ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]] + ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[SELECT]] + ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]] + ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[COPY1]](s32) + ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] ; GFX9-NEXT: $vgpr0 = COPY [[FEXP2_]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 @@ -47,12 +69,29 @@ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX6-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) - ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]] - ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[UV2]](s32) - ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]] - ; GFX6-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]] - ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_1]](s32), [[UV3]](s32) - ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] + ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[UV]] + ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]] + ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]] + ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[UV2]](s32) + ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] + ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]] + ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C]] + ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]] + ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]] + ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL1]](s32) + ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]] + ; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT2]], [[SELECT3]] + ; GFX6-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB1]](s32), [[UV3]](s32) + ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT3]] ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FEXP2_]](s32), [[FEXP2_1]](s32) ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; GFX9-LABEL: name: test_fpow_v2s32 @@ -62,12 +101,29 @@ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) - ; GFX9-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]] - ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[UV2]](s32) - ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]] - ; GFX9-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]] - ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_1]](s32), [[UV3]](s32) - ; GFX9-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] + ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[UV]] + ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]] + ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]] + ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[UV2]](s32) + ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] + ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]] + ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C]] + ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]] + ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]] + ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL1]](s32) + ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]] + ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT2]], [[SELECT3]] + ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB1]](s32), [[UV3]](s32) + ; GFX9-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT3]] ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FEXP2_]](s32), [[FEXP2_1]](s32) ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 @@ -89,15 +145,38 @@ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5 ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>) ; GFX6-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>) - ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]] - ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[UV3]](s32) - ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]] - ; GFX6-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]] - ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_1]](s32), [[UV4]](s32) - ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] - ; GFX6-NEXT: [[FLOG2_2:%[0-9]+]]:_(s32) = G_FLOG2 [[UV2]] - ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_2]](s32), [[UV5]](s32) - ; GFX6-NEXT: [[FEXP2_2:%[0-9]+]]:_(s32) = G_FEXP2 [[INT2]] + ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[UV]] + ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]] + ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]] + ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[UV3]](s32) + ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] + ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]] + ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C]] + ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]] + ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]] + ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL1]](s32) + ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]] + ; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT2]], [[SELECT3]] + ; GFX6-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB1]](s32), [[UV4]](s32) + ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT3]] + ; GFX6-NEXT: [[FABS2:%[0-9]+]]:_(s32) = G_FABS [[UV2]] + ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](s32), [[C]] + ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]] + ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[SELECT4]] + ; GFX6-NEXT: [[INT4:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](s32) + ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]] + ; GFX6-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[INT4]], [[SELECT5]] + ; GFX6-NEXT: [[INT5:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB2]](s32), [[UV5]](s32) + ; GFX6-NEXT: [[FEXP2_2:%[0-9]+]]:_(s32) = G_FEXP2 [[INT5]] ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FEXP2_]](s32), [[FEXP2_1]](s32), [[FEXP2_2]](s32) ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>) ; GFX9-LABEL: name: test_fpow_v3s32 @@ -107,15 +186,38 @@ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5 ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>) ; GFX9-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>) - ; GFX9-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]] - ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[UV3]](s32) - ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]] - ; GFX9-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]] - ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_1]](s32), [[UV4]](s32) - ; GFX9-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] - ; GFX9-NEXT: [[FLOG2_2:%[0-9]+]]:_(s32) = G_FLOG2 [[UV2]] - ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_2]](s32), [[UV5]](s32) - ; GFX9-NEXT: [[FEXP2_2:%[0-9]+]]:_(s32) = G_FEXP2 [[INT2]] + ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[UV]] + ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]] + ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]] + ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[UV3]](s32) + ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] + ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]] + ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C]] + ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]] + ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]] + ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL1]](s32) + ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]] + ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT2]], [[SELECT3]] + ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB1]](s32), [[UV4]](s32) + ; GFX9-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT3]] + ; GFX9-NEXT: [[FABS2:%[0-9]+]]:_(s32) = G_FABS [[UV2]] + ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](s32), [[C]] + ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]] + ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[SELECT4]] + ; GFX9-NEXT: [[INT4:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](s32) + ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]] + ; GFX9-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[INT4]], [[SELECT5]] + ; GFX9-NEXT: [[INT5:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB2]](s32), [[UV5]](s32) + ; GFX9-NEXT: [[FEXP2_2:%[0-9]+]]:_(s32) = G_FEXP2 [[INT5]] ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FEXP2_]](s32), [[FEXP2_1]](s32), [[FEXP2_2]](s32) ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>) %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 @@ -135,18 +237,40 @@ ; GFX6-NEXT: {{ $}} ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = nnan nsz G_FLOG2 [[COPY]] - ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[COPY1]](s32) - ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT]] + ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = nnan nsz G_FABS [[COPY]] + ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan nsz G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan nsz G_FMUL [[COPY]], [[SELECT]] + ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan nsz G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan nsz G_FSUB [[INT]], [[SELECT1]] + ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[COPY1]](s32) + ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT1]] ; GFX6-NEXT: $vgpr0 = COPY [[FEXP2_]](s32) ; GFX9-LABEL: name: test_fpow_s32_flags ; GFX9: liveins: $vgpr0, $vgpr1 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX9-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = nnan nsz G_FLOG2 [[COPY]] - ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[COPY1]](s32) - ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT]] + ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = nnan nsz G_FABS [[COPY]] + ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan nsz G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan nsz G_FMUL [[COPY]], [[SELECT]] + ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan nsz G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan nsz G_FSUB [[INT]], [[SELECT1]] + ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[COPY1]](s32) + ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT1]] ; GFX9-NEXT: $vgpr0 = COPY [[FEXP2_]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 @@ -169,9 +293,9 @@ ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16) - ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT]] - ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[FPEXT1]](s32) - ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]] + ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32) + ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT]](s32), [[FPEXT1]](s32) + ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FEXP2_]](s32) ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16) ; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) @@ -221,15 +345,15 @@ ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32) ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16) - ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT]] - ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[FPEXT1]](s32) - ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]] + ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32) + ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT]](s32), [[FPEXT1]](s32) + ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FEXP2_]](s32) ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16) ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16) - ; GFX6-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT2]] - ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_1]](s32), [[FPEXT3]](s32) - ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] + ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT2]](s32) + ; GFX6-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT2]](s32), [[FPEXT3]](s32) + ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT3]] ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FEXP2_1]](s32) ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16) ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16) @@ -293,15 +417,15 @@ ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32) ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16) - ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = nnan nsz G_FLOG2 [[FPEXT]] - ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[FPEXT1]](s32) - ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT]] + ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32) + ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT]](s32), [[FPEXT1]](s32) + ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT1]] ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FEXP2_]](s32) ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16) ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16) - ; GFX6-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = nnan nsz G_FLOG2 [[FPEXT2]] - ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_1]](s32), [[FPEXT3]](s32) - ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT1]] + ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT2]](s32) + ; GFX6-NEXT: [[INT3:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT2]](s32), [[FPEXT3]](s32) + ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT3]] ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FEXP2_1]](s32) ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16) ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16) Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir @@ -18,9 +18,9 @@ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) ; GFX6-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY1]](s32) - ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = nnan G_FLOG2 [[FPEXT]] - ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[SITOFP]](s32) - ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT]] + ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32) + ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT]](s32), [[SITOFP]](s32) + ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT1]] ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FEXP2_]](s32) ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16) ; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) @@ -59,9 +59,20 @@ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX6-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY1]](s32) - ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = nnan G_FLOG2 [[COPY]] - ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[SITOFP]](s32) - ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT]] + ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = nnan G_FABS [[COPY]] + ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[SELECT]] + ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[INT]], [[SELECT1]] + ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[SITOFP]](s32) + ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT1]] ; GFX6-NEXT: $vgpr0 = COPY [[FEXP2_]](s32) ; GFX9-LABEL: name: test_fpowi_s32_s32_flags ; GFX9: liveins: $vgpr0, $vgpr1 @@ -69,9 +80,20 @@ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY1]](s32) - ; GFX9-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = nnan G_FLOG2 [[COPY]] - ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[SITOFP]](s32) - ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT]] + ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000 + ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = nnan G_FABS [[COPY]] + ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]] + ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 + ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]] + ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[SELECT]] + ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32) + ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01 + ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C3]], [[C4]] + ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[INT]], [[SELECT1]] + ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[SITOFP]](s32) + ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT1]] ; GFX9-NEXT: $vgpr0 = COPY [[FEXP2_]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll @@ -36,8 +36,16 @@ ; GCN-LABEL: v_powi_f32: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cvt_f32_i32_e32 v1, v1 +; GCN-NEXT: v_mov_b32_e32 v2, 0x800000 +; GCN-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GCN-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +; GCN-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GCN-NEXT: v_mul_f32_e32 v0, v0, v2 ; GCN-NEXT: v_log_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, v1 +; GCN-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GCN-NEXT: v_sub_f32_e32 v0, v0, v2 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: s_setpc_b64 s[30:31] @@ -68,7 +76,15 @@ ; GCN-LABEL: v_powi_neg1_f32: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GCN-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-NEXT: v_mul_f32_e32 v0, v0, v1 ; GCN-NEXT: v_log_f32_e32 v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-NEXT: v_sub_f32_e32 v0, v0, v1 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, -1.0, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: s_setpc_b64 s[30:31] @@ -80,7 +96,15 @@ ; GCN-LABEL: v_powi_2_f32: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GCN-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-NEXT: v_mul_f32_e32 v0, v0, v1 ; GCN-NEXT: v_log_f32_e32 v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-NEXT: v_sub_f32_e32 v0, v0, v1 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, 2.0, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: s_setpc_b64 s[30:31] @@ -92,7 +116,15 @@ ; GCN-LABEL: v_powi_neg2_f32: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GCN-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-NEXT: v_mul_f32_e32 v0, v0, v1 ; GCN-NEXT: v_log_f32_e32 v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-NEXT: v_sub_f32_e32 v0, v0, v1 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, -2.0, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: s_setpc_b64 s[30:31] @@ -104,7 +136,15 @@ ; GCN-LABEL: v_powi_4_f32: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GCN-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-NEXT: v_mul_f32_e32 v0, v0, v1 ; GCN-NEXT: v_log_f32_e32 v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-NEXT: v_sub_f32_e32 v0, v0, v1 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, 4.0, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: s_setpc_b64 s[30:31] @@ -116,7 +156,15 @@ ; GCN-LABEL: v_powi_8_f32: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GCN-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-NEXT: v_mul_f32_e32 v0, v0, v1 ; GCN-NEXT: v_log_f32_e32 v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-NEXT: v_sub_f32_e32 v0, v0, v1 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, 0x41000000, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: s_setpc_b64 s[30:31] @@ -128,7 +176,15 @@ ; GCN-LABEL: v_powi_16_f32: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GCN-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-NEXT: v_mul_f32_e32 v0, v0, v1 ; GCN-NEXT: v_log_f32_e32 v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-NEXT: v_sub_f32_e32 v0, v0, v1 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, 0x41800000, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: s_setpc_b64 s[30:31] @@ -140,7 +196,15 @@ ; GCN-LABEL: v_powi_128_f32: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GCN-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-NEXT: v_mul_f32_e32 v0, v0, v1 ; GCN-NEXT: v_log_f32_e32 v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-NEXT: v_sub_f32_e32 v0, v0, v1 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, 0x43000000, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: s_setpc_b64 s[30:31] @@ -152,7 +216,15 @@ ; GCN-LABEL: v_powi_neg128_f32: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GCN-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-NEXT: v_mul_f32_e32 v0, v0, v1 ; GCN-NEXT: v_log_f32_e32 v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-NEXT: v_sub_f32_e32 v0, v0, v1 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, 0xc3000000, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: s_setpc_b64 s[30:31] Index: llvm/test/CodeGen/AMDGPU/llvm.log.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/llvm.log.ll +++ llvm/test/CodeGen/AMDGPU/llvm.log.ll @@ -10,76 +10,164 @@ ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) { -; SI-LABEL: s_log_f32: -; SI: ; %bb.0: -; SI-NEXT: s_load_dword s2, s[0:1], 0xb -; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; SI-NEXT: s_mov_b32 s3, 0xf000 -; SI-NEXT: s_waitcnt lgkmcnt(0) -; SI-NEXT: v_log_f32_e32 v0, s2 -; SI-NEXT: s_mov_b32 s2, -1 -; SI-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 -; SI-NEXT: s_endpgm -; -; VI-LABEL: s_log_f32: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_log_f32_e32 v0, s2 -; VI-NEXT: v_mul_f32_e32 v2, 0x3f317218, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: flat_store_dword v[0:1], v2 -; VI-NEXT: s_endpgm +; SI-SDAG-LABEL: s_log_f32: +; SI-SDAG: ; %bb.0: +; SI-SDAG-NEXT: s_load_dword s2, s[0:1], 0xb +; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000 +; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; SI-SDAG-NEXT: v_log_f32_e32 v1, v1 +; SI-SDAG-NEXT: s_mov_b32 s2, -1 +; SI-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0 +; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; SI-SDAG-NEXT: s_endpgm +; +; SI-GISEL-LABEL: s_log_f32: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_load_dword s2, s[0:1], 0xb +; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 +; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; SI-GISEL-NEXT: v_mul_f32_e32 v0, s2, v0 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: s_mov_b32 s2, -1 +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; SI-GISEL-NEXT: s_endpgm +; +; VI-SDAG-LABEL: s_log_f32: +; VI-SDAG: ; %bb.0: +; VI-SDAG-NEXT: s_load_dword s2, s[0:1], 0x2c +; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; VI-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; VI-SDAG-NEXT: v_log_f32_e32 v1, v1 +; VI-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0 +; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317218, v0 +; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; VI-SDAG-NEXT: flat_store_dword v[0:1], v2 +; VI-SDAG-NEXT: s_endpgm +; +; VI-GISEL-LABEL: s_log_f32: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_load_dword s2, s[0:1], 0x2c +; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; VI-GISEL-NEXT: v_mul_f32_e32 v0, s2, v0 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317218, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; VI-GISEL-NEXT: flat_store_dword v[0:1], v2 +; VI-GISEL-NEXT: s_endpgm ; ; GFX900-SDAG-LABEL: s_log_f32: ; GFX900-SDAG: ; %bb.0: -; GFX900-SDAG-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX900-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX900-SDAG-NEXT: s_load_dword s2, s[0:1], 0x2c +; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-SDAG-NEXT: v_log_f32_e32 v0, s4 +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; GFX900-SDAG-NEXT: v_log_f32_e32 v1, v1 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GFX900-SDAG-NEXT: global_store_dword v1, v0, s[2:3] +; GFX900-SDAG-NEXT: global_store_dword v2, v0, s[0:1] ; GFX900-SDAG-NEXT: s_endpgm ; ; GFX900-GISEL-LABEL: s_log_f32: ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_load_dword s2, s[0:1], 0x2c -; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s2 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s2, v0 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0 ; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1] ; GFX900-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log_f32: ; R600: ; %bb.0: -; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[] +; R600-NEXT: ALU 11, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 ; R600-NEXT: CF_END ; R600-NEXT: PAD ; R600-NEXT: ALU clause starting at 4: -; R600-NEXT: LOG_IEEE * T0.X, KC0[2].Z, -; R600-NEXT: MUL_IEEE T0.X, PS, literal.x, +; R600-NEXT: SETGT * T0.W, literal.x, KC0[2].Z, +; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; R600-NEXT: CNDE * T1.W, PV.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T1.W, KC0[2].Z, PV.W, +; R600-NEXT: CNDE * T0.W, T0.W, 0.0, literal.x, +; R600-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; R600-NEXT: LOG_IEEE * T0.X, PV.W, +; R600-NEXT: ADD * T0.W, PS, -T0.W, +; R600-NEXT: MUL_IEEE T0.X, PV.W, literal.x, ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, ; R600-NEXT: 1060205080(6.931472e-01), 2(2.802597e-45) ; ; CM-LABEL: s_log_f32: ; CM: ; %bb.0: -; CM-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: ALU 15, @4, KC0[CB0:0-32], KC1[] ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X ; CM-NEXT: CF_END ; CM-NEXT: PAD ; CM-NEXT: ALU clause starting at 4: -; CM-NEXT: LOG_IEEE T0.X, KC0[2].Z, -; CM-NEXT: LOG_IEEE T0.Y (MASKED), KC0[2].Z, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[2].Z, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[2].Z, -; CM-NEXT: MUL_IEEE * T0.X, PV.X, literal.x, +; CM-NEXT: SETGT * T0.W, literal.x, KC0[2].Z, +; CM-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; CM-NEXT: CNDE * T1.W, PV.W, 1.0, literal.x, +; CM-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; CM-NEXT: CNDE T0.Z, T0.W, 0.0, literal.x, +; CM-NEXT: MUL_IEEE * T0.W, KC0[2].Z, PV.W, +; CM-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; CM-NEXT: LOG_IEEE T0.X, T0.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: ADD * T0.W, PV.X, -T0.Z, +; CM-NEXT: MUL_IEEE * T0.X, PV.W, literal.x, ; CM-NEXT: 1060205080(6.931472e-01), 0(0.000000e+00) ; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) @@ -94,40 +182,81 @@ ; SI-SDAG-LABEL: s_log_v2f32: ; SI-SDAG: ; %bb.0: ; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000 -; SI-SDAG-NEXT: s_mov_b32 s6, -1 ; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; SI-SDAG-NEXT: v_log_f32_e32 v0, s3 -; SI-SDAG-NEXT: v_log_f32_e32 v2, s2 +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v4, s3, v4 +; SI-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; SI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; SI-SDAG-NEXT: v_log_f32_e32 v3, v1 +; SI-SDAG-NEXT: s_mov_b32 s6, -1 ; SI-SDAG-NEXT: s_mov_b32 s4, s0 +; SI-SDAG-NEXT: v_sub_f32_e32 v1, v4, v2 +; SI-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0 ; SI-SDAG-NEXT: s_mov_b32 s5, s1 -; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v0 -; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v2 +; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 +; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-SDAG-NEXT: s_endpgm ; ; SI-GISEL-LABEL: s_log_v2f32: ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-GISEL-NEXT: s_mov_b32 s4, 0x800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x4f800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; SI-GISEL-NEXT: v_log_f32_e32 v0, s2 -; SI-GISEL-NEXT: v_log_f32_e32 v1, s3 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2 +; SI-GISEL-NEXT: v_mov_b32_e32 v4, s3 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc +; SI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2 +; SI-GISEL-NEXT: v_mul_f32_e32 v0, s3, v0 +; SI-GISEL-NEXT: v_log_f32_e32 v2, v2 +; SI-GISEL-NEXT: v_log_f32_e32 v4, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; SI-GISEL-NEXT: s_mov_b32 s2, -1 -; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v2, v3 +; SI-GISEL-NEXT: v_sub_f32_e32 v1, v4, v1 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 +; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 ; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-GISEL-NEXT: s_endpgm ; ; VI-SDAG-LABEL: s_log_v2f32: ; VI-SDAG: ; %bb.0: ; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; VI-SDAG-NEXT: v_log_f32_e32 v0, s3 -; VI-SDAG-NEXT: v_log_f32_e32 v2, s2 -; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v0 -; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v2 +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; VI-SDAG-NEXT: v_mul_f32_e32 v4, s3, v4 +; VI-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; VI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; VI-SDAG-NEXT: v_log_f32_e32 v2, v1 +; VI-SDAG-NEXT: v_sub_f32_e32 v1, v4, v3 +; VI-SDAG-NEXT: v_sub_f32_e32 v0, v2, v0 ; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1 +; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 +; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0 ; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-SDAG-NEXT: s_endpgm @@ -135,73 +264,145 @@ ; VI-GISEL-LABEL: s_log_v2f32: ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; VI-GISEL-NEXT: s_mov_b32 s4, 0x800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x4f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; VI-GISEL-NEXT: v_log_f32_e32 v0, s2 -; VI-GISEL-NEXT: v_log_f32_e32 v1, s3 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, s3 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v4 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc +; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2 +; VI-GISEL-NEXT: v_mul_f32_e32 v0, s3, v0 +; VI-GISEL-NEXT: v_log_f32_e32 v2, v2 +; VI-GISEL-NEXT: v_log_f32_e32 v4, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v2, v3 +; VI-GISEL-NEXT: v_sub_f32_e32 v1, v4, v1 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0 ; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0 ; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-GISEL-NEXT: s_endpgm ; ; GFX900-SDAG-LABEL: s_log_v2f32: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-SDAG-NEXT: v_log_f32_e32 v0, s3 -; GFX900-SDAG-NEXT: v_log_f32_e32 v2, s2 -; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v0 -; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v2 -; GFX900-SDAG-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1] +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GFX900-SDAG-NEXT: v_mul_f32_e32 v4, s3, v4 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; GFX900-SDAG-NEXT: v_log_f32_e32 v4, v4 +; GFX900-SDAG-NEXT: v_log_f32_e32 v2, v1 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v4, v3 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v2, v0 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GFX900-SDAG-NEXT: global_store_dwordx2 v5, v[0:1], s[0:1] ; GFX900-SDAG-NEXT: s_endpgm ; ; GFX900-GISEL-LABEL: s_log_v2f32: ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x4f800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s2 -; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s3 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, s3 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v4 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc +; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s3, v0 +; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v2 +; GFX900-GISEL-NEXT: v_log_f32_e32 v4, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v2, v3 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v4, v1 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX900-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log_v2f32: ; R600: ; %bb.0: -; R600-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[] +; R600-NEXT: ALU 21, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; R600-NEXT: CF_END ; R600-NEXT: PAD ; R600-NEXT: ALU clause starting at 4: -; R600-NEXT: LOG_IEEE * T0.X, KC0[3].X, -; R600-NEXT: MUL_IEEE T0.Y, PS, literal.x, -; R600-NEXT: LOG_IEEE * T0.X, KC0[2].W, +; R600-NEXT: SETGT T0.W, literal.x, KC0[3].X, +; R600-NEXT: SETGT * T1.W, literal.x, KC0[2].W, +; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; R600-NEXT: CNDE * T2.W, PV.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T2.W, KC0[3].X, PV.W, +; R600-NEXT: CNDE * T3.W, T1.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T0.Z, KC0[2].W, PS, +; R600-NEXT: CNDE T0.W, T0.W, 0.0, literal.x, +; R600-NEXT: LOG_IEEE * T0.X, PV.W, +; R600-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; R600-NEXT: CNDE T1.Z, T1.W, 0.0, literal.x, +; R600-NEXT: ADD T0.W, PS, -PV.W, +; R600-NEXT: LOG_IEEE * T0.X, PV.Z, +; R600-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T0.Y, PV.W, literal.x, +; R600-NEXT: ADD * T0.W, PS, -PV.Z, ; R600-NEXT: 1060205080(6.931472e-01), 0(0.000000e+00) -; R600-NEXT: MUL_IEEE T0.X, PS, literal.x, +; R600-NEXT: MUL_IEEE T0.X, PV.W, literal.x, ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, ; R600-NEXT: 1060205080(6.931472e-01), 2(2.802597e-45) ; ; CM-LABEL: s_log_v2f32: ; CM: ; %bb.0: -; CM-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: ALU 27, @4, KC0[CB0:0-32], KC1[] ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X ; CM-NEXT: CF_END ; CM-NEXT: PAD ; CM-NEXT: ALU clause starting at 4: -; CM-NEXT: LOG_IEEE T0.X, KC0[3].X, -; CM-NEXT: LOG_IEEE T0.Y (MASKED), KC0[3].X, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[3].X, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[3].X, -; CM-NEXT: MUL_IEEE * T0.Y, PV.X, literal.x, +; CM-NEXT: SETGT * T0.W, literal.x, KC0[3].X, +; CM-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; CM-NEXT: CNDE T0.Z, PV.W, 1.0, literal.x, +; CM-NEXT: SETGT * T1.W, literal.y, KC0[2].W, +; CM-NEXT: 1333788672(4.294967e+09), 8388608(1.175494e-38) +; CM-NEXT: CNDE T0.Y, PV.W, 1.0, literal.x, +; CM-NEXT: CNDE T1.Z, T0.W, 0.0, literal.y, +; CM-NEXT: MUL_IEEE * T0.W, KC0[3].X, PV.Z, +; CM-NEXT: 1333788672(4.294967e+09), 1107296256(3.200000e+01) +; CM-NEXT: LOG_IEEE T0.X, T0.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: CNDE T1.Y, T1.W, 0.0, literal.x, +; CM-NEXT: ADD T0.Z, PV.X, -T1.Z, +; CM-NEXT: MUL_IEEE * T0.W, KC0[2].W, T0.Y, +; CM-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; CM-NEXT: LOG_IEEE T0.X, T0.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: MUL_IEEE T0.Y, T0.Z, literal.x, +; CM-NEXT: ADD * T0.W, PV.X, -T1.Y, ; CM-NEXT: 1060205080(6.931472e-01), 0(0.000000e+00) -; CM-NEXT: LOG_IEEE T0.X, KC0[2].W, -; CM-NEXT: LOG_IEEE T0.Y (MASKED), KC0[2].W, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[2].W, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[2].W, -; CM-NEXT: MUL_IEEE * T0.X, PV.X, literal.x, +; CM-NEXT: MUL_IEEE * T0.X, PV.W, literal.x, ; CM-NEXT: 1060205080(6.931472e-01), 0(0.000000e+00) ; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) @@ -214,16 +415,34 @@ ; SI-SDAG-LABEL: s_log_v3f32: ; SI-SDAG: ; %bb.0: ; SI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd +; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 ; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v4, s5, v4 +; SI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v5, 1.0, v2, vcc +; SI-SDAG-NEXT: v_sub_f32_e32 v3, v4, v3 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v0, s6, v0 +; SI-SDAG-NEXT: v_mul_f32_e32 v5, s4, v5 +; SI-SDAG-NEXT: v_log_f32_e32 v2, v0 +; SI-SDAG-NEXT: v_log_f32_e32 v5, v5 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc ; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000 +; SI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v6 ; SI-SDAG-NEXT: s_mov_b32 s2, -1 -; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; SI-SDAG-NEXT: v_log_f32_e32 v0, s5 -; SI-SDAG-NEXT: v_log_f32_e32 v2, s4 -; SI-SDAG-NEXT: v_log_f32_e32 v3, s6 -; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v0 -; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v2 -; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317218, v3 +; SI-SDAG-NEXT: v_sub_f32_e32 v0, v5, v4 +; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2 +; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v3 +; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-SDAG-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8 ; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-SDAG-NEXT: s_endpgm @@ -232,14 +451,35 @@ ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd ; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; SI-GISEL-NEXT: s_mov_b32 s2, -1 -; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 +; SI-GISEL-NEXT: s_mov_b32 s2, 0x800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; SI-GISEL-NEXT: v_log_f32_e32 v0, s4 -; SI-GISEL-NEXT: v_log_f32_e32 v1, s5 -; SI-GISEL-NEXT: v_log_f32_e32 v2, s6 +; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; SI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 +; SI-GISEL-NEXT: v_mov_b32_e32 v4, s5 +; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v1, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2 +; SI-GISEL-NEXT: v_mul_f32_e32 v4, s5, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; SI-GISEL-NEXT: v_log_f32_e32 v4, v4 +; SI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v2, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v1, v4, v5 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 +; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 +; SI-GISEL-NEXT: s_mov_b32 s2, -1 ; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2 ; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-GISEL-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8 @@ -248,15 +488,33 @@ ; VI-SDAG-LABEL: s_log_v3f32: ; VI-SDAG: ; %bb.0: ; VI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 +; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 ; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; VI-SDAG-NEXT: v_log_f32_e32 v0, s6 -; VI-SDAG-NEXT: v_log_f32_e32 v3, s4 -; VI-SDAG-NEXT: v_log_f32_e32 v1, s5 -; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317218, v0 -; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v3 +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc +; VI-SDAG-NEXT: v_mul_f32_e32 v4, s6, v4 +; VI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; VI-SDAG-NEXT: v_sub_f32_e32 v3, v4, v3 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; VI-SDAG-NEXT: v_mul_f32_e32 v4, s5, v4 +; VI-SDAG-NEXT: v_mul_f32_e32 v1, s4, v1 +; VI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; VI-SDAG-NEXT: v_log_f32_e32 v6, v1 +; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317218, v3 +; VI-SDAG-NEXT: v_sub_f32_e32 v1, v4, v5 +; VI-SDAG-NEXT: v_sub_f32_e32 v0, v6, v0 ; VI-SDAG-NEXT: v_mov_b32_e32 v4, s1 ; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 +; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; VI-SDAG-NEXT: v_mov_b32_e32 v3, s0 ; VI-SDAG-NEXT: flat_store_dwordx3 v[3:4], v[0:2] ; VI-SDAG-NEXT: s_endpgm @@ -265,12 +523,33 @@ ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-GISEL-NEXT: s_mov_b32 s2, 0x800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; VI-GISEL-NEXT: v_log_f32_e32 v0, s4 -; VI-GISEL-NEXT: v_log_f32_e32 v1, s5 -; VI-GISEL-NEXT: v_log_f32_e32 v2, s6 -; VI-GISEL-NEXT: v_mov_b32_e32 v4, s1 +; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; VI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5 +; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v4 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v1, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; VI-GISEL-NEXT: v_mul_f32_e32 v4, s5, v4 +; VI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v4, v4 +; VI-GISEL-NEXT: v_log_f32_e32 v2, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc ; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; VI-GISEL-NEXT: v_sub_f32_e32 v1, v4, v5 +; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, s1 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, s0 @@ -280,82 +559,159 @@ ; GFX900-SDAG-LABEL: s_log_v3f32: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 -; GFX900-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-SDAG-NEXT: v_log_f32_e32 v0, s6 -; GFX900-SDAG-NEXT: v_log_f32_e32 v1, s5 -; GFX900-SDAG-NEXT: v_log_f32_e32 v3, s4 -; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317218, v0 +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc +; GFX900-SDAG-NEXT: v_mul_f32_e32 v4, s6, v4 +; GFX900-SDAG-NEXT: v_log_f32_e32 v4, v4 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v2, vcc +; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v4, v3 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, s5, v6 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, s4, v1 +; GFX900-SDAG-NEXT: v_log_f32_e32 v6, v6 +; GFX900-SDAG-NEXT: v_log_f32_e32 v7, v1 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317218, v3 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v6, v4 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v7, v0 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 -; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v3 -; GFX900-SDAG-NEXT: global_store_dwordx3 v4, v[0:2], s[2:3] +; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GFX900-SDAG-NEXT: global_store_dwordx3 v5, v[0:2], s[0:1] ; GFX900-SDAG-NEXT: s_endpgm ; ; GFX900-GISEL-LABEL: s_log_v3f32: ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0 -; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX900-GISEL-NEXT: s_mov_b32 s0, 0x800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s4 -; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s5 -; GFX900-GISEL-NEXT: v_log_f32_e32 v2, s6 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, s5 +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v4 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v1, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, s5, v4 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v4, v4 +; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v4, v5 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2 -; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1] +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0 +; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3] ; GFX900-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log_v3f32: ; R600: ; %bb.0: -; R600-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[] -; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 0 +; R600-NEXT: ALU 33, @4, KC0[CB0:0-32], KC1[] +; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; R600-NEXT: CF_END ; R600-NEXT: ALU clause starting at 4: -; R600-NEXT: LOG_IEEE * T0.X, KC0[3].Z, -; R600-NEXT: MUL_IEEE T0.Y, PS, literal.x, -; R600-NEXT: LOG_IEEE * T0.X, KC0[3].Y, +; R600-NEXT: SETGT T0.W, literal.x, KC0[3].Z, +; R600-NEXT: SETGT * T1.W, literal.x, KC0[3].Y, +; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; R600-NEXT: CNDE * T2.W, PV.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T2.W, KC0[3].Z, PV.W, +; R600-NEXT: CNDE * T3.W, T1.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T0.Y, KC0[3].Y, PS, +; R600-NEXT: CNDE T0.Z, T0.W, 0.0, literal.x, +; R600-NEXT: SETGT T0.W, literal.y, KC0[3].W, +; R600-NEXT: LOG_IEEE * T0.X, PV.W, +; R600-NEXT: 1107296256(3.200000e+01), 8388608(1.175494e-38) +; R600-NEXT: CNDE T1.Y, T1.W, 0.0, literal.x, +; R600-NEXT: CNDE T1.Z, PV.W, 1.0, literal.y, +; R600-NEXT: ADD T1.W, PS, -PV.Z, +; R600-NEXT: LOG_IEEE * T0.X, PV.Y, +; R600-NEXT: 1107296256(3.200000e+01), 1333788672(4.294967e+09) +; R600-NEXT: MUL_IEEE T0.Y, PV.W, literal.x, +; R600-NEXT: MUL_IEEE T1.W, KC0[3].W, PV.Z, +; R600-NEXT: ADD * T2.W, PS, -PV.Y, ; R600-NEXT: 1060205080(6.931472e-01), 0(0.000000e+00) ; R600-NEXT: MUL_IEEE T0.X, PS, literal.x, -; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, -; R600-NEXT: 1060205080(6.931472e-01), 2(2.802597e-45) -; R600-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, -; R600-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; R600-NEXT: LSHR T2.X, PV.W, literal.x, -; R600-NEXT: LOG_IEEE * T0.Z, KC0[3].W, +; R600-NEXT: CNDE T0.W, T0.W, 0.0, literal.y, +; R600-NEXT: LOG_IEEE * T0.Z, PV.W, +; R600-NEXT: 1060205080(6.931472e-01), 1107296256(3.200000e+01) +; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x, +; R600-NEXT: ADD * T0.W, PS, -PV.W, +; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T2.X, PV.W, literal.x, +; R600-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; R600-NEXT: 1060205080(6.931472e-01), 8(1.121039e-44) +; R600-NEXT: LSHR * T3.X, PV.W, literal.x, ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; R600-NEXT: MUL_IEEE * T3.X, PS, literal.x, -; R600-NEXT: 1060205080(6.931472e-01), 0(0.000000e+00) ; ; CM-LABEL: s_log_v3f32: ; CM: ; %bb.0: -; CM-NEXT: ALU 22, @4, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T3.X -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X +; CM-NEXT: ALU 40, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T3.X +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2.X, T1.X ; CM-NEXT: CF_END ; CM-NEXT: ALU clause starting at 4: -; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, -; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: LSHR * T0.X, PV.W, literal.x, -; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; CM-NEXT: LOG_IEEE T0.X (MASKED), KC0[3].Z, -; CM-NEXT: LOG_IEEE T0.Y, KC0[3].Z, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[3].Z, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[3].Z, -; CM-NEXT: LOG_IEEE T0.X (MASKED), KC0[3].W, -; CM-NEXT: LOG_IEEE T0.Y (MASKED), KC0[3].W, -; CM-NEXT: LOG_IEEE T0.Z, KC0[3].W, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[3].W, -; CM-NEXT: MUL_IEEE T1.X, PV.Z, literal.x, -; CM-NEXT: MUL_IEEE * T2.Y, T0.Y, literal.x, -; CM-NEXT: 1060205080(6.931472e-01), 0(0.000000e+00) -; CM-NEXT: LOG_IEEE T0.X (MASKED), KC0[3].Y, -; CM-NEXT: LOG_IEEE T0.Y, KC0[3].Y, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[3].Y, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[3].Y, -; CM-NEXT: MUL_IEEE * T2.X, PV.Y, literal.x, +; CM-NEXT: SETGT * T0.W, literal.x, KC0[3].W, +; CM-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; CM-NEXT: CNDE T0.Y, PV.W, 1.0, literal.x, +; CM-NEXT: SETGT T0.Z, literal.y, KC0[3].Z, +; CM-NEXT: SETGT * T1.W, literal.y, KC0[3].Y, +; CM-NEXT: 1333788672(4.294967e+09), 8388608(1.175494e-38) +; CM-NEXT: CNDE T0.X, PV.W, 0.0, literal.x, +; CM-NEXT: CNDE T1.Y, PV.Z, 1.0, literal.y, +; CM-NEXT: CNDE T1.Z, T0.W, 0.0, literal.x, +; CM-NEXT: MUL_IEEE * T0.W, KC0[3].W, PV.Y, +; CM-NEXT: 1107296256(3.200000e+01), 1333788672(4.294967e+09) +; CM-NEXT: LOG_IEEE T0.X (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Y, T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: CNDE T1.X, T1.W, 1.0, literal.x, +; CM-NEXT: CNDE T2.Y, T0.Z, 0.0, literal.y, +; CM-NEXT: ADD T0.Z, PV.Y, -T1.Z, +; CM-NEXT: MUL_IEEE * T0.W, KC0[3].Z, T1.Y, +; CM-NEXT: 1333788672(4.294967e+09), 1107296256(3.200000e+01) +; CM-NEXT: LOG_IEEE T0.X (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Y, T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: MUL_IEEE T2.X, T0.Z, literal.x, +; CM-NEXT: ADD T0.Y, PV.Y, -T2.Y, +; CM-NEXT: ADD_INT T0.Z, KC0[2].Y, literal.y, +; CM-NEXT: MUL_IEEE * T0.W, KC0[3].Y, T1.X, +; CM-NEXT: 1060205080(6.931472e-01), 8(1.121039e-44) +; CM-NEXT: LOG_IEEE T0.X (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W, T0.W, +; CM-NEXT: LSHR T1.X, T0.Z, literal.x, +; CM-NEXT: MUL_IEEE T0.Y, T0.Y, literal.y, +; CM-NEXT: ADD * T0.W, PV.W, -T0.X, +; CM-NEXT: 2(2.802597e-45), 1060205080(6.931472e-01) +; CM-NEXT: MUL_IEEE * T0.X, PV.W, literal.x, ; CM-NEXT: 1060205080(6.931472e-01), 0(0.000000e+00) ; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) @@ -371,17 +727,40 @@ ; SI-SDAG: ; %bb.0: ; SI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd ; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x4f800000 +; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, 1.0, v4, vcc +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; SI-SDAG-NEXT: v_mul_f32_e32 v3, s7, v3 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v4, vcc +; SI-SDAG-NEXT: v_log_f32_e32 v3, v3 +; SI-SDAG-NEXT: v_mul_f32_e32 v6, s6, v6 +; SI-SDAG-NEXT: v_log_f32_e32 v6, v6 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; SI-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2 +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; SI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317218, v2 +; SI-SDAG-NEXT: v_sub_f32_e32 v2, v6, v5 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v4, vcc +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v4, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v6, s5, v6 +; SI-SDAG-NEXT: v_mul_f32_e32 v1, s4, v1 +; SI-SDAG-NEXT: v_log_f32_e32 v6, v6 +; SI-SDAG-NEXT: v_log_f32_e32 v4, v1 ; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000 ; SI-SDAG-NEXT: s_mov_b32 s2, -1 -; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; SI-SDAG-NEXT: v_log_f32_e32 v0, s7 -; SI-SDAG-NEXT: v_log_f32_e32 v1, s6 -; SI-SDAG-NEXT: v_log_f32_e32 v4, s5 -; SI-SDAG-NEXT: v_log_f32_e32 v5, s4 -; SI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317218, v0 -; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317218, v1 -; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v4 -; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v5 +; SI-SDAG-NEXT: v_sub_f32_e32 v1, v6, v5 +; SI-SDAG-NEXT: v_sub_f32_e32 v0, v4, v0 +; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2 +; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 +; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; SI-SDAG-NEXT: s_endpgm ; @@ -389,34 +768,83 @@ ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd ; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; SI-GISEL-NEXT: s_mov_b32 s2, -1 -; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 +; SI-GISEL-NEXT: s_mov_b32 s2, 0x800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x42000000 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; SI-GISEL-NEXT: v_log_f32_e32 v0, s4 -; SI-GISEL-NEXT: v_log_f32_e32 v1, s5 -; SI-GISEL-NEXT: v_log_f32_e32 v2, s6 -; SI-GISEL-NEXT: v_log_f32_e32 v3, s7 +; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v5, s5 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc +; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v5 +; SI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mul_f32_e32 v5, s5, v5 +; SI-GISEL-NEXT: v_log_f32_e32 v5, v5 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2 +; SI-GISEL-NEXT: v_sub_f32_e32 v1, v5, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v4, vcc +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s7, v2 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; SI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v5 +; SI-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2 +; SI-GISEL-NEXT: v_log_f32_e32 v5, v5 +; SI-GISEL-NEXT: v_log_f32_e32 v3, v2 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc ; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; SI-GISEL-NEXT: v_sub_f32_e32 v2, v5, v6 +; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 ; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2 ; SI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317218, v3 +; SI-GISEL-NEXT: s_mov_b32 s2, -1 +; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 ; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; SI-GISEL-NEXT: s_endpgm ; ; VI-SDAG-LABEL: s_log_v4f32: ; VI-SDAG: ; %bb.0: ; VI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 +; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; VI-SDAG-NEXT: v_log_f32_e32 v0, s7 -; VI-SDAG-NEXT: v_log_f32_e32 v1, s6 -; VI-SDAG-NEXT: v_log_f32_e32 v4, s5 -; VI-SDAG-NEXT: v_log_f32_e32 v5, s4 -; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317218, v0 -; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317218, v1 -; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v4 -; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v5 +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v2, vcc +; VI-SDAG-NEXT: v_mul_f32_e32 v4, s7, v4 +; VI-SDAG-NEXT: v_mul_f32_e32 v6, s6, v6 +; VI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; VI-SDAG-NEXT: v_log_f32_e32 v6, v6 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; VI-SDAG-NEXT: v_sub_f32_e32 v3, v4, v3 +; VI-SDAG-NEXT: v_sub_f32_e32 v4, v6, v5 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v2, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; VI-SDAG-NEXT: v_mul_f32_e32 v6, s5, v6 +; VI-SDAG-NEXT: v_mul_f32_e32 v1, s4, v1 +; VI-SDAG-NEXT: v_log_f32_e32 v6, v6 +; VI-SDAG-NEXT: v_log_f32_e32 v7, v1 +; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317218, v4 +; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317218, v3 +; VI-SDAG-NEXT: v_sub_f32_e32 v1, v6, v5 +; VI-SDAG-NEXT: v_sub_f32_e32 v0, v7, v0 ; VI-SDAG-NEXT: v_mov_b32_e32 v5, s1 +; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 +; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; VI-SDAG-NEXT: v_mov_b32_e32 v4, s0 ; VI-SDAG-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; VI-SDAG-NEXT: s_endpgm @@ -425,13 +853,39 @@ ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-GISEL-NEXT: s_mov_b32 s2, 0x800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x42000000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; VI-GISEL-NEXT: v_log_f32_e32 v0, s4 -; VI-GISEL-NEXT: v_log_f32_e32 v1, s5 -; VI-GISEL-NEXT: v_log_f32_e32 v2, s6 -; VI-GISEL-NEXT: v_log_f32_e32 v3, s7 -; VI-GISEL-NEXT: v_mov_b32_e32 v5, s1 +; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v5, s5 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc +; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v5 +; VI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mul_f32_e32 v5, s5, v5 +; VI-GISEL-NEXT: v_log_f32_e32 v5, v5 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2 +; VI-GISEL-NEXT: v_sub_f32_e32 v1, v5, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v4, vcc +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s7, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; VI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v5 +; VI-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2 +; VI-GISEL-NEXT: v_log_f32_e32 v5, v5 +; VI-GISEL-NEXT: v_log_f32_e32 v3, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc ; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; VI-GISEL-NEXT: v_sub_f32_e32 v2, v5, v6 +; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 +; VI-GISEL-NEXT: v_mov_b32_e32 v5, s1 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2 ; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317218, v3 @@ -443,89 +897,189 @@ ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX900-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0x4f800000 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-SDAG-NEXT: v_log_f32_e32 v0, s7 -; GFX900-SDAG-NEXT: v_log_f32_e32 v1, s6 -; GFX900-SDAG-NEXT: v_log_f32_e32 v5, s5 -; GFX900-SDAG-NEXT: v_log_f32_e32 v6, s4 -; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317218, v0 -; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317218, v1 -; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v5 -; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v6 -; GFX900-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, 1.0, v4, vcc +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, s7, v3 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v4, vcc +; GFX900-SDAG-NEXT: v_log_f32_e32 v3, v3 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, s6, v6 +; GFX900-SDAG-NEXT: v_log_f32_e32 v6, v6 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2 +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317218, v2 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v6, v5 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v4, vcc +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v4, vcc +; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, s5, v6 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, s4, v1 +; GFX900-SDAG-NEXT: v_log_f32_e32 v6, v6 +; GFX900-SDAG-NEXT: v_log_f32_e32 v4, v1 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v6, v5 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v4, v0 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GFX900-SDAG-NEXT: global_store_dwordx4 v7, v[0:3], s[2:3] ; GFX900-SDAG-NEXT: s_endpgm ; ; GFX900-GISEL-LABEL: s_log_v4f32: ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX900-GISEL-NEXT: s_mov_b32 s0, 0x800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x42000000 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s4 -; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s5 -; GFX900-GISEL-NEXT: v_log_f32_e32 v2, s6 -; GFX900-GISEL-NEXT: v_log_f32_e32 v3, s7 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, s5 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v5 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s5, v5 +; GFX900-GISEL-NEXT: v_log_f32_e32 v5, v5 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v5, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v4, vcc +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s7, v2 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s6, v5 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2 +; GFX900-GISEL-NEXT: v_log_f32_e32 v5, v5 +; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v2 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v5, v6 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317218, v3 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0 ; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX900-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log_v4f32: ; R600: ; %bb.0: -; R600-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[] +; R600-NEXT: ALU 38, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 ; R600-NEXT: CF_END ; R600-NEXT: PAD ; R600-NEXT: ALU clause starting at 4: -; R600-NEXT: LOG_IEEE * T0.X, KC0[4].X, -; R600-NEXT: MUL_IEEE T0.W, PS, literal.x, -; R600-NEXT: LOG_IEEE * T0.X, KC0[3].W, +; R600-NEXT: SETGT T0.W, literal.x, KC0[4].X, +; R600-NEXT: SETGT * T1.W, literal.x, KC0[3].W, +; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; R600-NEXT: CNDE * T2.W, PV.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T0.Z, KC0[4].X, PV.W, +; R600-NEXT: SETGT T2.W, literal.x, KC0[3].Z, +; R600-NEXT: CNDE * T3.W, T1.W, 1.0, literal.y, +; R600-NEXT: 8388608(1.175494e-38), 1333788672(4.294967e+09) +; R600-NEXT: MUL_IEEE T0.X, KC0[3].W, PS, +; R600-NEXT: SETGT T0.Y, literal.x, KC0[3].Y, +; R600-NEXT: CNDE T1.Z, T0.W, 0.0, literal.y, +; R600-NEXT: CNDE T0.W, PV.W, 1.0, literal.z, +; R600-NEXT: LOG_IEEE * T0.Z, PV.Z, +; R600-NEXT: 8388608(1.175494e-38), 1107296256(3.200000e+01) +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T1.X, KC0[3].Z, PV.W, +; R600-NEXT: ADD T1.Y, PS, -PV.Z, +; R600-NEXT: CNDE T0.Z, T1.W, 0.0, literal.x, +; R600-NEXT: CNDE T0.W, PV.Y, 1.0, literal.y, +; R600-NEXT: LOG_IEEE * T0.X, PV.X, +; R600-NEXT: 1107296256(3.200000e+01), 1333788672(4.294967e+09) +; R600-NEXT: MUL_IEEE T2.X, KC0[3].Y, PV.W, +; R600-NEXT: CNDE T2.Y, T2.W, 0.0, literal.x, +; R600-NEXT: ADD T0.Z, PS, -PV.Z, +; R600-NEXT: MUL_IEEE T0.W, PV.Y, literal.y, +; R600-NEXT: LOG_IEEE * T0.X, PV.X, +; R600-NEXT: 1107296256(3.200000e+01), 1060205080(6.931472e-01) +; R600-NEXT: CNDE T1.Y, T0.Y, 0.0, literal.x, +; R600-NEXT: MUL_IEEE T0.Z, PV.Z, literal.y, +; R600-NEXT: ADD T1.W, PS, -PV.Y, +; R600-NEXT: LOG_IEEE * T0.X, PV.X, +; R600-NEXT: 1107296256(3.200000e+01), 1060205080(6.931472e-01) +; R600-NEXT: MUL_IEEE T0.Y, PV.W, literal.x, +; R600-NEXT: ADD * T1.W, PS, -PV.Y, ; R600-NEXT: 1060205080(6.931472e-01), 0(0.000000e+00) -; R600-NEXT: MUL_IEEE T0.Z, PS, literal.x, -; R600-NEXT: LOG_IEEE * T0.X, KC0[3].Z, -; R600-NEXT: 1060205080(6.931472e-01), 0(0.000000e+00) -; R600-NEXT: MUL_IEEE T0.Y, PS, literal.x, -; R600-NEXT: LOG_IEEE * T0.X, KC0[3].Y, -; R600-NEXT: 1060205080(6.931472e-01), 0(0.000000e+00) -; R600-NEXT: MUL_IEEE T0.X, PS, literal.x, +; R600-NEXT: MUL_IEEE T0.X, PV.W, literal.x, ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, ; R600-NEXT: 1060205080(6.931472e-01), 2(2.802597e-45) ; ; CM-LABEL: s_log_v4f32: ; CM: ; %bb.0: -; CM-NEXT: ALU 25, @4, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X +; CM-NEXT: ALU 50, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T0.X ; CM-NEXT: CF_END ; CM-NEXT: PAD ; CM-NEXT: ALU clause starting at 4: -; CM-NEXT: LOG_IEEE T0.X, KC0[4].X, -; CM-NEXT: LOG_IEEE T0.Y (MASKED), KC0[4].X, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[4].X, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[4].X, -; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.x, -; CM-NEXT: 1060205080(6.931472e-01), 0(0.000000e+00) -; CM-NEXT: LOG_IEEE T0.X, KC0[3].W, -; CM-NEXT: LOG_IEEE T0.Y (MASKED), KC0[3].W, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[3].W, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[3].W, -; CM-NEXT: MUL_IEEE * T0.Z, PV.X, literal.x, -; CM-NEXT: 1060205080(6.931472e-01), 0(0.000000e+00) -; CM-NEXT: LOG_IEEE T0.X, KC0[3].Z, -; CM-NEXT: LOG_IEEE T0.Y (MASKED), KC0[3].Z, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[3].Z, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[3].Z, -; CM-NEXT: MUL_IEEE * T0.Y, PV.X, literal.x, +; CM-NEXT: SETGT T0.Z, literal.x, KC0[4].X, +; CM-NEXT: SETGT * T0.W, literal.x, KC0[3].Y, +; CM-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; CM-NEXT: CNDE T0.Y, PV.W, 1.0, literal.x, +; CM-NEXT: CNDE T1.Z, PV.Z, 1.0, literal.x, +; CM-NEXT: SETGT * T1.W, literal.y, KC0[3].W, +; CM-NEXT: 1333788672(4.294967e+09), 8388608(1.175494e-38) +; CM-NEXT: CNDE T0.X, PV.W, 1.0, literal.x, +; CM-NEXT: SETGT T1.Y, literal.y, KC0[3].Z, +; CM-NEXT: CNDE T0.Z, T0.Z, 0.0, literal.z, +; CM-NEXT: MUL_IEEE * T2.W, KC0[4].X, PV.Z, +; CM-NEXT: 1333788672(4.294967e+09), 8388608(1.175494e-38) +; CM-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; CM-NEXT: LOG_IEEE T1.X, T2.W, +; CM-NEXT: LOG_IEEE T1.Y (MASKED), T2.W, +; CM-NEXT: LOG_IEEE T1.Z (MASKED), T2.W, +; CM-NEXT: LOG_IEEE * T1.W (MASKED), T2.W, +; CM-NEXT: ADD T1.X, PV.X, -T0.Z, +; CM-NEXT: CNDE T2.Y, T1.Y, 1.0, literal.x, +; CM-NEXT: CNDE T0.Z, T1.W, 0.0, literal.y, +; CM-NEXT: MUL_IEEE * T1.W, KC0[3].W, T0.X, +; CM-NEXT: 1333788672(4.294967e+09), 1107296256(3.200000e+01) +; CM-NEXT: LOG_IEEE T0.X, T1.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T1.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T1.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T1.W, +; CM-NEXT: ADD T0.X, PV.X, -T0.Z, +; CM-NEXT: CNDE T1.Y, T1.Y, 0.0, literal.x, +; CM-NEXT: MUL_IEEE T0.Z, KC0[3].Z, T2.Y, +; CM-NEXT: MUL_IEEE * T1.W, T1.X, literal.y, +; CM-NEXT: 1107296256(3.200000e+01), 1060205080(6.931472e-01) +; CM-NEXT: LOG_IEEE T0.X (MASKED), T0.Z, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.Z, +; CM-NEXT: LOG_IEEE T0.Z, T0.Z, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.Z, +; CM-NEXT: CNDE T1.X, T0.W, 0.0, literal.x, +; CM-NEXT: ADD T1.Y, PV.Z, -T1.Y, +; CM-NEXT: MUL_IEEE T1.Z, T0.X, literal.y, +; CM-NEXT: MUL_IEEE * T0.W, KC0[3].Y, T0.Y, BS:VEC_021/SCL_122 +; CM-NEXT: 1107296256(3.200000e+01), 1060205080(6.931472e-01) +; CM-NEXT: LOG_IEEE T0.X, T0.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: MUL_IEEE T1.Y, T1.Y, literal.x, +; CM-NEXT: ADD * T0.W, PV.X, -T1.X, ; CM-NEXT: 1060205080(6.931472e-01), 0(0.000000e+00) -; CM-NEXT: LOG_IEEE T0.X, KC0[3].Y, -; CM-NEXT: LOG_IEEE T0.Y (MASKED), KC0[3].Y, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[3].Y, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[3].Y, -; CM-NEXT: MUL_IEEE * T0.X, PV.X, literal.x, +; CM-NEXT: MUL_IEEE * T1.X, PV.W, literal.x, ; CM-NEXT: 1060205080(6.931472e-01), 0(0.000000e+00) -; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) %result = call <4 x float> @llvm.log.v4f32(<4 x float> %in) store <4 x float> %result, ptr addrspace(1) %out @@ -533,12 +1087,35 @@ } define float @v_log_f32(float %in) { -; GCN-LABEL: v_log_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log_f32: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log_f32: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log_f32: ; R600: ; %bb.0: @@ -554,12 +1131,35 @@ } define float @v_log_fabs_f32(float %in) { -; GCN-LABEL: v_log_fabs_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e64 v0, |v0| -; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log_fabs_f32: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log_fabs_f32: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log_fabs_f32: ; R600: ; %bb.0: @@ -576,12 +1176,35 @@ } define float @v_log_fneg_fabs_f32(float %in) { -; GCN-LABEL: v_log_fneg_fabs_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e64 v0, -|v0| -; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log_fneg_fabs_f32: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x80800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e64 v0, -|v0|, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log_fneg_fabs_f32: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e64 v0, -|v0|, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log_fneg_fabs_f32: ; R600: ; %bb.0: @@ -599,12 +1222,35 @@ } define float @v_log_fneg_f32(float %in) { -; GCN-LABEL: v_log_fneg_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e64 v0, -v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log_fneg_f32: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x80800000 +; GCN-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e64 v0, -v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log_fneg_f32: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e64 v0, -v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log_fneg_f32: ; R600: ; %bb.0: @@ -621,12 +1267,27 @@ } define float @v_log_f32_fast(float %in) { -; GCN-LABEL: v_log_f32_fast: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log_f32_fast: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log_f32_fast: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log_f32_fast: ; R600: ; %bb.0: @@ -684,12 +1345,35 @@ } define float @v_log_f32_ninf(float %in) { -; GCN-LABEL: v_log_f32_ninf: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log_f32_ninf: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log_f32_ninf: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log_f32_ninf: ; R600: ; %bb.0: @@ -705,12 +1389,27 @@ } define float @v_log_f32_afn(float %in) { -; GCN-LABEL: v_log_f32_afn: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log_f32_afn: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log_f32_afn: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log_f32_afn: ; R600: ; %bb.0: @@ -747,12 +1446,27 @@ } define float @v_log_f32_afn_dynamic(float %in) #1 { -; GCN-LABEL: v_log_f32_afn_dynamic: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log_f32_afn_dynamic: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log_f32_afn_dynamic: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log_f32_afn_dynamic: ; R600: ; %bb.0: @@ -768,12 +1482,27 @@ } define float @v_fabs_log_f32_afn(float %in) { -; GCN-LABEL: v_fabs_log_f32_afn: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e64 v0, |v0| -; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_fabs_log_f32_afn: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_fabs_log_f32_afn: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_log_f32_e64 v0, |v0| +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_fabs_log_f32_afn: ; R600: ; %bb.0: @@ -811,12 +1540,35 @@ } define float @v_log_f32_nnan(float %in) { -; GCN-LABEL: v_log_f32_nnan: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log_f32_nnan: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log_f32_nnan: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log_f32_nnan: ; R600: ; %bb.0: @@ -853,12 +1605,35 @@ } define float @v_log_f32_nnan_dynamic(float %in) #1 { -; GCN-LABEL: v_log_f32_nnan_dynamic: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log_f32_nnan_dynamic: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log_f32_nnan_dynamic: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log_f32_nnan_dynamic: ; R600: ; %bb.0: @@ -895,12 +1670,35 @@ } define float @v_log_f32_ninf_dynamic(float %in) #1 { -; GCN-LABEL: v_log_f32_ninf_dynamic: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log_f32_ninf_dynamic: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log_f32_ninf_dynamic: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log_f32_ninf_dynamic: ; R600: ; %bb.0: @@ -916,12 +1714,35 @@ } define float @v_log_f32_nnan_ninf(float %in) { -; GCN-LABEL: v_log_f32_nnan_ninf: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log_f32_nnan_ninf: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log_f32_nnan_ninf: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log_f32_nnan_ninf: ; R600: ; %bb.0: @@ -958,12 +1779,35 @@ } define float @v_log_f32_nnan_ninf_dynamic(float %in) #1 { -; GCN-LABEL: v_log_f32_nnan_ninf_dynamic: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log_f32_nnan_ninf_dynamic: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log_f32_nnan_ninf_dynamic: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log_f32_nnan_ninf_dynamic: ; R600: ; %bb.0: @@ -1000,12 +1844,35 @@ } define float @v_log_f32_dynamic_mode(float %in) #1 { -; GCN-LABEL: v_log_f32_dynamic_mode: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log_f32_dynamic_mode: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log_f32_dynamic_mode: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log_f32_dynamic_mode: ; R600: ; %bb.0: @@ -1021,12 +1888,28 @@ } define float @v_log_f32_undef() { -; GCN-LABEL: v_log_f32_undef: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, s4 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log_f32_undef: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: v_log_f32_e32 v0, s4 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log_f32_undef: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GCN-GISEL-NEXT: v_mul_f32_e32 v1, s4, v1 +; GCN-GISEL-NEXT: v_mul_f32_e64 v2, s4, 1.0 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log_f32_undef: ; R600: ; %bb.0: @@ -1046,14 +1929,24 @@ ; GCN-SDAG: ; %bb.0: ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-SDAG-NEXT: v_log_f32_e32 v0, 0 +; GCN-SDAG-NEXT: v_add_f32_e32 v0, 0xc2000000, v0 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; GCN-GISEL-LABEL: v_log_f32_0: ; GCN-GISEL: ; %bb.0: ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0x3f317218 -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0xff800000, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e64 v2, 0, 1.0 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, 0, v0 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log_f32_0: @@ -1099,8 +1992,16 @@ ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000 ; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: v_log_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; @@ -1155,7 +2056,15 @@ ; GCN-SDAG-LABEL: v_log_f32_from_fpext_bf16: ; GCN-SDAG: ; %bb.0: ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 ; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] ; @@ -1851,3 +2760,5 @@ attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" } attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" } attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; SI: {{.*}} Index: llvm/test/CodeGen/AMDGPU/llvm.log10.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/llvm.log10.ll +++ llvm/test/CodeGen/AMDGPU/llvm.log10.ll @@ -10,76 +10,164 @@ ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) { -; SI-LABEL: s_log10_f32: -; SI: ; %bb.0: -; SI-NEXT: s_load_dword s2, s[0:1], 0xb -; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; SI-NEXT: s_mov_b32 s3, 0xf000 -; SI-NEXT: s_waitcnt lgkmcnt(0) -; SI-NEXT: v_log_f32_e32 v0, s2 -; SI-NEXT: s_mov_b32 s2, -1 -; SI-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 -; SI-NEXT: s_endpgm -; -; VI-LABEL: s_log10_f32: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_log_f32_e32 v0, s2 -; VI-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: flat_store_dword v[0:1], v2 -; VI-NEXT: s_endpgm +; SI-SDAG-LABEL: s_log10_f32: +; SI-SDAG: ; %bb.0: +; SI-SDAG-NEXT: s_load_dword s2, s[0:1], 0xb +; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000 +; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; SI-SDAG-NEXT: v_log_f32_e32 v1, v1 +; SI-SDAG-NEXT: s_mov_b32 s2, -1 +; SI-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0 +; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; SI-SDAG-NEXT: s_endpgm +; +; SI-GISEL-LABEL: s_log10_f32: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_load_dword s2, s[0:1], 0xb +; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 +; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; SI-GISEL-NEXT: v_mul_f32_e32 v0, s2, v0 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: s_mov_b32 s2, -1 +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; SI-GISEL-NEXT: s_endpgm +; +; VI-SDAG-LABEL: s_log10_f32: +; VI-SDAG: ; %bb.0: +; VI-SDAG-NEXT: s_load_dword s2, s[0:1], 0x2c +; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; VI-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; VI-SDAG-NEXT: v_log_f32_e32 v1, v1 +; VI-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0 +; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v0 +; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; VI-SDAG-NEXT: flat_store_dword v[0:1], v2 +; VI-SDAG-NEXT: s_endpgm +; +; VI-GISEL-LABEL: s_log10_f32: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_load_dword s2, s[0:1], 0x2c +; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; VI-GISEL-NEXT: v_mul_f32_e32 v0, s2, v0 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; VI-GISEL-NEXT: flat_store_dword v[0:1], v2 +; VI-GISEL-NEXT: s_endpgm ; ; GFX900-SDAG-LABEL: s_log10_f32: ; GFX900-SDAG: ; %bb.0: -; GFX900-SDAG-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX900-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX900-SDAG-NEXT: s_load_dword s2, s[0:1], 0x2c +; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-SDAG-NEXT: v_log_f32_e32 v0, s4 +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; GFX900-SDAG-NEXT: v_log_f32_e32 v1, v1 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GFX900-SDAG-NEXT: global_store_dword v1, v0, s[2:3] +; GFX900-SDAG-NEXT: global_store_dword v2, v0, s[0:1] ; GFX900-SDAG-NEXT: s_endpgm ; ; GFX900-GISEL-LABEL: s_log10_f32: ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_load_dword s2, s[0:1], 0x2c -; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s2 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s2, v0 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0 ; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1] ; GFX900-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log10_f32: ; R600: ; %bb.0: -; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[] +; R600-NEXT: ALU 11, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 ; R600-NEXT: CF_END ; R600-NEXT: PAD ; R600-NEXT: ALU clause starting at 4: -; R600-NEXT: LOG_IEEE * T0.X, KC0[2].Z, -; R600-NEXT: MUL_IEEE T0.X, PS, literal.x, +; R600-NEXT: SETGT * T0.W, literal.x, KC0[2].Z, +; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; R600-NEXT: CNDE * T1.W, PV.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T1.W, KC0[2].Z, PV.W, +; R600-NEXT: CNDE * T0.W, T0.W, 0.0, literal.x, +; R600-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; R600-NEXT: LOG_IEEE * T0.X, PV.W, +; R600-NEXT: ADD * T0.W, PS, -T0.W, +; R600-NEXT: MUL_IEEE T0.X, PV.W, literal.x, ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, ; R600-NEXT: 1050288283(3.010300e-01), 2(2.802597e-45) ; ; CM-LABEL: s_log10_f32: ; CM: ; %bb.0: -; CM-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: ALU 15, @4, KC0[CB0:0-32], KC1[] ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X ; CM-NEXT: CF_END ; CM-NEXT: PAD ; CM-NEXT: ALU clause starting at 4: -; CM-NEXT: LOG_IEEE T0.X, KC0[2].Z, -; CM-NEXT: LOG_IEEE T0.Y (MASKED), KC0[2].Z, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[2].Z, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[2].Z, -; CM-NEXT: MUL_IEEE * T0.X, PV.X, literal.x, +; CM-NEXT: SETGT * T0.W, literal.x, KC0[2].Z, +; CM-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; CM-NEXT: CNDE * T1.W, PV.W, 1.0, literal.x, +; CM-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; CM-NEXT: CNDE T0.Z, T0.W, 0.0, literal.x, +; CM-NEXT: MUL_IEEE * T0.W, KC0[2].Z, PV.W, +; CM-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; CM-NEXT: LOG_IEEE T0.X, T0.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: ADD * T0.W, PV.X, -T0.Z, +; CM-NEXT: MUL_IEEE * T0.X, PV.W, literal.x, ; CM-NEXT: 1050288283(3.010300e-01), 0(0.000000e+00) ; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) @@ -94,40 +182,81 @@ ; SI-SDAG-LABEL: s_log10_v2f32: ; SI-SDAG: ; %bb.0: ; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000 -; SI-SDAG-NEXT: s_mov_b32 s6, -1 ; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; SI-SDAG-NEXT: v_log_f32_e32 v0, s3 -; SI-SDAG-NEXT: v_log_f32_e32 v2, s2 +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v4, s3, v4 +; SI-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; SI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; SI-SDAG-NEXT: v_log_f32_e32 v3, v1 +; SI-SDAG-NEXT: s_mov_b32 s6, -1 ; SI-SDAG-NEXT: s_mov_b32 s4, s0 +; SI-SDAG-NEXT: v_sub_f32_e32 v1, v4, v2 +; SI-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0 ; SI-SDAG-NEXT: s_mov_b32 s5, s1 -; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v0 -; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v2 +; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 +; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-SDAG-NEXT: s_endpgm ; ; SI-GISEL-LABEL: s_log10_v2f32: ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-GISEL-NEXT: s_mov_b32 s4, 0x800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x4f800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; SI-GISEL-NEXT: v_log_f32_e32 v0, s2 -; SI-GISEL-NEXT: v_log_f32_e32 v1, s3 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2 +; SI-GISEL-NEXT: v_mov_b32_e32 v4, s3 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc +; SI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2 +; SI-GISEL-NEXT: v_mul_f32_e32 v0, s3, v0 +; SI-GISEL-NEXT: v_log_f32_e32 v2, v2 +; SI-GISEL-NEXT: v_log_f32_e32 v4, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; SI-GISEL-NEXT: s_mov_b32 s2, -1 -; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v2, v3 +; SI-GISEL-NEXT: v_sub_f32_e32 v1, v4, v1 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 +; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 ; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-GISEL-NEXT: s_endpgm ; ; VI-SDAG-LABEL: s_log10_v2f32: ; VI-SDAG: ; %bb.0: ; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; VI-SDAG-NEXT: v_log_f32_e32 v0, s3 -; VI-SDAG-NEXT: v_log_f32_e32 v2, s2 -; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v0 -; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v2 +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; VI-SDAG-NEXT: v_mul_f32_e32 v4, s3, v4 +; VI-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; VI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; VI-SDAG-NEXT: v_log_f32_e32 v2, v1 +; VI-SDAG-NEXT: v_sub_f32_e32 v1, v4, v3 +; VI-SDAG-NEXT: v_sub_f32_e32 v0, v2, v0 ; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1 +; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 +; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0 ; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-SDAG-NEXT: s_endpgm @@ -135,73 +264,145 @@ ; VI-GISEL-LABEL: s_log10_v2f32: ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; VI-GISEL-NEXT: s_mov_b32 s4, 0x800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x4f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; VI-GISEL-NEXT: v_log_f32_e32 v0, s2 -; VI-GISEL-NEXT: v_log_f32_e32 v1, s3 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, s3 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v4 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc +; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2 +; VI-GISEL-NEXT: v_mul_f32_e32 v0, s3, v0 +; VI-GISEL-NEXT: v_log_f32_e32 v2, v2 +; VI-GISEL-NEXT: v_log_f32_e32 v4, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v2, v3 +; VI-GISEL-NEXT: v_sub_f32_e32 v1, v4, v1 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0 ; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0 ; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-GISEL-NEXT: s_endpgm ; ; GFX900-SDAG-LABEL: s_log10_v2f32: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-SDAG-NEXT: v_log_f32_e32 v0, s3 -; GFX900-SDAG-NEXT: v_log_f32_e32 v2, s2 -; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v0 -; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v2 -; GFX900-SDAG-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1] +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GFX900-SDAG-NEXT: v_mul_f32_e32 v4, s3, v4 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; GFX900-SDAG-NEXT: v_log_f32_e32 v4, v4 +; GFX900-SDAG-NEXT: v_log_f32_e32 v2, v1 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v4, v3 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v2, v0 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GFX900-SDAG-NEXT: global_store_dwordx2 v5, v[0:1], s[0:1] ; GFX900-SDAG-NEXT: s_endpgm ; ; GFX900-GISEL-LABEL: s_log10_v2f32: ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x4f800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s2 -; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s3 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, s3 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v4 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc +; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s3, v0 +; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v2 +; GFX900-GISEL-NEXT: v_log_f32_e32 v4, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v2, v3 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v4, v1 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX900-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log10_v2f32: ; R600: ; %bb.0: -; R600-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[] +; R600-NEXT: ALU 21, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; R600-NEXT: CF_END ; R600-NEXT: PAD ; R600-NEXT: ALU clause starting at 4: -; R600-NEXT: LOG_IEEE * T0.X, KC0[3].X, -; R600-NEXT: MUL_IEEE T0.Y, PS, literal.x, -; R600-NEXT: LOG_IEEE * T0.X, KC0[2].W, +; R600-NEXT: SETGT T0.W, literal.x, KC0[3].X, +; R600-NEXT: SETGT * T1.W, literal.x, KC0[2].W, +; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; R600-NEXT: CNDE * T2.W, PV.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T2.W, KC0[3].X, PV.W, +; R600-NEXT: CNDE * T3.W, T1.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T0.Z, KC0[2].W, PS, +; R600-NEXT: CNDE T0.W, T0.W, 0.0, literal.x, +; R600-NEXT: LOG_IEEE * T0.X, PV.W, +; R600-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; R600-NEXT: CNDE T1.Z, T1.W, 0.0, literal.x, +; R600-NEXT: ADD T0.W, PS, -PV.W, +; R600-NEXT: LOG_IEEE * T0.X, PV.Z, +; R600-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T0.Y, PV.W, literal.x, +; R600-NEXT: ADD * T0.W, PS, -PV.Z, ; R600-NEXT: 1050288283(3.010300e-01), 0(0.000000e+00) -; R600-NEXT: MUL_IEEE T0.X, PS, literal.x, +; R600-NEXT: MUL_IEEE T0.X, PV.W, literal.x, ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, ; R600-NEXT: 1050288283(3.010300e-01), 2(2.802597e-45) ; ; CM-LABEL: s_log10_v2f32: ; CM: ; %bb.0: -; CM-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: ALU 27, @4, KC0[CB0:0-32], KC1[] ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X ; CM-NEXT: CF_END ; CM-NEXT: PAD ; CM-NEXT: ALU clause starting at 4: -; CM-NEXT: LOG_IEEE T0.X, KC0[3].X, -; CM-NEXT: LOG_IEEE T0.Y (MASKED), KC0[3].X, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[3].X, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[3].X, -; CM-NEXT: MUL_IEEE * T0.Y, PV.X, literal.x, +; CM-NEXT: SETGT * T0.W, literal.x, KC0[3].X, +; CM-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; CM-NEXT: CNDE T0.Z, PV.W, 1.0, literal.x, +; CM-NEXT: SETGT * T1.W, literal.y, KC0[2].W, +; CM-NEXT: 1333788672(4.294967e+09), 8388608(1.175494e-38) +; CM-NEXT: CNDE T0.Y, PV.W, 1.0, literal.x, +; CM-NEXT: CNDE T1.Z, T0.W, 0.0, literal.y, +; CM-NEXT: MUL_IEEE * T0.W, KC0[3].X, PV.Z, +; CM-NEXT: 1333788672(4.294967e+09), 1107296256(3.200000e+01) +; CM-NEXT: LOG_IEEE T0.X, T0.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: CNDE T1.Y, T1.W, 0.0, literal.x, +; CM-NEXT: ADD T0.Z, PV.X, -T1.Z, +; CM-NEXT: MUL_IEEE * T0.W, KC0[2].W, T0.Y, +; CM-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; CM-NEXT: LOG_IEEE T0.X, T0.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: MUL_IEEE T0.Y, T0.Z, literal.x, +; CM-NEXT: ADD * T0.W, PV.X, -T1.Y, ; CM-NEXT: 1050288283(3.010300e-01), 0(0.000000e+00) -; CM-NEXT: LOG_IEEE T0.X, KC0[2].W, -; CM-NEXT: LOG_IEEE T0.Y (MASKED), KC0[2].W, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[2].W, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[2].W, -; CM-NEXT: MUL_IEEE * T0.X, PV.X, literal.x, +; CM-NEXT: MUL_IEEE * T0.X, PV.W, literal.x, ; CM-NEXT: 1050288283(3.010300e-01), 0(0.000000e+00) ; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) @@ -214,16 +415,34 @@ ; SI-SDAG-LABEL: s_log10_v3f32: ; SI-SDAG: ; %bb.0: ; SI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd +; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 ; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v4, s5, v4 +; SI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v5, 1.0, v2, vcc +; SI-SDAG-NEXT: v_sub_f32_e32 v3, v4, v3 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v0, s6, v0 +; SI-SDAG-NEXT: v_mul_f32_e32 v5, s4, v5 +; SI-SDAG-NEXT: v_log_f32_e32 v2, v0 +; SI-SDAG-NEXT: v_log_f32_e32 v5, v5 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc ; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000 +; SI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v6 ; SI-SDAG-NEXT: s_mov_b32 s2, -1 -; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; SI-SDAG-NEXT: v_log_f32_e32 v0, s5 -; SI-SDAG-NEXT: v_log_f32_e32 v2, s4 -; SI-SDAG-NEXT: v_log_f32_e32 v3, s6 -; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v0 -; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v2 -; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v3 +; SI-SDAG-NEXT: v_sub_f32_e32 v0, v5, v4 +; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2 +; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v3 +; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-SDAG-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8 ; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-SDAG-NEXT: s_endpgm @@ -232,14 +451,35 @@ ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd ; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; SI-GISEL-NEXT: s_mov_b32 s2, -1 -; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 +; SI-GISEL-NEXT: s_mov_b32 s2, 0x800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; SI-GISEL-NEXT: v_log_f32_e32 v0, s4 -; SI-GISEL-NEXT: v_log_f32_e32 v1, s5 -; SI-GISEL-NEXT: v_log_f32_e32 v2, s6 +; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; SI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 +; SI-GISEL-NEXT: v_mov_b32_e32 v4, s5 +; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v1, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2 +; SI-GISEL-NEXT: v_mul_f32_e32 v4, s5, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; SI-GISEL-NEXT: v_log_f32_e32 v4, v4 +; SI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v2, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v1, v4, v5 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 +; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 +; SI-GISEL-NEXT: s_mov_b32 s2, -1 ; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2 ; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-GISEL-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8 @@ -248,15 +488,33 @@ ; VI-SDAG-LABEL: s_log10_v3f32: ; VI-SDAG: ; %bb.0: ; VI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 +; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 ; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; VI-SDAG-NEXT: v_log_f32_e32 v0, s6 -; VI-SDAG-NEXT: v_log_f32_e32 v3, s4 -; VI-SDAG-NEXT: v_log_f32_e32 v1, s5 -; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v0 -; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v3 +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc +; VI-SDAG-NEXT: v_mul_f32_e32 v4, s6, v4 +; VI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; VI-SDAG-NEXT: v_sub_f32_e32 v3, v4, v3 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; VI-SDAG-NEXT: v_mul_f32_e32 v4, s5, v4 +; VI-SDAG-NEXT: v_mul_f32_e32 v1, s4, v1 +; VI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; VI-SDAG-NEXT: v_log_f32_e32 v6, v1 +; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v3 +; VI-SDAG-NEXT: v_sub_f32_e32 v1, v4, v5 +; VI-SDAG-NEXT: v_sub_f32_e32 v0, v6, v0 ; VI-SDAG-NEXT: v_mov_b32_e32 v4, s1 ; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 +; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; VI-SDAG-NEXT: v_mov_b32_e32 v3, s0 ; VI-SDAG-NEXT: flat_store_dwordx3 v[3:4], v[0:2] ; VI-SDAG-NEXT: s_endpgm @@ -265,12 +523,33 @@ ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-GISEL-NEXT: s_mov_b32 s2, 0x800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; VI-GISEL-NEXT: v_log_f32_e32 v0, s4 -; VI-GISEL-NEXT: v_log_f32_e32 v1, s5 -; VI-GISEL-NEXT: v_log_f32_e32 v2, s6 -; VI-GISEL-NEXT: v_mov_b32_e32 v4, s1 +; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; VI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5 +; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v4 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v1, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; VI-GISEL-NEXT: v_mul_f32_e32 v4, s5, v4 +; VI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v4, v4 +; VI-GISEL-NEXT: v_log_f32_e32 v2, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc ; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; VI-GISEL-NEXT: v_sub_f32_e32 v1, v4, v5 +; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, s1 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, s0 @@ -280,82 +559,159 @@ ; GFX900-SDAG-LABEL: s_log10_v3f32: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 -; GFX900-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-SDAG-NEXT: v_log_f32_e32 v0, s6 -; GFX900-SDAG-NEXT: v_log_f32_e32 v1, s5 -; GFX900-SDAG-NEXT: v_log_f32_e32 v3, s4 -; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v0 +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc +; GFX900-SDAG-NEXT: v_mul_f32_e32 v4, s6, v4 +; GFX900-SDAG-NEXT: v_log_f32_e32 v4, v4 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v2, vcc +; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v4, v3 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, s5, v6 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, s4, v1 +; GFX900-SDAG-NEXT: v_log_f32_e32 v6, v6 +; GFX900-SDAG-NEXT: v_log_f32_e32 v7, v1 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v3 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v6, v4 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v7, v0 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 -; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v3 -; GFX900-SDAG-NEXT: global_store_dwordx3 v4, v[0:2], s[2:3] +; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GFX900-SDAG-NEXT: global_store_dwordx3 v5, v[0:2], s[0:1] ; GFX900-SDAG-NEXT: s_endpgm ; ; GFX900-GISEL-LABEL: s_log10_v3f32: ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0 -; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX900-GISEL-NEXT: s_mov_b32 s0, 0x800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s4 -; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s5 -; GFX900-GISEL-NEXT: v_log_f32_e32 v2, s6 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, s5 +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v4 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v1, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, s5, v4 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v4, v4 +; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v4, v5 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2 -; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1] +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0 +; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3] ; GFX900-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log10_v3f32: ; R600: ; %bb.0: -; R600-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[] -; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 0 +; R600-NEXT: ALU 33, @4, KC0[CB0:0-32], KC1[] +; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; R600-NEXT: CF_END ; R600-NEXT: ALU clause starting at 4: -; R600-NEXT: LOG_IEEE * T0.X, KC0[3].Z, -; R600-NEXT: MUL_IEEE T0.Y, PS, literal.x, -; R600-NEXT: LOG_IEEE * T0.X, KC0[3].Y, +; R600-NEXT: SETGT T0.W, literal.x, KC0[3].Z, +; R600-NEXT: SETGT * T1.W, literal.x, KC0[3].Y, +; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; R600-NEXT: CNDE * T2.W, PV.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T2.W, KC0[3].Z, PV.W, +; R600-NEXT: CNDE * T3.W, T1.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T0.Y, KC0[3].Y, PS, +; R600-NEXT: CNDE T0.Z, T0.W, 0.0, literal.x, +; R600-NEXT: SETGT T0.W, literal.y, KC0[3].W, +; R600-NEXT: LOG_IEEE * T0.X, PV.W, +; R600-NEXT: 1107296256(3.200000e+01), 8388608(1.175494e-38) +; R600-NEXT: CNDE T1.Y, T1.W, 0.0, literal.x, +; R600-NEXT: CNDE T1.Z, PV.W, 1.0, literal.y, +; R600-NEXT: ADD T1.W, PS, -PV.Z, +; R600-NEXT: LOG_IEEE * T0.X, PV.Y, +; R600-NEXT: 1107296256(3.200000e+01), 1333788672(4.294967e+09) +; R600-NEXT: MUL_IEEE T0.Y, PV.W, literal.x, +; R600-NEXT: MUL_IEEE T1.W, KC0[3].W, PV.Z, +; R600-NEXT: ADD * T2.W, PS, -PV.Y, ; R600-NEXT: 1050288283(3.010300e-01), 0(0.000000e+00) ; R600-NEXT: MUL_IEEE T0.X, PS, literal.x, -; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, -; R600-NEXT: 1050288283(3.010300e-01), 2(2.802597e-45) -; R600-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, -; R600-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; R600-NEXT: LSHR T2.X, PV.W, literal.x, -; R600-NEXT: LOG_IEEE * T0.Z, KC0[3].W, +; R600-NEXT: CNDE T0.W, T0.W, 0.0, literal.y, +; R600-NEXT: LOG_IEEE * T0.Z, PV.W, +; R600-NEXT: 1050288283(3.010300e-01), 1107296256(3.200000e+01) +; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x, +; R600-NEXT: ADD * T0.W, PS, -PV.W, +; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T2.X, PV.W, literal.x, +; R600-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, +; R600-NEXT: 1050288283(3.010300e-01), 8(1.121039e-44) +; R600-NEXT: LSHR * T3.X, PV.W, literal.x, ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; R600-NEXT: MUL_IEEE * T3.X, PS, literal.x, -; R600-NEXT: 1050288283(3.010300e-01), 0(0.000000e+00) ; ; CM-LABEL: s_log10_v3f32: ; CM: ; %bb.0: -; CM-NEXT: ALU 22, @4, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T3.X -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X +; CM-NEXT: ALU 40, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T3.X +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2.X, T1.X ; CM-NEXT: CF_END ; CM-NEXT: ALU clause starting at 4: -; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, -; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: LSHR * T0.X, PV.W, literal.x, -; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; CM-NEXT: LOG_IEEE T0.X (MASKED), KC0[3].Z, -; CM-NEXT: LOG_IEEE T0.Y, KC0[3].Z, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[3].Z, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[3].Z, -; CM-NEXT: LOG_IEEE T0.X (MASKED), KC0[3].W, -; CM-NEXT: LOG_IEEE T0.Y (MASKED), KC0[3].W, -; CM-NEXT: LOG_IEEE T0.Z, KC0[3].W, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[3].W, -; CM-NEXT: MUL_IEEE T1.X, PV.Z, literal.x, -; CM-NEXT: MUL_IEEE * T2.Y, T0.Y, literal.x, -; CM-NEXT: 1050288283(3.010300e-01), 0(0.000000e+00) -; CM-NEXT: LOG_IEEE T0.X (MASKED), KC0[3].Y, -; CM-NEXT: LOG_IEEE T0.Y, KC0[3].Y, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[3].Y, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[3].Y, -; CM-NEXT: MUL_IEEE * T2.X, PV.Y, literal.x, +; CM-NEXT: SETGT * T0.W, literal.x, KC0[3].W, +; CM-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; CM-NEXT: CNDE T0.Y, PV.W, 1.0, literal.x, +; CM-NEXT: SETGT T0.Z, literal.y, KC0[3].Z, +; CM-NEXT: SETGT * T1.W, literal.y, KC0[3].Y, +; CM-NEXT: 1333788672(4.294967e+09), 8388608(1.175494e-38) +; CM-NEXT: CNDE T0.X, PV.W, 0.0, literal.x, +; CM-NEXT: CNDE T1.Y, PV.Z, 1.0, literal.y, +; CM-NEXT: CNDE T1.Z, T0.W, 0.0, literal.x, +; CM-NEXT: MUL_IEEE * T0.W, KC0[3].W, PV.Y, +; CM-NEXT: 1107296256(3.200000e+01), 1333788672(4.294967e+09) +; CM-NEXT: LOG_IEEE T0.X (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Y, T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: CNDE T1.X, T1.W, 1.0, literal.x, +; CM-NEXT: CNDE T2.Y, T0.Z, 0.0, literal.y, +; CM-NEXT: ADD T0.Z, PV.Y, -T1.Z, +; CM-NEXT: MUL_IEEE * T0.W, KC0[3].Z, T1.Y, +; CM-NEXT: 1333788672(4.294967e+09), 1107296256(3.200000e+01) +; CM-NEXT: LOG_IEEE T0.X (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Y, T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: MUL_IEEE T2.X, T0.Z, literal.x, +; CM-NEXT: ADD T0.Y, PV.Y, -T2.Y, +; CM-NEXT: ADD_INT T0.Z, KC0[2].Y, literal.y, +; CM-NEXT: MUL_IEEE * T0.W, KC0[3].Y, T1.X, +; CM-NEXT: 1050288283(3.010300e-01), 8(1.121039e-44) +; CM-NEXT: LOG_IEEE T0.X (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W, T0.W, +; CM-NEXT: LSHR T1.X, T0.Z, literal.x, +; CM-NEXT: MUL_IEEE T0.Y, T0.Y, literal.y, +; CM-NEXT: ADD * T0.W, PV.W, -T0.X, +; CM-NEXT: 2(2.802597e-45), 1050288283(3.010300e-01) +; CM-NEXT: MUL_IEEE * T0.X, PV.W, literal.x, ; CM-NEXT: 1050288283(3.010300e-01), 0(0.000000e+00) ; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) @@ -371,17 +727,40 @@ ; SI-SDAG: ; %bb.0: ; SI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd ; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x4f800000 +; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, 1.0, v4, vcc +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; SI-SDAG-NEXT: v_mul_f32_e32 v3, s7, v3 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v4, vcc +; SI-SDAG-NEXT: v_log_f32_e32 v3, v3 +; SI-SDAG-NEXT: v_mul_f32_e32 v6, s6, v6 +; SI-SDAG-NEXT: v_log_f32_e32 v6, v6 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; SI-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2 +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; SI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a209b, v2 +; SI-SDAG-NEXT: v_sub_f32_e32 v2, v6, v5 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v4, vcc +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v4, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v6, s5, v6 +; SI-SDAG-NEXT: v_mul_f32_e32 v1, s4, v1 +; SI-SDAG-NEXT: v_log_f32_e32 v6, v6 +; SI-SDAG-NEXT: v_log_f32_e32 v4, v1 ; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000 ; SI-SDAG-NEXT: s_mov_b32 s2, -1 -; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; SI-SDAG-NEXT: v_log_f32_e32 v0, s7 -; SI-SDAG-NEXT: v_log_f32_e32 v1, s6 -; SI-SDAG-NEXT: v_log_f32_e32 v4, s5 -; SI-SDAG-NEXT: v_log_f32_e32 v5, s4 -; SI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a209b, v0 -; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v1 -; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v4 -; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v5 +; SI-SDAG-NEXT: v_sub_f32_e32 v1, v6, v5 +; SI-SDAG-NEXT: v_sub_f32_e32 v0, v4, v0 +; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2 +; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 +; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; SI-SDAG-NEXT: s_endpgm ; @@ -389,34 +768,83 @@ ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd ; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; SI-GISEL-NEXT: s_mov_b32 s2, -1 -; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 +; SI-GISEL-NEXT: s_mov_b32 s2, 0x800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x42000000 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; SI-GISEL-NEXT: v_log_f32_e32 v0, s4 -; SI-GISEL-NEXT: v_log_f32_e32 v1, s5 -; SI-GISEL-NEXT: v_log_f32_e32 v2, s6 -; SI-GISEL-NEXT: v_log_f32_e32 v3, s7 +; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v5, s5 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc +; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v5 +; SI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mul_f32_e32 v5, s5, v5 +; SI-GISEL-NEXT: v_log_f32_e32 v5, v5 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2 +; SI-GISEL-NEXT: v_sub_f32_e32 v1, v5, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v4, vcc +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s7, v2 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; SI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v5 +; SI-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2 +; SI-GISEL-NEXT: v_log_f32_e32 v5, v5 +; SI-GISEL-NEXT: v_log_f32_e32 v3, v2 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc ; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; SI-GISEL-NEXT: v_sub_f32_e32 v2, v5, v6 +; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 ; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2 ; SI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a209b, v3 +; SI-GISEL-NEXT: s_mov_b32 s2, -1 +; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 ; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; SI-GISEL-NEXT: s_endpgm ; ; VI-SDAG-LABEL: s_log10_v4f32: ; VI-SDAG: ; %bb.0: ; VI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 +; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; VI-SDAG-NEXT: v_log_f32_e32 v0, s7 -; VI-SDAG-NEXT: v_log_f32_e32 v1, s6 -; VI-SDAG-NEXT: v_log_f32_e32 v4, s5 -; VI-SDAG-NEXT: v_log_f32_e32 v5, s4 -; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a209b, v0 -; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v1 -; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v4 -; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v5 +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v2, vcc +; VI-SDAG-NEXT: v_mul_f32_e32 v4, s7, v4 +; VI-SDAG-NEXT: v_mul_f32_e32 v6, s6, v6 +; VI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; VI-SDAG-NEXT: v_log_f32_e32 v6, v6 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; VI-SDAG-NEXT: v_sub_f32_e32 v3, v4, v3 +; VI-SDAG-NEXT: v_sub_f32_e32 v4, v6, v5 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v2, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; VI-SDAG-NEXT: v_mul_f32_e32 v6, s5, v6 +; VI-SDAG-NEXT: v_mul_f32_e32 v1, s4, v1 +; VI-SDAG-NEXT: v_log_f32_e32 v6, v6 +; VI-SDAG-NEXT: v_log_f32_e32 v7, v1 +; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v4 +; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a209b, v3 +; VI-SDAG-NEXT: v_sub_f32_e32 v1, v6, v5 +; VI-SDAG-NEXT: v_sub_f32_e32 v0, v7, v0 ; VI-SDAG-NEXT: v_mov_b32_e32 v5, s1 +; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 +; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; VI-SDAG-NEXT: v_mov_b32_e32 v4, s0 ; VI-SDAG-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; VI-SDAG-NEXT: s_endpgm @@ -425,13 +853,39 @@ ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-GISEL-NEXT: s_mov_b32 s2, 0x800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x42000000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; VI-GISEL-NEXT: v_log_f32_e32 v0, s4 -; VI-GISEL-NEXT: v_log_f32_e32 v1, s5 -; VI-GISEL-NEXT: v_log_f32_e32 v2, s6 -; VI-GISEL-NEXT: v_log_f32_e32 v3, s7 -; VI-GISEL-NEXT: v_mov_b32_e32 v5, s1 +; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v5, s5 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc +; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v5 +; VI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mul_f32_e32 v5, s5, v5 +; VI-GISEL-NEXT: v_log_f32_e32 v5, v5 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2 +; VI-GISEL-NEXT: v_sub_f32_e32 v1, v5, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v4, vcc +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s7, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; VI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v5 +; VI-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2 +; VI-GISEL-NEXT: v_log_f32_e32 v5, v5 +; VI-GISEL-NEXT: v_log_f32_e32 v3, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc ; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; VI-GISEL-NEXT: v_sub_f32_e32 v2, v5, v6 +; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 +; VI-GISEL-NEXT: v_mov_b32_e32 v5, s1 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2 ; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a209b, v3 @@ -443,89 +897,189 @@ ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX900-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0x4f800000 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-SDAG-NEXT: v_log_f32_e32 v0, s7 -; GFX900-SDAG-NEXT: v_log_f32_e32 v1, s6 -; GFX900-SDAG-NEXT: v_log_f32_e32 v5, s5 -; GFX900-SDAG-NEXT: v_log_f32_e32 v6, s4 -; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a209b, v0 -; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v1 -; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v5 -; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v6 -; GFX900-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, 1.0, v4, vcc +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, s7, v3 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v4, vcc +; GFX900-SDAG-NEXT: v_log_f32_e32 v3, v3 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, s6, v6 +; GFX900-SDAG-NEXT: v_log_f32_e32 v6, v6 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2 +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a209b, v2 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v6, v5 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v4, vcc +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v4, vcc +; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, s5, v6 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, s4, v1 +; GFX900-SDAG-NEXT: v_log_f32_e32 v6, v6 +; GFX900-SDAG-NEXT: v_log_f32_e32 v4, v1 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v6, v5 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v4, v0 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GFX900-SDAG-NEXT: global_store_dwordx4 v7, v[0:3], s[2:3] ; GFX900-SDAG-NEXT: s_endpgm ; ; GFX900-GISEL-LABEL: s_log10_v4f32: ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX900-GISEL-NEXT: s_mov_b32 s0, 0x800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x42000000 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s4 -; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s5 -; GFX900-GISEL-NEXT: v_log_f32_e32 v2, s6 -; GFX900-GISEL-NEXT: v_log_f32_e32 v3, s7 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, s5 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v5 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s5, v5 +; GFX900-GISEL-NEXT: v_log_f32_e32 v5, v5 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v5, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v4, vcc +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s7, v2 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc +; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s6, v5 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2 +; GFX900-GISEL-NEXT: v_log_f32_e32 v5, v5 +; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v2 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v5, v6 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a209b, v3 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0 ; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX900-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log10_v4f32: ; R600: ; %bb.0: -; R600-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[] +; R600-NEXT: ALU 38, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 ; R600-NEXT: CF_END ; R600-NEXT: PAD ; R600-NEXT: ALU clause starting at 4: -; R600-NEXT: LOG_IEEE * T0.X, KC0[4].X, -; R600-NEXT: MUL_IEEE T0.W, PS, literal.x, -; R600-NEXT: LOG_IEEE * T0.X, KC0[3].W, +; R600-NEXT: SETGT T0.W, literal.x, KC0[4].X, +; R600-NEXT: SETGT * T1.W, literal.x, KC0[3].W, +; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; R600-NEXT: CNDE * T2.W, PV.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T0.Z, KC0[4].X, PV.W, +; R600-NEXT: SETGT T2.W, literal.x, KC0[3].Z, +; R600-NEXT: CNDE * T3.W, T1.W, 1.0, literal.y, +; R600-NEXT: 8388608(1.175494e-38), 1333788672(4.294967e+09) +; R600-NEXT: MUL_IEEE T0.X, KC0[3].W, PS, +; R600-NEXT: SETGT T0.Y, literal.x, KC0[3].Y, +; R600-NEXT: CNDE T1.Z, T0.W, 0.0, literal.y, +; R600-NEXT: CNDE T0.W, PV.W, 1.0, literal.z, +; R600-NEXT: LOG_IEEE * T0.Z, PV.Z, +; R600-NEXT: 8388608(1.175494e-38), 1107296256(3.200000e+01) +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T1.X, KC0[3].Z, PV.W, +; R600-NEXT: ADD T1.Y, PS, -PV.Z, +; R600-NEXT: CNDE T0.Z, T1.W, 0.0, literal.x, +; R600-NEXT: CNDE T0.W, PV.Y, 1.0, literal.y, +; R600-NEXT: LOG_IEEE * T0.X, PV.X, +; R600-NEXT: 1107296256(3.200000e+01), 1333788672(4.294967e+09) +; R600-NEXT: MUL_IEEE T2.X, KC0[3].Y, PV.W, +; R600-NEXT: CNDE T2.Y, T2.W, 0.0, literal.x, +; R600-NEXT: ADD T0.Z, PS, -PV.Z, +; R600-NEXT: MUL_IEEE T0.W, PV.Y, literal.y, +; R600-NEXT: LOG_IEEE * T0.X, PV.X, +; R600-NEXT: 1107296256(3.200000e+01), 1050288283(3.010300e-01) +; R600-NEXT: CNDE T1.Y, T0.Y, 0.0, literal.x, +; R600-NEXT: MUL_IEEE T0.Z, PV.Z, literal.y, +; R600-NEXT: ADD T1.W, PS, -PV.Y, +; R600-NEXT: LOG_IEEE * T0.X, PV.X, +; R600-NEXT: 1107296256(3.200000e+01), 1050288283(3.010300e-01) +; R600-NEXT: MUL_IEEE T0.Y, PV.W, literal.x, +; R600-NEXT: ADD * T1.W, PS, -PV.Y, ; R600-NEXT: 1050288283(3.010300e-01), 0(0.000000e+00) -; R600-NEXT: MUL_IEEE T0.Z, PS, literal.x, -; R600-NEXT: LOG_IEEE * T0.X, KC0[3].Z, -; R600-NEXT: 1050288283(3.010300e-01), 0(0.000000e+00) -; R600-NEXT: MUL_IEEE T0.Y, PS, literal.x, -; R600-NEXT: LOG_IEEE * T0.X, KC0[3].Y, -; R600-NEXT: 1050288283(3.010300e-01), 0(0.000000e+00) -; R600-NEXT: MUL_IEEE T0.X, PS, literal.x, +; R600-NEXT: MUL_IEEE T0.X, PV.W, literal.x, ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, ; R600-NEXT: 1050288283(3.010300e-01), 2(2.802597e-45) ; ; CM-LABEL: s_log10_v4f32: ; CM: ; %bb.0: -; CM-NEXT: ALU 25, @4, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X +; CM-NEXT: ALU 50, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T0.X ; CM-NEXT: CF_END ; CM-NEXT: PAD ; CM-NEXT: ALU clause starting at 4: -; CM-NEXT: LOG_IEEE T0.X, KC0[4].X, -; CM-NEXT: LOG_IEEE T0.Y (MASKED), KC0[4].X, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[4].X, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[4].X, -; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.x, -; CM-NEXT: 1050288283(3.010300e-01), 0(0.000000e+00) -; CM-NEXT: LOG_IEEE T0.X, KC0[3].W, -; CM-NEXT: LOG_IEEE T0.Y (MASKED), KC0[3].W, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[3].W, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[3].W, -; CM-NEXT: MUL_IEEE * T0.Z, PV.X, literal.x, -; CM-NEXT: 1050288283(3.010300e-01), 0(0.000000e+00) -; CM-NEXT: LOG_IEEE T0.X, KC0[3].Z, -; CM-NEXT: LOG_IEEE T0.Y (MASKED), KC0[3].Z, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[3].Z, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[3].Z, -; CM-NEXT: MUL_IEEE * T0.Y, PV.X, literal.x, +; CM-NEXT: SETGT T0.Z, literal.x, KC0[4].X, +; CM-NEXT: SETGT * T0.W, literal.x, KC0[3].Y, +; CM-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; CM-NEXT: CNDE T0.Y, PV.W, 1.0, literal.x, +; CM-NEXT: CNDE T1.Z, PV.Z, 1.0, literal.x, +; CM-NEXT: SETGT * T1.W, literal.y, KC0[3].W, +; CM-NEXT: 1333788672(4.294967e+09), 8388608(1.175494e-38) +; CM-NEXT: CNDE T0.X, PV.W, 1.0, literal.x, +; CM-NEXT: SETGT T1.Y, literal.y, KC0[3].Z, +; CM-NEXT: CNDE T0.Z, T0.Z, 0.0, literal.z, +; CM-NEXT: MUL_IEEE * T2.W, KC0[4].X, PV.Z, +; CM-NEXT: 1333788672(4.294967e+09), 8388608(1.175494e-38) +; CM-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; CM-NEXT: LOG_IEEE T1.X, T2.W, +; CM-NEXT: LOG_IEEE T1.Y (MASKED), T2.W, +; CM-NEXT: LOG_IEEE T1.Z (MASKED), T2.W, +; CM-NEXT: LOG_IEEE * T1.W (MASKED), T2.W, +; CM-NEXT: ADD T1.X, PV.X, -T0.Z, +; CM-NEXT: CNDE T2.Y, T1.Y, 1.0, literal.x, +; CM-NEXT: CNDE T0.Z, T1.W, 0.0, literal.y, +; CM-NEXT: MUL_IEEE * T1.W, KC0[3].W, T0.X, +; CM-NEXT: 1333788672(4.294967e+09), 1107296256(3.200000e+01) +; CM-NEXT: LOG_IEEE T0.X, T1.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T1.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T1.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T1.W, +; CM-NEXT: ADD T0.X, PV.X, -T0.Z, +; CM-NEXT: CNDE T1.Y, T1.Y, 0.0, literal.x, +; CM-NEXT: MUL_IEEE T0.Z, KC0[3].Z, T2.Y, +; CM-NEXT: MUL_IEEE * T1.W, T1.X, literal.y, +; CM-NEXT: 1107296256(3.200000e+01), 1050288283(3.010300e-01) +; CM-NEXT: LOG_IEEE T0.X (MASKED), T0.Z, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.Z, +; CM-NEXT: LOG_IEEE T0.Z, T0.Z, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.Z, +; CM-NEXT: CNDE T1.X, T0.W, 0.0, literal.x, +; CM-NEXT: ADD T1.Y, PV.Z, -T1.Y, +; CM-NEXT: MUL_IEEE T1.Z, T0.X, literal.y, +; CM-NEXT: MUL_IEEE * T0.W, KC0[3].Y, T0.Y, BS:VEC_021/SCL_122 +; CM-NEXT: 1107296256(3.200000e+01), 1050288283(3.010300e-01) +; CM-NEXT: LOG_IEEE T0.X, T0.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: MUL_IEEE T1.Y, T1.Y, literal.x, +; CM-NEXT: ADD * T0.W, PV.X, -T1.X, ; CM-NEXT: 1050288283(3.010300e-01), 0(0.000000e+00) -; CM-NEXT: LOG_IEEE T0.X, KC0[3].Y, -; CM-NEXT: LOG_IEEE T0.Y (MASKED), KC0[3].Y, -; CM-NEXT: LOG_IEEE T0.Z (MASKED), KC0[3].Y, -; CM-NEXT: LOG_IEEE * T0.W (MASKED), KC0[3].Y, -; CM-NEXT: MUL_IEEE * T0.X, PV.X, literal.x, +; CM-NEXT: MUL_IEEE * T1.X, PV.W, literal.x, ; CM-NEXT: 1050288283(3.010300e-01), 0(0.000000e+00) -; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) %result = call <4 x float> @llvm.log10.v4f32(<4 x float> %in) store <4 x float> %result, ptr addrspace(1) %out @@ -533,12 +1087,35 @@ } define float @v_log10_f32(float %in) { -; GCN-LABEL: v_log10_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log10_f32: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log10_f32: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log10_f32: ; R600: ; %bb.0: @@ -554,12 +1131,35 @@ } define float @v_log10_fabs_f32(float %in) { -; GCN-LABEL: v_log10_fabs_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e64 v0, |v0| -; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log10_fabs_f32: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log10_fabs_f32: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log10_fabs_f32: ; R600: ; %bb.0: @@ -576,12 +1176,35 @@ } define float @v_log10_fneg_fabs_f32(float %in) { -; GCN-LABEL: v_log10_fneg_fabs_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e64 v0, -|v0| -; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log10_fneg_fabs_f32: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x80800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e64 v0, -|v0|, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log10_fneg_fabs_f32: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e64 v0, -|v0|, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log10_fneg_fabs_f32: ; R600: ; %bb.0: @@ -599,12 +1222,35 @@ } define float @v_log10_fneg_f32(float %in) { -; GCN-LABEL: v_log10_fneg_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e64 v0, -v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log10_fneg_f32: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x80800000 +; GCN-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e64 v0, -v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log10_fneg_f32: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e64 v0, -v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log10_fneg_f32: ; R600: ; %bb.0: @@ -621,12 +1267,27 @@ } define float @v_log10_f32_fast(float %in) { -; GCN-LABEL: v_log10_f32_fast: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log10_f32_fast: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log10_f32_fast: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log10_f32_fast: ; R600: ; %bb.0: @@ -684,12 +1345,35 @@ } define float @v_log10_f32_ninf(float %in) { -; GCN-LABEL: v_log10_f32_ninf: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log10_f32_ninf: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log10_f32_ninf: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log10_f32_ninf: ; R600: ; %bb.0: @@ -705,12 +1389,27 @@ } define float @v_log10_f32_afn(float %in) { -; GCN-LABEL: v_log10_f32_afn: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log10_f32_afn: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log10_f32_afn: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log10_f32_afn: ; R600: ; %bb.0: @@ -747,12 +1446,27 @@ } define float @v_log10_f32_afn_dynamic(float %in) #1 { -; GCN-LABEL: v_log10_f32_afn_dynamic: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log10_f32_afn_dynamic: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log10_f32_afn_dynamic: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log10_f32_afn_dynamic: ; R600: ; %bb.0: @@ -768,12 +1482,27 @@ } define float @v_fabs_log10_f32_afn(float %in) { -; GCN-LABEL: v_fabs_log10_f32_afn: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e64 v0, |v0| -; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_fabs_log10_f32_afn: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_fabs_log10_f32_afn: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_log_f32_e64 v0, |v0| +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_fabs_log10_f32_afn: ; R600: ; %bb.0: @@ -811,12 +1540,35 @@ } define float @v_log10_f32_nnan(float %in) { -; GCN-LABEL: v_log10_f32_nnan: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log10_f32_nnan: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log10_f32_nnan: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log10_f32_nnan: ; R600: ; %bb.0: @@ -853,12 +1605,35 @@ } define float @v_log10_f32_nnan_dynamic(float %in) #1 { -; GCN-LABEL: v_log10_f32_nnan_dynamic: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log10_f32_nnan_dynamic: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log10_f32_nnan_dynamic: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log10_f32_nnan_dynamic: ; R600: ; %bb.0: @@ -895,12 +1670,35 @@ } define float @v_log10_f32_ninf_dynamic(float %in) #1 { -; GCN-LABEL: v_log10_f32_ninf_dynamic: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log10_f32_ninf_dynamic: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log10_f32_ninf_dynamic: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log10_f32_ninf_dynamic: ; R600: ; %bb.0: @@ -916,12 +1714,35 @@ } define float @v_log10_f32_nnan_ninf(float %in) { -; GCN-LABEL: v_log10_f32_nnan_ninf: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log10_f32_nnan_ninf: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log10_f32_nnan_ninf: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log10_f32_nnan_ninf: ; R600: ; %bb.0: @@ -958,12 +1779,35 @@ } define float @v_log10_f32_nnan_ninf_dynamic(float %in) #1 { -; GCN-LABEL: v_log10_f32_nnan_ninf_dynamic: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log10_f32_nnan_ninf_dynamic: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log10_f32_nnan_ninf_dynamic: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log10_f32_nnan_ninf_dynamic: ; R600: ; %bb.0: @@ -1000,12 +1844,35 @@ } define float @v_log10_f32_dynamic_mode(float %in) #1 { -; GCN-LABEL: v_log10_f32_dynamic_mode: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log10_f32_dynamic_mode: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log10_f32_dynamic_mode: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log10_f32_dynamic_mode: ; R600: ; %bb.0: @@ -1021,12 +1888,28 @@ } define float @v_log10_f32_undef() { -; GCN-LABEL: v_log10_f32_undef: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, s4 -; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log10_f32_undef: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: v_log_f32_e32 v0, s4 +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log10_f32_undef: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GCN-GISEL-NEXT: v_mul_f32_e32 v1, s4, v1 +; GCN-GISEL-NEXT: v_mul_f32_e64 v2, s4, 1.0 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log10_f32_undef: ; R600: ; %bb.0: @@ -1046,14 +1929,24 @@ ; GCN-SDAG: ; %bb.0: ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-SDAG-NEXT: v_log_f32_e32 v0, 0 +; GCN-SDAG-NEXT: v_add_f32_e32 v0, 0xc2000000, v0 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; GCN-GISEL-LABEL: v_log10_f32_0: ; GCN-GISEL: ; %bb.0: ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0x3e9a209b -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0xff800000, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e64 v2, 0, 1.0 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, 0, v0 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log10_f32_0: @@ -1099,8 +1992,16 @@ ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000 ; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: v_log_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; @@ -1155,7 +2056,15 @@ ; GCN-SDAG-LABEL: v_log10_f32_from_fpext_bf16: ; GCN-SDAG: ; %bb.0: ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 ; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] ; @@ -1851,3 +2760,5 @@ attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" } attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" } attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; SI: {{.*}} Index: llvm/test/CodeGen/AMDGPU/llvm.log2.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/llvm.log2.ll +++ llvm/test/CodeGen/AMDGPU/llvm.log2.ll @@ -10,62 +10,158 @@ ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) { -; SI-LABEL: s_log2_f32: -; SI: ; %bb.0: -; SI-NEXT: s_load_dword s2, s[0:1], 0xb -; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; SI-NEXT: s_mov_b32 s3, 0xf000 -; SI-NEXT: s_waitcnt lgkmcnt(0) -; SI-NEXT: v_log_f32_e32 v0, s2 -; SI-NEXT: s_mov_b32 s2, -1 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 -; SI-NEXT: s_endpgm -; -; VI-LABEL: s_log2_f32: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_log_f32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: flat_store_dword v[0:1], v2 -; VI-NEXT: s_endpgm -; -; GFX900-LABEL: s_log2_f32: -; GFX900: ; %bb.0: -; GFX900-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX900-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX900-NEXT: v_mov_b32_e32 v1, 0 -; GFX900-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-NEXT: v_log_f32_e32 v0, s4 -; GFX900-NEXT: global_store_dword v1, v0, s[2:3] -; GFX900-NEXT: s_endpgm +; SI-SDAG-LABEL: s_log2_f32: +; SI-SDAG: ; %bb.0: +; SI-SDAG-NEXT: s_load_dword s2, s[0:1], 0xb +; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000 +; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; SI-SDAG-NEXT: v_log_f32_e32 v1, v1 +; SI-SDAG-NEXT: s_mov_b32 s2, -1 +; SI-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0 +; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; SI-SDAG-NEXT: s_endpgm +; +; SI-GISEL-LABEL: s_log2_f32: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_load_dword s2, s[0:1], 0xb +; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 +; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; SI-GISEL-NEXT: v_mul_f32_e32 v0, s2, v0 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: s_mov_b32 s2, -1 +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; SI-GISEL-NEXT: s_endpgm +; +; VI-SDAG-LABEL: s_log2_f32: +; VI-SDAG: ; %bb.0: +; VI-SDAG-NEXT: s_load_dword s2, s[0:1], 0x2c +; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; VI-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; VI-SDAG-NEXT: v_log_f32_e32 v1, v1 +; VI-SDAG-NEXT: v_sub_f32_e32 v2, v1, v0 +; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; VI-SDAG-NEXT: flat_store_dword v[0:1], v2 +; VI-SDAG-NEXT: s_endpgm +; +; VI-GISEL-LABEL: s_log2_f32: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_load_dword s2, s[0:1], 0x2c +; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; VI-GISEL-NEXT: v_mul_f32_e32 v0, s2, v0 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 +; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; VI-GISEL-NEXT: flat_store_dword v[0:1], v2 +; VI-GISEL-NEXT: s_endpgm +; +; GFX900-SDAG-LABEL: s_log2_f32: +; GFX900-SDAG: ; %bb.0: +; GFX900-SDAG-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX900-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, s4, v1 +; GFX900-SDAG-NEXT: v_log_f32_e32 v1, v1 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0 +; GFX900-SDAG-NEXT: global_store_dword v2, v0, s[2:3] +; GFX900-SDAG-NEXT: s_endpgm +; +; GFX900-GISEL-LABEL: s_log2_f32: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_load_dword s2, s[0:1], 0x2c +; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s2, v0 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1] +; GFX900-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log2_f32: ; R600: ; %bb.0: -; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] -; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 +; R600-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[] +; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 ; R600-NEXT: CF_END ; R600-NEXT: PAD ; R600-NEXT: ALU clause starting at 4: -; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x, -; R600-NEXT: LOG_IEEE * T1.X, KC0[2].Z, +; R600-NEXT: SETGT * T0.W, literal.x, KC0[2].Z, +; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; R600-NEXT: CNDE * T1.W, PV.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T1.W, KC0[2].Z, PV.W, +; R600-NEXT: CNDE * T0.W, T0.W, 0.0, literal.x, +; R600-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; R600-NEXT: LOG_IEEE * T0.X, PV.W, +; R600-NEXT: ADD T0.X, PS, -T0.W, +; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; ; CM-LABEL: s_log2_f32: ; CM: ; %bb.0: -; CM-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X +; CM-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X ; CM-NEXT: CF_END ; CM-NEXT: PAD ; CM-NEXT: ALU clause starting at 4: -; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, +; CM-NEXT: SETGT * T0.W, literal.x, KC0[2].Z, +; CM-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; CM-NEXT: CNDE * T1.W, PV.W, 1.0, literal.x, +; CM-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; CM-NEXT: CNDE T0.Z, T0.W, 0.0, literal.x, +; CM-NEXT: MUL_IEEE * T0.W, KC0[2].Z, PV.W, +; CM-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; CM-NEXT: LOG_IEEE T0.X, T0.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: ADD * T0.X, PV.X, -T0.Z, +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; CM-NEXT: LOG_IEEE T1.X, KC0[2].Z, -; CM-NEXT: LOG_IEEE T1.Y (MASKED), KC0[2].Z, -; CM-NEXT: LOG_IEEE T1.Z (MASKED), KC0[2].Z, -; CM-NEXT: LOG_IEEE * T1.W (MASKED), KC0[2].Z, %result = call float @llvm.log2.f32(float %in) store float %result, ptr addrspace(1) %out ret void @@ -77,33 +173,74 @@ ; SI-SDAG-LABEL: s_log2_v2f32: ; SI-SDAG: ; %bb.0: ; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000 -; SI-SDAG-NEXT: s_mov_b32 s6, -1 ; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; SI-SDAG-NEXT: v_log_f32_e32 v1, s3 -; SI-SDAG-NEXT: v_log_f32_e32 v0, s2 +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v4, s3, v4 +; SI-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; SI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; SI-SDAG-NEXT: v_log_f32_e32 v3, v1 +; SI-SDAG-NEXT: s_mov_b32 s6, -1 ; SI-SDAG-NEXT: s_mov_b32 s4, s0 ; SI-SDAG-NEXT: s_mov_b32 s5, s1 +; SI-SDAG-NEXT: v_sub_f32_e32 v1, v4, v2 +; SI-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0 ; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-SDAG-NEXT: s_endpgm ; ; SI-GISEL-LABEL: s_log2_v2f32: ; SI-GISEL: ; %bb.0: -; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; SI-GISEL-NEXT: s_mov_b32 s0, 0x800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x4f800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; SI-GISEL-NEXT: v_log_f32_e32 v0, s2 -; SI-GISEL-NEXT: v_log_f32_e32 v1, s3 -; SI-GISEL-NEXT: s_mov_b32 s2, -1 -; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 -; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, s6 +; SI-GISEL-NEXT: v_mov_b32_e32 v3, s7 +; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v2 +; SI-GISEL-NEXT: v_cmp_gt_f32_e64 s[0:1], s0, v3 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, v0, s[0:1] +; SI-GISEL-NEXT: v_mul_f32_e32 v2, s6, v2 +; SI-GISEL-NEXT: v_mul_f32_e32 v0, s7, v0 +; SI-GISEL-NEXT: v_log_f32_e32 v2, v2 +; SI-GISEL-NEXT: v_log_f32_e32 v3, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[0:1] +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v2, v0 +; SI-GISEL-NEXT: v_sub_f32_e32 v1, v3, v1 +; SI-GISEL-NEXT: s_mov_b32 s6, -1 +; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 +; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-GISEL-NEXT: s_endpgm ; ; VI-SDAG-LABEL: s_log2_v2f32: ; VI-SDAG: ; %bb.0: ; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; VI-SDAG-NEXT: v_log_f32_e32 v1, s3 -; VI-SDAG-NEXT: v_log_f32_e32 v0, s2 +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; VI-SDAG-NEXT: v_mul_f32_e32 v4, s3, v4 +; VI-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; VI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; VI-SDAG-NEXT: v_log_f32_e32 v2, v1 +; VI-SDAG-NEXT: v_sub_f32_e32 v1, v4, v3 +; VI-SDAG-NEXT: v_sub_f32_e32 v0, v2, v0 ; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1 ; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0 ; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1] @@ -111,64 +248,136 @@ ; ; VI-GISEL-LABEL: s_log2_v2f32: ; VI-GISEL: ; %bb.0: -; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; VI-GISEL-NEXT: s_mov_b32 s0, 0x800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x4f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; VI-GISEL-NEXT: v_log_f32_e32 v0, s2 -; VI-GISEL-NEXT: v_log_f32_e32 v1, s3 -; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, s6 +; VI-GISEL-NEXT: v_mov_b32_e32 v3, s7 +; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v2 +; VI-GISEL-NEXT: v_cmp_gt_f32_e64 s[0:1], s0, v3 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, v0, s[0:1] +; VI-GISEL-NEXT: v_mul_f32_e32 v2, s6, v2 +; VI-GISEL-NEXT: v_mul_f32_e32 v0, s7, v0 +; VI-GISEL-NEXT: v_log_f32_e32 v2, v2 +; VI-GISEL-NEXT: v_log_f32_e32 v3, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[0:1] +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v2, v0 +; VI-GISEL-NEXT: v_sub_f32_e32 v1, v3, v1 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; VI-GISEL-NEXT: v_mov_b32_e32 v3, s5 ; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-GISEL-NEXT: s_endpgm ; ; GFX900-SDAG-LABEL: s_log2_v2f32: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-SDAG-NEXT: v_log_f32_e32 v1, s3 -; GFX900-SDAG-NEXT: v_log_f32_e32 v0, s2 -; GFX900-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GFX900-SDAG-NEXT: v_mul_f32_e32 v4, s3, v4 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, s2, v1 +; GFX900-SDAG-NEXT: v_log_f32_e32 v4, v4 +; GFX900-SDAG-NEXT: v_log_f32_e32 v2, v1 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v4, v3 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v2, v0 +; GFX900-SDAG-NEXT: global_store_dwordx2 v5, v[0:1], s[0:1] ; GFX900-SDAG-NEXT: s_endpgm ; ; GFX900-GISEL-LABEL: s_log2_v2f32: ; GFX900-GISEL: ; %bb.0: -; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX900-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX900-GISEL-NEXT: s_mov_b32 s0, 0x800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x4f800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s2 -; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s3 -; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, s7 +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v2 +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e64 s[0:1], s0, v3 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v0, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, v0, s[0:1] +; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s6, v2 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s7, v0 +; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v2 +; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[0:1] +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v2, v0 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v3, v1 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] ; GFX900-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log2_v2f32: ; R600: ; %bb.0: -; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[] +; R600-NEXT: ALU 18, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; R600-NEXT: CF_END ; R600-NEXT: PAD ; R600-NEXT: ALU clause starting at 4: -; R600-NEXT: LOG_IEEE * T0.Y, KC0[3].X, -; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x, -; R600-NEXT: LOG_IEEE * T0.X, KC0[2].W, +; R600-NEXT: SETGT T0.W, literal.x, KC0[3].X, +; R600-NEXT: SETGT * T1.W, literal.x, KC0[2].W, +; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; R600-NEXT: CNDE * T2.W, PV.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T2.W, KC0[3].X, PV.W, +; R600-NEXT: CNDE * T3.W, T1.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T0.Z, KC0[2].W, PS, +; R600-NEXT: CNDE T0.W, T0.W, 0.0, literal.x, +; R600-NEXT: LOG_IEEE * T0.X, PV.W, +; R600-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; R600-NEXT: ADD T0.Y, PS, -PV.W, +; R600-NEXT: CNDE T0.W, T1.W, 0.0, literal.x, +; R600-NEXT: LOG_IEEE * T0.X, PV.Z, +; R600-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; R600-NEXT: ADD T0.X, PS, -PV.W, +; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; ; CM-LABEL: s_log2_v2f32: ; CM: ; %bb.0: -; CM-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: ALU 23, @4, KC0[CB0:0-32], KC1[] ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T0.X ; CM-NEXT: CF_END ; CM-NEXT: PAD ; CM-NEXT: ALU clause starting at 4: +; CM-NEXT: SETGT * T0.W, literal.x, KC0[3].X, +; CM-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; CM-NEXT: CNDE T0.Z, PV.W, 1.0, literal.x, +; CM-NEXT: SETGT * T1.W, literal.y, KC0[2].W, +; CM-NEXT: 1333788672(4.294967e+09), 8388608(1.175494e-38) +; CM-NEXT: CNDE T0.Y, PV.W, 1.0, literal.x, +; CM-NEXT: CNDE T1.Z, T0.W, 0.0, literal.y, +; CM-NEXT: MUL_IEEE * T0.W, KC0[3].X, PV.Z, +; CM-NEXT: 1333788672(4.294967e+09), 1107296256(3.200000e+01) +; CM-NEXT: LOG_IEEE T0.X, T0.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: ADD T1.Y, PV.X, -T1.Z, +; CM-NEXT: CNDE T0.Z, T1.W, 0.0, literal.x, +; CM-NEXT: MUL_IEEE * T0.W, KC0[2].W, T0.Y, +; CM-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; CM-NEXT: LOG_IEEE T0.X, T0.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: ADD * T1.X, PV.X, -T0.Z, ; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; CM-NEXT: LOG_IEEE T1.X (MASKED), KC0[3].X, -; CM-NEXT: LOG_IEEE T1.Y, KC0[3].X, -; CM-NEXT: LOG_IEEE T1.Z (MASKED), KC0[3].X, -; CM-NEXT: LOG_IEEE * T1.W (MASKED), KC0[3].X, -; CM-NEXT: LOG_IEEE T1.X, KC0[2].W, -; CM-NEXT: LOG_IEEE T1.Y (MASKED), KC0[2].W, -; CM-NEXT: LOG_IEEE T1.Z (MASKED), KC0[2].W, -; CM-NEXT: LOG_IEEE * T1.W (MASKED), KC0[2].W, %result = call <2 x float> @llvm.log2.v2f32(<2 x float> %in) store <2 x float> %result, ptr addrspace(1) %out ret void @@ -179,12 +388,30 @@ ; SI-SDAG: ; %bb.0: ; SI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd ; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v3, vcc +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v4, s5, v4 +; SI-SDAG-NEXT: v_mul_f32_e32 v0, s6, v0 +; SI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; SI-SDAG-NEXT: v_mul_f32_e32 v6, s4, v6 +; SI-SDAG-NEXT: v_log_f32_e32 v3, v0 +; SI-SDAG-NEXT: v_log_f32_e32 v6, v6 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v7, 0, v1, vcc ; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000 ; SI-SDAG-NEXT: s_mov_b32 s2, -1 -; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; SI-SDAG-NEXT: v_log_f32_e32 v2, s6 -; SI-SDAG-NEXT: v_log_f32_e32 v1, s5 -; SI-SDAG-NEXT: v_log_f32_e32 v0, s4 +; SI-SDAG-NEXT: v_sub_f32_e32 v1, v4, v2 +; SI-SDAG-NEXT: v_sub_f32_e32 v2, v3, v7 +; SI-SDAG-NEXT: v_sub_f32_e32 v0, v6, v5 ; SI-SDAG-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8 ; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-SDAG-NEXT: s_endpgm @@ -192,26 +419,65 @@ ; SI-GISEL-LABEL: s_log2_v3f32: ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd -; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; SI-GISEL-NEXT: s_mov_b32 s2, -1 -; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 +; SI-GISEL-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9 +; SI-GISEL-NEXT: s_mov_b32 s0, 0x800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; SI-GISEL-NEXT: v_log_f32_e32 v0, s4 -; SI-GISEL-NEXT: v_log_f32_e32 v1, s5 -; SI-GISEL-NEXT: v_log_f32_e32 v2, s6 -; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 -; SI-GISEL-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8 +; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; SI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; SI-GISEL-NEXT: s_mov_b32 s10, -1 +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 +; SI-GISEL-NEXT: v_mov_b32_e32 v4, s5 +; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v1, vcc +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s6, v2 +; SI-GISEL-NEXT: v_mul_f32_e32 v4, s5, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v1, s[0:1] +; SI-GISEL-NEXT: v_log_f32_e32 v4, v4 +; SI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v2, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v1, v4, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1] +; SI-GISEL-NEXT: s_mov_b32 s11, 0xf000 +; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 +; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 +; SI-GISEL-NEXT: buffer_store_dword v2, off, s[8:11], 0 offset:8 ; SI-GISEL-NEXT: s_endpgm ; ; VI-SDAG-LABEL: s_log2_v3f32: ; VI-SDAG: ; %bb.0: ; VI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; VI-SDAG-NEXT: v_log_f32_e32 v2, s6 -; VI-SDAG-NEXT: v_log_f32_e32 v1, s5 -; VI-SDAG-NEXT: v_log_f32_e32 v0, s4 +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v3, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc +; VI-SDAG-NEXT: v_mul_f32_e32 v4, s6, v4 +; VI-SDAG-NEXT: v_mul_f32_e32 v1, s4, v1 +; VI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; VI-SDAG-NEXT: v_mul_f32_e32 v6, s5, v6 +; VI-SDAG-NEXT: v_log_f32_e32 v3, v1 +; VI-SDAG-NEXT: v_log_f32_e32 v6, v6 +; VI-SDAG-NEXT: v_sub_f32_e32 v2, v4, v2 +; VI-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0 ; VI-SDAG-NEXT: v_mov_b32_e32 v4, s1 +; VI-SDAG-NEXT: v_sub_f32_e32 v1, v6, v5 ; VI-SDAG-NEXT: v_mov_b32_e32 v3, s0 ; VI-SDAG-NEXT: flat_store_dwordx3 v[3:4], v[0:2] ; VI-SDAG-NEXT: s_endpgm @@ -219,13 +485,34 @@ ; VI-GISEL-LABEL: s_log2_v3f32: ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 -; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; VI-GISEL-NEXT: s_mov_b32 s0, 0x800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; VI-GISEL-NEXT: v_log_f32_e32 v0, s4 -; VI-GISEL-NEXT: v_log_f32_e32 v1, s5 -; VI-GISEL-NEXT: v_log_f32_e32 v2, s6 -; VI-GISEL-NEXT: v_mov_b32_e32 v4, s1 -; VI-GISEL-NEXT: v_mov_b32_e32 v3, s0 +; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; VI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5 +; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v4 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s6, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v1, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v1, s[0:1] +; VI-GISEL-NEXT: v_mul_f32_e32 v4, s5, v4 +; VI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v4, v4 +; VI-GISEL-NEXT: v_log_f32_e32 v2, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1] +; VI-GISEL-NEXT: v_sub_f32_e32 v1, v4, v1 +; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, s3 +; VI-GISEL-NEXT: v_mov_b32_e32 v3, s2 ; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2] ; VI-GISEL-NEXT: s_endpgm ; @@ -233,67 +520,146 @@ ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX900-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-SDAG-NEXT: v_log_f32_e32 v2, s6 -; GFX900-SDAG-NEXT: v_log_f32_e32 v1, s5 -; GFX900-SDAG-NEXT: v_log_f32_e32 v0, s4 -; GFX900-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3] +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v3, vcc +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc +; GFX900-SDAG-NEXT: v_mul_f32_e32 v4, s6, v4 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, s5, v6 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, s4, v1 +; GFX900-SDAG-NEXT: v_log_f32_e32 v4, v4 +; GFX900-SDAG-NEXT: v_log_f32_e32 v6, v6 +; GFX900-SDAG-NEXT: v_log_f32_e32 v3, v1 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v4, v2 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v6, v5 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0 +; GFX900-SDAG-NEXT: global_store_dwordx3 v7, v[0:2], s[2:3] ; GFX900-SDAG-NEXT: s_endpgm ; ; GFX900-GISEL-LABEL: s_log2_v3f32: ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0 +; GFX900-GISEL-NEXT: s_mov_b32 s0, 0x800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s4 -; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s5 -; GFX900-GISEL-NEXT: v_log_f32_e32 v2, s6 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc +; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, s5 +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v4 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s6, v2 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v1, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v1, s[0:1] +; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, s5, v4 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v4, v4 +; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1] +; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v4, v1 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0 ; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3] ; GFX900-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log2_v3f32: ; R600: ; %bb.0: -; R600-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] -; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 0 -; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 +; R600-NEXT: ALU 29, @4, KC0[CB0:0-32], KC1[] +; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0 +; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1 ; R600-NEXT: CF_END ; R600-NEXT: ALU clause starting at 4: -; R600-NEXT: LOG_IEEE * T0.Y, KC0[3].Z, -; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x, -; R600-NEXT: ADD_INT T0.W, KC0[2].Y, literal.y, -; R600-NEXT: LOG_IEEE * T0.X, KC0[3].Y, -; R600-NEXT: 2(2.802597e-45), 8(1.121039e-44) -; R600-NEXT: LSHR T2.X, PV.W, literal.x, -; R600-NEXT: LOG_IEEE * T3.X, KC0[3].W, +; R600-NEXT: SETGT T0.W, literal.x, KC0[3].Z, +; R600-NEXT: SETGT * T1.W, literal.x, KC0[3].Y, +; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; R600-NEXT: CNDE * T2.W, PV.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T2.W, KC0[3].Z, PV.W, +; R600-NEXT: CNDE * T3.W, T1.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T0.Y, KC0[3].Y, PS, +; R600-NEXT: SETGT T0.Z, literal.x, KC0[3].W, +; R600-NEXT: CNDE T0.W, T0.W, 0.0, literal.y, +; R600-NEXT: LOG_IEEE * T0.X, PV.W, +; R600-NEXT: 8388608(1.175494e-38), 1107296256(3.200000e+01) +; R600-NEXT: ADD T1.Y, PS, -PV.W, +; R600-NEXT: CNDE T1.Z, PV.Z, 1.0, literal.x, +; R600-NEXT: CNDE T0.W, T1.W, 0.0, literal.y, +; R600-NEXT: LOG_IEEE * T0.X, PV.Y, +; R600-NEXT: 1333788672(4.294967e+09), 1107296256(3.200000e+01) +; R600-NEXT: ADD T1.X, PS, -PV.W, +; R600-NEXT: MUL_IEEE T0.W, KC0[3].W, PV.Z, +; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, +; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; R600-NEXT: CNDE T1.W, T0.Z, 0.0, literal.x, +; R600-NEXT: LOG_IEEE * T0.Y, PV.W, +; R600-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; R600-NEXT: ADD T2.X, PS, -PV.W, +; R600-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, +; R600-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; R600-NEXT: LSHR * T3.X, PV.W, literal.x, ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; ; CM-LABEL: s_log2_v3f32: ; CM: ; %bb.0: -; CM-NEXT: ALU 17, @4, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T3, T1.X -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2.X, T0.X +; CM-NEXT: ALU 35, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T3.X +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T2.X ; CM-NEXT: CF_END ; CM-NEXT: ALU clause starting at 4: -; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, -; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) -; CM-NEXT: LSHR * T0.X, PV.W, literal.x, +; CM-NEXT: SETGT * T0.W, literal.x, KC0[3].W, +; CM-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; CM-NEXT: CNDE T0.Y, PV.W, 1.0, literal.x, +; CM-NEXT: SETGT T0.Z, literal.y, KC0[3].Z, +; CM-NEXT: SETGT * T1.W, literal.y, KC0[3].Y, +; CM-NEXT: 1333788672(4.294967e+09), 8388608(1.175494e-38) +; CM-NEXT: CNDE T0.X, PV.W, 1.0, literal.x, +; CM-NEXT: CNDE T1.Y, PV.Z, 1.0, literal.x, +; CM-NEXT: CNDE T1.Z, T0.W, 0.0, literal.y, +; CM-NEXT: MUL_IEEE * T0.W, KC0[3].W, PV.Y, +; CM-NEXT: 1333788672(4.294967e+09), 1107296256(3.200000e+01) +; CM-NEXT: LOG_IEEE T0.X (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Y, T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: ADD T1.X, PV.Y, -T1.Z, +; CM-NEXT: CNDE T0.Y, T0.Z, 0.0, literal.x, +; CM-NEXT: ADD_INT T0.Z, KC0[2].Y, literal.y, +; CM-NEXT: MUL_IEEE * T0.W, KC0[3].Z, T1.Y, +; CM-NEXT: 1107296256(3.200000e+01), 8(1.121039e-44) +; CM-NEXT: LOG_IEEE T0.X (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W, T0.W, +; CM-NEXT: LSHR T2.X, T0.Z, literal.x, +; CM-NEXT: ADD T0.Y, PV.W, -T0.Y, +; CM-NEXT: CNDE T0.Z, T1.W, 0.0, literal.y, +; CM-NEXT: MUL_IEEE * T0.W, KC0[3].Y, T0.X, +; CM-NEXT: 2(2.802597e-45), 1107296256(3.200000e+01) +; CM-NEXT: LOG_IEEE T0.X, T0.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: ADD * T0.X, PV.X, -T0.Z, +; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, -; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; CM-NEXT: LOG_IEEE T2.X, KC0[3].W, -; CM-NEXT: LOG_IEEE T2.Y (MASKED), KC0[3].W, -; CM-NEXT: LOG_IEEE T2.Z (MASKED), KC0[3].W, -; CM-NEXT: LOG_IEEE * T2.W (MASKED), KC0[3].W, -; CM-NEXT: LOG_IEEE T3.X (MASKED), KC0[3].Z, -; CM-NEXT: LOG_IEEE T3.Y, KC0[3].Z, -; CM-NEXT: LOG_IEEE T3.Z (MASKED), KC0[3].Z, -; CM-NEXT: LOG_IEEE * T3.W (MASKED), KC0[3].Z, -; CM-NEXT: LOG_IEEE T3.X, KC0[3].Y, -; CM-NEXT: LOG_IEEE T3.Y (MASKED), KC0[3].Y, -; CM-NEXT: LOG_IEEE T3.Z (MASKED), KC0[3].Y, -; CM-NEXT: LOG_IEEE * T3.W (MASKED), KC0[3].Y, %result = call <3 x float> @llvm.log2.v3f32(<3 x float> %in) store <3 x float> %result, ptr addrspace(1) %out ret void @@ -304,42 +670,114 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in) { ; SI-SDAG-LABEL: s_log2_v4f32: ; SI-SDAG: ; %bb.0: -; SI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd -; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000 -; SI-SDAG-NEXT: s_mov_b32 s2, -1 +; SI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd +; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000 ; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; SI-SDAG-NEXT: v_log_f32_e32 v3, s7 -; SI-SDAG-NEXT: v_log_f32_e32 v2, s6 -; SI-SDAG-NEXT: v_log_f32_e32 v1, s5 -; SI-SDAG-NEXT: v_log_f32_e32 v0, s4 -; SI-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v3, vcc +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v7, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc +; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v4, s3, v4 +; SI-SDAG-NEXT: v_mul_f32_e32 v6, s2, v6 +; SI-SDAG-NEXT: v_mul_f32_e32 v8, s1, v8 +; SI-SDAG-NEXT: v_mul_f32_e32 v1, s0, v1 +; SI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; SI-SDAG-NEXT: v_log_f32_e32 v6, v6 +; SI-SDAG-NEXT: v_log_f32_e32 v8, v8 +; SI-SDAG-NEXT: v_log_f32_e32 v9, v1 +; SI-SDAG-NEXT: s_mov_b32 s6, -1 +; SI-SDAG-NEXT: v_sub_f32_e32 v3, v4, v2 +; SI-SDAG-NEXT: v_sub_f32_e32 v2, v6, v5 +; SI-SDAG-NEXT: v_sub_f32_e32 v1, v8, v7 +; SI-SDAG-NEXT: v_sub_f32_e32 v0, v9, v0 +; SI-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; SI-SDAG-NEXT: s_endpgm ; ; SI-GISEL-LABEL: s_log2_v4f32: ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd -; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; SI-GISEL-NEXT: s_mov_b32 s2, -1 -; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 +; SI-GISEL-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9 +; SI-GISEL-NEXT: s_mov_b32 s0, 0x800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x42000000 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; SI-GISEL-NEXT: v_log_f32_e32 v0, s4 -; SI-GISEL-NEXT: v_log_f32_e32 v1, s5 -; SI-GISEL-NEXT: v_log_f32_e32 v2, s6 -; SI-GISEL-NEXT: v_log_f32_e32 v3, s7 -; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 +; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, s5 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc +; SI-GISEL-NEXT: v_cmp_gt_f32_e64 s[0:1], s0, v1 +; SI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v3, s[0:1] +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mul_f32_e32 v1, s5, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v1, v1 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1] +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2 +; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1] +; SI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v5 +; SI-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2 +; SI-GISEL-NEXT: v_log_f32_e32 v5, v5 +; SI-GISEL-NEXT: v_log_f32_e32 v3, v2 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1] +; SI-GISEL-NEXT: v_sub_f32_e32 v2, v5, v2 +; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 +; SI-GISEL-NEXT: s_mov_b32 s10, -1 +; SI-GISEL-NEXT: s_mov_b32 s11, 0xf000 +; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 ; SI-GISEL-NEXT: s_endpgm ; ; VI-SDAG-LABEL: s_log2_v4f32: ; VI-SDAG: ; %bb.0: ; VI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; VI-SDAG-NEXT: v_log_f32_e32 v3, s7 -; VI-SDAG-NEXT: v_log_f32_e32 v2, s6 -; VI-SDAG-NEXT: v_log_f32_e32 v1, s5 -; VI-SDAG-NEXT: v_log_f32_e32 v0, s4 +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v3, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v7, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v8, 1.0, v3, vcc +; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; VI-SDAG-NEXT: v_mul_f32_e32 v4, s7, v4 +; VI-SDAG-NEXT: v_mul_f32_e32 v6, s6, v6 +; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc +; VI-SDAG-NEXT: v_log_f32_e32 v4, v4 +; VI-SDAG-NEXT: v_log_f32_e32 v6, v6 +; VI-SDAG-NEXT: v_mul_f32_e32 v8, s5, v8 +; VI-SDAG-NEXT: v_mul_f32_e32 v1, s4, v1 +; VI-SDAG-NEXT: v_log_f32_e32 v8, v8 +; VI-SDAG-NEXT: v_log_f32_e32 v9, v1 +; VI-SDAG-NEXT: v_sub_f32_e32 v3, v4, v2 +; VI-SDAG-NEXT: v_sub_f32_e32 v2, v6, v5 ; VI-SDAG-NEXT: v_mov_b32_e32 v5, s1 +; VI-SDAG-NEXT: v_sub_f32_e32 v1, v8, v7 +; VI-SDAG-NEXT: v_sub_f32_e32 v0, v9, v0 ; VI-SDAG-NEXT: v_mov_b32_e32 v4, s0 ; VI-SDAG-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; VI-SDAG-NEXT: s_endpgm @@ -347,14 +785,40 @@ ; VI-GISEL-LABEL: s_log2_v4f32: ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 -; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; VI-GISEL-NEXT: s_mov_b32 s0, 0x800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x42000000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; VI-GISEL-NEXT: v_log_f32_e32 v0, s4 -; VI-GISEL-NEXT: v_log_f32_e32 v1, s5 -; VI-GISEL-NEXT: v_log_f32_e32 v2, s6 -; VI-GISEL-NEXT: v_log_f32_e32 v3, s7 -; VI-GISEL-NEXT: v_mov_b32_e32 v5, s1 -; VI-GISEL-NEXT: v_mov_b32_e32 v4, s0 +; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, s5 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc +; VI-GISEL-NEXT: v_cmp_gt_f32_e64 s[0:1], s0, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v3, s[0:1] +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mul_f32_e32 v1, s5, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v1, v1 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1] +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2 +; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1] +; VI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v5 +; VI-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2 +; VI-GISEL-NEXT: v_log_f32_e32 v5, v5 +; VI-GISEL-NEXT: v_log_f32_e32 v3, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1] +; VI-GISEL-NEXT: v_sub_f32_e32 v2, v5, v2 +; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 +; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, s2 ; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; VI-GISEL-NEXT: s_endpgm ; @@ -362,12 +826,35 @@ ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX900-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-SDAG-NEXT: v_log_f32_e32 v3, s7 -; GFX900-SDAG-NEXT: v_log_f32_e32 v2, s6 -; GFX900-SDAG-NEXT: v_log_f32_e32 v1, s5 -; GFX900-SDAG-NEXT: v_log_f32_e32 v0, s4 +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v7, 1.0, v3, vcc +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v8, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v9, 1.0, v3, vcc +; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc +; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, s7, v5 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v7, s6, v7 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v9, s5, v9 +; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, s4, v1 +; GFX900-SDAG-NEXT: v_log_f32_e32 v5, v5 +; GFX900-SDAG-NEXT: v_log_f32_e32 v7, v7 +; GFX900-SDAG-NEXT: v_log_f32_e32 v9, v9 +; GFX900-SDAG-NEXT: v_log_f32_e32 v10, v1 +; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v5, v2 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v7, v6 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v9, v8 +; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v10, v0 ; GFX900-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX900-SDAG-NEXT: s_endpgm ; @@ -375,65 +862,167 @@ ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX900-GISEL-NEXT: s_mov_b32 s0, 0x800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x42000000 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s4 -; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s5 -; GFX900-GISEL-NEXT: v_log_f32_e32 v2, s6 -; GFX900-GISEL-NEXT: v_log_f32_e32 v3, s7 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc +; GFX900-GISEL-NEXT: v_cmp_gt_f32_e64 s[0:1], s0, v1 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v3, s[0:1] +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s5, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1] +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1] +; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s6, v5 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2 +; GFX900-GISEL-NEXT: v_log_f32_e32 v5, v5 +; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v2 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1] +; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v5, v2 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0 ; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX900-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log2_v4f32: ; R600: ; %bb.0: -; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[] +; R600-NEXT: ALU 33, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 ; R600-NEXT: CF_END ; R600-NEXT: PAD ; R600-NEXT: ALU clause starting at 4: -; R600-NEXT: LOG_IEEE * T0.W, KC0[4].X, -; R600-NEXT: LOG_IEEE * T0.Z, KC0[3].W, -; R600-NEXT: LOG_IEEE * T0.Y, KC0[3].Z, -; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x, -; R600-NEXT: LOG_IEEE * T0.X, KC0[3].Y, +; R600-NEXT: SETGT T0.W, literal.x, KC0[4].X, +; R600-NEXT: SETGT * T1.W, literal.x, KC0[3].W, +; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; R600-NEXT: CNDE * T2.W, PV.W, 1.0, literal.x, +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T0.Z, KC0[4].X, PV.W, +; R600-NEXT: SETGT T2.W, literal.x, KC0[3].Z, +; R600-NEXT: CNDE * T3.W, T1.W, 1.0, literal.y, +; R600-NEXT: 8388608(1.175494e-38), 1333788672(4.294967e+09) +; R600-NEXT: MUL_IEEE T0.X, KC0[3].W, PS, +; R600-NEXT: CNDE T0.Y, T0.W, 0.0, literal.x, +; R600-NEXT: SETGT T1.Z, literal.y, KC0[3].Y, +; R600-NEXT: CNDE T0.W, PV.W, 1.0, literal.z, +; R600-NEXT: LOG_IEEE * T0.Z, PV.Z, +; R600-NEXT: 1107296256(3.200000e+01), 8388608(1.175494e-38) +; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00) +; R600-NEXT: MUL_IEEE T1.X, KC0[3].Z, PV.W, +; R600-NEXT: CNDE T1.Y, T1.W, 0.0, literal.x, +; R600-NEXT: CNDE T2.Z, PV.Z, 1.0, literal.y, +; R600-NEXT: ADD T0.W, PS, -PV.Y, +; R600-NEXT: LOG_IEEE * T0.X, PV.X, +; R600-NEXT: 1107296256(3.200000e+01), 1333788672(4.294967e+09) +; R600-NEXT: MUL_IEEE T2.Y, KC0[3].Y, PV.Z, +; R600-NEXT: ADD T0.Z, PS, -PV.Y, +; R600-NEXT: CNDE T1.W, T2.W, 0.0, literal.x, +; R600-NEXT: LOG_IEEE * T0.X, PV.X, +; R600-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; R600-NEXT: ADD T0.Y, PS, -PV.W, +; R600-NEXT: CNDE T1.W, T1.Z, 0.0, literal.x, +; R600-NEXT: LOG_IEEE * T0.X, PV.Y, +; R600-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; R600-NEXT: ADD T0.X, PS, -PV.W, +; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; ; CM-LABEL: s_log2_v4f32: ; CM: ; %bb.0: -; CM-NEXT: ALU 17, @4, KC0[CB0:0-32], KC1[] -; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T0.X +; CM-NEXT: ALU 43, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X ; CM-NEXT: CF_END ; CM-NEXT: PAD ; CM-NEXT: ALU clause starting at 4: -; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, +; CM-NEXT: SETGT * T0.W, literal.x, KC0[4].X, +; CM-NEXT: 8388608(1.175494e-38), 0(0.000000e+00) +; CM-NEXT: CNDE T0.Y, PV.W, 1.0, literal.x, +; CM-NEXT: SETGT T0.Z, literal.y, KC0[3].W, +; CM-NEXT: SETGT * T1.W, literal.y, KC0[3].Z, +; CM-NEXT: 1333788672(4.294967e+09), 8388608(1.175494e-38) +; CM-NEXT: CNDE T0.X, PV.W, 1.0, literal.x, +; CM-NEXT: CNDE T1.Y, T0.W, 0.0, literal.y, +; CM-NEXT: CNDE T1.Z, PV.Z, 1.0, literal.x, +; CM-NEXT: MUL_IEEE * T0.W, KC0[4].X, PV.Y, +; CM-NEXT: 1333788672(4.294967e+09), 1107296256(3.200000e+01) +; CM-NEXT: LOG_IEEE T0.X (MASKED), T0.W, +; CM-NEXT: LOG_IEEE T0.Y, T0.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.W, +; CM-NEXT: CNDE T1.X, T0.Z, 0.0, literal.x, +; CM-NEXT: SETGT T2.Y, literal.y, KC0[3].Y, +; CM-NEXT: MUL_IEEE T0.Z, KC0[3].W, T1.Z, +; CM-NEXT: ADD * T0.W, PV.Y, -T1.Y, +; CM-NEXT: 1107296256(3.200000e+01), 8388608(1.175494e-38) +; CM-NEXT: LOG_IEEE T0.X (MASKED), T0.Z, +; CM-NEXT: LOG_IEEE T0.Y, T0.Z, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T0.Z, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T0.Z, +; CM-NEXT: CNDE T2.X, T2.Y, 1.0, literal.x, +; CM-NEXT: CNDE T1.Y, T1.W, 0.0, literal.y, +; CM-NEXT: ADD T0.Z, PV.Y, -T1.X, +; CM-NEXT: MUL_IEEE * T1.W, KC0[3].Z, T0.X, BS:VEC_021/SCL_122 +; CM-NEXT: 1333788672(4.294967e+09), 1107296256(3.200000e+01) +; CM-NEXT: LOG_IEEE T0.X, T1.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T1.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T1.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T1.W, +; CM-NEXT: ADD T0.Y, PV.X, -T1.Y, +; CM-NEXT: CNDE T1.Z, T2.Y, 0.0, literal.x, +; CM-NEXT: MUL_IEEE * T1.W, KC0[3].Y, T2.X, +; CM-NEXT: 1107296256(3.200000e+01), 0(0.000000e+00) +; CM-NEXT: LOG_IEEE T0.X, T1.W, +; CM-NEXT: LOG_IEEE T0.Y (MASKED), T1.W, +; CM-NEXT: LOG_IEEE T0.Z (MASKED), T1.W, +; CM-NEXT: LOG_IEEE * T0.W (MASKED), T1.W, +; CM-NEXT: ADD * T0.X, PV.X, -T1.Z, +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; CM-NEXT: LOG_IEEE T1.X (MASKED), KC0[4].X, -; CM-NEXT: LOG_IEEE T1.Y (MASKED), KC0[4].X, -; CM-NEXT: LOG_IEEE T1.Z (MASKED), KC0[4].X, -; CM-NEXT: LOG_IEEE * T1.W, KC0[4].X, -; CM-NEXT: LOG_IEEE T1.X (MASKED), KC0[3].W, -; CM-NEXT: LOG_IEEE T1.Y (MASKED), KC0[3].W, -; CM-NEXT: LOG_IEEE T1.Z, KC0[3].W, -; CM-NEXT: LOG_IEEE * T1.W (MASKED), KC0[3].W, -; CM-NEXT: LOG_IEEE T1.X (MASKED), KC0[3].Z, -; CM-NEXT: LOG_IEEE T1.Y, KC0[3].Z, -; CM-NEXT: LOG_IEEE T1.Z (MASKED), KC0[3].Z, -; CM-NEXT: LOG_IEEE * T1.W (MASKED), KC0[3].Z, -; CM-NEXT: LOG_IEEE T1.X, KC0[3].Y, -; CM-NEXT: LOG_IEEE T1.Y (MASKED), KC0[3].Y, -; CM-NEXT: LOG_IEEE T1.Z (MASKED), KC0[3].Y, -; CM-NEXT: LOG_IEEE * T1.W (MASKED), KC0[3].Y, %result = call <4 x float> @llvm.log2.v4f32(<4 x float> %in) store <4 x float> %result, ptr addrspace(1) %out ret void } define float @v_log2_f32(float %in) { -; GCN-LABEL: v_log2_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log2_f32: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log2_f32: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log2_f32: ; R600: ; %bb.0: @@ -449,11 +1038,33 @@ } define float @v_log2_fabs_f32(float %in) { -; GCN-LABEL: v_log2_fabs_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e64 v0, |v0| -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log2_fabs_f32: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log2_fabs_f32: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log2_fabs_f32: ; R600: ; %bb.0: @@ -470,11 +1081,33 @@ } define float @v_log2_fneg_fabs_f32(float %in) { -; GCN-LABEL: v_log2_fneg_fabs_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e64 v0, -|v0| -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log2_fneg_fabs_f32: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x80800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e64 v0, -|v0|, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log2_fneg_fabs_f32: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e64 v0, -|v0|, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log2_fneg_fabs_f32: ; R600: ; %bb.0: @@ -492,11 +1125,33 @@ } define float @v_log2_fneg_f32(float %in) { -; GCN-LABEL: v_log2_fneg_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e64 v0, -v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log2_fneg_f32: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x80800000 +; GCN-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e64 v0, -v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log2_fneg_f32: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e64 v0, -v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log2_fneg_f32: ; R600: ; %bb.0: @@ -573,11 +1228,33 @@ } define float @v_log2_f32_ninf(float %in) { -; GCN-LABEL: v_log2_f32_ninf: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log2_f32_ninf: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log2_f32_ninf: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log2_f32_ninf: ; R600: ; %bb.0: @@ -694,11 +1371,33 @@ } define float @v_log2_f32_nnan(float %in) { -; GCN-LABEL: v_log2_f32_nnan: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log2_f32_nnan: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log2_f32_nnan: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log2_f32_nnan: ; R600: ; %bb.0: @@ -734,11 +1433,33 @@ } define float @v_log2_f32_nnan_dynamic(float %in) #1 { -; GCN-LABEL: v_log2_f32_nnan_dynamic: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log2_f32_nnan_dynamic: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log2_f32_nnan_dynamic: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log2_f32_nnan_dynamic: ; R600: ; %bb.0: @@ -774,11 +1495,33 @@ } define float @v_log2_f32_ninf_dynamic(float %in) #1 { -; GCN-LABEL: v_log2_f32_ninf_dynamic: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log2_f32_ninf_dynamic: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log2_f32_ninf_dynamic: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log2_f32_ninf_dynamic: ; R600: ; %bb.0: @@ -794,11 +1537,33 @@ } define float @v_log2_f32_nnan_ninf(float %in) { -; GCN-LABEL: v_log2_f32_nnan_ninf: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log2_f32_nnan_ninf: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log2_f32_nnan_ninf: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log2_f32_nnan_ninf: ; R600: ; %bb.0: @@ -834,11 +1599,33 @@ } define float @v_log2_f32_nnan_ninf_dynamic(float %in) #1 { -; GCN-LABEL: v_log2_f32_nnan_ninf_dynamic: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log2_f32_nnan_ninf_dynamic: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log2_f32_nnan_ninf_dynamic: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log2_f32_nnan_ninf_dynamic: ; R600: ; %bb.0: @@ -874,11 +1661,33 @@ } define float @v_log2_f32_dynamic_mode(float %in) #1 { -; GCN-LABEL: v_log2_f32_dynamic_mode: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, v0 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log2_f32_dynamic_mode: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log2_f32_dynamic_mode: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc +; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log2_f32_dynamic_mode: ; R600: ; %bb.0: @@ -894,11 +1703,26 @@ } define float @v_log2_f32_undef() { -; GCN-LABEL: v_log2_f32_undef: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_log_f32_e32 v0, s4 -; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-SDAG-LABEL: v_log2_f32_undef: +; GCN-SDAG: ; %bb.0: +; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: v_log_f32_e32 v0, s4 +; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GCN-GISEL-LABEL: v_log2_f32_undef: +; GCN-GISEL: ; %bb.0: +; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GCN-GISEL-NEXT: v_mul_f32_e32 v1, s4, v1 +; GCN-GISEL-NEXT: v_mul_f32_e64 v2, s4, 1.0 +; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc +; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_log2_f32_undef: ; R600: ; %bb.0: @@ -918,6 +1742,7 @@ ; GCN-SDAG: ; %bb.0: ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-SDAG-NEXT: v_log_f32_e32 v0, 0 +; GCN-SDAG-NEXT: v_add_f32_e32 v0, 0xc2000000, v0 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; GCN-GISEL-LABEL: v_log2_f32_0: @@ -978,8 +1803,16 @@ ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000 ; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: v_log_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; SI-GISEL-LABEL: v_log2_f32_from_fpext_math_f16: @@ -1037,7 +1870,15 @@ ; GCN-SDAG-LABEL: v_log2_f32_from_fpext_bf16: ; GCN-SDAG: ; %bb.0: ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-SDAG-NEXT: s_mov_b32 s4, 0x800000 +; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc +; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 ; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 +; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; GCN-GISEL-LABEL: v_log2_f32_from_fpext_bf16: @@ -1072,6 +1913,7 @@ ret float %result } +; FIXME: Fold out fp16_to_fp (FP_TO_FP16) on no-f16 targets define half @v_log2_f16(half %in) { ; SI-SDAG-LABEL: v_log2_f16: ; SI-SDAG: ; %bb.0: @@ -1079,6 +1921,8 @@ ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-SDAG-NEXT: v_log_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; SI-GISEL-LABEL: v_log2_f16: @@ -1126,6 +1970,8 @@ ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 ; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0| ; SI-SDAG-NEXT: v_log_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; SI-GISEL-LABEL: v_log2_fabs_f16: @@ -1174,6 +2020,8 @@ ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 ; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, -|v0| ; SI-SDAG-NEXT: v_log_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; SI-GISEL-LABEL: v_log2_fneg_fabs_f16: @@ -1223,6 +2071,8 @@ ; SI-SDAG-NEXT: v_cvt_f16_f32_e64 v0, -v0 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-SDAG-NEXT: v_log_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; SI-GISEL-LABEL: v_log2_fneg_f16: @@ -1271,6 +2121,8 @@ ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-SDAG-NEXT: v_log_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; SI-GISEL-LABEL: v_log2_f16_fast: @@ -1321,6 +2173,10 @@ ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-SDAG-NEXT: v_log_f32_e32 v0, v0 ; SI-SDAG-NEXT: v_log_f32_e32 v1, v1 +; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; SI-GISEL-LABEL: v_log2_v2f16: @@ -1389,6 +2245,10 @@ ; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v1, |v1| ; SI-SDAG-NEXT: v_log_f32_e32 v0, v0 ; SI-SDAG-NEXT: v_log_f32_e32 v1, v1 +; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; SI-GISEL-LABEL: v_log2_fabs_v2f16: @@ -1469,6 +2329,10 @@ ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-SDAG-NEXT: v_log_f32_e32 v0, v0 ; SI-SDAG-NEXT: v_log_f32_e32 v1, v1 +; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; SI-GISEL-LABEL: v_log2_fneg_fabs_v2f16: @@ -1550,6 +2414,10 @@ ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-SDAG-NEXT: v_log_f32_e32 v0, v0 ; SI-SDAG-NEXT: v_log_f32_e32 v1, v1 +; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; SI-GISEL-LABEL: v_log2_fneg_v2f16: @@ -1626,6 +2494,10 @@ ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-SDAG-NEXT: v_log_f32_e32 v0, v0 ; SI-SDAG-NEXT: v_log_f32_e32 v1, v1 +; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; SI-GISEL-LABEL: v_log2_v2f16_fast: @@ -1697,3 +2569,5 @@ attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" } attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" } attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; SI: {{.*}}