diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -16391,6 +16391,23 @@
   if (SDValue R = performANDORCSELCombine(N, DAG))
     return R;
 
+  SDLoc DL(N);
+  AArch64CC::CondCode AArch64CC;
+  SDValue Cmp,Cset;
+
+  if (!DCI.isBeforeLegalize() &&
+    (Cmp = emitConjunction(DAG, SDValue(N, 0), AArch64CC))){
+
+  unsigned ZeroReg = VT.getSizeInBits() == 32 ? AArch64::WZR : AArch64::XZR;
+  AArch64CC::CondCode InvertedCC = AArch64CC::getInvertedCondCode(AArch64CC);
+
+  Cset = DAG.getNode(AArch64ISD::CSINC, DL, VT,
+                    DAG.getRegister(ZeroReg, VT), DAG.getRegister(ZeroReg, VT),
+                    DAG.getConstant(InvertedCC, DL, MVT::i32), Cmp);
+
+  return Cset;
+  }
+
   if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
     return SDValue();