diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -296,9 +296,13 @@
   Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
 
   if (IsStridedOrIndexed) {
-    Operands.push_back(Node->getOperand(CurOp++)); // Index.
+    SDValue StrideOrIndex = Node->getOperand(CurOp++);
+    if (IndexVT && StrideOrIndex.hasOneUse() &&
+        StrideOrIndex.getOpcode() == ISD::ZERO_EXTEND)
+      StrideOrIndex = StrideOrIndex.getOperand(0);
+    Operands.push_back(StrideOrIndex); // Index.
     if (IndexVT)
-      *IndexVT = Operands.back()->getSimpleValueType(0);
+      *IndexVT = StrideOrIndex->getSimpleValueType(0);
   }
 
   if (IsMasked) {
diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
@@ -1343,10 +1343,9 @@
 define <vscale x 1 x i64> @intrinsic_vloxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vzext.vf8 v9, v8
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vloxei64.v v8, (a0), v9
+; CHECK-NEXT:    vloxei8.v v9, (a0), v8
+; CHECK-NEXT:    vmv.v.v v8, v9
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %1 to <vscale x 1 x i64>
@@ -1362,10 +1361,8 @@
 define <vscale x 1 x i64> @intrinsic_vloxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vzext.vf8 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxei.ll b/llvm/test/CodeGen/RISCV/rvv/vloxei.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vloxei.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vloxei.ll
@@ -5066,10 +5066,9 @@
 define <vscale x 1 x i64> @intrinsic_vloxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vzext.vf4 v9, v8
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vloxei32.v v8, (a0), v9
+; CHECK-NEXT:    vloxei8.v v9, (a0), v8
+; CHECK-NEXT:    vmv.v.v v8, v9
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %1 to <vscale x 1 x i32>
@@ -5085,10 +5084,8 @@
 define <vscale x 1 x i64> @intrinsic_vloxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vzext.vf4 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
@@ -1344,10 +1344,9 @@
 define <vscale x 1 x i64> @intrinsic_vluxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vzext.vf8 v9, v8
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vluxei64.v v8, (a0), v9
+; CHECK-NEXT:    vluxei8.v v9, (a0), v8
+; CHECK-NEXT:    vmv.v.v v8, v9
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %1 to <vscale x 1 x i64>
@@ -1363,10 +1362,8 @@
 define <vscale x 1 x i64> @intrinsic_vluxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vzext.vf8 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vluxei.ll b/llvm/test/CodeGen/RISCV/rvv/vluxei.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vluxei.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vluxei.ll
@@ -5066,10 +5066,9 @@
 define <vscale x 1 x i64> @intrinsic_vluxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vzext.vf4 v9, v8
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vluxei32.v v8, (a0), v9
+; CHECK-NEXT:    vluxei8.v v9, (a0), v8
+; CHECK-NEXT:    vmv.v.v v8, v9
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %1 to <vscale x 1 x i32>
@@ -5085,10 +5084,8 @@
 define <vscale x 1 x i64> @intrinsic_vluxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vzext.vf4 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
@@ -1295,10 +1295,8 @@
 define void @intrinsic_vsoxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
 ; CHECK-LABEL: intrinsic_vsoxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vzext.vf8 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vsoxei64.v v8, (a0), v10
+; CHECK-NEXT:    vsoxei8.v v8, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
@@ -1314,10 +1312,8 @@
 define void @intrinsic_vsoxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 ; CHECK-LABEL: intrinsic_vsoxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vzext.vf8 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vsoxei64.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vsoxei8.v v8, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsoxei.ll b/llvm/test/CodeGen/RISCV/rvv/vsoxei.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vsoxei.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsoxei.ll
@@ -4882,10 +4882,8 @@
 define void @intrinsic_vsoxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vsoxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vzext.vf4 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vsoxei32.v v8, (a0), v10
+; CHECK-NEXT:    vsoxei8.v v8, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
@@ -4901,10 +4899,8 @@
 define void @intrinsic_vsoxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
 ; CHECK-LABEL: intrinsic_vsoxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vzext.vf4 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vsoxei32.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vsoxei8.v v8, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
@@ -1295,10 +1295,8 @@
 define void @intrinsic_vsuxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
 ; CHECK-LABEL: intrinsic_vsuxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vzext.vf8 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vsuxei64.v v8, (a0), v10
+; CHECK-NEXT:    vsuxei8.v v8, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
@@ -1314,10 +1312,8 @@
 define void @intrinsic_vsuxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 ; CHECK-LABEL: intrinsic_vsuxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vzext.vf8 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vsuxei64.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxei8.v v8, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsuxei.ll b/llvm/test/CodeGen/RISCV/rvv/vsuxei.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vsuxei.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsuxei.ll
@@ -4882,10 +4882,8 @@
 define void @intrinsic_vsuxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vsuxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vzext.vf4 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vsuxei32.v v8, (a0), v10
+; CHECK-NEXT:    vsuxei8.v v8, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
@@ -4901,10 +4899,8 @@
 define void @intrinsic_vsuxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
 ; CHECK-LABEL: intrinsic_vsuxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vzext.vf4 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vsuxei32.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxei8.v v8, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>