diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll @@ -1,10 +1,11 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; This test just checks that the compiler doesn't crash. -; FUNC-LABEL: {{^}}v32i8_to_v8i32: +; GCN-LABEL: {{^}}v32i8_to_v8i32: define amdgpu_ps float @v32i8_to_v8i32(ptr addrspace(4) inreg) #0 { entry: %1 = load <32 x i8>, ptr addrspace(4) %0 @@ -15,8 +16,8 @@ ret float %5 } -; FUNC-LABEL: {{^}}i8ptr_v16i8ptr: -; SI: s_endpgm +; GCN-LABEL: {{^}}i8ptr_v16i8ptr: +; GCN: s_endpgm define amdgpu_kernel void @i8ptr_v16i8ptr(ptr addrspace(1) %out, ptr addrspace(1) %in) { entry: %0 = load <16 x i8>, ptr addrspace(1) %in @@ -74,8 +75,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v2i32_to_f64: -; SI: s_endpgm +; GCN-LABEL: {{^}}bitcast_v2i32_to_f64: +; GCN: s_endpgm define amdgpu_kernel void @bitcast_v2i32_to_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) { %val = load <2 x i32>, ptr addrspace(1) %in, align 8 %add = add <2 x i32> %val, @@ -85,8 +86,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_f64_to_v2i32: -; SI: s_endpgm +; GCN-LABEL: {{^}}bitcast_f64_to_v2i32: +; GCN: s_endpgm define amdgpu_kernel void @bitcast_f64_to_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) { %val = load double, ptr addrspace(1) %in, align 8 %add = fadd double %val, 4.0 @@ -95,7 +96,7 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v2i64_to_v2f64: +; GCN-LABEL: {{^}}bitcast_v2i64_to_v2f64: define amdgpu_kernel void @bitcast_v2i64_to_v2f64(i32 %cond, ptr addrspace(1) %out, <2 x i64> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -111,7 +112,7 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v2f64_to_v2i64: +; GCN-LABEL: {{^}}bitcast_v2f64_to_v2i64: define amdgpu_kernel void @bitcast_v2f64_to_v2i64(i32 %cond, ptr addrspace(1) %out, <2 x double> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -127,7 +128,7 @@ ret void } -; FUNC-LABEL: {{^}}v4i16_to_f64: +; GCN-LABEL: {{^}}v4i16_to_f64: define amdgpu_kernel void @v4i16_to_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { %load = load <4 x i16>, ptr addrspace(1) %in, align 4 %add.v4i16 = add <4 x i16> %load, @@ -137,7 +138,7 @@ ret void } -; FUNC-LABEL: {{^}}v4f16_to_f64: +; GCN-LABEL: {{^}}v4f16_to_f64: define amdgpu_kernel void @v4f16_to_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { %load = load <4 x half>, ptr addrspace(1) %in, align 4 %add.v4half = fadd <4 x half> %load, @@ -147,7 +148,7 @@ ret void } -; FUNC-LABEL: {{^}}f64_to_v4f16: +; GCN-LABEL: {{^}}f64_to_v4f16: define amdgpu_kernel void @f64_to_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { %load = load double, ptr addrspace(1) %in, align 4 %fadd32 = fadd double %load, 1.0 @@ -157,7 +158,7 @@ ret void } -; FUNC-LABEL: {{^}}f64_to_v4i16: +; GCN-LABEL: {{^}}f64_to_v4i16: define amdgpu_kernel void @f64_to_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { %load = load double, ptr addrspace(1) %in, align 4 %fadd32 = fadd double %load, 1.0 @@ -167,7 +168,7 @@ ret void } -; FUNC-LABEL: {{^}}v4i16_to_i64: +; GCN-LABEL: {{^}}v4i16_to_i64: define amdgpu_kernel void @v4i16_to_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { %load = load <4 x i16>, ptr addrspace(1) %in, align 4 %add.v4i16 = add <4 x i16> %load, @@ -177,7 +178,7 @@ ret void } -; FUNC-LABEL: {{^}}v4f16_to_i64: +; GCN-LABEL: {{^}}v4f16_to_i64: define amdgpu_kernel void @v4f16_to_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { %load = load <4 x half>, ptr addrspace(1) %in, align 4 %add.v4half = fadd <4 x half> %load, @@ -187,7 +188,7 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_i64_to_v4i16: +; GCN-LABEL: {{^}}bitcast_i64_to_v4i16: define amdgpu_kernel void @bitcast_i64_to_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in) { %val = load i64, ptr addrspace(1) %in, align 8 %add = add i64 %val, 4 @@ -197,7 +198,7 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_i64_to_v4f16: +; GCN-LABEL: {{^}}bitcast_i64_to_v4f16: define amdgpu_kernel void @bitcast_i64_to_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %in) { %val = load i64, ptr addrspace(1) %in, align 8 %add = add i64 %val, 4 @@ -207,7 +208,7 @@ ret void } -; FUNC-LABEL: {{^}}v4i16_to_v2f32: +; GCN-LABEL: {{^}}v4i16_to_v2f32: define amdgpu_kernel void @v4i16_to_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { %load = load <4 x i16>, ptr addrspace(1) %in, align 4 %add.v4i16 = add <4 x i16> %load, @@ -217,7 +218,7 @@ ret void } -; FUNC-LABEL: {{^}}v4f16_to_v2f32: +; GCN-LABEL: {{^}}v4f16_to_v2f32: define amdgpu_kernel void @v4f16_to_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { %load = load <4 x half>, ptr addrspace(1) %in, align 4 %add.v4half = fadd <4 x half> %load, @@ -227,7 +228,7 @@ ret void } -; FUNC-LABEL: {{^}}v2f32_to_v4i16: +; GCN-LABEL: {{^}}v2f32_to_v4i16: define amdgpu_kernel void @v2f32_to_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { %load = load <2 x float>, ptr addrspace(1) %in, align 4 %add.v2f32 = fadd <2 x float> %load, @@ -237,7 +238,7 @@ ret void } -; FUNC-LABEL: {{^}}v2f32_to_v4f16: +; GCN-LABEL: {{^}}v2f32_to_v4f16: define amdgpu_kernel void @v2f32_to_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { %load = load <2 x float>, ptr addrspace(1) %in, align 4 %add.v2f32 = fadd <2 x float> %load, @@ -247,7 +248,7 @@ ret void } -; FUNC-LABEL: {{^}}v4i16_to_v2i32: +; GCN-LABEL: {{^}}v4i16_to_v2i32: define amdgpu_kernel void @v4i16_to_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { %load = load <4 x i16>, ptr addrspace(1) %in, align 4 %add.v4i16 = add <4 x i16> %load, @@ -257,7 +258,7 @@ ret void } -; FUNC-LABEL: {{^}}v4f16_to_v2i32: +; GCN-LABEL: {{^}}v4f16_to_v2i32: define amdgpu_kernel void @v4f16_to_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { %load = load <4 x half>, ptr addrspace(1) %in, align 4 %add.v4half = fadd <4 x half> %load, @@ -267,7 +268,7 @@ ret void } -; FUNC-LABEL: {{^}}v2i32_to_v4i16: +; GCN-LABEL: {{^}}v2i32_to_v4i16: define amdgpu_kernel void @v2i32_to_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { %load = load <2 x i32>, ptr addrspace(1) %in, align 4 %add.v2i32 = add <2 x i32> %load, @@ -277,7 +278,7 @@ ret void } -; FUNC-LABEL: {{^}}v2i32_to_v4f16: +; GCN-LABEL: {{^}}v2i32_to_v4f16: define amdgpu_kernel void @v2i32_to_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { %load = load <2 x i32>, ptr addrspace(1) %in, align 4 %add.v2i32 = add <2 x i32> %load, @@ -289,8 +290,8 @@ declare <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32>, i32, i32 immarg) -; FUNC-LABEL: {{^}}bitcast_v4f32_to_v2i64: -; GCN: s_buffer_load_dwordx4 +; GCN-LABEL: {{^}}bitcast_v4f32_to_v2i64: +; GCN: s_buffer_load_{{dwordx4|b128}} define <2 x i64> @bitcast_v4f32_to_v2i64(<2 x i64> %arg) { %val = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> undef, i32 0, i32 0) %cast = bitcast <4 x float> %val to <2 x i64> @@ -300,7 +301,7 @@ declare half @llvm.canonicalize.f16(half) -; FUNC-LABEL: {{^}}bitcast_f32_to_v1i32: +; GCN-LABEL: {{^}}bitcast_f32_to_v1i32: define amdgpu_kernel void @bitcast_f32_to_v1i32(ptr addrspace(1) %out) { %f16 = call arcp afn half @llvm.canonicalize.f16(half 0xH03F0) %f32 = fpext half %f16 to float @@ -310,7 +311,7 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v4i64_to_v16i16: +; GCN-LABEL: {{^}}bitcast_v4i64_to_v16i16: define amdgpu_kernel void @bitcast_v4i64_to_v16i16(i32 %cond, ptr addrspace(1) %out, <4 x i64> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -328,7 +329,7 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v4f64_to_v16f16: +; GCN-LABEL: {{^}}bitcast_v4f64_to_v16f16: define amdgpu_kernel void @bitcast_v4f64_to_v16f16(i32 %cond, ptr addrspace(1) %out, <4 x double> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -346,7 +347,7 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v16i16_to_v4i64: +; GCN-LABEL: {{^}}bitcast_v16i16_to_v4i64: define amdgpu_kernel void @bitcast_v16i16_to_v4i64(i32 %cond, ptr addrspace(1) %out, <16 x i16> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -364,7 +365,7 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v16f16_to_v4f64: +; GCN-LABEL: {{^}}bitcast_v16f16_to_v4f64: define amdgpu_kernel void @bitcast_v16f16_to_v4f64(i32 %cond, ptr addrspace(1) %out, <16 x half> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -382,8 +383,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v20f16_to_v5f64: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v20f16_to_v5f64: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v20f16_to_v5f64(i32 %cond, ptr addrspace(1) %out, <20 x half> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -401,8 +402,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v10f32_to_v5f64: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v10f32_to_v5f64: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v10f32_to_v5f64(i32 %cond, ptr addrspace(1) %out, <10 x float> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -420,8 +421,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v10i32_to_v5f64: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v10i32_to_v5f64: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v10i32_to_v5f64(i32 %cond, ptr addrspace(1) %out, <10 x i32> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -439,8 +440,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v10f32_to_v5i64: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v10f32_to_v5i64: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v10f32_to_v5i64(i32 %cond, ptr addrspace(1) %out, <10 x float> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -458,8 +459,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v10i32_to_v5i64: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v10i32_to_v5i64: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v10i32_to_v5i64(i32 %cond, ptr addrspace(1) %out, <10 x i32> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -477,8 +478,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v40i8_to_v5f64: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v40i8_to_v5f64: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v40i8_to_v5f64(i32 %cond, ptr addrspace(1) %out, <40 x i8> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -496,8 +497,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v40i8_to_v5i64: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v40i8_to_v5i64: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v40i8_to_v5i64(i32 %cond, ptr addrspace(1) %out, <40 x i8> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -515,8 +516,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v5f64_to_v10f32: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v5f64_to_v10f32: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v5f64_to_v10f32(i32 %cond, ptr addrspace(1) %out, <5 x double> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -534,8 +535,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v5f64_to_v10i32: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v5f64_to_v10i32: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v5f64_to_v10i32(i32 %cond, ptr addrspace(1) %out, <5 x double> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -553,8 +554,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v5i64_to_v10f32: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v5i64_to_v10f32: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v5i64_to_v10f32(i32 %cond, ptr addrspace(1) %out, <5 x i64> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -572,8 +573,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v5i64_to_v10i32: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v5i64_to_v10i32: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v5i64_to_v10i32(i32 %cond, ptr addrspace(1) %out, <5 x i64> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -591,8 +592,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v6f64_to_v12i32: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v6f64_to_v12i32: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v6f64_to_v12i32(i32 %cond, ptr addrspace(1) %out, <6 x double> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -610,8 +611,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v6f64_to_v12f32: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v6f64_to_v12f32: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v6f64_to_v12f32(i32 %cond, ptr addrspace(1) %out, <6 x double> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -629,8 +630,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v12i32_to_v6i64: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v12i32_to_v6i64: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v12i32_to_v6i64(i32 %cond, ptr addrspace(1) %out, <12 x i32> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -648,8 +649,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v12i32_to_v6f64: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v12i32_to_v6f64: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v12i32_to_v6f64(i32 %cond, ptr addrspace(1) %out, <12 x i32> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -667,8 +668,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v6i64_to_v12i32: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v6i64_to_v12i32: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v6i64_to_v12i32(i32 %cond, ptr addrspace(1) %out, <6 x i64> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -686,8 +687,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v7i64_to_v14i32: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v7i64_to_v14i32: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v7i64_to_v14i32(i32 %cond, ptr addrspace(1) %out, <7 x i64> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -705,8 +706,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v7f64_to_v14i32: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v7f64_to_v14i32: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v7f64_to_v14i32(i32 %cond, ptr addrspace(1) %out, <7 x double> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -724,8 +725,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v9i64_to_v18i32: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v9i64_to_v18i32: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v9i64_to_v18i32(i32 %cond, ptr addrspace(1) %out, <9 x i64> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -743,8 +744,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v10i64_to_v20i32: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v10i64_to_v20i32: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v10i64_to_v20i32(i32 %cond, ptr addrspace(1) %out, <10 x i64> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -762,8 +763,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v11i64_to_v20i32: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v11i64_to_v20i32: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v11i64_to_v20i32(i32 %cond, ptr addrspace(1) %out, <11 x i64> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -781,8 +782,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v12i64_to_v22i32: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v12i64_to_v22i32: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v12i64_to_v22i32(i32 %cond, ptr addrspace(1) %out, <12 x i64> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -800,8 +801,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v13i64_to_v24i32: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v13i64_to_v24i32: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v13i64_to_v24i32(i32 %cond, ptr addrspace(1) %out, <13 x i64> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -819,8 +820,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v14i64_to_v26i32: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v14i64_to_v26i32: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v14i64_to_v26i32(i32 %cond, ptr addrspace(1) %out, <14 x i64> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -838,8 +839,8 @@ ret void } -; FUNC-LABEL: {{^}}bitcast_v15i64_to_v26i32: -; SI: ScratchSize: 0 +; GCN-LABEL: {{^}}bitcast_v15i64_to_v26i32: +; GCN: ScratchSize: 0 define amdgpu_kernel void @bitcast_v15i64_to_v26i32(i32 %cond, ptr addrspace(1) %out, <15 x i64> %value) { entry: %cmp0 = icmp eq i32 %cond, 0 diff --git a/llvm/test/CodeGen/AMDGPU/bitreverse.ll b/llvm/test/CodeGen/AMDGPU/bitreverse.ll --- a/llvm/test/CodeGen/AMDGPU/bitreverse.ll +++ b/llvm/test/CodeGen/AMDGPU/bitreverse.ll @@ -3,6 +3,8 @@ ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=FLAT ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=FLAT ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=fiji -global-isel -verify-machineinstrs | FileCheck %s --check-prefix=GISEL +; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=GFX11-FLAT +; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -global-isel -verify-machineinstrs | FileCheck %s --check-prefix=GFX11-GISEL declare i32 @llvm.amdgcn.workitem.id.x() #1 @@ -56,6 +58,36 @@ ; GISEL-NEXT: v_mov_b32_e32 v1, s1 ; GISEL-NEXT: flat_store_short v[0:1], v2 ; GISEL-NEXT: s_endpgm +; +; GFX11-FLAT-LABEL: s_brev_i16: +; GFX11-FLAT: ; %bb.0: +; GFX11-FLAT-NEXT: s_clause 0x1 +; GFX11-FLAT-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-FLAT-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-FLAT-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FLAT-NEXT: s_brev_b32 s2, s2 +; GFX11-FLAT-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-FLAT-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX11-FLAT-NEXT: global_store_d16_hi_b16 v0, v1, s[0:1] +; GFX11-FLAT-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-FLAT-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: s_brev_i16: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_clause 0x1 +; GFX11-GISEL-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_brev_b32 s2, s2 +; GFX11-GISEL-NEXT: s_lshr_b32 s2, s2, 16 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-GISEL-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %brev = call i16 @llvm.bitreverse.i16(i16 %val) #1 store i16 %brev, ptr addrspace(1) %out ret void @@ -114,6 +146,34 @@ ; GISEL-NEXT: v_mov_b32_e32 v1, s1 ; GISEL-NEXT: flat_store_short v[0:1], v2 ; GISEL-NEXT: s_endpgm +; +; GFX11-FLAT-LABEL: v_brev_i16: +; GFX11-FLAT: ; %bb.0: +; GFX11-FLAT-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-FLAT-NEXT: s_mov_b32 s7, 0x31016000 +; GFX11-FLAT-NEXT: s_mov_b32 s6, -1 +; GFX11-FLAT-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-FLAT-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FLAT-NEXT: s_mov_b32 s4, s2 +; GFX11-FLAT-NEXT: s_mov_b32 s5, s3 +; GFX11-FLAT-NEXT: buffer_load_u16 v0, off, s[4:7], 0 +; GFX11-FLAT-NEXT: s_waitcnt vmcnt(0) +; GFX11-FLAT-NEXT: v_bfrev_b32_e32 v0, v0 +; GFX11-FLAT-NEXT: global_store_d16_hi_b16 v1, v0, s[0:1] +; GFX11-FLAT-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-FLAT-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: v_brev_i16: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: global_load_u16 v1, v0, s[2:3] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: v_bfrev_b32_e32 v1, v1 +; GFX11-GISEL-NEXT: global_store_d16_hi_b16 v0, v1, s[0:1] +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %val = load i16, ptr addrspace(1) %valptr %brev = call i16 @llvm.bitreverse.i16(i16 %val) #1 store i16 %brev, ptr addrspace(1) %out @@ -156,6 +216,35 @@ ; GISEL-NEXT: v_mov_b32_e32 v1, s1 ; GISEL-NEXT: flat_store_dword v[0:1], v2 ; GISEL-NEXT: s_endpgm +; +; GFX11-FLAT-LABEL: s_brev_i32: +; GFX11-FLAT: ; %bb.0: +; GFX11-FLAT-NEXT: s_clause 0x1 +; GFX11-FLAT-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-FLAT-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-FLAT-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-FLAT-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FLAT-NEXT: s_brev_b32 s2, s2 +; GFX11-FLAT-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-FLAT-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-FLAT-NEXT: s_mov_b32 s2, -1 +; GFX11-FLAT-NEXT: buffer_store_b32 v0, off, s[0:3], 0 +; GFX11-FLAT-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-FLAT-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: s_brev_i32: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_clause 0x1 +; GFX11-GISEL-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_brev_b32 s2, s2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %brev = call i32 @llvm.bitreverse.i32(i32 %val) #1 store i32 %brev, ptr addrspace(1) %out ret void @@ -213,6 +302,32 @@ ; GISEL-NEXT: v_mov_b32_e32 v1, s1 ; GISEL-NEXT: flat_store_dword v[0:1], v2 ; GISEL-NEXT: s_endpgm +; +; GFX11-FLAT-LABEL: v_brev_i32: +; GFX11-FLAT: ; %bb.0: +; GFX11-FLAT-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-FLAT-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-FLAT-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FLAT-NEXT: global_load_b32 v0, v0, s[2:3] +; GFX11-FLAT-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-FLAT-NEXT: s_mov_b32 s2, -1 +; GFX11-FLAT-NEXT: s_waitcnt vmcnt(0) +; GFX11-FLAT-NEXT: v_bfrev_b32_e32 v0, v0 +; GFX11-FLAT-NEXT: buffer_store_b32 v0, off, s[0:3], 0 +; GFX11-FLAT-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-FLAT-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: v_brev_i32: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: global_load_b32 v0, v0, s[2:3] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: v_bfrev_b32_e32 v0, v0 +; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid %val = load i32, ptr addrspace(1) %gep @@ -264,6 +379,35 @@ ; GISEL-NEXT: v_mov_b32_e32 v2, s0 ; GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GISEL-NEXT: s_endpgm +; +; GFX11-FLAT-LABEL: s_brev_v2i32: +; GFX11-FLAT: ; %bb.0: +; GFX11-FLAT-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-FLAT-NEXT: s_mov_b32 s7, 0x31016000 +; GFX11-FLAT-NEXT: s_mov_b32 s6, -1 +; GFX11-FLAT-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FLAT-NEXT: s_brev_b32 s2, s2 +; GFX11-FLAT-NEXT: s_brev_b32 s3, s3 +; GFX11-FLAT-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-FLAT-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX11-FLAT-NEXT: s_mov_b32 s4, s0 +; GFX11-FLAT-NEXT: s_mov_b32 s5, s1 +; GFX11-FLAT-NEXT: buffer_store_b64 v[0:1], off, s[4:7], 0 +; GFX11-FLAT-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-FLAT-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: s_brev_v2i32: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_brev_b32 s2, s2 +; GFX11-GISEL-NEXT: s_brev_b32 s3, s3 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %brev = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %val) #1 store <2 x i32> %brev, ptr addrspace(1) %out ret void @@ -324,6 +468,35 @@ ; GISEL-NEXT: v_bfrev_b32_e32 v1, v1 ; GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GISEL-NEXT: s_endpgm +; +; GFX11-FLAT-LABEL: v_brev_v2i32: +; GFX11-FLAT: ; %bb.0: +; GFX11-FLAT-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-FLAT-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX11-FLAT-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FLAT-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX11-FLAT-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-FLAT-NEXT: s_mov_b32 s2, -1 +; GFX11-FLAT-NEXT: s_waitcnt vmcnt(0) +; GFX11-FLAT-NEXT: v_bfrev_b32_e32 v1, v1 +; GFX11-FLAT-NEXT: v_bfrev_b32_e32 v0, v0 +; GFX11-FLAT-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0 +; GFX11-FLAT-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-FLAT-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: v_brev_v2i32: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: v_bfrev_b32_e32 v0, v0 +; GFX11-GISEL-NEXT: v_bfrev_b32_e32 v1, v1 +; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr <2 x i32>, ptr addrspace(1) %valptr, i32 %tid %val = load <2 x i32>, ptr addrspace(1) %gep @@ -372,6 +545,30 @@ ; GISEL-NEXT: v_mov_b32_e32 v2, s0 ; GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GISEL-NEXT: s_endpgm +; +; GFX11-FLAT-LABEL: s_brev_i64: +; GFX11-FLAT: ; %bb.0: +; GFX11-FLAT-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-FLAT-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FLAT-NEXT: s_brev_b64 s[4:5], s[2:3] +; GFX11-FLAT-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-FLAT-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 +; GFX11-FLAT-NEXT: s_mov_b32 s2, -1 +; GFX11-FLAT-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0 +; GFX11-FLAT-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-FLAT-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: s_brev_i64: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_brev_b64 s[2:3], s[2:3] +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %brev = call i64 @llvm.bitreverse.i64(i64 %val) #1 store i64 %brev, ptr addrspace(1) %out ret void @@ -432,6 +629,35 @@ ; GISEL-NEXT: v_bfrev_b32_e32 v2, v0 ; GISEL-NEXT: flat_store_dwordx2 v[3:4], v[1:2] ; GISEL-NEXT: s_endpgm +; +; GFX11-FLAT-LABEL: v_brev_i64: +; GFX11-FLAT: ; %bb.0: +; GFX11-FLAT-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-FLAT-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX11-FLAT-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FLAT-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX11-FLAT-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-FLAT-NEXT: s_mov_b32 s2, -1 +; GFX11-FLAT-NEXT: s_waitcnt vmcnt(0) +; GFX11-FLAT-NEXT: v_bfrev_b32_e32 v2, v0 +; GFX11-FLAT-NEXT: v_bfrev_b32_e32 v1, v1 +; GFX11-FLAT-NEXT: buffer_store_b64 v[1:2], off, s[0:3], 0 +; GFX11-FLAT-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-FLAT-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: v_brev_i64: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: v_bfrev_b32_e32 v1, v1 +; GFX11-GISEL-NEXT: v_bfrev_b32_e32 v2, v0 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-GISEL-NEXT: global_store_b64 v0, v[1:2], s[0:1] +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr i64, ptr addrspace(1) %valptr, i32 %tid %val = load i64, ptr addrspace(1) %gep @@ -488,6 +714,37 @@ ; GISEL-NEXT: v_mov_b32_e32 v5, s9 ; GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; GISEL-NEXT: s_endpgm +; +; GFX11-FLAT-LABEL: s_brev_v2i64: +; GFX11-FLAT: ; %bb.0: +; GFX11-FLAT-NEXT: s_clause 0x1 +; GFX11-FLAT-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 +; GFX11-FLAT-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-FLAT-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FLAT-NEXT: s_brev_b64 s[2:3], s[4:5] +; GFX11-FLAT-NEXT: s_brev_b64 s[4:5], s[6:7] +; GFX11-FLAT-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX11-FLAT-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5 +; GFX11-FLAT-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-FLAT-NEXT: s_mov_b32 s2, -1 +; GFX11-FLAT-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 +; GFX11-FLAT-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-FLAT-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: s_brev_v2i64: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_clause 0x1 +; GFX11-GISEL-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 +; GFX11-GISEL-NEXT: s_load_b64 s[8:9], s[0:1], 0x24 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_brev_b64 s[0:1], s[4:5] +; GFX11-GISEL-NEXT: s_brev_b64 s[2:3], s[6:7] +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-GISEL-NEXT: global_store_b128 v4, v[0:3], s[8:9] +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %brev = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %val) #1 store <2 x i64> %brev, ptr addrspace(1) %out ret void @@ -554,6 +811,39 @@ ; GISEL-NEXT: v_mov_b32_e32 v1, s1 ; GISEL-NEXT: flat_store_dwordx4 v[0:1], v[4:7] ; GISEL-NEXT: s_endpgm +; +; GFX11-FLAT-LABEL: v_brev_v2i64: +; GFX11-FLAT: ; %bb.0: +; GFX11-FLAT-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-FLAT-NEXT: v_lshlrev_b32_e32 v0, 4, v0 +; GFX11-FLAT-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FLAT-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX11-FLAT-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-FLAT-NEXT: s_mov_b32 s2, -1 +; GFX11-FLAT-NEXT: s_waitcnt vmcnt(0) +; GFX11-FLAT-NEXT: v_bfrev_b32_e32 v4, v2 +; GFX11-FLAT-NEXT: v_bfrev_b32_e32 v3, v3 +; GFX11-FLAT-NEXT: v_bfrev_b32_e32 v2, v0 +; GFX11-FLAT-NEXT: v_bfrev_b32_e32 v1, v1 +; GFX11-FLAT-NEXT: buffer_store_b128 v[1:4], off, s[0:3], 0 +; GFX11-FLAT-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-FLAT-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: v_brev_v2i64: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v0, 4, v0 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: v_bfrev_b32_e32 v4, v1 +; GFX11-GISEL-NEXT: v_bfrev_b32_e32 v5, v0 +; GFX11-GISEL-NEXT: v_bfrev_b32_e32 v6, v3 +; GFX11-GISEL-NEXT: v_bfrev_b32_e32 v7, v2 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-GISEL-NEXT: global_store_b128 v0, v[4:7], s[0:1] +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr <2 x i64> , ptr addrspace(1) %valptr, i32 %tid %val = load <2 x i64>, ptr addrspace(1) %gep @@ -584,6 +874,26 @@ ; GISEL-NEXT: v_bfrev_b32_e32 v0, v0 ; GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FLAT-LABEL: missing_truncate_promote_bitreverse: +; GFX11-FLAT: ; %bb.0: ; %bb +; GFX11-FLAT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FLAT-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-FLAT-NEXT: v_bfrev_b32_e32 v0, v0 +; GFX11-FLAT-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FLAT-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX11-FLAT-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX11-FLAT-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: missing_truncate_promote_bitreverse: +; GFX11-GISEL: ; %bb.0: ; %bb +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: v_bfrev_b32_e32 v0, v0 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX11-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] bb: %tmp = trunc i32 %arg to i16 %tmp1 = call i16 @llvm.bitreverse.i16(i16 %tmp) diff --git a/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll b/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll --- a/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll @@ -1,36 +1,93 @@ -; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI %s +; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI %s +; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s -; GCN-LABEL: {{^}}br_cc_f16: -; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] -; GCN: buffer_load_ushort v[[B_F16:[0-9]+]] - -; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] -; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]] -; SI: v_cmp_nlt_f32_e32 vcc, v[[A_F32]], v[[B_F32]] -; VI: v_cmp_nlt_f16_e32 vcc, v[[A_F16]], v[[B_F16]] -; GCN: s_cbranch_vccnz - -; SI: one{{$}} -; SI: v_cvt_f16_f32_e32 v[[CVT:[0-9]+]], v[[A_F32]] - -; SI: two{{$}} -; SI: v_cvt_f16_f32_e32 v[[CVT]], v[[B_F32]] - -; SI: one{{$}} -; SI: buffer_store_short v[[CVT]] -; SI: s_endpgm - - - -; VI: one{{$}} -; VI: buffer_store_short v[[A_F16]] -; VI: s_endpgm - -; VI: two{{$}} -; VI: buffer_store_short v[[B_F16]] -; VI: s_endpgm define amdgpu_kernel void @br_cc_f16( +; SI-LABEL: br_cc_f16: +; SI: ; %bb.0: ; %entry +; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd +; SI-NEXT: s_mov_b32 s3, 0xf000 +; SI-NEXT: s_mov_b32 s2, -1 +; SI-NEXT: s_mov_b32 s10, s2 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b32 s0, s6 +; SI-NEXT: s_mov_b32 s1, s7 +; SI-NEXT: s_mov_b32 s11, s3 +; SI-NEXT: buffer_load_ushort v0, off, s[0:3], 0 glc +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 glc +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SI-NEXT: v_cmp_nlt_f32_e32 vcc, v0, v1 +; SI-NEXT: s_cbranch_vccnz .LBB0_2 +; SI-NEXT: ; %bb.1: ; %one +; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SI-NEXT: s_branch .LBB0_3 +; SI-NEXT: .LBB0_2: ; %two +; SI-NEXT: v_cvt_f16_f32_e32 v0, v1 +; SI-NEXT: .LBB0_3: ; %one +; SI-NEXT: s_mov_b32 s6, s2 +; SI-NEXT: s_mov_b32 s7, s3 +; SI-NEXT: buffer_store_short v0, off, s[4:7], 0 +; SI-NEXT: s_endpgm +; +; VI-LABEL: br_cc_f16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 +; VI-NEXT: s_mov_b32 s3, 0xf000 +; VI-NEXT: s_mov_b32 s2, -1 +; VI-NEXT: s_mov_b32 s10, s2 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_mov_b32 s0, s6 +; VI-NEXT: s_mov_b32 s1, s7 +; VI-NEXT: s_mov_b32 s11, s3 +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], 0 glc +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 glc +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_mov_b32 s6, s2 +; VI-NEXT: s_mov_b32 s7, s3 +; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v0, v1 +; VI-NEXT: s_cbranch_vccnz .LBB0_2 +; VI-NEXT: ; %bb.1: ; %one +; VI-NEXT: buffer_store_short v0, off, s[4:7], 0 +; VI-NEXT: s_endpgm +; VI-NEXT: .LBB0_2: ; %two +; VI-NEXT: buffer_store_short v1, off, s[4:7], 0 +; VI-NEXT: s_endpgm +; +; GFX11-LABEL: br_cc_f16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-NEXT: s_load_b64 s[8:9], s[0:1], 0x34 +; GFX11-NEXT: s_mov_b32 s2, -1 +; GFX11-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-NEXT: s_mov_b32 s10, s2 +; GFX11-NEXT: s_mov_b32 s11, s3 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_mov_b32 s0, s6 +; GFX11-NEXT: s_mov_b32 s1, s7 +; GFX11-NEXT: buffer_load_u16 v0, off, s[0:3], 0 glc dlc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: buffer_load_u16 v1, off, s[8:11], 0 glc dlc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: s_mov_b32 s6, s2 +; GFX11-NEXT: s_mov_b32 s7, s3 +; GFX11-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v1 +; GFX11-NEXT: s_cbranch_vccnz .LBB0_2 +; GFX11-NEXT: ; %bb.1: ; %one +; GFX11-NEXT: buffer_store_b16 v0, off, s[4:7], 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; GFX11-NEXT: .LBB0_2: ; %two +; GFX11-NEXT: buffer_store_b16 v1, off, s[4:7], 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %b) { @@ -49,27 +106,73 @@ ret void } -; GCN-LABEL: {{^}}br_cc_f16_imm_a: -; GCN: buffer_load_ushort v[[B_F16:[0-9]+]] - -; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]] -; SI: v_cmp_nlt_f32_e32 vcc, 0.5, v[[B_F32]] -; SI: s_cbranch_vccnz - -; VI: v_cmp_nlt_f16_e32 vcc, 0.5, v[[B_F16]] -; VI: s_cbranch_vccnz - -; GCN: one{{$}} -; GCN: v_mov_b32_e32 v[[A_F16:[0-9]+]], 0x380{{0|1}}{{$}} - -; SI: buffer_store_short v[[A_F16]] -; SI: s_endpgm - - -; GCN: two{{$}} -; SI: v_cvt_f16_f32_e32 v[[B_F16:[0-9]+]], v[[B_F32]] - define amdgpu_kernel void @br_cc_f16_imm_a( +; SI-LABEL: br_cc_f16_imm_a: +; SI: ; %bb.0: ; %entry +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, -1 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b32 s4, s2 +; SI-NEXT: s_mov_b32 s5, s3 +; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SI-NEXT: v_cmp_nlt_f32_e32 vcc, 0.5, v0 +; SI-NEXT: s_cbranch_vccnz .LBB1_2 +; SI-NEXT: ; %bb.1: ; %one +; SI-NEXT: s_mov_b32 s2, s6 +; SI-NEXT: s_mov_b32 s3, s7 +; SI-NEXT: v_mov_b32_e32 v0, 0x3800 +; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 +; SI-NEXT: s_endpgm +; SI-NEXT: .LBB1_2: ; %two +; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SI-NEXT: s_mov_b32 s2, s6 +; SI-NEXT: s_mov_b32 s3, s7 +; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 +; SI-NEXT: s_endpgm +; +; VI-LABEL: br_cc_f16_imm_a: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; VI-NEXT: s_mov_b32 s7, 0xf000 +; VI-NEXT: s_mov_b32 s6, -1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_mov_b32 s4, s2 +; VI-NEXT: s_mov_b32 s5, s3 +; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 +; VI-NEXT: s_mov_b32 s2, s6 +; VI-NEXT: s_mov_b32 s3, s7 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_cmp_nlt_f16_e32 vcc, 0.5, v0 +; VI-NEXT: s_cbranch_vccnz .LBB1_2 +; VI-NEXT: ; %bb.1: ; %one +; VI-NEXT: v_mov_b32_e32 v0, 0x3800 +; VI-NEXT: .LBB1_2: ; %two +; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 +; VI-NEXT: s_endpgm +; +; GFX11-LABEL: br_cc_f16_imm_a: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_mov_b32 s7, 0x31016000 +; GFX11-NEXT: s_mov_b32 s6, -1 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_mov_b32 s4, s2 +; GFX11-NEXT: s_mov_b32 s5, s3 +; GFX11-NEXT: buffer_load_u16 v0, off, s[4:7], 0 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_cmp_nlt_f16_e32 vcc_lo, 0.5, v0 +; GFX11-NEXT: s_cbranch_vccnz .LBB1_2 +; GFX11-NEXT: ; %bb.1: ; %one +; GFX11-NEXT: v_mov_b32_e32 v0, 0x3800 +; GFX11-NEXT: .LBB1_2: ; %two +; GFX11-NEXT: s_mov_b32 s2, s6 +; GFX11-NEXT: s_mov_b32 s3, s7 +; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %b) { entry: @@ -86,23 +189,75 @@ ret void } -; GCN-LABEL: {{^}}br_cc_f16_imm_b: -; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] - -; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] -; SI: v_cmp_ngt_f32_e32 vcc, 0.5, v[[A_F32]] - -; VI: v_cmp_ngt_f16_e32 vcc, 0.5, v[[A_F16]] -; GCN: s_cbranch_vccnz - -; GCN: one{{$}} -; SI: v_cvt_f16_f32_e32 v[[A_F16:[0-9]+]], v[[A_F32]] - -; GCN: two{{$}} -; GCN: v_mov_b32_e32 v[[B_F16:[0-9]+]], 0x3800{{$}} -; GCN: buffer_store_short v[[B_F16]] -; GCN: s_endpgm define amdgpu_kernel void @br_cc_f16_imm_b( +; SI-LABEL: br_cc_f16_imm_b: +; SI: ; %bb.0: ; %entry +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, -1 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b32 s4, s2 +; SI-NEXT: s_mov_b32 s5, s3 +; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0.5, v0 +; SI-NEXT: s_cbranch_vccnz .LBB2_2 +; SI-NEXT: ; %bb.1: ; %one +; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SI-NEXT: s_mov_b32 s2, s6 +; SI-NEXT: s_mov_b32 s3, s7 +; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 +; SI-NEXT: s_endpgm +; SI-NEXT: .LBB2_2: ; %two +; SI-NEXT: s_mov_b32 s2, s6 +; SI-NEXT: s_mov_b32 s3, s7 +; SI-NEXT: v_mov_b32_e32 v0, 0x3800 +; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 +; SI-NEXT: s_endpgm +; +; VI-LABEL: br_cc_f16_imm_b: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; VI-NEXT: s_mov_b32 s7, 0xf000 +; VI-NEXT: s_mov_b32 s6, -1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_mov_b32 s4, s2 +; VI-NEXT: s_mov_b32 s5, s3 +; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 +; VI-NEXT: s_mov_b32 s2, s6 +; VI-NEXT: s_mov_b32 s3, s7 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_cmp_ngt_f16_e32 vcc, 0.5, v0 +; VI-NEXT: s_cbranch_vccnz .LBB2_2 +; VI-NEXT: ; %bb.1: ; %one +; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 +; VI-NEXT: s_endpgm +; VI-NEXT: .LBB2_2: ; %two +; VI-NEXT: v_mov_b32_e32 v0, 0x3800 +; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 +; VI-NEXT: s_endpgm +; +; GFX11-LABEL: br_cc_f16_imm_b: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_mov_b32 s7, 0x31016000 +; GFX11-NEXT: s_mov_b32 s6, -1 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_mov_b32 s4, s2 +; GFX11-NEXT: s_mov_b32 s5, s3 +; GFX11-NEXT: buffer_load_u16 v0, off, s[4:7], 0 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_cmp_ngt_f16_e32 vcc_lo, 0.5, v0 +; GFX11-NEXT: s_cbranch_vccz .LBB2_2 +; GFX11-NEXT: ; %bb.1: ; %two +; GFX11-NEXT: v_mov_b32_e32 v0, 0x3800 +; GFX11-NEXT: .LBB2_2: ; %one +; GFX11-NEXT: s_mov_b32 s2, s6 +; GFX11-NEXT: s_mov_b32 s3, s7 +; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a) { entry: diff --git a/llvm/test/CodeGen/AMDGPU/bswap.ll b/llvm/test/CodeGen/AMDGPU/bswap.ll --- a/llvm/test/CodeGen/AMDGPU/bswap.ll +++ b/llvm/test/CodeGen/AMDGPU/bswap.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=amdgcn-- -verify-machineinstrs | FileCheck %s --check-prefix=SI ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI +; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=GFX11 declare i16 @llvm.bswap.i16(i16) nounwind readnone declare <2 x i16> @llvm.bswap.v2i16(<2 x i16>) nounwind readnone @@ -45,6 +46,19 @@ ; VI-NEXT: v_perm_b32 v0, 0, s2, v0 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; VI-NEXT: s_endpgm +; +; GFX11-LABEL: test_bswap_i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX11-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_perm_b32 v0, 0, s2, 0x10203 +; GFX11-NEXT: s_mov_b32 s2, -1 +; GFX11-NEXT: buffer_store_b32 v0, off, s[0:3], 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %val = load i32, ptr addrspace(1) %in, align 4 %bswap = call i32 @llvm.bswap.i32(i32 %val) nounwind readnone store i32 %bswap, ptr addrspace(1) %out, align 4 @@ -85,6 +99,20 @@ ; VI-NEXT: v_perm_b32 v0, 0, s2, v0 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; VI-NEXT: s_endpgm +; +; GFX11-LABEL: test_bswap_v2i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[4:5], s[2:3], 0x0 +; GFX11-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-NEXT: s_mov_b32 s2, -1 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_perm_b32 v1, 0, s5, 0x10203 +; GFX11-NEXT: v_perm_b32 v0, 0, s4, 0x10203 +; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %val = load <2 x i32>, ptr addrspace(1) %in, align 8 %bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %val) nounwind readnone store <2 x i32> %bswap, ptr addrspace(1) %out, align 8 @@ -133,6 +161,22 @@ ; VI-NEXT: v_perm_b32 v0, 0, s8, v0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; VI-NEXT: s_endpgm +; +; GFX11-LABEL: test_bswap_v4i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x0 +; GFX11-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-NEXT: s_mov_b32 s2, -1 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_perm_b32 v3, 0, s7, 0x10203 +; GFX11-NEXT: v_perm_b32 v2, 0, s6, 0x10203 +; GFX11-NEXT: v_perm_b32 v1, 0, s5, 0x10203 +; GFX11-NEXT: v_perm_b32 v0, 0, s4, 0x10203 +; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %val = load <4 x i32>, ptr addrspace(1) %in, align 16 %bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val) nounwind readnone store <4 x i32> %bswap, ptr addrspace(1) %out, align 16 @@ -199,6 +243,28 @@ ; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:16 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 ; VI-NEXT: s_endpgm +; +; GFX11-LABEL: test_bswap_v8i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[8:11], s[0:1], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b256 s[0:7], s[10:11], 0x0 +; GFX11-NEXT: s_mov_b32 s11, 0x31016000 +; GFX11-NEXT: s_mov_b32 s10, -1 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_perm_b32 v7, 0, s7, 0x10203 +; GFX11-NEXT: v_perm_b32 v6, 0, s6, 0x10203 +; GFX11-NEXT: v_perm_b32 v5, 0, s5, 0x10203 +; GFX11-NEXT: v_perm_b32 v4, 0, s4, 0x10203 +; GFX11-NEXT: v_perm_b32 v3, 0, s3, 0x10203 +; GFX11-NEXT: v_perm_b32 v2, 0, s2, 0x10203 +; GFX11-NEXT: v_perm_b32 v1, 0, s1, 0x10203 +; GFX11-NEXT: v_perm_b32 v0, 0, s0, 0x10203 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: buffer_store_b128 v[4:7], off, s[8:11], 0 offset:16 +; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[8:11], 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %val = load <8 x i32>, ptr addrspace(1) %in, align 32 %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %val) nounwind readnone store <8 x i32> %bswap, ptr addrspace(1) %out, align 32 @@ -239,6 +305,20 @@ ; VI-NEXT: v_perm_b32 v0, 0, s3, v0 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; VI-NEXT: s_endpgm +; +; GFX11-LABEL: test_bswap_i64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[4:5], s[2:3], 0x0 +; GFX11-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-NEXT: s_mov_b32 s2, -1 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_perm_b32 v1, 0, s4, 0x10203 +; GFX11-NEXT: v_perm_b32 v0, 0, s5, 0x10203 +; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %val = load i64, ptr addrspace(1) %in, align 8 %bswap = call i64 @llvm.bswap.i64(i64 %val) nounwind readnone store i64 %bswap, ptr addrspace(1) %out, align 8 @@ -287,6 +367,22 @@ ; VI-NEXT: v_perm_b32 v0, 0, s9, v0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; VI-NEXT: s_endpgm +; +; GFX11-LABEL: test_bswap_v2i64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x0 +; GFX11-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-NEXT: s_mov_b32 s2, -1 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_perm_b32 v3, 0, s6, 0x10203 +; GFX11-NEXT: v_perm_b32 v2, 0, s7, 0x10203 +; GFX11-NEXT: v_perm_b32 v1, 0, s4, 0x10203 +; GFX11-NEXT: v_perm_b32 v0, 0, s5, 0x10203 +; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %val = load <2 x i64>, ptr addrspace(1) %in, align 16 %bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %val) nounwind readnone store <2 x i64> %bswap, ptr addrspace(1) %out, align 16 @@ -353,6 +449,28 @@ ; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:16 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 ; VI-NEXT: s_endpgm +; +; GFX11-LABEL: test_bswap_v4i64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[8:11], s[0:1], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b256 s[0:7], s[10:11], 0x0 +; GFX11-NEXT: s_mov_b32 s11, 0x31016000 +; GFX11-NEXT: s_mov_b32 s10, -1 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_perm_b32 v7, 0, s6, 0x10203 +; GFX11-NEXT: v_perm_b32 v6, 0, s7, 0x10203 +; GFX11-NEXT: v_perm_b32 v5, 0, s4, 0x10203 +; GFX11-NEXT: v_perm_b32 v4, 0, s5, 0x10203 +; GFX11-NEXT: v_perm_b32 v3, 0, s2, 0x10203 +; GFX11-NEXT: v_perm_b32 v2, 0, s3, 0x10203 +; GFX11-NEXT: v_perm_b32 v1, 0, s0, 0x10203 +; GFX11-NEXT: v_perm_b32 v0, 0, s1, 0x10203 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: buffer_store_b128 v[4:7], off, s[8:11], 0 offset:16 +; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[8:11], 0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %val = load <4 x i64>, ptr addrspace(1) %in, align 32 %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %val) nounwind readnone store <4 x i64> %bswap, ptr addrspace(1) %out, align 32 @@ -378,6 +496,15 @@ ; VI-NEXT: v_perm_b32 v0, 0, v0, s4 ; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 ; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: missing_truncate_promote_bswap: +; GFX11: ; %bb.0: ; %bb +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX11-NEXT: s_setpc_b64 s[30:31] bb: %tmp = trunc i32 %arg to i16 %tmp1 = call i16 @llvm.bswap.i16(i16 %tmp) @@ -403,6 +530,13 @@ ; VI-NEXT: s_mov_b32 s4, 0xc0c0001 ; VI-NEXT: v_perm_b32 v0, 0, v0, s4 ; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bswap_i16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bswap = call i16 @llvm.bswap.i16(i16 %src) ret i16 %bswap } @@ -424,6 +558,13 @@ ; VI-NEXT: s_mov_b32 s4, 0xc0c0001 ; VI-NEXT: v_perm_b32 v0, 0, v0, s4 ; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bswap_i16_zext_to_i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bswap = call i16 @llvm.bswap.i16(i16 %src) %zext = zext i16 %bswap to i32 ret i32 %zext @@ -447,6 +588,15 @@ ; VI-NEXT: v_perm_b32 v0, 0, v0, s4 ; VI-NEXT: v_bfe_i32 v0, v0, 0, 16 ; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bswap_i16_sext_to_i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bswap = call i16 @llvm.bswap.i16(i16 %src) %zext = sext i16 %bswap to i32 ret i32 %zext @@ -475,6 +625,13 @@ ; VI-NEXT: s_mov_b32 s4, 0x2030001 ; VI-NEXT: v_perm_b32 v0, 0, v0, s4 ; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bswap_v2i16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0x2030001 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bswap = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %src) ret <2 x i16> %bswap } @@ -507,6 +664,14 @@ ; VI-NEXT: v_perm_b32 v0, 0, v0, s4 ; VI-NEXT: v_perm_b32 v1, 0, v1, s4 ; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bswap_v3i16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0x2030001 +; GFX11-NEXT: v_perm_b32 v1, 0, v1, 0x2030001 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bswap = call <3 x i16> @llvm.bswap.v3i16(<3 x i16> %src) ret <3 x i16> %bswap } @@ -545,6 +710,14 @@ ; VI-NEXT: v_perm_b32 v0, 0, v0, s4 ; VI-NEXT: v_perm_b32 v1, 0, v1, s4 ; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bswap_v4i16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0x2030001 +; GFX11-NEXT: v_perm_b32 v1, 0, v1, 0x2030001 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bswap = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %src) ret <4 x i16> %bswap } @@ -573,6 +746,17 @@ ; VI-NEXT: v_alignbit_b32 v0, v2, v0, 16 ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2 ; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bswap_i48: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_perm_b32 v2, 0, v0, 0x10203 +; GFX11-NEXT: v_perm_b32 v0, 0, v1, 0x10203 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-NEXT: v_alignbit_b32 v0, v2, v0, 16 +; GFX11-NEXT: s_setpc_b64 s[30:31] %trunc = trunc i64 %src to i48 %bswap = call i48 @llvm.bswap.i48(i48 %trunc) %zext = zext i48 %bswap to i64 diff --git a/llvm/test/CodeGen/AMDGPU/clamp-modifier.ll b/llvm/test/CodeGen/AMDGPU/clamp-modifier.ll --- a/llvm/test/CodeGen/AMDGPU/clamp-modifier.ll +++ b/llvm/test/CodeGen/AMDGPU/clamp-modifier.ll @@ -1,12 +1,65 @@ -; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s -; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89 %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9 %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI %s +; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX8 %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s +; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s -; GCN-LABEL: {{^}}v_clamp_add_src_f32: -; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] -; GCN-NOT: [[A]] -; GCN: v_add_f32_e64 v{{[0-9]+}}, [[A]], 1.0 clamp{{$}} define amdgpu_kernel void @v_clamp_add_src_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { +; SI-LABEL: v_clamp_add_src_f32: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp +; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_clamp_add_src_f32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f32_e64 v2, v3, 1.0 clamp +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_clamp_add_src_f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dword v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_clamp_add_src_f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -18,11 +71,76 @@ ret void } -; GCN-LABEL: {{^}}v_clamp_multi_use_src_f32: -; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] -; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], 1.0, [[A]]{{$}} -; GCN: v_max_f32_e64 v{{[0-9]+}}, [[ADD]], [[ADD]] clamp{{$}} define amdgpu_kernel void @v_clamp_multi_use_src_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { +; SI-LABEL: v_clamp_multi_use_src_f32: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_mov_b32 s6, -1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_add_f32_e32 v2, 1.0, v2 +; SI-NEXT: v_max_f32_e64 v3, v2, v2 clamp +; SI-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_clamp_multi_use_src_f32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f32_e32 v2, 1.0, v3 +; GFX8-NEXT: v_max_f32_e64 v3, v2, v2 clamp +; GFX8-NEXT: flat_store_dword v[0:1], v3 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_clamp_multi_use_src_f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dword v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 +; GFX9-NEXT: v_max_f32_e64 v2, v1, v1 clamp +; GFX9-NEXT: global_store_dword v0, v2, s[0:1] +; GFX9-NEXT: global_store_dword v[0:1], v1, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_clamp_multi_use_src_f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_add_f32_e32 v1, 1.0, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_max_f32_e64 v2, v1, v1 clamp +; GFX11-NEXT: global_store_b32 v0, v2, s[0:1] +; GFX11-NEXT: global_store_b32 v[0:1], v1, off dlc +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -35,11 +153,62 @@ ret void } -; GCN-LABEL: {{^}}v_clamp_dbg_use_src_f32: -; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] -; GCN-NOT: [[A]] -; GCN: v_add_f32_e64 v{{[0-9]+}}, [[A]], 1.0 clamp{{$}} define amdgpu_kernel void @v_clamp_dbg_use_src_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { +; SI-LABEL: v_clamp_dbg_use_src_f32: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp +; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_clamp_dbg_use_src_f32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f32_e64 v2, v3, 1.0 clamp +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_clamp_dbg_use_src_f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dword v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_clamp_dbg_use_src_f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -52,11 +221,67 @@ ret void } -; GCN-LABEL: {{^}}v_clamp_add_neg_src_f32: -; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] -; GCN: v_floor_f32_e32 [[FLOOR:v[0-9]+]], [[A]] -; GCN: v_max_f32_e64 v{{[0-9]+}}, -[[FLOOR]], -[[FLOOR]] clamp{{$}} define amdgpu_kernel void @v_clamp_add_neg_src_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { +; SI-LABEL: v_clamp_add_neg_src_f32: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_floor_f32_e32 v2, v2 +; SI-NEXT: v_max_f32_e64 v2, -v2, -v2 clamp +; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_clamp_add_neg_src_f32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_floor_f32_e32 v2, v3 +; GFX8-NEXT: v_max_f32_e64 v2, -v2, -v2 clamp +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_clamp_add_neg_src_f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dword v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_floor_f32_e32 v1, v1 +; GFX9-NEXT: v_max_f32_e64 v1, -v1, -v1 clamp +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_clamp_add_neg_src_f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_floor_f32_e32 v1, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_max_f32_e64 v1, -v1, -v1 clamp +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -69,11 +294,67 @@ ret void } -; GCN-LABEL: {{^}}v_non_clamp_max_f32: -; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] -; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], 1.0, [[A]]{{$}} -; GCN: v_max_f32_e32 v{{[0-9]+}}, 0, [[ADD]]{{$}} define amdgpu_kernel void @v_non_clamp_max_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { +; SI-LABEL: v_non_clamp_max_f32: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_add_f32_e32 v2, 1.0, v2 +; SI-NEXT: v_max_f32_e32 v2, 0, v2 +; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_non_clamp_max_f32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f32_e32 v2, 1.0, v3 +; GFX8-NEXT: v_max_f32_e32 v2, 0, v2 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_non_clamp_max_f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dword v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 +; GFX9-NEXT: v_max_f32_e32 v1, 0, v1 +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_non_clamp_max_f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_add_f32_e32 v1, 1.0, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_max_f32_e32 v1, 0, v1 +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -84,10 +365,62 @@ ret void } -; GCN-LABEL: {{^}}v_clamp_add_src_f32_denormals: -; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] -; GCN: v_add_f32_e64 [[ADD:v[0-9]+]], [[A]], 1.0 clamp{{$}} define amdgpu_kernel void @v_clamp_add_src_f32_denormals(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #2 { +; SI-LABEL: v_clamp_add_src_f32_denormals: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp +; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_clamp_add_src_f32_denormals: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f32_e64 v2, v3, 1.0 clamp +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_clamp_add_src_f32_denormals: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dword v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_clamp_add_src_f32_denormals: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -99,14 +432,64 @@ ret void } -; GCN-LABEL: {{^}}v_clamp_add_src_f16_denorm: -; GCN: {{buffer|flat|global}}_load_ushort [[A:v[0-9]+]] -; GFX89: v_add_f16_e64 [[ADD:v[0-9]+]], [[A]], 1.0 clamp{{$}} - -; SI: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], [[A]] -; SI: v_add_f32_e64 [[ADD:v[0-9]+]], [[CVT]], 1.0 clamp{{$}} -; SI: v_cvt_f16_f32_e32 v{{[0-9]+}}, [[ADD]] define amdgpu_kernel void @v_clamp_add_src_f16_denorm(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { +; SI-LABEL: v_clamp_add_src_f16_denorm: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_clamp_add_src_f16_denorm: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 1, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ushort v3, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f16_e64 v2, v3, 1.0 clamp +; GFX8-NEXT: flat_store_short v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_clamp_add_src_f16_denorm: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_add_f16_e64 v1, v1, 1.0 clamp +; GFX9-NEXT: global_store_short v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_clamp_add_src_f16_denorm: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_u16 v1, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_add_f16_e64 v1, v1, 1.0 clamp +; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid @@ -118,15 +501,64 @@ ret void } -; GCN-LABEL: {{^}}v_clamp_add_src_f16_no_denormals: -; GCN: {{buffer|flat|global}}_load_ushort [[A:v[0-9]+]] -; GFX89-NOT: [[A]] -; GFX89: v_add_f16_e64 v{{[0-9]+}}, [[A]], 1.0 clamp{{$}} - -; SI: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], [[A]] -; SI: v_add_f32_e64 [[ADD:v[0-9]+]], [[CVT]], 1.0 clamp{{$}} -; SI: v_cvt_f16_f32_e32 v{{[0-9]+}}, [[ADD]] define amdgpu_kernel void @v_clamp_add_src_f16_no_denormals(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #3 { +; SI-LABEL: v_clamp_add_src_f16_no_denormals: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_clamp_add_src_f16_no_denormals: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 1, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ushort v3, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f16_e64 v2, v3, 1.0 clamp +; GFX8-NEXT: flat_store_short v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_clamp_add_src_f16_no_denormals: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_add_f16_e64 v1, v1, 1.0 clamp +; GFX9-NEXT: global_store_short v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_clamp_add_src_f16_no_denormals: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_u16 v1, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_add_f16_e64 v1, v1, 1.0 clamp +; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid @@ -138,11 +570,66 @@ ret void } -; GCN-LABEL: {{^}}v_clamp_add_src_v2f32: -; GCN: {{buffer|flat|global}}_load_dwordx2 v[[[A:[0-9]+]]:[[B:[0-9]+]]] -; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, v[[A]], 1.0 clamp{{$}} -; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, v[[B]], 1.0 clamp{{$}} define amdgpu_kernel void @v_clamp_add_src_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { +; SI-LABEL: v_clamp_add_src_v2f32: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp +; SI-NEXT: v_add_f32_e64 v3, v3, 1.0 clamp +; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_clamp_add_src_v2f32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v2 +; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp +; GFX8-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp +; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_clamp_add_src_v2f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp +; GFX9-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_clamp_add_src_v2f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp +; GFX11-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x float>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x float>, ptr addrspace(1) %out, i32 %tid @@ -154,10 +641,62 @@ ret void } -; GCN-LABEL: {{^}}v_clamp_add_src_f64: -; GCN: {{buffer|flat|global}}_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]] -; GCN: v_add_f64 v{{\[[0-9]+:[0-9]+\]}}, [[A]], 1.0 clamp{{$}} define amdgpu_kernel void @v_clamp_add_src_f64(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { +; SI-LABEL: v_clamp_add_src_f64: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 clamp +; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_clamp_add_src_f64: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v2 +; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 clamp +; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_clamp_add_src_f64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 clamp +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_clamp_add_src_f64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 clamp +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr double, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr double, ptr addrspace(1) %out, i32 %tid @@ -169,9 +708,72 @@ ret void } -; GCN-LABEL: {{^}}v_clamp_mac_to_mad: -; GCN: v_mad_f32 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]}} clamp{{$}} define amdgpu_kernel void @v_clamp_mac_to_mad(ptr addrspace(1) %out, ptr addrspace(1) %aptr, float %a) #0 { +; SI-LABEL: v_clamp_mac_to_mad: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; SI-NEXT: s_load_dword s8, s[0:1], 0xd +; SI-NEXT: s_mov_b32 s3, 0xf000 +; SI-NEXT: s_mov_b32 s2, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[0:1], s[6:7] +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_mov_b64 s[6:7], s[2:3] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mad_f32 v3, s8, s8, v2 clamp +; SI-NEXT: v_add_f32_e32 v2, v3, v2 +; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_clamp_mac_to_mad: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dword s0, s[0:1], 0x34 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s7 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, s5 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_f32 v2, s0, s0, v3 clamp +; GFX8-NEXT: v_add_f32_e32 v2, v2, v3 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_clamp_mac_to_mad: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NEXT: s_load_dword s2, s[0:1], 0x34 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dword v1, v0, s[6:7] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_mad_f32 v2, s2, s2, v1 clamp +; GFX9-NEXT: v_add_f32_e32 v1, v2, v1 +; GFX9-NEXT: global_store_dword v0, v1, s[4:5] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_clamp_mac_to_mad: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x34 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v1, v0, s[6:7] +; GFX11-NEXT: v_mul_f32_e64 v2, s0, s0 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_f32_e64 v2, v2, v1 clamp +; GFX11-NEXT: v_add_f32_e32 v1, v2, v1 +; GFX11-NEXT: global_store_b32 v0, v1, s[4:5] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -186,11 +788,73 @@ ret void } - -; GCN-LABEL: {{^}}v_clamp_add_src_v2f16_denorm: -; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] -; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[A]], 1.0 op_sel_hi:[1,0] clamp{{$}} define amdgpu_kernel void @v_clamp_add_src_v2f16_denorm(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { +; SI-LABEL: v_clamp_add_src_v2f16_denorm: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; SI-NEXT: v_add_f32_e64 v3, v3, 1.0 clamp +; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp +; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_or_b32_e32 v2, v2, v3 +; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_clamp_add_src_v2f16_denorm: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: v_mov_b32_e32 v4, 0x3c00 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f16_e64 v2, v3, 1.0 clamp +; GFX8-NEXT: v_add_f16_sdwa v3, v3, v4 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_e32 v2, v2, v3 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_clamp_add_src_v2f16_denorm: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dword v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] clamp +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_clamp_add_src_v2f16_denorm: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] clamp +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -202,10 +866,73 @@ ret void } -; GCN-LABEL: {{^}}v_clamp_add_src_v2f16_no_denormals: -; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] -; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[A]], 1.0 op_sel_hi:[1,0] clamp{{$}} define amdgpu_kernel void @v_clamp_add_src_v2f16_no_denormals(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #3 { +; SI-LABEL: v_clamp_add_src_v2f16_no_denormals: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; SI-NEXT: v_add_f32_e64 v3, v3, 1.0 clamp +; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp +; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_or_b32_e32 v2, v2, v3 +; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_clamp_add_src_v2f16_no_denormals: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: v_mov_b32_e32 v4, 0x3c00 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f16_e64 v2, v3, 1.0 clamp +; GFX8-NEXT: v_add_f16_sdwa v3, v3, v4 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_e32 v2, v2, v3 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_clamp_add_src_v2f16_no_denormals: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dword v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] clamp +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_clamp_add_src_v2f16_no_denormals: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] clamp +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -217,11 +944,86 @@ ret void } -; GCN-LABEL: {{^}}v_clamp_add_src_v2f16_denorm_neg: -; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] -; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[A]], 1.0 op_sel_hi:[1,0]{{$}} -; GFX9: v_pk_max_f16 [[MAX:v[0-9]+]], [[ADD]], [[ADD]] neg_lo:[1,1] neg_hi:[1,1] clamp{{$}} define amdgpu_kernel void @v_clamp_add_src_v2f16_denorm_neg(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { +; SI-LABEL: v_clamp_add_src_v2f16_denorm_neg: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; SI-NEXT: v_add_f32_e32 v3, 1.0, v3 +; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 +; SI-NEXT: v_add_f32_e32 v2, 1.0, v2 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_or_b32_e32 v2, v2, v3 +; SI-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e64 v3, v3 clamp +; SI-NEXT: v_cvt_f32_f16_e64 v2, v2 clamp +; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_or_b32_e32 v2, v2, v3 +; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_clamp_add_src_v2f16_denorm_neg: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: v_mov_b32_e32 v4, 0x3c00 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f16_e32 v2, 1.0, v3 +; GFX8-NEXT: v_add_f16_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_max_f16_sdwa v3, -v3, -v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_max_f16_e64 v2, -v2, -v2 clamp +; GFX8-NEXT: v_or_b32_e32 v2, v2, v3 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_clamp_add_src_v2f16_denorm_neg: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dword v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 neg_lo:[1,1] neg_hi:[1,1] clamp +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_clamp_add_src_v2f16_denorm_neg: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 neg_lo:[1,1] neg_hi:[1,1] clamp +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -234,11 +1036,78 @@ ret void } -; GCN-LABEL: {{^}}v_clamp_add_src_v2f16_denorm_neg_lo: -; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] -; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[A]], 1.0 op_sel_hi:[1,0]{{$}} -; GFX9: v_pk_max_f16 [[MAX:v[0-9]+]], [[ADD]], [[ADD]] neg_lo:[1,1] clamp{{$}} define amdgpu_kernel void @v_clamp_add_src_v2f16_denorm_neg_lo(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { +; SI-LABEL: v_clamp_add_src_v2f16_denorm_neg_lo: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; SI-NEXT: v_add_f32_e32 v2, 1.0, v2 +; SI-NEXT: v_add_f32_e64 v3, v3, 1.0 clamp +; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 +; SI-NEXT: v_max_f32_e64 v2, -v2, -v2 clamp +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_or_b32_e32 v2, v2, v3 +; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_clamp_add_src_v2f16_denorm_neg_lo: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: v_mov_b32_e32 v4, 0x3c00 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f16_e32 v2, 1.0, v3 +; GFX8-NEXT: v_add_f16_sdwa v3, v3, v4 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_max_f16_e64 v2, -v2, -v2 clamp +; GFX8-NEXT: v_or_b32_e32 v2, v2, v3 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_clamp_add_src_v2f16_denorm_neg_lo: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dword v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 neg_lo:[1,1] clamp +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_clamp_add_src_v2f16_denorm_neg_lo: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 neg_lo:[1,1] clamp +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -253,11 +1122,78 @@ ret void } -; GCN-LABEL: {{^}}v_clamp_add_src_v2f16_denorm_neg_hi: -; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] -; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[A]], 1.0 op_sel_hi:[1,0]{{$}} -; GFX9: v_pk_max_f16 [[MAX:v[0-9]+]], [[ADD]], [[ADD]] neg_hi:[1,1] clamp{{$}} define amdgpu_kernel void @v_clamp_add_src_v2f16_denorm_neg_hi(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { +; SI-LABEL: v_clamp_add_src_v2f16_denorm_neg_hi: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; SI-NEXT: v_add_f32_e32 v3, 1.0, v3 +; SI-NEXT: v_max_f32_e64 v3, -v3, -v3 clamp +; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp +; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_or_b32_e32 v2, v2, v3 +; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_clamp_add_src_v2f16_denorm_neg_hi: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: v_mov_b32_e32 v4, 0x3c00 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f16_e64 v2, v3, 1.0 clamp +; GFX8-NEXT: v_add_f16_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_max_f16_sdwa v3, -v3, -v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_or_b32_e32 v2, v2, v3 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_clamp_add_src_v2f16_denorm_neg_hi: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dword v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 neg_hi:[1,1] clamp +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_clamp_add_src_v2f16_denorm_neg_hi: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 neg_hi:[1,1] clamp +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -272,11 +1208,76 @@ ret void } -; GCN-LABEL: {{^}}v_clamp_add_src_v2f16_denorm_shuf: -; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] -; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[A]], 1.0 op_sel_hi:[1,0]{{$}} -; GFX9: v_pk_max_f16 [[MAX:v[0-9]+]], [[ADD]], [[ADD]] op_sel:[1,1] op_sel_hi:[0,0] clamp{{$}} define amdgpu_kernel void @v_clamp_add_src_v2f16_denorm_shuf(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { +; SI-LABEL: v_clamp_add_src_v2f16_denorm_shuf: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v3, v2 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; SI-NEXT: v_add_f32_e64 v3, v3, 1.0 clamp +; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 +; SI-NEXT: v_add_f32_e64 v2, v2, 1.0 clamp +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_or_b32_e32 v2, v2, v3 +; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_clamp_add_src_v2f16_denorm_shuf: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: v_mov_b32_e32 v4, 0x3c00 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f16_sdwa v2, v3, v4 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_add_f16_sdwa v3, v3, v4 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_or_b32_e32 v2, v2, v3 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_clamp_add_src_v2f16_denorm_shuf: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dword v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 op_sel:[1,1] op_sel_hi:[0,0] clamp +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_clamp_add_src_v2f16_denorm_shuf: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 op_sel:[1,1] op_sel_hi:[0,0] clamp +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -290,11 +1291,75 @@ ret void } -; GCN-LABEL: {{^}}v_no_clamp_add_src_v2f16_f32_src: -; GCN-DAG: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] -; GFX9: v_add_f32_e32 [[ADD:v[0-9]+]], 1.0, [[A]]{{$}} -; GFX9: v_pk_max_f16 [[CLAMP:v[0-9]+]], [[ADD]], [[ADD]] clamp{{$}} define amdgpu_kernel void @v_no_clamp_add_src_v2f16_f32_src(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { +; SI-LABEL: v_no_clamp_add_src_v2f16_f32_src: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_add_f32_e32 v2, 1.0, v2 +; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e64 v3, v3 clamp +; SI-NEXT: v_cvt_f32_f16_e64 v2, v2 clamp +; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_or_b32_e32 v2, v2, v3 +; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_no_clamp_add_src_v2f16_f32_src: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f32_e32 v2, 1.0, v3 +; GFX8-NEXT: v_max_f16_sdwa v3, v2, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_e64 v2, v2, v2 clamp +; GFX8-NEXT: v_or_b32_e32 v2, v2, v3 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_no_clamp_add_src_v2f16_f32_src: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dword v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 +; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 clamp +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_no_clamp_add_src_v2f16_f32_src: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_add_f32_e32 v1, 1.0, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 clamp +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -308,11 +1373,78 @@ ret void } -; GCN-LABEL: {{^}}v_no_clamp_add_packed_src_f32: -; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] -; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[A]], 1.0 op_sel_hi:[1,0]{{$}} -; GFX9: v_max_f32_e64 [[CLAMP:v[0-9]+]], [[ADD]], [[ADD]] clamp{{$}} define amdgpu_kernel void @v_no_clamp_add_packed_src_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { +; SI-LABEL: v_no_clamp_add_packed_src_f32: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; SI-NEXT: v_mov_b32_e32 v1, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; SI-NEXT: v_add_f32_e32 v3, 1.0, v3 +; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 +; SI-NEXT: v_add_f32_e32 v2, 1.0, v2 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_or_b32_e32 v2, v2, v3 +; SI-NEXT: v_max_f32_e64 v2, v2, v2 clamp +; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_no_clamp_add_packed_src_f32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GFX8-NEXT: v_mov_b32_e32 v4, 0x3c00 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f16_sdwa v2, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_add_f16_e32 v3, 1.0, v3 +; GFX8-NEXT: v_or_b32_e32 v2, v3, v2 +; GFX8-NEXT: v_max_f32_e64 v2, v2, v2 clamp +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_no_clamp_add_packed_src_f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dword v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_max_f32_e64 v1, v1, v1 clamp +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_no_clamp_add_packed_src_f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_max_f32_e64 v1, v1, v1 clamp +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -327,11 +1459,78 @@ ; Since the high bits are zeroed, it probably would be OK in this case ; to use clamp. -; GCN-LABEL: {{^}}v_no_clamp_add_src_v2f16_f16_src: -; GCN-DAG: {{buffer|flat|global}}_load_ushort [[A:v[0-9]+]] -; GFX9: v_add_f16_e32 [[ADD:v[0-9]+]], 1.0, [[A]]{{$}} -; GFX9: v_pk_max_f16 [[CLAMP:v[0-9]+]], [[ADD]], [[ADD]] clamp{{$}} define amdgpu_kernel void @v_no_clamp_add_src_v2f16_f16_src(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { +; SI-LABEL: v_no_clamp_add_src_v2f16_f16_src: +; SI: ; %bb.0: +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, 0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 1, v0 +; SI-NEXT: v_mov_b32_e32 v2, 0 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_mov_b64 s[4:5], s[2:3] +; SI-NEXT: buffer_load_ushort v1, v[1:2], s[4:7], 0 addr64 +; SI-NEXT: v_cvt_f32_f16_e64 v3, s6 clamp +; SI-NEXT: s_mov_b64 s[2:3], s[6:7] +; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SI-NEXT: v_add_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: v_cvt_f32_f16_e64 v1, v1 clamp +; SI-NEXT: v_cvt_f16_f32_e32 v4, v1 +; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v0 +; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v3 +; SI-NEXT: v_or_b32_e32 v0, v4, v0 +; SI-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr64 +; SI-NEXT: s_endpgm +; +; GFX8-LABEL: v_no_clamp_add_src_v2f16_f16_src: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 1, v0 +; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s3 +; GFX8-NEXT: v_add_u32_e32 v1, vcc, s2, v1 +; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc +; GFX8-NEXT: flat_load_ushort v2, v[1:2] +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_f16_e64 v2, v2, 1.0 clamp +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: v_no_clamp_add_src_v2f16_f16_src: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v0 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_ushort v1, v1, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_add_f16_e32 v1, 1.0, v1 +; GFX9-NEXT: v_pk_max_f16 v1, v1, v1 clamp +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v_no_clamp_add_src_v2f16_f16_src: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v1, 1, v0 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_u16 v1, v1, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_add_f16_e32 v1, 1.0, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; GFX11-NEXT: v_pk_max_f16 v1, v1, v1 clamp +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -348,20 +1547,37 @@ ; FIXME: Worse code pre-gfx9 -; GCN-LABEL: {{^}}v_clamp_cvt_pkrtz_src_v2f16_denorm: -; GFX9: s_waitcnt -; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, v1 clamp{{$}} -; GFX9-NEXT: s_setpc_b64 - -; VI: v_cvt_pkrtz_f16_f32 v0, v0, v1{{$}} -; VI: v_max_f16_sdwa -; VI: v_max_f16_e64 -; VI: v_or_b32 - -; SI: v_cvt_pkrtz_f16_f32_e32 v0, v0, v1{{$}} -; SI-DAG: v_cvt_f32_f16_e64 v0, v0 clamp -; SI-DAG: v_cvt_f32_f16_e64 v1, v1 clamp define <2 x half> @v_clamp_cvt_pkrtz_src_v2f16_denorm(float %a, float %b) #0 { +; SI-LABEL: v_clamp_cvt_pkrtz_src_v2f16_denorm: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_cvt_pkrtz_f16_f32_e32 v0, v0, v1 +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0 +; SI-NEXT: v_cvt_f32_f16_e64 v0, v0 clamp +; SI-NEXT: v_cvt_f32_f16_e64 v1, v1 clamp +; SI-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_clamp_cvt_pkrtz_src_v2f16_denorm: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, v1 +; GFX8-NEXT: v_max_f16_sdwa v1, v0, v0 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_e64 v0, v0, v0 clamp +; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_clamp_cvt_pkrtz_src_v2f16_denorm: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, v1 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_clamp_cvt_pkrtz_src_v2f16_denorm: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_cvt_pk_rtz_f16_f32_e64 v0, v0, v1 clamp +; GFX11-NEXT: s_setpc_b64 s[30:31] %add = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %a, float %b) %max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %add, <2 x half> zeroinitializer) %clamp = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> ) diff --git a/llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll b/llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll --- a/llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX8 %s +; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11 %s ; FIXME: This should be merged with sint_to_fp.ll, but s_sint_to_fp_v2i64 crashes on r600 @@ -50,6 +51,33 @@ ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: flat_store_short v[0:1], v2 ; GFX8-NEXT: s_endpgm +; +; GFX11-LABEL: s_sint_to_fp_i64_to_f16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_xor_b32 s4, s2, s3 +; GFX11-NEXT: s_cls_i32 s5, s3 +; GFX11-NEXT: s_ashr_i32 s4, s4, 31 +; GFX11-NEXT: s_add_i32 s5, s5, -1 +; GFX11-NEXT: s_add_i32 s4, s4, 32 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_min_u32 s4, s5, s4 +; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], s4 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_min_u32 s2, s2, 1 +; GFX11-NEXT: s_or_b32 s2, s3, s2 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_cvt_f32_i32_e32 v0, s2 +; GFX11-NEXT: s_sub_i32 s2, 32, s4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_ldexp_f32 v0, v0, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX11-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %result = sitofp i64 %in to half store half %result, ptr addrspace(1) %out ret void @@ -114,6 +142,36 @@ ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; GFX8-NEXT: flat_store_short v[0:1], v3 ; GFX8-NEXT: s_endpgm +; +; GFX11-LABEL: v_sint_to_fp_i64_to_f16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v1, 3, v0 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b64 v[1:2], v1, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_xor_b32_e32 v3, v1, v2 +; GFX11-NEXT: v_cls_i32_e32 v4, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v3 +; GFX11-NEXT: v_add_nc_u32_e32 v4, -1, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_nc_u32_e32 v3, 32, v3 +; GFX11-NEXT: v_min_u32_e32 v3, v4, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b64 v[1:2], v3, v[1:2] +; GFX11-NEXT: v_min_u32_e32 v1, 1, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_or_b32_e32 v1, v2, v1 +; GFX11-NEXT: v_sub_nc_u32_e32 v2, 32, v3 +; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_ldexp_f32 v1, v1, v2 +; GFX11-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid %out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid @@ -167,6 +225,31 @@ ; GFX8-NEXT: v_ldexp_f32 v2, v2, s0 ; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: s_endpgm +; +; GFX11-LABEL: s_sint_to_fp_i64_to_f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_xor_b32 s4, s2, s3 +; GFX11-NEXT: s_cls_i32 s5, s3 +; GFX11-NEXT: s_ashr_i32 s4, s4, 31 +; GFX11-NEXT: s_add_i32 s5, s5, -1 +; GFX11-NEXT: s_add_i32 s4, s4, 32 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_min_u32 s4, s5, s4 +; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], s4 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_min_u32 s2, s2, 1 +; GFX11-NEXT: s_or_b32 s2, s3, s2 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_cvt_f32_i32_e32 v0, s2 +; GFX11-NEXT: s_sub_i32 s2, 32, s4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_ldexp_f32 v0, v0, s2 +; GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %result = sitofp i64 %in to float store float %result, ptr addrspace(1) %out ret void @@ -229,6 +312,35 @@ ; GFX8-NEXT: v_ldexp_f32 v2, v5, v2 ; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: s_endpgm +; +; GFX11-LABEL: v_sint_to_fp_i64_to_f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v1, 3, v0 +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_load_b64 v[1:2], v1, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_xor_b32_e32 v3, v1, v2 +; GFX11-NEXT: v_cls_i32_e32 v4, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v3 +; GFX11-NEXT: v_add_nc_u32_e32 v4, -1, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_nc_u32_e32 v3, 32, v3 +; GFX11-NEXT: v_min_u32_e32 v3, v4, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b64 v[1:2], v3, v[1:2] +; GFX11-NEXT: v_min_u32_e32 v1, 1, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_or_b32_e32 v1, v2, v1 +; GFX11-NEXT: v_sub_nc_u32_e32 v2, 32, v3 +; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_ldexp_f32 v1, v1, v2 +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -306,6 +418,42 @@ ; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GFX8-NEXT: s_endpgm +; +; GFX11-LABEL: s_sint_to_fp_v2i64_to_v2f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v3, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_xor_b32 s3, s6, s7 +; GFX11-NEXT: s_xor_b32 s9, s4, s5 +; GFX11-NEXT: s_cls_i32 s2, s7 +; GFX11-NEXT: s_cls_i32 s8, s5 +; GFX11-NEXT: s_ashr_i32 s3, s3, 31 +; GFX11-NEXT: s_ashr_i32 s9, s9, 31 +; GFX11-NEXT: s_add_i32 s2, s2, -1 +; GFX11-NEXT: s_add_i32 s8, s8, -1 +; GFX11-NEXT: s_add_i32 s3, s3, 32 +; GFX11-NEXT: s_add_i32 s9, s9, 32 +; GFX11-NEXT: s_min_u32 s10, s2, s3 +; GFX11-NEXT: s_min_u32 s8, s8, s9 +; GFX11-NEXT: s_lshl_b64 s[2:3], s[6:7], s10 +; GFX11-NEXT: s_lshl_b64 s[4:5], s[4:5], s8 +; GFX11-NEXT: s_min_u32 s2, s2, 1 +; GFX11-NEXT: s_min_u32 s4, s4, 1 +; GFX11-NEXT: s_or_b32 s2, s3, s2 +; GFX11-NEXT: s_or_b32 s3, s5, s4 +; GFX11-NEXT: v_cvt_f32_i32_e32 v0, s2 +; GFX11-NEXT: v_cvt_f32_i32_e32 v2, s3 +; GFX11-NEXT: s_sub_i32 s2, 32, s10 +; GFX11-NEXT: s_sub_i32 s3, 32, s8 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_ldexp_f32 v1, v0, s2 +; GFX11-NEXT: v_ldexp_f32 v0, v2, s3 +; GFX11-NEXT: global_store_b64 v3, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %result = sitofp <2 x i64> %in to <2 x float> store <2 x float> %result, ptr addrspace(1) %out ret void @@ -447,6 +595,73 @@ ; GFX8-NEXT: v_ldexp_f32 v2, v4, v12 ; GFX8-NEXT: flat_store_dwordx4 v[9:10], v[0:3] ; GFX8-NEXT: s_endpgm +; +; GFX11-LABEL: v_sint_to_fp_v4i64_to_v4f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v5, 5, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_load_b128 v[1:4], v5, s[2:3] offset:16 +; GFX11-NEXT: global_load_b128 v[5:8], v5, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(1) +; GFX11-NEXT: v_xor_b32_e32 v9, v3, v4 +; GFX11-NEXT: v_xor_b32_e32 v11, v1, v2 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_xor_b32_e32 v13, v7, v8 +; GFX11-NEXT: v_xor_b32_e32 v15, v5, v6 +; GFX11-NEXT: v_cls_i32_e32 v10, v4 +; GFX11-NEXT: v_cls_i32_e32 v12, v2 +; GFX11-NEXT: v_cls_i32_e32 v14, v8 +; GFX11-NEXT: v_cls_i32_e32 v16, v6 +; GFX11-NEXT: v_ashrrev_i32_e32 v9, 31, v9 +; GFX11-NEXT: v_ashrrev_i32_e32 v11, 31, v11 +; GFX11-NEXT: v_ashrrev_i32_e32 v13, 31, v13 +; GFX11-NEXT: v_ashrrev_i32_e32 v15, 31, v15 +; GFX11-NEXT: v_add_nc_u32_e32 v10, -1, v10 +; GFX11-NEXT: v_add_nc_u32_e32 v12, -1, v12 +; GFX11-NEXT: v_add_nc_u32_e32 v14, -1, v14 +; GFX11-NEXT: v_add_nc_u32_e32 v16, -1, v16 +; GFX11-NEXT: v_add_nc_u32_e32 v9, 32, v9 +; GFX11-NEXT: v_add_nc_u32_e32 v11, 32, v11 +; GFX11-NEXT: v_add_nc_u32_e32 v13, 32, v13 +; GFX11-NEXT: v_add_nc_u32_e32 v15, 32, v15 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_min_u32_e32 v9, v10, v9 +; GFX11-NEXT: v_min_u32_e32 v10, v12, v11 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_min_u32_e32 v11, v14, v13 +; GFX11-NEXT: v_min_u32_e32 v12, v16, v15 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_lshlrev_b64 v[3:4], v9, v[3:4] +; GFX11-NEXT: v_lshlrev_b64 v[1:2], v10, v[1:2] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_lshlrev_b64 v[7:8], v11, v[7:8] +; GFX11-NEXT: v_lshlrev_b64 v[5:6], v12, v[5:6] +; GFX11-NEXT: v_sub_nc_u32_e32 v9, 32, v9 +; GFX11-NEXT: v_sub_nc_u32_e32 v10, 32, v10 +; GFX11-NEXT: v_min_u32_e32 v3, 1, v3 +; GFX11-NEXT: v_min_u32_e32 v1, 1, v1 +; GFX11-NEXT: v_min_u32_e32 v7, 1, v7 +; GFX11-NEXT: v_min_u32_e32 v5, 1, v5 +; GFX11-NEXT: v_sub_nc_u32_e32 v11, 32, v11 +; GFX11-NEXT: v_or_b32_e32 v3, v4, v3 +; GFX11-NEXT: v_or_b32_e32 v1, v2, v1 +; GFX11-NEXT: v_or_b32_e32 v2, v8, v7 +; GFX11-NEXT: v_or_b32_e32 v4, v6, v5 +; GFX11-NEXT: v_sub_nc_u32_e32 v5, 32, v12 +; GFX11-NEXT: v_cvt_f32_i32_e32 v3, v3 +; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1 +; GFX11-NEXT: v_cvt_f32_i32_e32 v6, v2 +; GFX11-NEXT: v_cvt_f32_i32_e32 v4, v4 +; GFX11-NEXT: v_lshlrev_b32_e32 v7, 4, v0 +; GFX11-NEXT: v_ldexp_f32 v3, v3, v9 +; GFX11-NEXT: v_ldexp_f32 v2, v1, v10 +; GFX11-NEXT: v_ldexp_f32 v1, v6, v11 +; GFX11-NEXT: v_ldexp_f32 v0, v4, v5 +; GFX11-NEXT: global_store_b128 v7, v[0:3], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %in.gep = getelementptr <4 x i64>, ptr addrspace(1) %in, i32 %tid %out.gep = getelementptr <4 x float>, ptr addrspace(1) %out, i32 %tid @@ -531,6 +746,47 @@ ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: s_endpgm +; +; GFX11-LABEL: s_sint_to_fp_v2i64_to_v2f16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_xor_b32 s3, s6, s7 +; GFX11-NEXT: s_xor_b32 s9, s4, s5 +; GFX11-NEXT: s_cls_i32 s2, s7 +; GFX11-NEXT: s_cls_i32 s8, s5 +; GFX11-NEXT: s_ashr_i32 s3, s3, 31 +; GFX11-NEXT: s_ashr_i32 s9, s9, 31 +; GFX11-NEXT: s_add_i32 s2, s2, -1 +; GFX11-NEXT: s_add_i32 s8, s8, -1 +; GFX11-NEXT: s_add_i32 s3, s3, 32 +; GFX11-NEXT: s_add_i32 s9, s9, 32 +; GFX11-NEXT: s_min_u32 s10, s2, s3 +; GFX11-NEXT: s_min_u32 s8, s8, s9 +; GFX11-NEXT: s_lshl_b64 s[2:3], s[6:7], s10 +; GFX11-NEXT: s_lshl_b64 s[4:5], s[4:5], s8 +; GFX11-NEXT: s_min_u32 s2, s2, 1 +; GFX11-NEXT: s_min_u32 s4, s4, 1 +; GFX11-NEXT: s_or_b32 s2, s3, s2 +; GFX11-NEXT: s_or_b32 s3, s5, s4 +; GFX11-NEXT: v_cvt_f32_i32_e32 v0, s2 +; GFX11-NEXT: v_cvt_f32_i32_e32 v1, s3 +; GFX11-NEXT: s_sub_i32 s2, 32, s10 +; GFX11-NEXT: s_sub_i32 s3, 32, s8 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_ldexp_f32 v0, v0, s2 +; GFX11-NEXT: v_ldexp_f32 v1, v1, s3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX11-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_pack_b32_f16 v0, v1, v0 +; GFX11-NEXT: global_store_b32 v2, v0, s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %result = sitofp <2 x i64> %in to <2 x half> store <2 x half> %result, ptr addrspace(1) %out ret void @@ -686,6 +942,82 @@ ; GFX8-NEXT: v_or_b32_e32 v3, v6, v5 ; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3] ; GFX8-NEXT: s_endpgm +; +; GFX11-LABEL: v_sint_to_fp_v4i64_to_v4f16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_lshlrev_b32_e32 v5, 5, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_load_b128 v[1:4], v5, s[2:3] offset:16 +; GFX11-NEXT: global_load_b128 v[5:8], v5, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(1) +; GFX11-NEXT: v_xor_b32_e32 v9, v3, v4 +; GFX11-NEXT: v_xor_b32_e32 v11, v1, v2 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_xor_b32_e32 v13, v7, v8 +; GFX11-NEXT: v_xor_b32_e32 v15, v5, v6 +; GFX11-NEXT: v_cls_i32_e32 v10, v4 +; GFX11-NEXT: v_cls_i32_e32 v12, v2 +; GFX11-NEXT: v_cls_i32_e32 v14, v8 +; GFX11-NEXT: v_cls_i32_e32 v16, v6 +; GFX11-NEXT: v_ashrrev_i32_e32 v9, 31, v9 +; GFX11-NEXT: v_ashrrev_i32_e32 v11, 31, v11 +; GFX11-NEXT: v_ashrrev_i32_e32 v13, 31, v13 +; GFX11-NEXT: v_ashrrev_i32_e32 v15, 31, v15 +; GFX11-NEXT: v_add_nc_u32_e32 v10, -1, v10 +; GFX11-NEXT: v_add_nc_u32_e32 v12, -1, v12 +; GFX11-NEXT: v_add_nc_u32_e32 v14, -1, v14 +; GFX11-NEXT: v_add_nc_u32_e32 v16, -1, v16 +; GFX11-NEXT: v_add_nc_u32_e32 v9, 32, v9 +; GFX11-NEXT: v_add_nc_u32_e32 v11, 32, v11 +; GFX11-NEXT: v_add_nc_u32_e32 v13, 32, v13 +; GFX11-NEXT: v_add_nc_u32_e32 v15, 32, v15 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_min_u32_e32 v9, v10, v9 +; GFX11-NEXT: v_min_u32_e32 v10, v12, v11 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_min_u32_e32 v11, v14, v13 +; GFX11-NEXT: v_min_u32_e32 v12, v16, v15 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_lshlrev_b64 v[3:4], v9, v[3:4] +; GFX11-NEXT: v_lshlrev_b64 v[1:2], v10, v[1:2] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_lshlrev_b64 v[7:8], v11, v[7:8] +; GFX11-NEXT: v_lshlrev_b64 v[5:6], v12, v[5:6] +; GFX11-NEXT: v_sub_nc_u32_e32 v9, 32, v9 +; GFX11-NEXT: v_sub_nc_u32_e32 v10, 32, v10 +; GFX11-NEXT: v_min_u32_e32 v3, 1, v3 +; GFX11-NEXT: v_min_u32_e32 v1, 1, v1 +; GFX11-NEXT: v_min_u32_e32 v7, 1, v7 +; GFX11-NEXT: v_min_u32_e32 v5, 1, v5 +; GFX11-NEXT: v_sub_nc_u32_e32 v11, 32, v11 +; GFX11-NEXT: v_or_b32_e32 v3, v4, v3 +; GFX11-NEXT: v_or_b32_e32 v1, v2, v1 +; GFX11-NEXT: v_or_b32_e32 v2, v8, v7 +; GFX11-NEXT: v_or_b32_e32 v4, v6, v5 +; GFX11-NEXT: v_sub_nc_u32_e32 v5, 32, v12 +; GFX11-NEXT: v_cvt_f32_i32_e32 v3, v3 +; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1 +; GFX11-NEXT: v_cvt_f32_i32_e32 v2, v2 +; GFX11-NEXT: v_cvt_f32_i32_e32 v4, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_ldexp_f32 v3, v3, v9 +; GFX11-NEXT: v_ldexp_f32 v1, v1, v10 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_ldexp_f32 v2, v2, v11 +; GFX11-NEXT: v_ldexp_f32 v4, v4, v5 +; GFX11-NEXT: v_lshlrev_b32_e32 v5, 3, v0 +; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GFX11-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX11-NEXT: v_cvt_f16_f32_e32 v4, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_pack_b32_f16 v1, v1, v3 +; GFX11-NEXT: v_pack_b32_f16 v0, v4, v2 +; GFX11-NEXT: global_store_b64 v5, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %in.gep = getelementptr <4 x i64>, ptr addrspace(1) %in, i32 %tid %out.gep = getelementptr <4 x half>, ptr addrspace(1) %out, i32 %tid