diff --git a/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp b/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
--- a/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
+++ b/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
@@ -84,7 +84,7 @@
              "without hoisting."));
 
 static cl::opt<bool> ConstHoistGEP(
-    "consthoist-gep", cl::init(false), cl::Hidden,
+    "consthoist-gep", cl::init(true), cl::Hidden,
     cl::desc("Try hoisting constant gep expressions"));
 
 static cl::opt<unsigned>
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
@@ -1,5 +1,5 @@
 ; REQUIRES: asserts
-; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -consthoist-gep=false -o - 2>&1 > /dev/null | FileCheck %s
 
 ; CHECK:       ********** MI Scheduling **********
 ; We need second, post-ra scheduling to have VSTM instruction combined from single-stores
diff --git a/llvm/test/CodeGen/PowerPC/pr52894-32bit.ll b/llvm/test/CodeGen/PowerPC/pr52894-32bit.ll
--- a/llvm/test/CodeGen/PowerPC/pr52894-32bit.ll
+++ b/llvm/test/CodeGen/PowerPC/pr52894-32bit.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
-; RUN:   -mcpu=pwr8 -mtriple=powerpcle < %s | FileCheck %s
+; RUN:   -mcpu=pwr8 -mtriple=powerpcle -consthoist-gep=false < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
-; RUN:   -mcpu=pwr8 -mtriple=powerpc < %s | FileCheck %s
+; RUN:   -mcpu=pwr8 -mtriple=powerpc -consthoist-gep=false < %s | FileCheck %s
 %struct.d = type { [131072 x i32] }
 
 @a = dso_local local_unnamed_addr global [4096 x i32] zeroinitializer, align 4
diff --git a/llvm/test/CodeGen/PowerPC/pr52894.ll b/llvm/test/CodeGen/PowerPC/pr52894.ll
--- a/llvm/test/CodeGen/PowerPC/pr52894.ll
+++ b/llvm/test/CodeGen/PowerPC/pr52894.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
-; RUN:   -mcpu=pwr8 -mtriple=powerpc64le < %s | FileCheck %s
+; RUN:   -mcpu=pwr8 -mtriple=powerpc64le -consthoist-gep=false < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
-; RUN:   -mcpu=pwr8 -mtriple=powerpc64 < %s | FileCheck %s
+; RUN:   -mcpu=pwr8 -mtriple=powerpc64 -consthoist-gep=false < %s | FileCheck %s
 %struct.d = type { [131072 x i32] }
 
 @a = dso_local local_unnamed_addr global [4096 x i32] zeroinitializer, align 4
diff --git a/llvm/test/CodeGen/RISCV/global-merge.ll b/llvm/test/CodeGen/RISCV/global-merge.ll
--- a/llvm/test/CodeGen/RISCV/global-merge.ll
+++ b/llvm/test/CodeGen/RISCV/global-merge.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -riscv-enable-global-merge -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -riscv-enable-global-merge -verify-machineinstrs -consthoist-gep=false < %s \
 ; RUN:   | FileCheck %s
-; RUN: llc -mtriple=riscv64 -riscv-enable-global-merge -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -riscv-enable-global-merge -verify-machineinstrs -consthoist-gep=false < %s \
 ; RUN:   | FileCheck %s
 
 @ig1 = internal global i32 0, align 4
diff --git a/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll b/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
--- a/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
+++ b/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
@@ -35,8 +35,9 @@
 ; CHECK-NEXT:    lw a1, 164(a0)
 ; CHECK-NEXT:    blez a1, .LBB1_2
 ; CHECK-NEXT:  # %bb.1: # %if.then
+; CHECK-NEXT:    addi a0, a0, 160
 ; CHECK-NEXT:    li a1, 10
-; CHECK-NEXT:    sw a1, 160(a0)
+; CHECK-NEXT:    sw a1, 0(a0)
 ; CHECK-NEXT:  .LBB1_2: # %if.end
 ; CHECK-NEXT:    ret
 entry:
@@ -119,12 +120,12 @@
 ; CHECK-NEXT:    lui a0, %hi(s)
 ; CHECK-NEXT:    addi a0, a0, %lo(s)
 ; CHECK-NEXT:    lw a1, 164(a0)
+; CHECK-NEXT:    addi a0, a0, 160
 ; CHECK-NEXT:    beqz a1, .LBB7_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
-; CHECK-NEXT:    addi a0, a0, 168
+; CHECK-NEXT:    addi a0, a0, 8
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB7_2: # %if.then
-; CHECK-NEXT:    addi a0, a0, 160
 ; CHECK-NEXT:    ret
 entry:
   %0 = load i32, ptr getelementptr inbounds (%struct.S, ptr @s, i32 0, i32 2), align 4
@@ -284,12 +285,14 @@
 define dso_local void @rmw_with_control_flow() nounwind {
 ; CHECK-LABEL: rmw_with_control_flow:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lui a0, %hi(s+164)
-; CHECK-NEXT:    lw a1, %lo(s+164)(a0)
+; CHECK-NEXT:    lui a0, %hi(s)
+; CHECK-NEXT:    addi a0, a0, %lo(s)
+; CHECK-NEXT:    lw a1, 164(a0)
 ; CHECK-NEXT:    blez a1, .LBB17_2
 ; CHECK-NEXT:  # %bb.1: # %if.then
+; CHECK-NEXT:    addi a0, a0, 164
 ; CHECK-NEXT:    li a1, 10
-; CHECK-NEXT:    sw a1, %lo(s+164)(a0)
+; CHECK-NEXT:    sw a1, 0(a0)
 ; CHECK-NEXT:  .LBB17_2: # %if.end
 ; CHECK-NEXT:    ret
 entry:
diff --git a/llvm/test/CodeGen/RISCV/unroll-loop-cse.ll b/llvm/test/CodeGen/RISCV/unroll-loop-cse.ll
--- a/llvm/test/CodeGen/RISCV/unroll-loop-cse.ll
+++ b/llvm/test/CodeGen/RISCV/unroll-loop-cse.ll
@@ -17,34 +17,28 @@
 ; CHECK-NEXT:    li a0, 1
 ; CHECK-NEXT:    bne a3, a4, .LBB0_6
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    addi a1, a1, %lo(x)
-; CHECK-NEXT:    lw a1, 4(a1)
 ; CHECK-NEXT:    addi a2, a2, %lo(check)
-; CHECK-NEXT:    lw a2, 4(a2)
-; CHECK-NEXT:    bne a1, a2, .LBB0_6
+; CHECK-NEXT:    addi a3, a1, %lo(x)
+; CHECK-NEXT:    lw a1, 4(a3)
+; CHECK-NEXT:    lw a4, 4(a2)
+; CHECK-NEXT:    bne a1, a4, .LBB0_6
 ; CHECK-NEXT:  # %bb.2:
-; CHECK-NEXT:    lui a1, %hi(x)
-; CHECK-NEXT:    addi a1, a1, %lo(x)
-; CHECK-NEXT:    lw a3, 8(a1)
-; CHECK-NEXT:    lui a2, %hi(check)
-; CHECK-NEXT:    addi a2, a2, %lo(check)
-; CHECK-NEXT:    lw a4, 8(a2)
+; CHECK-NEXT:    addi a1, a2, 4
+; CHECK-NEXT:    addi a2, a3, 4
+; CHECK-NEXT:    lw a3, 4(a2)
+; CHECK-NEXT:    lw a4, 4(a1)
 ; CHECK-NEXT:    bne a3, a4, .LBB0_6
 ; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    lw a1, 12(a1)
-; CHECK-NEXT:    lw a2, 12(a2)
-; CHECK-NEXT:    bne a1, a2, .LBB0_6
+; CHECK-NEXT:    lw a3, 8(a2)
+; CHECK-NEXT:    lw a4, 8(a1)
+; CHECK-NEXT:    bne a3, a4, .LBB0_6
 ; CHECK-NEXT:  # %bb.4:
-; CHECK-NEXT:    lui a1, %hi(x)
-; CHECK-NEXT:    addi a1, a1, %lo(x)
-; CHECK-NEXT:    lw a3, 16(a1)
-; CHECK-NEXT:    lui a2, %hi(check)
-; CHECK-NEXT:    addi a2, a2, %lo(check)
-; CHECK-NEXT:    lw a4, 16(a2)
+; CHECK-NEXT:    lw a3, 12(a2)
+; CHECK-NEXT:    lw a4, 12(a1)
 ; CHECK-NEXT:    bne a3, a4, .LBB0_6
 ; CHECK-NEXT:  # %bb.5:
-; CHECK-NEXT:    lw a0, 20(a1)
-; CHECK-NEXT:    lw a1, 20(a2)
+; CHECK-NEXT:    lw a0, 16(a2)
+; CHECK-NEXT:    lw a1, 16(a1)
 ; CHECK-NEXT:    xor a0, a0, a1
 ; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:  .LBB0_6:
diff --git a/llvm/test/CodeGen/Thumb/consthoist-imm8-costs-1.ll b/llvm/test/CodeGen/Thumb/consthoist-imm8-costs-1.ll
--- a/llvm/test/CodeGen/Thumb/consthoist-imm8-costs-1.ll
+++ b/llvm/test/CodeGen/Thumb/consthoist-imm8-costs-1.ll
@@ -1,4 +1,4 @@
-; RUN: llc %s -o - | FileCheck %s
+; RUN: llc -consthoist-gep=false %s -o - | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
 target triple = "thumbv6m-none-unknown-musleabi"
diff --git a/llvm/test/CodeGen/Thumb2/mve-blockplacement.ll b/llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
--- a/llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve -consthoist-gep=false %s -o - | FileCheck %s
 
 @var_36 = hidden local_unnamed_addr global i8 0, align 1
 @arr_61 = hidden local_unnamed_addr global [1 x i32] zeroinitializer, align 4
diff --git a/llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll b/llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll
--- a/llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll
@@ -528,239 +528,238 @@
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
 ; CHECK-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT:    .pad #12
-; CHECK-NEXT:    sub sp, #12
+; CHECK-NEXT:    .pad #24
+; CHECK-NEXT:    sub sp, #24
 ; CHECK-NEXT:    cmp r0, #0
 ; CHECK-NEXT:    mov.w r1, #11
 ; CHECK-NEXT:    cinc r1, r1, ne
 ; CHECK-NEXT:    movs r0, #38
 ; CHECK-NEXT:    mul r2, r1, r0
-; CHECK-NEXT:    str r1, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT:    str r1, [sp, #20] @ 4-byte Spill
 ; CHECK-NEXT:    movw r0, :lower16:arr_22
 ; CHECK-NEXT:    vmov.i32 q0, #0x0
 ; CHECK-NEXT:    movt r0, :upper16:arr_22
 ; CHECK-NEXT:    add.w r1, r2, #15
 ; CHECK-NEXT:    lsrs r3, r1, #4
-; CHECK-NEXT:    strd r3, r2, [sp] @ 8-byte Folded Spill
+; CHECK-NEXT:    strd r3, r2, [sp, #8] @ 8-byte Folded Spill
 ; CHECK-NEXT:    wlstp.8 lr, r2, .LBB19_2
 ; CHECK-NEXT:  .LBB19_1: @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vstrb.8 q0, [r0], #16
 ; CHECK-NEXT:    letp lr, .LBB19_1
 ; CHECK-NEXT:  .LBB19_2: @ %entry
-; CHECK-NEXT:    ldr r0, [sp, #8] @ 4-byte Reload
-; CHECK-NEXT:    movw r6, :lower16:arr_20
-; CHECK-NEXT:    movt r6, :upper16:arr_20
-; CHECK-NEXT:    add.w r3, r6, #80
+; CHECK-NEXT:    movw r2, :lower16:arr_21
+; CHECK-NEXT:    ldr r0, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT:    movt r2, :upper16:arr_21
+; CHECK-NEXT:    movw r3, :lower16:arr_20
+; CHECK-NEXT:    adds r2, #36
+; CHECK-NEXT:    movt r3, :upper16:arr_20
 ; CHECK-NEXT:    dls lr, r0
-; CHECK-NEXT:    movw r0, :lower16:arr_21
-; CHECK-NEXT:    movt r0, :upper16:arr_21
-; CHECK-NEXT:    add.w r5, r0, #36
-; CHECK-NEXT:    add.w r11, r6, #128
-; CHECK-NEXT:    add.w r7, r6, #112
-; CHECK-NEXT:    add.w r2, r6, #96
-; CHECK-NEXT:    add.w r4, r6, #64
-; CHECK-NEXT:    add.w r0, r6, #48
-; CHECK-NEXT:    add.w r1, r6, #32
-; CHECK-NEXT:    add.w r12, r6, #16
-; CHECK-NEXT:    adr r6, .LCPI19_0
-; CHECK-NEXT:    vldrw.u32 q0, [r6]
-; CHECK-NEXT:    movw r6, :lower16:arr_20
-; CHECK-NEXT:    mov.w r8, #327685
-; CHECK-NEXT:    mov.w r9, #5
+; CHECK-NEXT:    str r2, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT:    adr r2, .LCPI19_0
+; CHECK-NEXT:    add.w r10, r3, #128
+; CHECK-NEXT:    vldrw.u32 q0, [r2]
+; CHECK-NEXT:    add.w r11, r3, #112
+; CHECK-NEXT:    add.w r4, r3, #96
+; CHECK-NEXT:    add.w r6, r3, #80
+; CHECK-NEXT:    add.w r7, r3, #64
+; CHECK-NEXT:    add.w r5, r3, #48
+; CHECK-NEXT:    add.w r0, r3, #32
+; CHECK-NEXT:    add.w r1, r3, #16
+; CHECK-NEXT:    mov r2, r3
+; CHECK-NEXT:    ldr r3, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT:    mov.w r12, #327685
+; CHECK-NEXT:    mov.w r8, #5
 ; CHECK-NEXT:    vmov.i16 q1, #0x5
-; CHECK-NEXT:    mov.w r10, #0
-; CHECK-NEXT:    movt r6, :upper16:arr_20
+; CHECK-NEXT:    mov.w r9, #0
 ; CHECK-NEXT:  .LBB19_3: @ %for.cond8.preheader
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    str r8, [r5, #-4]
-; CHECK-NEXT:    vstrh.16 q1, [r5, #-36]
-; CHECK-NEXT:    strh.w r9, [r5]
-; CHECK-NEXT:    vstrh.16 q1, [r5, #-20]
-; CHECK-NEXT:    vstrw.32 q0, [r3]
-; CHECK-NEXT:    vstrh.16 q0, [r12], #152
-; CHECK-NEXT:    vstrh.16 q0, [r6], #152
+; CHECK-NEXT:    str r12, [r3, #-4]
+; CHECK-NEXT:    vstrh.16 q1, [r3, #-36]
+; CHECK-NEXT:    strh.w r8, [r3]
+; CHECK-NEXT:    vstrh.16 q1, [r3, #-20]
+; CHECK-NEXT:    vstrw.32 q0, [r6]
 ; CHECK-NEXT:    vstrh.16 q0, [r1], #152
-; CHECK-NEXT:    vstrh.16 q0, [r0], #152
-; CHECK-NEXT:    vstrh.16 q0, [r4], #152
 ; CHECK-NEXT:    vstrh.16 q0, [r2], #152
+; CHECK-NEXT:    vstrh.16 q0, [r0], #152
+; CHECK-NEXT:    vstrh.16 q0, [r5], #152
 ; CHECK-NEXT:    vstrh.16 q0, [r7], #152
+; CHECK-NEXT:    vstrh.16 q0, [r4], #152
 ; CHECK-NEXT:    vstrh.16 q0, [r11], #152
-; CHECK-NEXT:    strd r9, r10, [r3, #64]
-; CHECK-NEXT:    adds r5, #38
-; CHECK-NEXT:    adds r3, #152
+; CHECK-NEXT:    vstrh.16 q0, [r10], #152
+; CHECK-NEXT:    strd r8, r9, [r6, #64]
+; CHECK-NEXT:    adds r3, #38
+; CHECK-NEXT:    adds r6, #152
 ; CHECK-NEXT:    le lr, .LBB19_3
 ; CHECK-NEXT:  @ %bb.4: @ %for.cond.cleanup6
 ; CHECK-NEXT:    movw r0, :lower16:arr_22
-; CHECK-NEXT:    ldr r2, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT:    ldr r2, [sp, #12] @ 4-byte Reload
 ; CHECK-NEXT:    movt r0, :upper16:arr_22
-; CHECK-NEXT:    ldr r3, [sp] @ 4-byte Reload
+; CHECK-NEXT:    ldr r3, [sp, #8] @ 4-byte Reload
 ; CHECK-NEXT:    add.w r0, r0, #1824
 ; CHECK-NEXT:    vmov.i32 q1, #0x0
+; CHECK-NEXT:    str r0, [sp, #4] @ 4-byte Spill
 ; CHECK-NEXT:    wlstp.8 lr, r2, .LBB19_6
 ; CHECK-NEXT:  .LBB19_5: @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vstrb.8 q1, [r0], #16
 ; CHECK-NEXT:    letp lr, .LBB19_5
 ; CHECK-NEXT:  .LBB19_6: @ %for.cond.cleanup6
-; CHECK-NEXT:    movw r6, :lower16:arr_20
-; CHECK-NEXT:    movw r0, #7376
-; CHECK-NEXT:    movt r6, :upper16:arr_20
-; CHECK-NEXT:    adds r3, r6, r0
+; CHECK-NEXT:    movw r2, :lower16:arr_20
 ; CHECK-NEXT:    movw r0, #7408
-; CHECK-NEXT:    add.w r12, r6, r0
+; CHECK-NEXT:    movt r2, :upper16:arr_20
+; CHECK-NEXT:    add.w r11, r2, r0
+; CHECK-NEXT:    movw r0, #7376
+; CHECK-NEXT:    adds r6, r2, r0
 ; CHECK-NEXT:    movw r0, #7344
-; CHECK-NEXT:    add.w r9, r6, r0
+; CHECK-NEXT:    adds r7, r2, r0
 ; CHECK-NEXT:    movw r0, #7312
-; CHECK-NEXT:    adds r2, r6, r0
-; CHECK-NEXT:    movw r0, :lower16:arr_21
-; CHECK-NEXT:    add.w r1, r6, #7424
-; CHECK-NEXT:    add.w r7, r6, #7392
-; CHECK-NEXT:    add.w r4, r6, #7360
-; CHECK-NEXT:    add.w r5, r6, #7328
-; CHECK-NEXT:    add.w r8, r6, #7296
-; CHECK-NEXT:    ldr r6, [sp, #8] @ 4-byte Reload
-; CHECK-NEXT:    movt r0, :upper16:arr_21
-; CHECK-NEXT:    addw r0, r0, #1860
-; CHECK-NEXT:    mov.w r10, #5
-; CHECK-NEXT:    dls lr, r6
-; CHECK-NEXT:    mov.w r6, #327685
+; CHECK-NEXT:    add.w r5, r2, #7424
+; CHECK-NEXT:    add r0, r2
+; CHECK-NEXT:    add.w r3, r2, #7392
+; CHECK-NEXT:    add.w r12, r2, #7360
+; CHECK-NEXT:    add.w r4, r2, #7328
+; CHECK-NEXT:    add.w r2, r2, #7296
+; CHECK-NEXT:    str r2, [sp] @ 4-byte Spill
+; CHECK-NEXT:    ldr r2, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT:    mov.w r9, #327685
+; CHECK-NEXT:    ldr r1, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT:    mov.w r8, #5
+; CHECK-NEXT:    dls lr, r2
 ; CHECK-NEXT:    vmov.i16 q1, #0x5
-; CHECK-NEXT:    mov.w r11, #0
+; CHECK-NEXT:    ldr r2, [sp] @ 4-byte Reload
+; CHECK-NEXT:    add.w r1, r1, #1824
+; CHECK-NEXT:    mov.w r10, #0
 ; CHECK-NEXT:  .LBB19_7: @ %for.cond8.preheader.1
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    str r6, [r0, #-4]
-; CHECK-NEXT:    vstrh.16 q1, [r0, #-36]
-; CHECK-NEXT:    strh.w r10, [r0]
-; CHECK-NEXT:    vstrh.16 q1, [r0, #-20]
-; CHECK-NEXT:    vstrw.32 q0, [r3]
+; CHECK-NEXT:    str r9, [r1, #-4]
+; CHECK-NEXT:    vstrh.16 q1, [r1, #-36]
+; CHECK-NEXT:    strh.w r8, [r1]
+; CHECK-NEXT:    vstrh.16 q1, [r1, #-20]
+; CHECK-NEXT:    vstrw.32 q0, [r6]
+; CHECK-NEXT:    vstrh.16 q0, [r0], #152
 ; CHECK-NEXT:    vstrh.16 q0, [r2], #152
-; CHECK-NEXT:    vstrh.16 q0, [r8], #152
-; CHECK-NEXT:    vstrh.16 q0, [r5], #152
-; CHECK-NEXT:    vstrh.16 q0, [r9], #152
 ; CHECK-NEXT:    vstrh.16 q0, [r4], #152
 ; CHECK-NEXT:    vstrh.16 q0, [r7], #152
 ; CHECK-NEXT:    vstrh.16 q0, [r12], #152
-; CHECK-NEXT:    vstrh.16 q0, [r1], #152
-; CHECK-NEXT:    strd r10, r11, [r3, #64]
-; CHECK-NEXT:    adds r0, #38
-; CHECK-NEXT:    adds r3, #152
+; CHECK-NEXT:    vstrh.16 q0, [r3], #152
+; CHECK-NEXT:    vstrh.16 q0, [r11], #152
+; CHECK-NEXT:    vstrh.16 q0, [r5], #152
+; CHECK-NEXT:    strd r8, r10, [r6, #64]
+; CHECK-NEXT:    adds r1, #38
+; CHECK-NEXT:    adds r6, #152
 ; CHECK-NEXT:    le lr, .LBB19_7
 ; CHECK-NEXT:  @ %bb.8: @ %for.cond.cleanup6.1
-; CHECK-NEXT:    movw r0, :lower16:arr_22
-; CHECK-NEXT:    ldr r2, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT:    movt r0, :upper16:arr_22
-; CHECK-NEXT:    ldr r3, [sp] @ 4-byte Reload
-; CHECK-NEXT:    add.w r0, r0, #3648
+; CHECK-NEXT:    ldr r0, [sp, #4] @ 4-byte Reload
 ; CHECK-NEXT:    vmov.i32 q1, #0x0
+; CHECK-NEXT:    ldr r2, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT:    ldr r3, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT:    add.w r0, r0, #1824
 ; CHECK-NEXT:    wlstp.8 lr, r2, .LBB19_10
 ; CHECK-NEXT:  .LBB19_9: @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vstrb.8 q1, [r0], #16
 ; CHECK-NEXT:    letp lr, .LBB19_9
 ; CHECK-NEXT:  .LBB19_10: @ %for.cond.cleanup6.1
-; CHECK-NEXT:    movw r7, :lower16:arr_20
-; CHECK-NEXT:    movw r0, #14672
-; CHECK-NEXT:    movt r7, :upper16:arr_20
-; CHECK-NEXT:    adds r3, r7, r0
+; CHECK-NEXT:    movw r2, :lower16:arr_20
 ; CHECK-NEXT:    movw r0, #14704
-; CHECK-NEXT:    add.w r12, r7, r0
+; CHECK-NEXT:    movt r2, :upper16:arr_20
+; CHECK-NEXT:    add.w r12, r2, r0
 ; CHECK-NEXT:    movw r0, #14688
-; CHECK-NEXT:    add.w r8, r7, r0
+; CHECK-NEXT:    add.w r9, r2, r0
+; CHECK-NEXT:    movw r0, #14672
+; CHECK-NEXT:    ldr r3, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT:    ldr r6, [sp] @ 4-byte Reload
+; CHECK-NEXT:    adds r7, r2, r0
+; CHECK-NEXT:    ldr r5, [sp, #20] @ 4-byte Reload
 ; CHECK-NEXT:    movw r0, #14640
-; CHECK-NEXT:    add.w r9, r7, r0
+; CHECK-NEXT:    movw r1, #14608
+; CHECK-NEXT:    add.w r8, r2, r0
 ; CHECK-NEXT:    movw r0, #14624
-; CHECK-NEXT:    adds r2, r7, r0
-; CHECK-NEXT:    movw r0, #14608
-; CHECK-NEXT:    movw r1, :lower16:arr_21
-; CHECK-NEXT:    add r0, r7
-; CHECK-NEXT:    add.w r4, r7, #14720
-; CHECK-NEXT:    add.w r5, r7, #14656
-; CHECK-NEXT:    add.w r6, r7, #14592
-; CHECK-NEXT:    ldr r7, [sp, #8] @ 4-byte Reload
-; CHECK-NEXT:    movt r1, :upper16:arr_21
-; CHECK-NEXT:    addw r1, r1, #3684
+; CHECK-NEXT:    dls lr, r5
+; CHECK-NEXT:    add r0, r2
+; CHECK-NEXT:    add r1, r2
+; CHECK-NEXT:    add.w r4, r2, #14720
+; CHECK-NEXT:    add.w r3, r3, #3648
+; CHECK-NEXT:    add.w r2, r2, #14656
+; CHECK-NEXT:    add.w r6, r6, #7296
+; CHECK-NEXT:    mov.w r5, #327685
 ; CHECK-NEXT:    mov.w r10, #5
-; CHECK-NEXT:    dls lr, r7
-; CHECK-NEXT:    mov.w r7, #327685
 ; CHECK-NEXT:    vmov.i16 q1, #0x5
 ; CHECK-NEXT:    mov.w r11, #0
 ; CHECK-NEXT:  .LBB19_11: @ %for.cond8.preheader.2
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    str r7, [r1, #-4]
-; CHECK-NEXT:    vstrh.16 q1, [r1, #-36]
-; CHECK-NEXT:    strh.w r10, [r1]
-; CHECK-NEXT:    vstrh.16 q1, [r1, #-20]
-; CHECK-NEXT:    vstrw.32 q0, [r3]
-; CHECK-NEXT:    vstrh.16 q0, [r0], #152
+; CHECK-NEXT:    str r5, [r3, #-4]
+; CHECK-NEXT:    vstrh.16 q1, [r3, #-36]
+; CHECK-NEXT:    strh.w r10, [r3]
+; CHECK-NEXT:    vstrh.16 q1, [r3, #-20]
+; CHECK-NEXT:    vstrw.32 q0, [r7]
+; CHECK-NEXT:    vstrh.16 q0, [r1], #152
 ; CHECK-NEXT:    vstrh.16 q0, [r6], #152
+; CHECK-NEXT:    vstrh.16 q0, [r0], #152
+; CHECK-NEXT:    vstrh.16 q0, [r8], #152
 ; CHECK-NEXT:    vstrh.16 q0, [r2], #152
 ; CHECK-NEXT:    vstrh.16 q0, [r9], #152
-; CHECK-NEXT:    vstrh.16 q0, [r5], #152
-; CHECK-NEXT:    vstrh.16 q0, [r8], #152
 ; CHECK-NEXT:    vstrh.16 q0, [r12], #152
 ; CHECK-NEXT:    vstrh.16 q0, [r4], #152
-; CHECK-NEXT:    strd r10, r11, [r3, #64]
-; CHECK-NEXT:    adds r1, #38
-; CHECK-NEXT:    adds r3, #152
+; CHECK-NEXT:    strd r10, r11, [r7, #64]
+; CHECK-NEXT:    adds r3, #38
+; CHECK-NEXT:    adds r7, #152
 ; CHECK-NEXT:    le lr, .LBB19_11
 ; CHECK-NEXT:  @ %bb.12: @ %for.cond.cleanup6.2
-; CHECK-NEXT:    movw r0, :lower16:arr_22
-; CHECK-NEXT:    ldrd r2, r1, [sp] @ 8-byte Folded Reload
-; CHECK-NEXT:    movt r0, :upper16:arr_22
+; CHECK-NEXT:    ldr r0, [sp, #4] @ 4-byte Reload
 ; CHECK-NEXT:    vmov.i32 q1, #0x0
-; CHECK-NEXT:    add.w r0, r0, #5472
+; CHECK-NEXT:    ldrd r2, r1, [sp, #8] @ 8-byte Folded Reload
+; CHECK-NEXT:    add.w r0, r0, #3648
 ; CHECK-NEXT:    wlstp.8 lr, r1, .LBB19_14
 ; CHECK-NEXT:  .LBB19_13: @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vstrb.8 q1, [r0], #16
 ; CHECK-NEXT:    letp lr, .LBB19_13
 ; CHECK-NEXT:  .LBB19_14: @ %for.cond.cleanup6.2
-; CHECK-NEXT:    movw r2, :lower16:arr_21
-; CHECK-NEXT:    movw r1, #5508
-; CHECK-NEXT:    movt r2, :upper16:arr_21
-; CHECK-NEXT:    movw r7, :lower16:arr_20
-; CHECK-NEXT:    add r2, r1
-; CHECK-NEXT:    movw r1, #22000
-; CHECK-NEXT:    movt r7, :upper16:arr_20
-; CHECK-NEXT:    add.w r12, r7, r1
-; CHECK-NEXT:    movw r1, #21984
-; CHECK-NEXT:    add.w r8, r7, r1
-; CHECK-NEXT:    movw r1, #21952
-; CHECK-NEXT:    add.w r9, r7, r1
-; CHECK-NEXT:    movw r1, #21936
+; CHECK-NEXT:    movw r2, :lower16:arr_20
+; CHECK-NEXT:    movw r0, #22000
+; CHECK-NEXT:    movt r2, :upper16:arr_20
+; CHECK-NEXT:    add.w r12, r2, r0
+; CHECK-NEXT:    movw r0, #21984
+; CHECK-NEXT:    add.w r8, r2, r0
 ; CHECK-NEXT:    movw r0, #21968
-; CHECK-NEXT:    adds r5, r7, r1
-; CHECK-NEXT:    movw r1, #21920
-; CHECK-NEXT:    movw r3, #21904
-; CHECK-NEXT:    adds r4, r7, r3
-; CHECK-NEXT:    add r0, r7
-; CHECK-NEXT:    add r1, r7
-; CHECK-NEXT:    add.w r3, r7, #22016
-; CHECK-NEXT:    add.w r6, r7, #21888
-; CHECK-NEXT:    ldr r7, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT:    adds r3, r2, r0
+; CHECK-NEXT:    movw r0, #21952
+; CHECK-NEXT:    add.w r9, r2, r0
+; CHECK-NEXT:    movw r0, #21936
+; CHECK-NEXT:    adds r6, r2, r0
+; CHECK-NEXT:    movw r0, #21920
+; CHECK-NEXT:    adds r1, r2, r0
+; CHECK-NEXT:    movw r0, #21904
+; CHECK-NEXT:    adds r5, r2, r0
+; CHECK-NEXT:    ldr r0, [sp, #16] @ 4-byte Reload
 ; CHECK-NEXT:    mov.w r10, #5
+; CHECK-NEXT:    ldr r7, [sp, #20] @ 4-byte Reload
 ; CHECK-NEXT:    vmov.i16 q1, #0x5
-; CHECK-NEXT:    mov.w r11, #0
+; CHECK-NEXT:    add.w r4, r0, #5472
+; CHECK-NEXT:    add.w r0, r2, #22016
 ; CHECK-NEXT:    dls lr, r7
+; CHECK-NEXT:    add.w r2, r2, #21888
 ; CHECK-NEXT:    mov.w r7, #327685
+; CHECK-NEXT:    mov.w r11, #0
 ; CHECK-NEXT:  .LBB19_15: @ %for.cond8.preheader.3
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    str r7, [r2, #-4]
-; CHECK-NEXT:    vstrh.16 q1, [r2, #-36]
-; CHECK-NEXT:    strh.w r10, [r2]
-; CHECK-NEXT:    vstrh.16 q1, [r2, #-20]
-; CHECK-NEXT:    vstrw.32 q0, [r0]
-; CHECK-NEXT:    vstrh.16 q0, [r4], #152
-; CHECK-NEXT:    vstrh.16 q0, [r6], #152
-; CHECK-NEXT:    vstrh.16 q0, [r1], #152
+; CHECK-NEXT:    str r7, [r4, #-4]
+; CHECK-NEXT:    vstrh.16 q1, [r4, #-36]
+; CHECK-NEXT:    strh.w r10, [r4]
+; CHECK-NEXT:    vstrh.16 q1, [r4, #-20]
+; CHECK-NEXT:    vstrw.32 q0, [r3]
 ; CHECK-NEXT:    vstrh.16 q0, [r5], #152
+; CHECK-NEXT:    vstrh.16 q0, [r2], #152
+; CHECK-NEXT:    vstrh.16 q0, [r1], #152
+; CHECK-NEXT:    vstrh.16 q0, [r6], #152
 ; CHECK-NEXT:    vstrh.16 q0, [r9], #152
 ; CHECK-NEXT:    vstrh.16 q0, [r8], #152
 ; CHECK-NEXT:    vstrh.16 q0, [r12], #152
-; CHECK-NEXT:    vstrh.16 q0, [r3], #152
-; CHECK-NEXT:    strd r10, r11, [r0, #64]
-; CHECK-NEXT:    adds r2, #38
-; CHECK-NEXT:    adds r0, #152
+; CHECK-NEXT:    vstrh.16 q0, [r0], #152
+; CHECK-NEXT:    strd r10, r11, [r3, #64]
+; CHECK-NEXT:    adds r4, #38
+; CHECK-NEXT:    adds r3, #152
 ; CHECK-NEXT:    le lr, .LBB19_15
 ; CHECK-NEXT:  @ %bb.16: @ %for.cond.cleanup6.3
-; CHECK-NEXT:    add sp, #12
+; CHECK-NEXT:    add sp, #24
 ; CHECK-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  @ %bb.17:
diff --git a/llvm/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll b/llvm/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll
--- a/llvm/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll
+++ b/llvm/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -frame-pointer=all | FileCheck %s
+; RUN: llc -consthoist-gep=false < %s -mtriple=i386-apple-darwin -relocation-model=pic -frame-pointer=all | FileCheck %s
 ; Don't fold re-materialized load into a two address instruction
 
 	%"struct.Smarts::Runnable" = type { ptr, i32 }
diff --git a/llvm/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll b/llvm/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll
--- a/llvm/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll
+++ b/llvm/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | FileCheck %s
+; RUN: llvm-as < %s | llc -consthoist-gep=false | FileCheck %s
 ; PR 5247
 ; check that cmp/test is not scheduled before the add
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
diff --git a/llvm/test/CodeGen/X86/AMX/amx-across-func.ll b/llvm/test/CodeGen/X86/AMX/amx-across-func.ll
--- a/llvm/test/CodeGen/X86/AMX/amx-across-func.ll
+++ b/llvm/test/CodeGen/X86/AMX/amx-across-func.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -verify-machineinstrs -enable-ipra | FileCheck -check-prefix=IPRA %s
-; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -verify-machineinstrs | FileCheck -check-prefix=O0 %s
+; RUN: llc -consthoist-gep=false < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -verify-machineinstrs | FileCheck %s
+; RUN: llc -consthoist-gep=false < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -verify-machineinstrs -enable-ipra | FileCheck -check-prefix=IPRA %s
+; RUN: llc -consthoist-gep=false < %s -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -verify-machineinstrs | FileCheck -check-prefix=O0 %s
 
 @buf = dso_local global [3072 x i8] zeroinitializer, align 64
 
diff --git a/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll b/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
--- a/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
+++ b/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -verify-machineinstrs -consthoist-gep=false | FileCheck %s
 @buf = dso_local global [3072 x i8] zeroinitializer, align 16
 
 define dso_local void @test1(i16 signext %0, i16 signext %1) nounwind {
diff --git a/llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll b/llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
--- a/llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
+++ b/llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -verify-machineinstrs | FileCheck %s
+; RUN: llc -consthoist-gep=false < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -verify-machineinstrs | FileCheck %s
 
 @buf = dso_local global [3072 x i8] zeroinitializer, align 64
 
diff --git a/llvm/test/CodeGen/X86/hoist-spill-lpad.ll b/llvm/test/CodeGen/X86/hoist-spill-lpad.ll
--- a/llvm/test/CodeGen/X86/hoist-spill-lpad.ll
+++ b/llvm/test/CodeGen/X86/hoist-spill-lpad.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s | FileCheck %s
+; RUN: llc -consthoist-gep=false < %s | FileCheck %s
 ;
 ; PR27612. The following spill is hoisted from two locations: the fall
 ; through succ block and the landingpad block of a call which may throw
diff --git a/llvm/test/CodeGen/XCore/codemodel.ll b/llvm/test/CodeGen/XCore/codemodel.ll
--- a/llvm/test/CodeGen/XCore/codemodel.ll
+++ b/llvm/test/CodeGen/XCore/codemodel.ll
@@ -1,13 +1,13 @@
 
-; RUN: not --crash llc < %s -march=xcore -code-model=medium 2>&1 | FileCheck %s -check-prefix=BAD_CM
-; RUN: not --crash llc < %s -march=xcore -code-model=kernel 2>&1 | FileCheck %s -check-prefix=BAD_CM
-; RUN: not --crash llc < %s -march=xcore -code-model=tiny 2>&1 | FileCheck %s -check-prefix=BAD_CM
+; RUN: not --crash llc -consthoist-gep=false < %s -march=xcore -code-model=medium 2>&1 | FileCheck %s -check-prefix=BAD_CM
+; RUN: not --crash llc -consthoist-gep=false < %s -march=xcore -code-model=kernel 2>&1 | FileCheck %s -check-prefix=BAD_CM
+; RUN: not --crash llc -consthoist-gep=false < %s -march=xcore -code-model=tiny 2>&1 | FileCheck %s -check-prefix=BAD_CM
 ; BAD_CM: Target only supports CodeModel Small or Large
 
 
-; RUN: llc < %s -march=xcore | FileCheck %s
-; RUN: llc < %s -march=xcore -code-model=small | FileCheck %s
-; RUN: llc < %s -march=xcore -code-model=large | FileCheck %s -check-prefix=LARGE
+; RUN: llc -consthoist-gep=false < %s -march=xcore | FileCheck %s
+; RUN: llc -consthoist-gep=false < %s -march=xcore -code-model=small | FileCheck %s
+; RUN: llc -consthoist-gep=false < %s -march=xcore -code-model=large | FileCheck %s -check-prefix=LARGE
 
 
 ; CHECK-LABEL: test: