diff --git a/llvm/include/llvm/CodeGen/RegisterScavenging.h b/llvm/include/llvm/CodeGen/RegisterScavenging.h
--- a/llvm/include/llvm/CodeGen/RegisterScavenging.h
+++ b/llvm/include/llvm/CodeGen/RegisterScavenging.h
@@ -160,23 +160,6 @@
         A.push_back(I.FrameIndex);
   }
 
-  /// Make a register of the specific register class
-  /// available and do the appropriate bookkeeping. SPAdj is the stack
-  /// adjustment due to call frame, it's passed along to eliminateFrameIndex().
-  /// Returns the scavenged register.
-  /// This is deprecated as it depends on the quality of the kill flags being
-  /// present; Use scavengeRegisterBackwards() instead!
-  ///
-  /// If \p AllowSpill is false, fail if a spill is required to make the
-  /// register available, and return NoRegister.
-  Register scavengeRegister(const TargetRegisterClass *RC,
-                            MachineBasicBlock::iterator I, int SPAdj,
-                            bool AllowSpill = true);
-  Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
-                            bool AllowSpill = true) {
-    return scavengeRegister(RegClass, MBBI, SPAdj, AllowSpill);
-  }
-
   /// Make a register of the specific register class available from the current
   /// position backwards to the place before \p To. If \p RestoreAfter is true
   /// this includes the instruction following the current position.
@@ -217,16 +200,6 @@
   /// Remove all Reg Units that \p Reg contains from \p BV.
   void removeRegUnits(BitVector &BV, MCRegister Reg);
 
-  /// Return the candidate register that is unused for the longest after
-  /// StartMI. UseMI is set to the instruction where the search stopped.
-  ///
-  /// No more than InstrLimit instructions are inspected.
-  Register findSurvivorReg(MachineBasicBlock::iterator StartMI,
-                           BitVector &Candidates,
-                           ArrayRef<MCPhysReg> AllocationOrder,
-                           unsigned InstrLimit,
-                           MachineBasicBlock::iterator &UseMI);
-
   /// Initialize RegisterScavenger.
   void init(MachineBasicBlock &MBB);
 
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -270,79 +270,6 @@
   return Mask;
 }
 
-Register RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
-                                       BitVector &Candidates,
-                                       ArrayRef<MCPhysReg> AllocationOrder,
-                                       unsigned InstrLimit,
-                                       MachineBasicBlock::iterator &UseMI) {
-  auto FindFirstCandidate = [&]() -> int {
-    for (MCPhysReg Reg : AllocationOrder) {
-      if (Candidates.test(Reg))
-        return Reg;
-    }
-    return -1;
-  };
-
-  int Survivor = FindFirstCandidate();
-  assert(Survivor > 0 && "No candidates for scavenging");
-
-  MachineBasicBlock::iterator ME = MBB->getFirstTerminator();
-  assert(StartMI != ME && "MI already at terminator");
-  MachineBasicBlock::iterator RestorePointMI = StartMI;
-  MachineBasicBlock::iterator MI = StartMI;
-
-  bool inVirtLiveRange = false;
-  for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
-    if (MI->isDebugOrPseudoInstr()) {
-      ++InstrLimit; // Don't count debug instructions
-      continue;
-    }
-    bool isVirtKillInsn = false;
-    bool isVirtDefInsn = false;
-    // Remove any candidates touched by instruction.
-    for (const MachineOperand &MO : MI->operands()) {
-      if (MO.isRegMask())
-        Candidates.clearBitsNotInMask(MO.getRegMask());
-      if (!MO.isReg() || MO.isUndef() || !MO.getReg())
-        continue;
-      if (MO.getReg().isVirtual()) {
-        if (MO.isDef())
-          isVirtDefInsn = true;
-        else if (MO.isKill())
-          isVirtKillInsn = true;
-        continue;
-      }
-      for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
-        Candidates.reset(*AI);
-    }
-    // If we're not in a virtual reg's live range, this is a valid
-    // restore point.
-    if (!inVirtLiveRange) RestorePointMI = MI;
-
-    // Update whether we're in the live range of a virtual register
-    if (isVirtKillInsn) inVirtLiveRange = false;
-    if (isVirtDefInsn) inVirtLiveRange = true;
-
-    // Was our survivor untouched by this instruction?
-    if (Candidates.test(Survivor))
-      continue;
-
-    // All candidates gone?
-    if (Candidates.none())
-      break;
-
-    Survivor = FindFirstCandidate();
-  }
-  // If we ran off the end, that's where we want to restore.
-  if (MI == ME) RestorePointMI = ME;
-  assert(RestorePointMI != StartMI &&
-         "No available scavenger restore location!");
-
-  // We ran out of candidates, so stop the search.
-  UseMI = RestorePointMI;
-  return Survivor;
-}
-
 /// Given the bitvector \p Available of free register units at position
 /// \p From. Search backwards to find a register that is part of \p
 /// Candidates and not used/clobbered until the point \p To. If there is
@@ -519,74 +446,6 @@
   return Scavenged[SI];
 }
 
-Register RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
-                                        MachineBasicBlock::iterator I,
-                                        int SPAdj, bool AllowSpill) {
-  MachineInstr &MI = *I;
-  const MachineFunction &MF = *MI.getMF();
-  // Consider all allocatable registers in the register class initially
-  BitVector Candidates = TRI->getAllocatableSet(MF, RC);
-
-  // Exclude all the registers being used by the instruction.
-  for (const MachineOperand &MO : MI.operands()) {
-    if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
-        !MO.getReg().isVirtual())
-      for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
-        Candidates.reset(*AI);
-  }
-
-  // If we have already scavenged some registers, remove them from the
-  // candidates. If we end up recursively calling eliminateFrameIndex, we don't
-  // want to be clobbering previously scavenged registers or their associated
-  // stack slots.
-  for (ScavengedInfo &SI : Scavenged) {
-    if (SI.Reg) {
-      if (isRegUsed(SI.Reg)) {
-        LLVM_DEBUG(
-          dbgs() << "Removing " << printReg(SI.Reg, TRI) <<
-          " from scavenging candidates since it was already scavenged\n");
-        for (MCRegAliasIterator AI(SI.Reg, TRI, true); AI.isValid(); ++AI)
-          Candidates.reset(*AI);
-      }
-    }
-  }
-
-  // Try to find a register that's unused if there is one, as then we won't
-  // have to spill.
-  BitVector Available = getRegsAvailable(RC);
-  Available &= Candidates;
-  if (Available.any())
-    Candidates = Available;
-
-  // Find the register whose use is furthest away.
-  MachineBasicBlock::iterator UseMI;
-  Register SReg =
-      findSurvivorReg(I, Candidates, RC->getRawAllocationOrder(MF), 25, UseMI);
-
-  // If we found an unused register there is no reason to spill it.
-  if (!isRegUsed(SReg)) {
-    LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n");
-    return SReg;
-  }
-
-  if (!AllowSpill)
-    return 0;
-
-#ifndef NDEBUG
-  for (ScavengedInfo &SI : Scavenged) {
-    assert(SI.Reg != SReg && "scavenged a previously scavenged register");
-  }
-#endif
-
-  ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
-  Scavenged.Restore = &*std::prev(UseMI);
-
-  LLVM_DEBUG(dbgs() << "Scavenged register (with spill): "
-                    << printReg(SReg, TRI) << "\n");
-
-  return SReg;
-}
-
 Register RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
                                                  MachineBasicBlock::iterator To,
                                                  bool RestoreAfter, int SPAdj,