diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -12650,6 +12650,18 @@ } break; } + case RISCVISD::VSLIDEUP_VL: { + // vslidedown and vslideup are semantically identical when the + // slide amount is 0, and vslidedown doesn't have the register + // overlap constraint that vslideup does. So canonicalize + // vslideups with a slide amount of 0 to vslidedown. + if (isa(N->getOperand(2)) && + N->getConstantOperandVal(2) == 0) { + return DAG.getNode(RISCVISD::VSLIDEDOWN_VL, SDLoc(N), N->getValueType(0), + N->ops()); + } + break; + } case ISD::INTRINSIC_WO_CHAIN: { unsigned IntNo = N->getConstantOperandVal(0); switch (IntNo) { diff --git a/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll --- a/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll @@ -473,7 +473,7 @@ ; CHECK-NEXT: vslidedown.vx v11, v10, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: vslideup.vi v9, v11, 0 +; CHECK-NEXT: vslidedown.vi v9, v11, 0 ; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma ; CHECK-NEXT: vslideup.vx v8, v10, a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll @@ -1433,7 +1433,7 @@ ; LMULMAX8-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX8-NEXT: vmv.v.i v17, 0 ; LMULMAX8-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; LMULMAX8-NEXT: vslideup.vi v17, v16, 0 +; LMULMAX8-NEXT: vslidedown.vi v17, v16, 0 ; LMULMAX8-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX8-NEXT: vmsne.vi v16, v17, 0 ; LMULMAX8-NEXT: addi a0, sp, 136 @@ -1471,7 +1471,7 @@ ; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX4-NEXT: vmv.v.i v13, 0 ; LMULMAX4-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; LMULMAX4-NEXT: vslideup.vi v13, v12, 0 +; LMULMAX4-NEXT: vslidedown.vi v13, v12, 0 ; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX4-NEXT: vmsne.vi v12, v13, 0 ; LMULMAX4-NEXT: addi a0, sp, 136 @@ -1515,7 +1515,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX2-NEXT: vmv.v.i v11, 0 ; LMULMAX2-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; LMULMAX2-NEXT: vslideup.vi v11, v10, 0 +; LMULMAX2-NEXT: vslidedown.vi v11, v10, 0 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX2-NEXT: vmsne.vi v10, v11, 0 ; LMULMAX2-NEXT: addi a0, sp, 136 @@ -1571,7 +1571,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX1-NEXT: vmv.v.i v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; LMULMAX1-NEXT: vslideup.vi v10, v9, 0 +; LMULMAX1-NEXT: vslidedown.vi v10, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX1-NEXT: vmsne.vi v9, v10, 0 ; LMULMAX1-NEXT: addi a0, sp, 136 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll @@ -536,7 +536,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a0) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll @@ -347,7 +347,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX2-NEXT: vmv.v.i v9, 0 ; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; LMULMAX2-NEXT: vslideup.vi v9, v8, 0 +; LMULMAX2-NEXT: vslidedown.vi v9, v8, 0 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX2-NEXT: vmsne.vi v8, v9, 0 ; LMULMAX2-NEXT: vsm.v v8, (a1) @@ -363,7 +363,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 +; LMULMAX1-NEXT: vslidedown.vi v9, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX1-NEXT: vmsne.vi v8, v9, 0 ; LMULMAX1-NEXT: vsm.v v8, (a1) @@ -391,7 +391,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX2-NEXT: vmv.v.i v9, 0 ; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; LMULMAX2-NEXT: vslideup.vi v9, v8, 0 +; LMULMAX2-NEXT: vslidedown.vi v9, v8, 0 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX2-NEXT: vmsne.vi v8, v9, 0 ; LMULMAX2-NEXT: vsm.v v8, (a1) @@ -412,7 +412,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 +; LMULMAX1-NEXT: vslidedown.vi v9, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX1-NEXT: vmsne.vi v8, v9, 0 ; LMULMAX1-NEXT: vsm.v v8, (a1) @@ -441,7 +441,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX2-NEXT: vmv.v.i v9, 0 ; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; LMULMAX2-NEXT: vslideup.vi v9, v8, 0 +; LMULMAX2-NEXT: vslidedown.vi v9, v8, 0 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX2-NEXT: vmsne.vi v8, v9, 0 ; LMULMAX2-NEXT: vsm.v v8, (a1) @@ -463,7 +463,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 +; LMULMAX1-NEXT: vslidedown.vi v9, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX1-NEXT: vmsne.vi v8, v9, 0 ; LMULMAX1-NEXT: vsm.v v8, (a1) @@ -483,7 +483,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a0) @@ -508,7 +508,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a0) @@ -527,7 +527,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a0) @@ -552,7 +552,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a0) @@ -578,7 +578,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a0) @@ -603,7 +603,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a0) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll @@ -43,7 +43,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 3, e32, m1, tu, ma ; LMULMAX1-NEXT: vslideup.vi v11, v10, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, ma -; LMULMAX1-NEXT: vslideup.vi v11, v12, 0 +; LMULMAX1-NEXT: vslidedown.vi v11, v12, 0 ; LMULMAX1-NEXT: vmv1r.v v8, v11 ; LMULMAX1-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll @@ -47,7 +47,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a2) @@ -72,7 +72,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a2) @@ -97,7 +97,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a2) @@ -122,7 +122,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a2) @@ -211,7 +211,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a2) @@ -236,7 +236,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a2) @@ -469,7 +469,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a2) @@ -496,7 +496,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a2) @@ -552,7 +552,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a1) @@ -577,7 +577,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a1) @@ -602,7 +602,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a1) @@ -627,7 +627,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a1) @@ -716,7 +716,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a1) @@ -741,7 +741,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a1) @@ -975,7 +975,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a1) @@ -1003,7 +1003,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a1) @@ -1060,7 +1060,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a1) @@ -1085,7 +1085,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a1) @@ -1110,7 +1110,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a1) @@ -1135,7 +1135,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a1) @@ -1224,7 +1224,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a1) @@ -1249,7 +1249,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a1) @@ -1483,7 +1483,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a1) @@ -1511,7 +1511,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a1) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll @@ -15,7 +15,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vle32.v v12, (a0) ; CHECK-NEXT: vsetivli zero, 2, e32, m4, tu, ma -; CHECK-NEXT: vslideup.vi v8, v12, 0 +; CHECK-NEXT: vslidedown.vi v8, v12, 0 ; CHECK-NEXT: ret %sv = load <2 x i32>, ptr %svp %v = call @llvm.vector.insert.v2i32.nxv8i32( %vec, <2 x i32> %sv, i64 0) @@ -54,19 +54,19 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-NEXT: vle32.v v12, (a0) ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m4, tu, ma -; LMULMAX2-NEXT: vslideup.vi v8, v12, 0 +; LMULMAX2-NEXT: vslidedown.vi v8, v12, 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_nxv8i32_v8i32_0: ; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; LMULMAX1-NEXT: vle32.v v12, (a1) +; LMULMAX1-NEXT: vle32.v v12, (a0) +; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vle32.v v16, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m4, tu, ma -; LMULMAX1-NEXT: vslideup.vi v8, v16, 0 +; LMULMAX1-NEXT: vslidedown.vi v8, v12, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e32, m4, tu, ma -; LMULMAX1-NEXT: vslideup.vi v8, v12, 4 +; LMULMAX1-NEXT: vslideup.vi v8, v16, 4 ; LMULMAX1-NEXT: ret %sv = load <8 x i32>, ptr %svp %v = call @llvm.vector.insert.v8i32.nxv8i32( %vec, <8 x i32> %sv, i64 0) @@ -117,7 +117,7 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: ret @@ -167,7 +167,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-NEXT: vle32.v v10, (a0) ; LMULMAX2-NEXT: vsetivli zero, 2, e32, m2, tu, ma -; LMULMAX2-NEXT: vslideup.vi v10, v8, 0 +; LMULMAX2-NEXT: vslidedown.vi v10, v8, 0 ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-NEXT: vse32.v v10, (a0) ; LMULMAX2-NEXT: ret @@ -179,7 +179,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, ma -; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 +; LMULMAX1-NEXT: vslidedown.vi v9, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vse32.v v9, (a0) ; LMULMAX1-NEXT: ret @@ -280,7 +280,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vle16.v v9, (a1) ; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v8, v9, 0 +; CHECK-NEXT: vslidedown.vi v8, v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret @@ -318,7 +318,7 @@ ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX2-NEXT: vlm.v v9, (a1) ; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf4, tu, ma -; LMULMAX2-NEXT: vslideup.vi v8, v9, 0 +; LMULMAX2-NEXT: vslidedown.vi v8, v9, 0 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, ma ; LMULMAX2-NEXT: vsm.v v8, (a0) ; LMULMAX2-NEXT: ret @@ -330,7 +330,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX1-NEXT: vlm.v v9, (a1) ; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, tu, ma -; LMULMAX1-NEXT: vslideup.vi v8, v9, 0 +; LMULMAX1-NEXT: vslidedown.vi v8, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vsm.v v8, (a0) ; LMULMAX1-NEXT: ret @@ -363,7 +363,7 @@ ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX1-NEXT: vlm.v v9, (a1) ; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, tu, ma -; LMULMAX1-NEXT: vslideup.vi v8, v9, 0 +; LMULMAX1-NEXT: vslidedown.vi v8, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vsm.v v8, (a0) ; LMULMAX1-NEXT: ret @@ -389,7 +389,7 @@ ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a0) @@ -433,7 +433,7 @@ ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v8, v9, 0 +; CHECK-NEXT: vslidedown.vi v8, v9, 0 ; CHECK-NEXT: ret %sv = load <2 x i16>, ptr %svp %c = call @llvm.vector.insert.v2i16.nxv2i16( %v, <2 x i16> %sv, i64 0) @@ -466,7 +466,7 @@ ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret @@ -481,7 +481,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vlm.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, tu, ma -; CHECK-NEXT: vslideup.vi v0, v8, 0 +; CHECK-NEXT: vslidedown.vi v0, v8, 0 ; CHECK-NEXT: ret %sv = load <8 x i1>, ptr %svp %c = call @llvm.vector.insert.v8i1.nxv8i1( %v, <8 x i1> %sv, i64 0) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll @@ -523,7 +523,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vrgather.vi v8, v9, 3 ; CHECK-NEXT: ret @@ -690,7 +690,7 @@ ; CHECK-LABEL: merge_end_into_end: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> @@ -711,7 +711,7 @@ ; CHECK-LABEL: merge_start_into_start: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v8, v9, 0 +; CHECK-NEXT: vslidedown.vi v8, v9, 0 ; CHECK-NEXT: ret %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> ret <8 x i8> %res diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll @@ -262,7 +262,7 @@ ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vslideup.vi v8, v24, 0 +; RV32-NEXT: vslidedown.vi v8, v24, 0 ; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: li a3, 41 ; RV32-NEXT: mul a1, a1, a3 @@ -335,7 +335,7 @@ ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vrgather.vv v24, v8, v16, v0.t ; RV32-NEXT: vsetivli zero, 12, e32, m4, tu, ma -; RV32-NEXT: vslideup.vi v4, v24, 0 +; RV32-NEXT: vslidedown.vi v4, v24, 0 ; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: li a3, 25 ; RV32-NEXT: mul a1, a1, a3 @@ -419,7 +419,7 @@ ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vslideup.vi v12, v8, 0 +; RV32-NEXT: vslidedown.vi v12, v8, 0 ; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: li a3, 37 ; RV32-NEXT: mul a1, a1, a3 @@ -501,7 +501,7 @@ ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vslideup.vi v12, v8, 0 +; RV32-NEXT: vslidedown.vi v12, v8, 0 ; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: slli a3, a1, 5 ; RV32-NEXT: add a1, a3, a1 @@ -572,7 +572,7 @@ ; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vrgather.vv v8, v16, v24, v0.t ; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma -; RV32-NEXT: vslideup.vi v4, v8, 0 +; RV32-NEXT: vslidedown.vi v4, v8, 0 ; RV32-NEXT: lui a1, %hi(.LCPI6_13) ; RV32-NEXT: addi a1, a1, %lo(.LCPI6_13) ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu @@ -638,7 +638,7 @@ ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vslideup.vi v12, v8, 0 +; RV32-NEXT: vslidedown.vi v12, v8, 0 ; RV32-NEXT: addi a1, a0, 320 ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vse32.v v12, (a1) @@ -768,7 +768,7 @@ ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vslideup.vi v8, v16, 0 +; RV64-NEXT: vslidedown.vi v8, v16, 0 ; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: li a2, 29 ; RV64-NEXT: mul a1, a1, a2 @@ -826,7 +826,7 @@ ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vrgather.vi v8, v16, 3, v0.t ; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma -; RV64-NEXT: vslideup.vi v8, v24, 0 +; RV64-NEXT: vslidedown.vi v8, v24, 0 ; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: li a2, 25 ; RV64-NEXT: mul a1, a1, a2 @@ -899,7 +899,7 @@ ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vslideup.vi v8, v24, 0 +; RV64-NEXT: vslidedown.vi v8, v24, 0 ; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: li a2, 45 ; RV64-NEXT: mul a1, a1, a2 @@ -991,7 +991,7 @@ ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vslideup.vi v8, v16, 0 +; RV64-NEXT: vslidedown.vi v8, v16, 0 ; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: li a2, 41 ; RV64-NEXT: mul a1, a1, a2 @@ -1085,7 +1085,7 @@ ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vslideup.vi v8, v16, 0 +; RV64-NEXT: vslidedown.vi v8, v16, 0 ; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: slli a2, a1, 5 ; RV64-NEXT: add a1, a2, a1 @@ -1156,7 +1156,7 @@ ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vrgather.vv v8, v24, v16, v0.t ; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma -; RV64-NEXT: vslideup.vi v4, v8, 0 +; RV64-NEXT: vslidedown.vi v4, v8, 0 ; RV64-NEXT: addi a1, a0, 320 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vse64.v v4, (a1) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll @@ -35,7 +35,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a0) @@ -59,7 +59,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a0) @@ -93,7 +93,7 @@ ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vsm.v v8, (a0) diff --git a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll --- a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll @@ -62,7 +62,7 @@ ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v8, v9, 0 +; CHECK-NEXT: vslidedown.vi v8, v9, 0 ; CHECK-NEXT: ret %v = call @llvm.vector.insert.nxv1i8.nxv4i8( %vec, %subvec, i64 0) ret %v @@ -215,7 +215,7 @@ ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: vslideup.vi v8, v16, 0 +; CHECK-NEXT: vslidedown.vi v8, v16, 0 ; CHECK-NEXT: ret %v = call @llvm.vector.insert.nxv1i32.nxv16i32( %vec, %subvec, i64 0) ret %v @@ -240,7 +240,7 @@ ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: vslideup.vi v11, v16, 0 +; CHECK-NEXT: vslidedown.vi v11, v16, 0 ; CHECK-NEXT: ret %v = call @llvm.vector.insert.nxv1i32.nxv16i32( %vec, %subvec, i64 6) ret %v @@ -252,7 +252,7 @@ ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma -; CHECK-NEXT: vslideup.vi v8, v10, 0 +; CHECK-NEXT: vslidedown.vi v8, v10, 0 ; CHECK-NEXT: ret %v = call @llvm.vector.insert.nxv1i8.nxv16i8( %vec, %subvec, i64 0) ret %v @@ -332,7 +332,7 @@ ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: vslideup.vi v8, v16, 0 +; CHECK-NEXT: vslidedown.vi v8, v16, 0 ; CHECK-NEXT: ret %v = call @llvm.vector.insert.nxv2f16.nxv32f16( %vec, %subvec, i64 0) ret %v @@ -392,7 +392,7 @@ ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v0, v8, 0 +; CHECK-NEXT: vslidedown.vi v0, v8, 0 ; CHECK-NEXT: ret %vec = call @llvm.vector.insert.nxv8i1.nxv32i1( %v, %sv, i64 0) ret %vec @@ -424,7 +424,7 @@ ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma -; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslidedown.vi v9, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll --- a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll +++ b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll @@ -631,7 +631,7 @@ ; CHECK-NEXT: vle16.v v12, (a0) ; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetivli zero, 16, e16, m4, tu, ma -; CHECK-NEXT: vslideup.vi v16, v8, 0 +; CHECK-NEXT: vslidedown.vi v16, v8, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vrgather.vv v8, v16, v12 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll --- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll @@ -11,7 +11,7 @@ ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vmclr.m v9 ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, tu, ma -; CHECK-NEXT: vslideup.vi v9, v0, 0 +; CHECK-NEXT: vslidedown.vi v9, v0, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vslideup.vi v9, v8, 2 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma @@ -60,34 +60,32 @@ define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) { ; RV32-LABEL: vector_interleave_v4i64_v2i64: ; RV32: # %bb.0: -; RV32-NEXT: vmv1r.v v10, v8 ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; RV32-NEXT: vmv.v.i v12, 0 +; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vsetivli zero, 2, e64, m2, tu, ma -; RV32-NEXT: vslideup.vi v12, v10, 0 +; RV32-NEXT: vslidedown.vi v10, v8, 0 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; RV32-NEXT: lui a0, %hi(.LCPI3_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI3_0) -; RV32-NEXT: vle16.v v10, (a0) +; RV32-NEXT: vle16.v v12, (a0) ; RV32-NEXT: vmv1r.v v8, v9 -; RV32-NEXT: vslideup.vi v12, v8, 2 -; RV32-NEXT: vrgatherei16.vv v8, v12, v10 +; RV32-NEXT: vslideup.vi v10, v8, 2 +; RV32-NEXT: vrgatherei16.vv v8, v10, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: vector_interleave_v4i64_v2i64: ; RV64: # %bb.0: -; RV64-NEXT: vmv1r.v v10, v8 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; RV64-NEXT: vmv.v.i v12, 0 +; RV64-NEXT: vmv.v.i v10, 0 ; RV64-NEXT: vsetivli zero, 2, e64, m2, tu, ma -; RV64-NEXT: vslideup.vi v12, v10, 0 +; RV64-NEXT: vslidedown.vi v10, v8, 0 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; RV64-NEXT: lui a0, %hi(.LCPI3_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI3_0) -; RV64-NEXT: vle64.v v10, (a0) +; RV64-NEXT: vle64.v v12, (a0) ; RV64-NEXT: vmv1r.v v8, v9 -; RV64-NEXT: vslideup.vi v12, v8, 2 -; RV64-NEXT: vrgather.vv v8, v12, v10 +; RV64-NEXT: vslideup.vi v10, v8, 2 +; RV64-NEXT: vrgather.vv v8, v10, v12 ; RV64-NEXT: ret %res = call <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b) ret <4 x i64> %res @@ -168,34 +166,32 @@ define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double> %b) { ; RV32-LABEL: vector_interleave_v4f64_v2f64: ; RV32: # %bb.0: -; RV32-NEXT: vmv1r.v v10, v8 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; RV32-NEXT: vmv.v.i v12, 0 +; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vsetivli zero, 2, e64, m2, tu, ma -; RV32-NEXT: vslideup.vi v12, v10, 0 +; RV32-NEXT: vslidedown.vi v10, v8, 0 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; RV32-NEXT: lui a0, %hi(.LCPI9_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI9_0) -; RV32-NEXT: vle16.v v10, (a0) +; RV32-NEXT: vle16.v v12, (a0) ; RV32-NEXT: vmv1r.v v8, v9 -; RV32-NEXT: vslideup.vi v12, v8, 2 -; RV32-NEXT: vrgatherei16.vv v8, v12, v10 +; RV32-NEXT: vslideup.vi v10, v8, 2 +; RV32-NEXT: vrgatherei16.vv v8, v10, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: vector_interleave_v4f64_v2f64: ; RV64: # %bb.0: -; RV64-NEXT: vmv1r.v v10, v8 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; RV64-NEXT: vmv.v.i v12, 0 +; RV64-NEXT: vmv.v.i v10, 0 ; RV64-NEXT: vsetivli zero, 2, e64, m2, tu, ma -; RV64-NEXT: vslideup.vi v12, v10, 0 +; RV64-NEXT: vslidedown.vi v10, v8, 0 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; RV64-NEXT: lui a0, %hi(.LCPI9_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI9_0) -; RV64-NEXT: vle64.v v10, (a0) +; RV64-NEXT: vle64.v v12, (a0) ; RV64-NEXT: vmv1r.v v8, v9 -; RV64-NEXT: vslideup.vi v12, v8, 2 -; RV64-NEXT: vrgather.vv v8, v12, v10 +; RV64-NEXT: vslideup.vi v10, v8, 2 +; RV64-NEXT: vrgather.vv v8, v10, v12 ; RV64-NEXT: ret %res = call <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b) ret <4 x double> %res diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll @@ -1033,7 +1033,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma ; CHECK-NEXT: vslideup.vx v10, v12, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: vslideup.vi v11, v12, 0 +; CHECK-NEXT: vslidedown.vi v11, v12, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma ; CHECK-NEXT: vslideup.vx v11, v12, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma @@ -1120,7 +1120,7 @@ ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma ; CHECK-NEXT: vslideup.vx v10, v12, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: vslideup.vi v11, v12, 0 +; CHECK-NEXT: vslidedown.vi v11, v12, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma ; CHECK-NEXT: vslideup.vx v11, v12, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma