diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -10322,6 +10322,10 @@ if (isInt<12>(Imm + 1)) return DAG.getSetCC(DL, VT, N01, DAG.getConstant(Imm + 1, DL, VT), CC); } + // Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond)) + if (!(CC == ISD::SETULT || CC == ISD::SETULE || CC == ISD::SETLT || + CC == ISD::SETOEQ)) + return DAG.getSetCC(DL, VT, N00, N01, ISD::getSetCCInverse(CC, VT)); } if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget)) diff --git a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll --- a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll @@ -661,8 +661,8 @@ define void @br_fcmp_ugt(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_ugt: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: fle.d a0, fa0, fa1 -; RV32IFD-NEXT: beqz a0, .LBB10_2 +; RV32IFD-NEXT: flt.d a0, fa1, fa0 +; RV32IFD-NEXT: bnez a0, .LBB10_2 ; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB10_2: # %if.then @@ -672,8 +672,8 @@ ; ; RV64IFD-LABEL: br_fcmp_ugt: ; RV64IFD: # %bb.0: -; RV64IFD-NEXT: fle.d a0, fa0, fa1 -; RV64IFD-NEXT: beqz a0, .LBB10_2 +; RV64IFD-NEXT: flt.d a0, fa1, fa0 +; RV64IFD-NEXT: bnez a0, .LBB10_2 ; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB10_2: # %if.then @@ -685,16 +685,16 @@ ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: sw a2, 0(sp) -; RV32IZFINXZDINX-NEXT: sw a3, 4(sp) -; RV32IZFINXZDINX-NEXT: lw a2, 0(sp) -; RV32IZFINXZDINX-NEXT: lw a3, 4(sp) ; RV32IZFINXZDINX-NEXT: sw a0, 0(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 4(sp) ; RV32IZFINXZDINX-NEXT: lw a0, 0(sp) ; RV32IZFINXZDINX-NEXT: lw a1, 4(sp) -; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a2 -; RV32IZFINXZDINX-NEXT: beqz a0, .LBB10_2 +; RV32IZFINXZDINX-NEXT: sw a2, 0(sp) +; RV32IZFINXZDINX-NEXT: sw a3, 4(sp) +; RV32IZFINXZDINX-NEXT: lw a2, 0(sp) +; RV32IZFINXZDINX-NEXT: lw a3, 4(sp) +; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0 +; RV32IZFINXZDINX-NEXT: bnez a0, .LBB10_2 ; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 @@ -704,8 +704,8 @@ ; ; RV64IZFINXZDINX-LABEL: br_fcmp_ugt: ; RV64IZFINXZDINX: # %bb.0: -; RV64IZFINXZDINX-NEXT: fle.d a0, a0, a1 -; RV64IZFINXZDINX-NEXT: beqz a0, .LBB10_2 +; RV64IZFINXZDINX-NEXT: flt.d a0, a1, a0 +; RV64IZFINXZDINX-NEXT: bnez a0, .LBB10_2 ; RV64IZFINXZDINX-NEXT: # %bb.1: # %if.else ; RV64IZFINXZDINX-NEXT: ret ; RV64IZFINXZDINX-NEXT: .LBB10_2: # %if.then @@ -724,8 +724,8 @@ define void @br_fcmp_uge(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_uge: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: flt.d a0, fa0, fa1 -; RV32IFD-NEXT: beqz a0, .LBB11_2 +; RV32IFD-NEXT: fle.d a0, fa1, fa0 +; RV32IFD-NEXT: bnez a0, .LBB11_2 ; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB11_2: # %if.then @@ -735,8 +735,8 @@ ; ; RV64IFD-LABEL: br_fcmp_uge: ; RV64IFD: # %bb.0: -; RV64IFD-NEXT: flt.d a0, fa0, fa1 -; RV64IFD-NEXT: beqz a0, .LBB11_2 +; RV64IFD-NEXT: fle.d a0, fa1, fa0 +; RV64IFD-NEXT: bnez a0, .LBB11_2 ; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB11_2: # %if.then @@ -748,16 +748,16 @@ ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: sw a2, 0(sp) -; RV32IZFINXZDINX-NEXT: sw a3, 4(sp) -; RV32IZFINXZDINX-NEXT: lw a2, 0(sp) -; RV32IZFINXZDINX-NEXT: lw a3, 4(sp) ; RV32IZFINXZDINX-NEXT: sw a0, 0(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 4(sp) ; RV32IZFINXZDINX-NEXT: lw a0, 0(sp) ; RV32IZFINXZDINX-NEXT: lw a1, 4(sp) -; RV32IZFINXZDINX-NEXT: flt.d a0, a0, a2 -; RV32IZFINXZDINX-NEXT: beqz a0, .LBB11_2 +; RV32IZFINXZDINX-NEXT: sw a2, 0(sp) +; RV32IZFINXZDINX-NEXT: sw a3, 4(sp) +; RV32IZFINXZDINX-NEXT: lw a2, 0(sp) +; RV32IZFINXZDINX-NEXT: lw a3, 4(sp) +; RV32IZFINXZDINX-NEXT: fle.d a0, a2, a0 +; RV32IZFINXZDINX-NEXT: bnez a0, .LBB11_2 ; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 @@ -767,8 +767,8 @@ ; ; RV64IZFINXZDINX-LABEL: br_fcmp_uge: ; RV64IZFINXZDINX: # %bb.0: -; RV64IZFINXZDINX-NEXT: flt.d a0, a0, a1 -; RV64IZFINXZDINX-NEXT: beqz a0, .LBB11_2 +; RV64IZFINXZDINX-NEXT: fle.d a0, a1, a0 +; RV64IZFINXZDINX-NEXT: bnez a0, .LBB11_2 ; RV64IZFINXZDINX-NEXT: # %bb.1: # %if.else ; RV64IZFINXZDINX-NEXT: ret ; RV64IZFINXZDINX-NEXT: .LBB11_2: # %if.then @@ -787,8 +787,8 @@ define void @br_fcmp_ult(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_ult: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: fle.d a0, fa1, fa0 -; RV32IFD-NEXT: beqz a0, .LBB12_2 +; RV32IFD-NEXT: flt.d a0, fa0, fa1 +; RV32IFD-NEXT: bnez a0, .LBB12_2 ; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB12_2: # %if.then @@ -798,8 +798,8 @@ ; ; RV64IFD-LABEL: br_fcmp_ult: ; RV64IFD: # %bb.0: -; RV64IFD-NEXT: fle.d a0, fa1, fa0 -; RV64IFD-NEXT: beqz a0, .LBB12_2 +; RV64IFD-NEXT: flt.d a0, fa0, fa1 +; RV64IFD-NEXT: bnez a0, .LBB12_2 ; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB12_2: # %if.then @@ -811,16 +811,16 @@ ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: sw a0, 0(sp) -; RV32IZFINXZDINX-NEXT: sw a1, 4(sp) -; RV32IZFINXZDINX-NEXT: lw a0, 0(sp) -; RV32IZFINXZDINX-NEXT: lw a1, 4(sp) ; RV32IZFINXZDINX-NEXT: sw a2, 0(sp) ; RV32IZFINXZDINX-NEXT: sw a3, 4(sp) ; RV32IZFINXZDINX-NEXT: lw a2, 0(sp) ; RV32IZFINXZDINX-NEXT: lw a3, 4(sp) -; RV32IZFINXZDINX-NEXT: fle.d a0, a2, a0 -; RV32IZFINXZDINX-NEXT: beqz a0, .LBB12_2 +; RV32IZFINXZDINX-NEXT: sw a0, 0(sp) +; RV32IZFINXZDINX-NEXT: sw a1, 4(sp) +; RV32IZFINXZDINX-NEXT: lw a0, 0(sp) +; RV32IZFINXZDINX-NEXT: lw a1, 4(sp) +; RV32IZFINXZDINX-NEXT: flt.d a0, a0, a2 +; RV32IZFINXZDINX-NEXT: bnez a0, .LBB12_2 ; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 @@ -830,8 +830,8 @@ ; ; RV64IZFINXZDINX-LABEL: br_fcmp_ult: ; RV64IZFINXZDINX: # %bb.0: -; RV64IZFINXZDINX-NEXT: fle.d a0, a1, a0 -; RV64IZFINXZDINX-NEXT: beqz a0, .LBB12_2 +; RV64IZFINXZDINX-NEXT: flt.d a0, a0, a1 +; RV64IZFINXZDINX-NEXT: bnez a0, .LBB12_2 ; RV64IZFINXZDINX-NEXT: # %bb.1: # %if.else ; RV64IZFINXZDINX-NEXT: ret ; RV64IZFINXZDINX-NEXT: .LBB12_2: # %if.then @@ -850,8 +850,8 @@ define void @br_fcmp_ule(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_ule: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: flt.d a0, fa1, fa0 -; RV32IFD-NEXT: beqz a0, .LBB13_2 +; RV32IFD-NEXT: fle.d a0, fa0, fa1 +; RV32IFD-NEXT: bnez a0, .LBB13_2 ; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB13_2: # %if.then @@ -861,8 +861,8 @@ ; ; RV64IFD-LABEL: br_fcmp_ule: ; RV64IFD: # %bb.0: -; RV64IFD-NEXT: flt.d a0, fa1, fa0 -; RV64IFD-NEXT: beqz a0, .LBB13_2 +; RV64IFD-NEXT: fle.d a0, fa0, fa1 +; RV64IFD-NEXT: bnez a0, .LBB13_2 ; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB13_2: # %if.then @@ -874,16 +874,16 @@ ; RV32IZFINXZDINX: # %bb.0: ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: sw a0, 0(sp) -; RV32IZFINXZDINX-NEXT: sw a1, 4(sp) -; RV32IZFINXZDINX-NEXT: lw a0, 0(sp) -; RV32IZFINXZDINX-NEXT: lw a1, 4(sp) ; RV32IZFINXZDINX-NEXT: sw a2, 0(sp) ; RV32IZFINXZDINX-NEXT: sw a3, 4(sp) ; RV32IZFINXZDINX-NEXT: lw a2, 0(sp) ; RV32IZFINXZDINX-NEXT: lw a3, 4(sp) -; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0 -; RV32IZFINXZDINX-NEXT: beqz a0, .LBB13_2 +; RV32IZFINXZDINX-NEXT: sw a0, 0(sp) +; RV32IZFINXZDINX-NEXT: sw a1, 4(sp) +; RV32IZFINXZDINX-NEXT: lw a0, 0(sp) +; RV32IZFINXZDINX-NEXT: lw a1, 4(sp) +; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a2 +; RV32IZFINXZDINX-NEXT: bnez a0, .LBB13_2 ; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 @@ -893,8 +893,8 @@ ; ; RV64IZFINXZDINX-LABEL: br_fcmp_ule: ; RV64IZFINXZDINX: # %bb.0: -; RV64IZFINXZDINX-NEXT: flt.d a0, a1, a0 -; RV64IZFINXZDINX-NEXT: beqz a0, .LBB13_2 +; RV64IZFINXZDINX-NEXT: fle.d a0, a0, a1 +; RV64IZFINXZDINX-NEXT: bnez a0, .LBB13_2 ; RV64IZFINXZDINX-NEXT: # %bb.1: # %if.else ; RV64IZFINXZDINX-NEXT: ret ; RV64IZFINXZDINX-NEXT: .LBB13_2: # %if.then diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll --- a/llvm/test/CodeGen/RISCV/double-convert.ll +++ b/llvm/test/CodeGen/RISCV/double-convert.ll @@ -756,11 +756,11 @@ ; RV32IFD-NEXT: lui a0, %hi(.LCPI12_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_0)(a0) ; RV32IFD-NEXT: fmv.d fs0, fa0 -; RV32IFD-NEXT: fle.d s0, fa5, fa0 +; RV32IFD-NEXT: flt.d s0, fa0, fa5 ; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: beqz s0, .LBB12_2 +; RV32IFD-NEXT: bnez s0, .LBB12_2 ; RV32IFD-NEXT: # %bb.1: # %start ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB12_2: # %start @@ -775,8 +775,8 @@ ; RV32IFD-NEXT: neg a4, a1 ; RV32IFD-NEXT: and a1, a4, a2 ; RV32IFD-NEXT: neg a2, a3 -; RV32IFD-NEXT: neg a3, s0 -; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: addi s0, s0, -1 +; RV32IFD-NEXT: and a0, s0, a0 ; RV32IFD-NEXT: or a0, a2, a0 ; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -808,10 +808,10 @@ ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_0) ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI12_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_0)(a2) -; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0 +; RV32IZFINXZDINX-NEXT: flt.d a2, s0, a2 ; RV32IZFINXZDINX-NEXT: lui a5, 524288 ; RV32IZFINXZDINX-NEXT: lui a3, 524288 -; RV32IZFINXZDINX-NEXT: beqz a2, .LBB12_2 +; RV32IZFINXZDINX-NEXT: bnez a2, .LBB12_2 ; RV32IZFINXZDINX-NEXT: # %bb.1: # %start ; RV32IZFINXZDINX-NEXT: mv a3, a1 ; RV32IZFINXZDINX-NEXT: .LBB12_2: # %start @@ -826,7 +826,7 @@ ; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0 ; RV32IZFINXZDINX-NEXT: neg a5, a1 ; RV32IZFINXZDINX-NEXT: and a1, a5, a3 -; RV32IZFINXZDINX-NEXT: neg a2, a2 +; RV32IZFINXZDINX-NEXT: addi a2, a2, -1 ; RV32IZFINXZDINX-NEXT: and a0, a2, a0 ; RV32IZFINXZDINX-NEXT: neg a2, a4 ; RV32IZFINXZDINX-NEXT: or a0, a2, a0 @@ -1016,8 +1016,8 @@ ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fcvt.d.w fa5, zero -; RV32IFD-NEXT: fle.d a0, fa5, fa0 -; RV32IFD-NEXT: neg s0, a0 +; RV32IFD-NEXT: flt.d a0, fa0, fa5 +; RV32IFD-NEXT: addi s0, a0, -1 ; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: lui a2, %hi(.LCPI14_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI14_0)(a2) @@ -1057,8 +1057,8 @@ ; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI14_0) ; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI14_0+4)(a4) ; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI14_0)(a4) -; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0 -; RV32IZFINXZDINX-NEXT: neg a2, a2 +; RV32IZFINXZDINX-NEXT: flt.d a2, s0, a2 +; RV32IZFINXZDINX-NEXT: addi a2, a2, -1 ; RV32IZFINXZDINX-NEXT: and a0, a2, a0 ; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0 ; RV32IZFINXZDINX-NEXT: neg a3, a3 diff --git a/llvm/test/CodeGen/RISCV/double-fcmp.ll b/llvm/test/CodeGen/RISCV/double-fcmp.ll --- a/llvm/test/CodeGen/RISCV/double-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/double-fcmp.ll @@ -531,30 +531,27 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind { ; CHECKIFD-LABEL: fcmp_ugt: ; CHECKIFD: # %bb.0: -; CHECKIFD-NEXT: fle.d a0, fa0, fa1 -; CHECKIFD-NEXT: xori a0, a0, 1 +; CHECKIFD-NEXT: flt.d a0, fa1, fa0 ; CHECKIFD-NEXT: ret ; ; CHECKRV32IZFINXZDINX-LABEL: fcmp_ugt: ; CHECKRV32IZFINXZDINX: # %bb.0: ; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16 -; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp) -; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp) -; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp) -; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp) ; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp) ; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp) -; CHECKRV32IZFINXZDINX-NEXT: fle.d a0, a0, a2 -; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1 +; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp) +; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp) +; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp) +; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp) +; CHECKRV32IZFINXZDINX-NEXT: flt.d a0, a2, a0 ; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; CHECKRV32IZFINXZDINX-NEXT: ret ; ; CHECKRV64IZFINXZDINX-LABEL: fcmp_ugt: ; CHECKRV64IZFINXZDINX: # %bb.0: -; CHECKRV64IZFINXZDINX-NEXT: fle.d a0, a0, a1 -; CHECKRV64IZFINXZDINX-NEXT: xori a0, a0, 1 +; CHECKRV64IZFINXZDINX-NEXT: flt.d a0, a1, a0 ; CHECKRV64IZFINXZDINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ugt: @@ -584,30 +581,27 @@ define i32 @fcmp_uge(double %a, double %b) nounwind { ; CHECKIFD-LABEL: fcmp_uge: ; CHECKIFD: # %bb.0: -; CHECKIFD-NEXT: flt.d a0, fa0, fa1 -; CHECKIFD-NEXT: xori a0, a0, 1 +; CHECKIFD-NEXT: fle.d a0, fa1, fa0 ; CHECKIFD-NEXT: ret ; ; CHECKRV32IZFINXZDINX-LABEL: fcmp_uge: ; CHECKRV32IZFINXZDINX: # %bb.0: ; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16 -; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp) -; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp) -; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp) -; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp) ; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp) ; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp) -; CHECKRV32IZFINXZDINX-NEXT: flt.d a0, a0, a2 -; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1 +; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp) +; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp) +; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp) +; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp) +; CHECKRV32IZFINXZDINX-NEXT: fle.d a0, a2, a0 ; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; CHECKRV32IZFINXZDINX-NEXT: ret ; ; CHECKRV64IZFINXZDINX-LABEL: fcmp_uge: ; CHECKRV64IZFINXZDINX: # %bb.0: -; CHECKRV64IZFINXZDINX-NEXT: flt.d a0, a0, a1 -; CHECKRV64IZFINXZDINX-NEXT: xori a0, a0, 1 +; CHECKRV64IZFINXZDINX-NEXT: fle.d a0, a1, a0 ; CHECKRV64IZFINXZDINX-NEXT: ret ; ; RV32I-LABEL: fcmp_uge: @@ -639,30 +633,27 @@ define i32 @fcmp_ult(double %a, double %b) nounwind { ; CHECKIFD-LABEL: fcmp_ult: ; CHECKIFD: # %bb.0: -; CHECKIFD-NEXT: fle.d a0, fa1, fa0 -; CHECKIFD-NEXT: xori a0, a0, 1 +; CHECKIFD-NEXT: flt.d a0, fa0, fa1 ; CHECKIFD-NEXT: ret ; ; CHECKRV32IZFINXZDINX-LABEL: fcmp_ult: ; CHECKRV32IZFINXZDINX: # %bb.0: ; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16 -; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp) -; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp) -; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp) -; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp) ; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp) ; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp) ; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp) ; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp) -; CHECKRV32IZFINXZDINX-NEXT: fle.d a0, a2, a0 -; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1 +; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp) +; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp) +; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp) +; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp) +; CHECKRV32IZFINXZDINX-NEXT: flt.d a0, a0, a2 ; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; CHECKRV32IZFINXZDINX-NEXT: ret ; ; CHECKRV64IZFINXZDINX-LABEL: fcmp_ult: ; CHECKRV64IZFINXZDINX: # %bb.0: -; CHECKRV64IZFINXZDINX-NEXT: fle.d a0, a1, a0 -; CHECKRV64IZFINXZDINX-NEXT: xori a0, a0, 1 +; CHECKRV64IZFINXZDINX-NEXT: flt.d a0, a0, a1 ; CHECKRV64IZFINXZDINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ult: @@ -692,30 +683,27 @@ define i32 @fcmp_ule(double %a, double %b) nounwind { ; CHECKIFD-LABEL: fcmp_ule: ; CHECKIFD: # %bb.0: -; CHECKIFD-NEXT: flt.d a0, fa1, fa0 -; CHECKIFD-NEXT: xori a0, a0, 1 +; CHECKIFD-NEXT: fle.d a0, fa0, fa1 ; CHECKIFD-NEXT: ret ; ; CHECKRV32IZFINXZDINX-LABEL: fcmp_ule: ; CHECKRV32IZFINXZDINX: # %bb.0: ; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16 -; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp) -; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp) -; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp) -; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp) ; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp) ; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp) ; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp) ; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp) -; CHECKRV32IZFINXZDINX-NEXT: flt.d a0, a2, a0 -; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1 +; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp) +; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp) +; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp) +; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp) +; CHECKRV32IZFINXZDINX-NEXT: fle.d a0, a0, a2 ; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; CHECKRV32IZFINXZDINX-NEXT: ret ; ; CHECKRV64IZFINXZDINX-LABEL: fcmp_ule: ; CHECKRV64IZFINXZDINX: # %bb.0: -; CHECKRV64IZFINXZDINX-NEXT: flt.d a0, a1, a0 -; CHECKRV64IZFINXZDINX-NEXT: xori a0, a0, 1 +; CHECKRV64IZFINXZDINX-NEXT: fle.d a0, a0, a1 ; CHECKRV64IZFINXZDINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ule: diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll --- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll +++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll @@ -33,13 +33,14 @@ ; RV32IFD-NEXT: fld fa4, %lo(.LCPI1_0)(a0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1) ; RV32IFD-NEXT: fld fa3, %lo(.LCPI1_1)(a0) -; RV32IFD-NEXT: flt.d a0, fa5, fa4 -; RV32IFD-NEXT: flt.d a1, fa3, fa5 -; RV32IFD-NEXT: or a0, a0, a1 -; RV32IFD-NEXT: beqz a0, .LBB1_2 +; RV32IFD-NEXT: fle.d a0, fa4, fa5 +; RV32IFD-NEXT: fle.d a1, fa5, fa3 +; RV32IFD-NEXT: and a0, a0, a1 +; RV32IFD-NEXT: bnez a0, .LBB1_2 ; RV32IFD-NEXT: # %bb.1: # %if.then ; RV32IFD-NEXT: call abort@plt ; RV32IFD-NEXT: .LBB1_2: # %if.end +; RV32IFD-NEXT: li a0, 0 ; RV32IFD-NEXT: call exit@plt ; ; RV32IZFINXZDINX-LABEL: main: @@ -59,13 +60,14 @@ ; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI1_1) ; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI1_1+4)(a4) ; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_1)(a4) -; RV32IZFINXZDINX-NEXT: flt.d a2, a0, a2 -; RV32IZFINXZDINX-NEXT: flt.d a0, a4, a0 -; RV32IZFINXZDINX-NEXT: or a0, a2, a0 -; RV32IZFINXZDINX-NEXT: beqz a0, .LBB1_2 +; RV32IZFINXZDINX-NEXT: fle.d a2, a2, a0 +; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a4 +; RV32IZFINXZDINX-NEXT: and a0, a2, a0 +; RV32IZFINXZDINX-NEXT: bnez a0, .LBB1_2 ; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.then ; RV32IZFINXZDINX-NEXT: call abort@plt ; RV32IZFINXZDINX-NEXT: .LBB1_2: # %if.end +; RV32IZFINXZDINX-NEXT: li a0, 0 ; RV32IZFINXZDINX-NEXT: call exit@plt entry: %call = call double @test(double 2.000000e+00) diff --git a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll --- a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll @@ -58,11 +58,11 @@ ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI1_0)(a0) ; RV32IFD-NEXT: fmv.d fs0, fa0 -; RV32IFD-NEXT: fle.d s0, fa5, fa0 +; RV32IFD-NEXT: flt.d s0, fa0, fa5 ; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: beqz s0, .LBB1_2 +; RV32IFD-NEXT: bnez s0, .LBB1_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB1_2: @@ -77,8 +77,8 @@ ; RV32IFD-NEXT: neg a4, a1 ; RV32IFD-NEXT: and a1, a4, a2 ; RV32IFD-NEXT: neg a2, a3 -; RV32IFD-NEXT: neg a3, s0 -; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: addi s0, s0, -1 +; RV32IFD-NEXT: and a0, s0, a0 ; RV32IFD-NEXT: or a0, a2, a0 ; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -111,11 +111,11 @@ ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_0) ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI1_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a2) -; RV32IZFINXZDINX-NEXT: fle.d s0, a2, s2 +; RV32IZFINXZDINX-NEXT: flt.d s0, s2, a2 ; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 -; RV32IZFINXZDINX-NEXT: beqz s0, .LBB1_2 +; RV32IZFINXZDINX-NEXT: bnez s0, .LBB1_2 ; RV32IZFINXZDINX-NEXT: # %bb.1: ; RV32IZFINXZDINX-NEXT: mv a2, a1 ; RV32IZFINXZDINX-NEXT: .LBB1_2: @@ -130,8 +130,8 @@ ; RV32IZFINXZDINX-NEXT: feq.d a1, s2, s2 ; RV32IZFINXZDINX-NEXT: neg a4, a1 ; RV32IZFINXZDINX-NEXT: and a1, a4, a2 -; RV32IZFINXZDINX-NEXT: neg a2, s0 -; RV32IZFINXZDINX-NEXT: and a0, a2, a0 +; RV32IZFINXZDINX-NEXT: addi s0, s0, -1 +; RV32IZFINXZDINX-NEXT: and a0, s0, a0 ; RV32IZFINXZDINX-NEXT: neg a2, a3 ; RV32IZFINXZDINX-NEXT: or a0, a2, a0 ; RV32IZFINXZDINX-NEXT: and a0, a4, a0 @@ -207,8 +207,8 @@ ; RV32IFD-NEXT: flt.d a0, fa5, fa0 ; RV32IFD-NEXT: neg s0, a0 ; RV32IFD-NEXT: fcvt.d.w fa5, zero -; RV32IFD-NEXT: fle.d a0, fa5, fa0 -; RV32IFD-NEXT: neg s1, a0 +; RV32IFD-NEXT: flt.d a0, fa0, fa5 +; RV32IFD-NEXT: addi s1, a0, -1 ; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: and a0, s1, a0 ; RV32IFD-NEXT: or a0, s0, a0 @@ -235,29 +235,27 @@ ; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: call floor@plt ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) ; RV32IZFINXZDINX-NEXT: lw s1, 12(sp) -; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero -; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0 -; RV32IZFINXZDINX-NEXT: neg s2, a2 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI3_0) -; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI3_0+4)(a2) -; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI3_0)(a2) -; RV32IZFINXZDINX-NEXT: and a0, s2, a0 -; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0 -; RV32IZFINXZDINX-NEXT: neg a2, a2 -; RV32IZFINXZDINX-NEXT: or a0, a2, a0 -; RV32IZFINXZDINX-NEXT: and a1, s2, a1 -; RV32IZFINXZDINX-NEXT: or a1, a2, a1 +; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero +; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI3_0) +; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI3_0+4)(a4) +; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI3_0)(a4) +; RV32IZFINXZDINX-NEXT: flt.d a2, s0, a2 +; RV32IZFINXZDINX-NEXT: addi a2, a2, -1 +; RV32IZFINXZDINX-NEXT: and a0, a2, a0 +; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0 +; RV32IZFINXZDINX-NEXT: neg a3, a3 +; RV32IZFINXZDINX-NEXT: or a0, a3, a0 +; RV32IZFINXZDINX-NEXT: and a1, a2, a1 +; RV32IZFINXZDINX-NEXT: or a1, a3, a1 ; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 32 ; RV32IZFINXZDINX-NEXT: ret ; @@ -324,11 +322,11 @@ ; RV32IFD-NEXT: lui a0, %hi(.LCPI5_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI5_0)(a0) ; RV32IFD-NEXT: fmv.d fs0, fa0 -; RV32IFD-NEXT: fle.d s0, fa5, fa0 +; RV32IFD-NEXT: flt.d s0, fa0, fa5 ; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: beqz s0, .LBB5_2 +; RV32IFD-NEXT: bnez s0, .LBB5_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB5_2: @@ -343,8 +341,8 @@ ; RV32IFD-NEXT: neg a4, a1 ; RV32IFD-NEXT: and a1, a4, a2 ; RV32IFD-NEXT: neg a2, a3 -; RV32IFD-NEXT: neg a3, s0 -; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: addi s0, s0, -1 +; RV32IFD-NEXT: and a0, s0, a0 ; RV32IFD-NEXT: or a0, a2, a0 ; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -377,11 +375,11 @@ ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI5_0) ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI5_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI5_0)(a2) -; RV32IZFINXZDINX-NEXT: fle.d s0, a2, s2 +; RV32IZFINXZDINX-NEXT: flt.d s0, s2, a2 ; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 -; RV32IZFINXZDINX-NEXT: beqz s0, .LBB5_2 +; RV32IZFINXZDINX-NEXT: bnez s0, .LBB5_2 ; RV32IZFINXZDINX-NEXT: # %bb.1: ; RV32IZFINXZDINX-NEXT: mv a2, a1 ; RV32IZFINXZDINX-NEXT: .LBB5_2: @@ -396,8 +394,8 @@ ; RV32IZFINXZDINX-NEXT: feq.d a1, s2, s2 ; RV32IZFINXZDINX-NEXT: neg a4, a1 ; RV32IZFINXZDINX-NEXT: and a1, a4, a2 -; RV32IZFINXZDINX-NEXT: neg a2, s0 -; RV32IZFINXZDINX-NEXT: and a0, a2, a0 +; RV32IZFINXZDINX-NEXT: addi s0, s0, -1 +; RV32IZFINXZDINX-NEXT: and a0, s0, a0 ; RV32IZFINXZDINX-NEXT: neg a2, a3 ; RV32IZFINXZDINX-NEXT: or a0, a2, a0 ; RV32IZFINXZDINX-NEXT: and a0, a4, a0 @@ -473,8 +471,8 @@ ; RV32IFD-NEXT: flt.d a0, fa5, fa0 ; RV32IFD-NEXT: neg s0, a0 ; RV32IFD-NEXT: fcvt.d.w fa5, zero -; RV32IFD-NEXT: fle.d a0, fa5, fa0 -; RV32IFD-NEXT: neg s1, a0 +; RV32IFD-NEXT: flt.d a0, fa0, fa5 +; RV32IFD-NEXT: addi s1, a0, -1 ; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: and a0, s1, a0 ; RV32IFD-NEXT: or a0, s0, a0 @@ -501,29 +499,27 @@ ; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: call ceil@plt ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) ; RV32IZFINXZDINX-NEXT: lw s1, 12(sp) -; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero -; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0 -; RV32IZFINXZDINX-NEXT: neg s2, a2 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI7_0) -; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI7_0+4)(a2) -; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI7_0)(a2) -; RV32IZFINXZDINX-NEXT: and a0, s2, a0 -; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0 -; RV32IZFINXZDINX-NEXT: neg a2, a2 -; RV32IZFINXZDINX-NEXT: or a0, a2, a0 -; RV32IZFINXZDINX-NEXT: and a1, s2, a1 -; RV32IZFINXZDINX-NEXT: or a1, a2, a1 +; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero +; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI7_0) +; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI7_0+4)(a4) +; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI7_0)(a4) +; RV32IZFINXZDINX-NEXT: flt.d a2, s0, a2 +; RV32IZFINXZDINX-NEXT: addi a2, a2, -1 +; RV32IZFINXZDINX-NEXT: and a0, a2, a0 +; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0 +; RV32IZFINXZDINX-NEXT: neg a3, a3 +; RV32IZFINXZDINX-NEXT: or a0, a3, a0 +; RV32IZFINXZDINX-NEXT: and a1, a2, a1 +; RV32IZFINXZDINX-NEXT: or a1, a3, a1 ; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 32 ; RV32IZFINXZDINX-NEXT: ret ; @@ -590,11 +586,11 @@ ; RV32IFD-NEXT: lui a0, %hi(.LCPI9_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI9_0)(a0) ; RV32IFD-NEXT: fmv.d fs0, fa0 -; RV32IFD-NEXT: fle.d s0, fa5, fa0 +; RV32IFD-NEXT: flt.d s0, fa0, fa5 ; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: beqz s0, .LBB9_2 +; RV32IFD-NEXT: bnez s0, .LBB9_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB9_2: @@ -609,8 +605,8 @@ ; RV32IFD-NEXT: neg a4, a1 ; RV32IFD-NEXT: and a1, a4, a2 ; RV32IFD-NEXT: neg a2, a3 -; RV32IFD-NEXT: neg a3, s0 -; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: addi s0, s0, -1 +; RV32IFD-NEXT: and a0, s0, a0 ; RV32IFD-NEXT: or a0, a2, a0 ; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -643,11 +639,11 @@ ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI9_0) ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI9_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI9_0)(a2) -; RV32IZFINXZDINX-NEXT: fle.d s0, a2, s2 +; RV32IZFINXZDINX-NEXT: flt.d s0, s2, a2 ; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 -; RV32IZFINXZDINX-NEXT: beqz s0, .LBB9_2 +; RV32IZFINXZDINX-NEXT: bnez s0, .LBB9_2 ; RV32IZFINXZDINX-NEXT: # %bb.1: ; RV32IZFINXZDINX-NEXT: mv a2, a1 ; RV32IZFINXZDINX-NEXT: .LBB9_2: @@ -662,8 +658,8 @@ ; RV32IZFINXZDINX-NEXT: feq.d a1, s2, s2 ; RV32IZFINXZDINX-NEXT: neg a4, a1 ; RV32IZFINXZDINX-NEXT: and a1, a4, a2 -; RV32IZFINXZDINX-NEXT: neg a2, s0 -; RV32IZFINXZDINX-NEXT: and a0, a2, a0 +; RV32IZFINXZDINX-NEXT: addi s0, s0, -1 +; RV32IZFINXZDINX-NEXT: and a0, s0, a0 ; RV32IZFINXZDINX-NEXT: neg a2, a3 ; RV32IZFINXZDINX-NEXT: or a0, a2, a0 ; RV32IZFINXZDINX-NEXT: and a0, a4, a0 @@ -739,8 +735,8 @@ ; RV32IFD-NEXT: flt.d a0, fa5, fa0 ; RV32IFD-NEXT: neg s0, a0 ; RV32IFD-NEXT: fcvt.d.w fa5, zero -; RV32IFD-NEXT: fle.d a0, fa5, fa0 -; RV32IFD-NEXT: neg s1, a0 +; RV32IFD-NEXT: flt.d a0, fa0, fa5 +; RV32IFD-NEXT: addi s1, a0, -1 ; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: and a0, s1, a0 ; RV32IFD-NEXT: or a0, s0, a0 @@ -767,29 +763,27 @@ ; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: call trunc@plt ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) ; RV32IZFINXZDINX-NEXT: lw s1, 12(sp) -; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero -; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0 -; RV32IZFINXZDINX-NEXT: neg s2, a2 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI11_0) -; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI11_0+4)(a2) -; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI11_0)(a2) -; RV32IZFINXZDINX-NEXT: and a0, s2, a0 -; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0 -; RV32IZFINXZDINX-NEXT: neg a2, a2 -; RV32IZFINXZDINX-NEXT: or a0, a2, a0 -; RV32IZFINXZDINX-NEXT: and a1, s2, a1 -; RV32IZFINXZDINX-NEXT: or a1, a2, a1 +; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero +; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI11_0) +; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI11_0+4)(a4) +; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI11_0)(a4) +; RV32IZFINXZDINX-NEXT: flt.d a2, s0, a2 +; RV32IZFINXZDINX-NEXT: addi a2, a2, -1 +; RV32IZFINXZDINX-NEXT: and a0, a2, a0 +; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0 +; RV32IZFINXZDINX-NEXT: neg a3, a3 +; RV32IZFINXZDINX-NEXT: or a0, a3, a0 +; RV32IZFINXZDINX-NEXT: and a1, a2, a1 +; RV32IZFINXZDINX-NEXT: or a1, a3, a1 ; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 32 ; RV32IZFINXZDINX-NEXT: ret ; @@ -856,11 +850,11 @@ ; RV32IFD-NEXT: lui a0, %hi(.LCPI13_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI13_0)(a0) ; RV32IFD-NEXT: fmv.d fs0, fa0 -; RV32IFD-NEXT: fle.d s0, fa5, fa0 +; RV32IFD-NEXT: flt.d s0, fa0, fa5 ; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: beqz s0, .LBB13_2 +; RV32IFD-NEXT: bnez s0, .LBB13_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB13_2: @@ -875,8 +869,8 @@ ; RV32IFD-NEXT: neg a4, a1 ; RV32IFD-NEXT: and a1, a4, a2 ; RV32IFD-NEXT: neg a2, a3 -; RV32IFD-NEXT: neg a3, s0 -; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: addi s0, s0, -1 +; RV32IFD-NEXT: and a0, s0, a0 ; RV32IFD-NEXT: or a0, a2, a0 ; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -909,11 +903,11 @@ ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI13_0) ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI13_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI13_0)(a2) -; RV32IZFINXZDINX-NEXT: fle.d s0, a2, s2 +; RV32IZFINXZDINX-NEXT: flt.d s0, s2, a2 ; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 -; RV32IZFINXZDINX-NEXT: beqz s0, .LBB13_2 +; RV32IZFINXZDINX-NEXT: bnez s0, .LBB13_2 ; RV32IZFINXZDINX-NEXT: # %bb.1: ; RV32IZFINXZDINX-NEXT: mv a2, a1 ; RV32IZFINXZDINX-NEXT: .LBB13_2: @@ -928,8 +922,8 @@ ; RV32IZFINXZDINX-NEXT: feq.d a1, s2, s2 ; RV32IZFINXZDINX-NEXT: neg a4, a1 ; RV32IZFINXZDINX-NEXT: and a1, a4, a2 -; RV32IZFINXZDINX-NEXT: neg a2, s0 -; RV32IZFINXZDINX-NEXT: and a0, a2, a0 +; RV32IZFINXZDINX-NEXT: addi s0, s0, -1 +; RV32IZFINXZDINX-NEXT: and a0, s0, a0 ; RV32IZFINXZDINX-NEXT: neg a2, a3 ; RV32IZFINXZDINX-NEXT: or a0, a2, a0 ; RV32IZFINXZDINX-NEXT: and a0, a4, a0 @@ -1005,8 +999,8 @@ ; RV32IFD-NEXT: flt.d a0, fa5, fa0 ; RV32IFD-NEXT: neg s0, a0 ; RV32IFD-NEXT: fcvt.d.w fa5, zero -; RV32IFD-NEXT: fle.d a0, fa5, fa0 -; RV32IFD-NEXT: neg s1, a0 +; RV32IFD-NEXT: flt.d a0, fa0, fa5 +; RV32IFD-NEXT: addi s1, a0, -1 ; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: and a0, s1, a0 ; RV32IFD-NEXT: or a0, s0, a0 @@ -1033,29 +1027,27 @@ ; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: call round@plt ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) ; RV32IZFINXZDINX-NEXT: lw s1, 12(sp) -; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero -; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0 -; RV32IZFINXZDINX-NEXT: neg s2, a2 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI15_0) -; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI15_0+4)(a2) -; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI15_0)(a2) -; RV32IZFINXZDINX-NEXT: and a0, s2, a0 -; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0 -; RV32IZFINXZDINX-NEXT: neg a2, a2 -; RV32IZFINXZDINX-NEXT: or a0, a2, a0 -; RV32IZFINXZDINX-NEXT: and a1, s2, a1 -; RV32IZFINXZDINX-NEXT: or a1, a2, a1 +; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero +; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI15_0) +; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI15_0+4)(a4) +; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI15_0)(a4) +; RV32IZFINXZDINX-NEXT: flt.d a2, s0, a2 +; RV32IZFINXZDINX-NEXT: addi a2, a2, -1 +; RV32IZFINXZDINX-NEXT: and a0, a2, a0 +; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0 +; RV32IZFINXZDINX-NEXT: neg a3, a3 +; RV32IZFINXZDINX-NEXT: or a0, a3, a0 +; RV32IZFINXZDINX-NEXT: and a1, a2, a1 +; RV32IZFINXZDINX-NEXT: or a1, a3, a1 ; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 32 ; RV32IZFINXZDINX-NEXT: ret ; @@ -1122,11 +1114,11 @@ ; RV32IFD-NEXT: lui a0, %hi(.LCPI17_0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI17_0)(a0) ; RV32IFD-NEXT: fmv.d fs0, fa0 -; RV32IFD-NEXT: fle.d s0, fa5, fa0 +; RV32IFD-NEXT: flt.d s0, fa0, fa5 ; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: beqz s0, .LBB17_2 +; RV32IFD-NEXT: bnez s0, .LBB17_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB17_2: @@ -1141,8 +1133,8 @@ ; RV32IFD-NEXT: neg a4, a1 ; RV32IFD-NEXT: and a1, a4, a2 ; RV32IFD-NEXT: neg a2, a3 -; RV32IFD-NEXT: neg a3, s0 -; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: addi s0, s0, -1 +; RV32IFD-NEXT: and a0, s0, a0 ; RV32IFD-NEXT: or a0, a2, a0 ; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1175,11 +1167,11 @@ ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI17_0) ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI17_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI17_0)(a2) -; RV32IZFINXZDINX-NEXT: fle.d s0, a2, s2 +; RV32IZFINXZDINX-NEXT: flt.d s0, s2, a2 ; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 -; RV32IZFINXZDINX-NEXT: beqz s0, .LBB17_2 +; RV32IZFINXZDINX-NEXT: bnez s0, .LBB17_2 ; RV32IZFINXZDINX-NEXT: # %bb.1: ; RV32IZFINXZDINX-NEXT: mv a2, a1 ; RV32IZFINXZDINX-NEXT: .LBB17_2: @@ -1194,8 +1186,8 @@ ; RV32IZFINXZDINX-NEXT: feq.d a1, s2, s2 ; RV32IZFINXZDINX-NEXT: neg a4, a1 ; RV32IZFINXZDINX-NEXT: and a1, a4, a2 -; RV32IZFINXZDINX-NEXT: neg a2, s0 -; RV32IZFINXZDINX-NEXT: and a0, a2, a0 +; RV32IZFINXZDINX-NEXT: addi s0, s0, -1 +; RV32IZFINXZDINX-NEXT: and a0, s0, a0 ; RV32IZFINXZDINX-NEXT: neg a2, a3 ; RV32IZFINXZDINX-NEXT: or a0, a2, a0 ; RV32IZFINXZDINX-NEXT: and a0, a4, a0 @@ -1271,8 +1263,8 @@ ; RV32IFD-NEXT: flt.d a0, fa5, fa0 ; RV32IFD-NEXT: neg s0, a0 ; RV32IFD-NEXT: fcvt.d.w fa5, zero -; RV32IFD-NEXT: fle.d a0, fa5, fa0 -; RV32IFD-NEXT: neg s1, a0 +; RV32IFD-NEXT: flt.d a0, fa0, fa5 +; RV32IFD-NEXT: addi s1, a0, -1 ; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: and a0, s1, a0 ; RV32IFD-NEXT: or a0, s0, a0 @@ -1299,29 +1291,27 @@ ; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: call roundeven@plt ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp) ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) ; RV32IZFINXZDINX-NEXT: lw s1, 12(sp) -; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero -; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0 -; RV32IZFINXZDINX-NEXT: neg s2, a2 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI19_0) -; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI19_0+4)(a2) -; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI19_0)(a2) -; RV32IZFINXZDINX-NEXT: and a0, s2, a0 -; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0 -; RV32IZFINXZDINX-NEXT: neg a2, a2 -; RV32IZFINXZDINX-NEXT: or a0, a2, a0 -; RV32IZFINXZDINX-NEXT: and a1, s2, a1 -; RV32IZFINXZDINX-NEXT: or a1, a2, a1 +; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero +; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI19_0) +; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI19_0+4)(a4) +; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI19_0)(a4) +; RV32IZFINXZDINX-NEXT: flt.d a2, s0, a2 +; RV32IZFINXZDINX-NEXT: addi a2, a2, -1 +; RV32IZFINXZDINX-NEXT: and a0, a2, a0 +; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0 +; RV32IZFINXZDINX-NEXT: neg a3, a3 +; RV32IZFINXZDINX-NEXT: or a0, a3, a0 +; RV32IZFINXZDINX-NEXT: and a1, a2, a1 +; RV32IZFINXZDINX-NEXT: or a1, a3, a1 ; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 32 ; RV32IZFINXZDINX-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll --- a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll @@ -418,8 +418,8 @@ define double @select_fcmp_ugt(double %a, double %b) nounwind { ; CHECK-LABEL: select_fcmp_ugt: ; CHECK: # %bb.0: -; CHECK-NEXT: fle.d a0, fa0, fa1 -; CHECK-NEXT: beqz a0, .LBB9_2 +; CHECK-NEXT: flt.d a0, fa1, fa0 +; CHECK-NEXT: bnez a0, .LBB9_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: fmv.d fa0, fa1 ; CHECK-NEXT: .LBB9_2: @@ -428,16 +428,16 @@ ; CHECKRV32ZDINX-LABEL: select_fcmp_ugt: ; CHECKRV32ZDINX: # %bb.0: ; CHECKRV32ZDINX-NEXT: addi sp, sp, -16 -; CHECKRV32ZDINX-NEXT: sw a2, 8(sp) -; CHECKRV32ZDINX-NEXT: sw a3, 12(sp) -; CHECKRV32ZDINX-NEXT: lw a2, 8(sp) -; CHECKRV32ZDINX-NEXT: lw a3, 12(sp) ; CHECKRV32ZDINX-NEXT: sw a0, 8(sp) ; CHECKRV32ZDINX-NEXT: sw a1, 12(sp) ; CHECKRV32ZDINX-NEXT: lw a0, 8(sp) ; CHECKRV32ZDINX-NEXT: lw a1, 12(sp) -; CHECKRV32ZDINX-NEXT: fle.d a4, a0, a2 -; CHECKRV32ZDINX-NEXT: beqz a4, .LBB9_2 +; CHECKRV32ZDINX-NEXT: sw a2, 8(sp) +; CHECKRV32ZDINX-NEXT: sw a3, 12(sp) +; CHECKRV32ZDINX-NEXT: lw a2, 8(sp) +; CHECKRV32ZDINX-NEXT: lw a3, 12(sp) +; CHECKRV32ZDINX-NEXT: flt.d a4, a2, a0 +; CHECKRV32ZDINX-NEXT: bnez a4, .LBB9_2 ; CHECKRV32ZDINX-NEXT: # %bb.1: ; CHECKRV32ZDINX-NEXT: mv a0, a2 ; CHECKRV32ZDINX-NEXT: .LBB9_2: @@ -450,8 +450,8 @@ ; ; CHECKRV64ZDINX-LABEL: select_fcmp_ugt: ; CHECKRV64ZDINX: # %bb.0: -; CHECKRV64ZDINX-NEXT: fle.d a2, a0, a1 -; CHECKRV64ZDINX-NEXT: beqz a2, .LBB9_2 +; CHECKRV64ZDINX-NEXT: flt.d a2, a1, a0 +; CHECKRV64ZDINX-NEXT: bnez a2, .LBB9_2 ; CHECKRV64ZDINX-NEXT: # %bb.1: ; CHECKRV64ZDINX-NEXT: mv a0, a1 ; CHECKRV64ZDINX-NEXT: .LBB9_2: @@ -464,8 +464,8 @@ define double @select_fcmp_uge(double %a, double %b) nounwind { ; CHECK-LABEL: select_fcmp_uge: ; CHECK: # %bb.0: -; CHECK-NEXT: flt.d a0, fa0, fa1 -; CHECK-NEXT: beqz a0, .LBB10_2 +; CHECK-NEXT: fle.d a0, fa1, fa0 +; CHECK-NEXT: bnez a0, .LBB10_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: fmv.d fa0, fa1 ; CHECK-NEXT: .LBB10_2: @@ -474,16 +474,16 @@ ; CHECKRV32ZDINX-LABEL: select_fcmp_uge: ; CHECKRV32ZDINX: # %bb.0: ; CHECKRV32ZDINX-NEXT: addi sp, sp, -16 -; CHECKRV32ZDINX-NEXT: sw a2, 8(sp) -; CHECKRV32ZDINX-NEXT: sw a3, 12(sp) -; CHECKRV32ZDINX-NEXT: lw a2, 8(sp) -; CHECKRV32ZDINX-NEXT: lw a3, 12(sp) ; CHECKRV32ZDINX-NEXT: sw a0, 8(sp) ; CHECKRV32ZDINX-NEXT: sw a1, 12(sp) ; CHECKRV32ZDINX-NEXT: lw a0, 8(sp) ; CHECKRV32ZDINX-NEXT: lw a1, 12(sp) -; CHECKRV32ZDINX-NEXT: flt.d a4, a0, a2 -; CHECKRV32ZDINX-NEXT: beqz a4, .LBB10_2 +; CHECKRV32ZDINX-NEXT: sw a2, 8(sp) +; CHECKRV32ZDINX-NEXT: sw a3, 12(sp) +; CHECKRV32ZDINX-NEXT: lw a2, 8(sp) +; CHECKRV32ZDINX-NEXT: lw a3, 12(sp) +; CHECKRV32ZDINX-NEXT: fle.d a4, a2, a0 +; CHECKRV32ZDINX-NEXT: bnez a4, .LBB10_2 ; CHECKRV32ZDINX-NEXT: # %bb.1: ; CHECKRV32ZDINX-NEXT: mv a0, a2 ; CHECKRV32ZDINX-NEXT: .LBB10_2: @@ -496,8 +496,8 @@ ; ; CHECKRV64ZDINX-LABEL: select_fcmp_uge: ; CHECKRV64ZDINX: # %bb.0: -; CHECKRV64ZDINX-NEXT: flt.d a2, a0, a1 -; CHECKRV64ZDINX-NEXT: beqz a2, .LBB10_2 +; CHECKRV64ZDINX-NEXT: fle.d a2, a1, a0 +; CHECKRV64ZDINX-NEXT: bnez a2, .LBB10_2 ; CHECKRV64ZDINX-NEXT: # %bb.1: ; CHECKRV64ZDINX-NEXT: mv a0, a1 ; CHECKRV64ZDINX-NEXT: .LBB10_2: @@ -510,8 +510,8 @@ define double @select_fcmp_ult(double %a, double %b) nounwind { ; CHECK-LABEL: select_fcmp_ult: ; CHECK: # %bb.0: -; CHECK-NEXT: fle.d a0, fa1, fa0 -; CHECK-NEXT: beqz a0, .LBB11_2 +; CHECK-NEXT: flt.d a0, fa0, fa1 +; CHECK-NEXT: bnez a0, .LBB11_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: fmv.d fa0, fa1 ; CHECK-NEXT: .LBB11_2: @@ -520,16 +520,16 @@ ; CHECKRV32ZDINX-LABEL: select_fcmp_ult: ; CHECKRV32ZDINX: # %bb.0: ; CHECKRV32ZDINX-NEXT: addi sp, sp, -16 -; CHECKRV32ZDINX-NEXT: sw a0, 8(sp) -; CHECKRV32ZDINX-NEXT: sw a1, 12(sp) -; CHECKRV32ZDINX-NEXT: lw a0, 8(sp) -; CHECKRV32ZDINX-NEXT: lw a1, 12(sp) ; CHECKRV32ZDINX-NEXT: sw a2, 8(sp) ; CHECKRV32ZDINX-NEXT: sw a3, 12(sp) ; CHECKRV32ZDINX-NEXT: lw a2, 8(sp) ; CHECKRV32ZDINX-NEXT: lw a3, 12(sp) -; CHECKRV32ZDINX-NEXT: fle.d a4, a2, a0 -; CHECKRV32ZDINX-NEXT: beqz a4, .LBB11_2 +; CHECKRV32ZDINX-NEXT: sw a0, 8(sp) +; CHECKRV32ZDINX-NEXT: sw a1, 12(sp) +; CHECKRV32ZDINX-NEXT: lw a0, 8(sp) +; CHECKRV32ZDINX-NEXT: lw a1, 12(sp) +; CHECKRV32ZDINX-NEXT: flt.d a4, a0, a2 +; CHECKRV32ZDINX-NEXT: bnez a4, .LBB11_2 ; CHECKRV32ZDINX-NEXT: # %bb.1: ; CHECKRV32ZDINX-NEXT: mv a0, a2 ; CHECKRV32ZDINX-NEXT: .LBB11_2: @@ -542,8 +542,8 @@ ; ; CHECKRV64ZDINX-LABEL: select_fcmp_ult: ; CHECKRV64ZDINX: # %bb.0: -; CHECKRV64ZDINX-NEXT: fle.d a2, a1, a0 -; CHECKRV64ZDINX-NEXT: beqz a2, .LBB11_2 +; CHECKRV64ZDINX-NEXT: flt.d a2, a0, a1 +; CHECKRV64ZDINX-NEXT: bnez a2, .LBB11_2 ; CHECKRV64ZDINX-NEXT: # %bb.1: ; CHECKRV64ZDINX-NEXT: mv a0, a1 ; CHECKRV64ZDINX-NEXT: .LBB11_2: @@ -556,8 +556,8 @@ define double @select_fcmp_ule(double %a, double %b) nounwind { ; CHECK-LABEL: select_fcmp_ule: ; CHECK: # %bb.0: -; CHECK-NEXT: flt.d a0, fa1, fa0 -; CHECK-NEXT: beqz a0, .LBB12_2 +; CHECK-NEXT: fle.d a0, fa0, fa1 +; CHECK-NEXT: bnez a0, .LBB12_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: fmv.d fa0, fa1 ; CHECK-NEXT: .LBB12_2: @@ -566,16 +566,16 @@ ; CHECKRV32ZDINX-LABEL: select_fcmp_ule: ; CHECKRV32ZDINX: # %bb.0: ; CHECKRV32ZDINX-NEXT: addi sp, sp, -16 -; CHECKRV32ZDINX-NEXT: sw a0, 8(sp) -; CHECKRV32ZDINX-NEXT: sw a1, 12(sp) -; CHECKRV32ZDINX-NEXT: lw a0, 8(sp) -; CHECKRV32ZDINX-NEXT: lw a1, 12(sp) ; CHECKRV32ZDINX-NEXT: sw a2, 8(sp) ; CHECKRV32ZDINX-NEXT: sw a3, 12(sp) ; CHECKRV32ZDINX-NEXT: lw a2, 8(sp) ; CHECKRV32ZDINX-NEXT: lw a3, 12(sp) -; CHECKRV32ZDINX-NEXT: flt.d a4, a2, a0 -; CHECKRV32ZDINX-NEXT: beqz a4, .LBB12_2 +; CHECKRV32ZDINX-NEXT: sw a0, 8(sp) +; CHECKRV32ZDINX-NEXT: sw a1, 12(sp) +; CHECKRV32ZDINX-NEXT: lw a0, 8(sp) +; CHECKRV32ZDINX-NEXT: lw a1, 12(sp) +; CHECKRV32ZDINX-NEXT: fle.d a4, a0, a2 +; CHECKRV32ZDINX-NEXT: bnez a4, .LBB12_2 ; CHECKRV32ZDINX-NEXT: # %bb.1: ; CHECKRV32ZDINX-NEXT: mv a0, a2 ; CHECKRV32ZDINX-NEXT: .LBB12_2: @@ -588,8 +588,8 @@ ; ; CHECKRV64ZDINX-LABEL: select_fcmp_ule: ; CHECKRV64ZDINX: # %bb.0: -; CHECKRV64ZDINX-NEXT: flt.d a2, a1, a0 -; CHECKRV64ZDINX-NEXT: beqz a2, .LBB12_2 +; CHECKRV64ZDINX-NEXT: fle.d a2, a0, a1 +; CHECKRV64ZDINX-NEXT: bnez a2, .LBB12_2 ; CHECKRV64ZDINX-NEXT: # %bb.1: ; CHECKRV64ZDINX-NEXT: mv a0, a1 ; CHECKRV64ZDINX-NEXT: .LBB12_2: @@ -799,30 +799,30 @@ define signext i32 @select_fcmp_uge_negone_zero(double %a, double %b) nounwind { ; CHECK-LABEL: select_fcmp_uge_negone_zero: ; CHECK: # %bb.0: -; CHECK-NEXT: fle.d a0, fa0, fa1 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: flt.d a0, fa1, fa0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret ; ; CHECKRV32ZDINX-LABEL: select_fcmp_uge_negone_zero: ; CHECKRV32ZDINX: # %bb.0: ; CHECKRV32ZDINX-NEXT: addi sp, sp, -16 -; CHECKRV32ZDINX-NEXT: sw a2, 8(sp) -; CHECKRV32ZDINX-NEXT: sw a3, 12(sp) -; CHECKRV32ZDINX-NEXT: lw a2, 8(sp) -; CHECKRV32ZDINX-NEXT: lw a3, 12(sp) ; CHECKRV32ZDINX-NEXT: sw a0, 8(sp) ; CHECKRV32ZDINX-NEXT: sw a1, 12(sp) ; CHECKRV32ZDINX-NEXT: lw a0, 8(sp) ; CHECKRV32ZDINX-NEXT: lw a1, 12(sp) -; CHECKRV32ZDINX-NEXT: fle.d a0, a0, a2 -; CHECKRV32ZDINX-NEXT: addi a0, a0, -1 +; CHECKRV32ZDINX-NEXT: sw a2, 8(sp) +; CHECKRV32ZDINX-NEXT: sw a3, 12(sp) +; CHECKRV32ZDINX-NEXT: lw a2, 8(sp) +; CHECKRV32ZDINX-NEXT: lw a3, 12(sp) +; CHECKRV32ZDINX-NEXT: flt.d a0, a2, a0 +; CHECKRV32ZDINX-NEXT: neg a0, a0 ; CHECKRV32ZDINX-NEXT: addi sp, sp, 16 ; CHECKRV32ZDINX-NEXT: ret ; ; CHECKRV64ZDINX-LABEL: select_fcmp_uge_negone_zero: ; CHECKRV64ZDINX: # %bb.0: -; CHECKRV64ZDINX-NEXT: fle.d a0, a0, a1 -; CHECKRV64ZDINX-NEXT: addi a0, a0, -1 +; CHECKRV64ZDINX-NEXT: flt.d a0, a1, a0 +; CHECKRV64ZDINX-NEXT: neg a0, a0 ; CHECKRV64ZDINX-NEXT: ret %1 = fcmp ugt double %a, %b %2 = select i1 %1, i32 -1, i32 0 @@ -832,30 +832,33 @@ define signext i32 @select_fcmp_uge_1_2(double %a, double %b) nounwind { ; CHECK-LABEL: select_fcmp_uge_1_2: ; CHECK: # %bb.0: -; CHECK-NEXT: fle.d a0, fa0, fa1 -; CHECK-NEXT: addi a0, a0, 1 +; CHECK-NEXT: flt.d a0, fa1, fa0 +; CHECK-NEXT: li a1, 2 +; CHECK-NEXT: sub a0, a1, a0 ; CHECK-NEXT: ret ; ; CHECKRV32ZDINX-LABEL: select_fcmp_uge_1_2: ; CHECKRV32ZDINX: # %bb.0: ; CHECKRV32ZDINX-NEXT: addi sp, sp, -16 -; CHECKRV32ZDINX-NEXT: sw a2, 8(sp) -; CHECKRV32ZDINX-NEXT: sw a3, 12(sp) -; CHECKRV32ZDINX-NEXT: lw a2, 8(sp) -; CHECKRV32ZDINX-NEXT: lw a3, 12(sp) ; CHECKRV32ZDINX-NEXT: sw a0, 8(sp) ; CHECKRV32ZDINX-NEXT: sw a1, 12(sp) ; CHECKRV32ZDINX-NEXT: lw a0, 8(sp) ; CHECKRV32ZDINX-NEXT: lw a1, 12(sp) -; CHECKRV32ZDINX-NEXT: fle.d a0, a0, a2 -; CHECKRV32ZDINX-NEXT: addi a0, a0, 1 +; CHECKRV32ZDINX-NEXT: sw a2, 8(sp) +; CHECKRV32ZDINX-NEXT: sw a3, 12(sp) +; CHECKRV32ZDINX-NEXT: lw a2, 8(sp) +; CHECKRV32ZDINX-NEXT: lw a3, 12(sp) +; CHECKRV32ZDINX-NEXT: flt.d a0, a2, a0 +; CHECKRV32ZDINX-NEXT: li a1, 2 +; CHECKRV32ZDINX-NEXT: sub a0, a1, a0 ; CHECKRV32ZDINX-NEXT: addi sp, sp, 16 ; CHECKRV32ZDINX-NEXT: ret ; ; CHECKRV64ZDINX-LABEL: select_fcmp_uge_1_2: ; CHECKRV64ZDINX: # %bb.0: -; CHECKRV64ZDINX-NEXT: fle.d a0, a0, a1 -; CHECKRV64ZDINX-NEXT: addi a0, a0, 1 +; CHECKRV64ZDINX-NEXT: flt.d a0, a1, a0 +; CHECKRV64ZDINX-NEXT: li a1, 2 +; CHECKRV64ZDINX-NEXT: sub a0, a1, a0 ; CHECKRV64ZDINX-NEXT: ret %1 = fcmp ugt double %a, %b %2 = select i1 %1, i32 1, i32 2 diff --git a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll --- a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll @@ -572,8 +572,8 @@ define void @br_fcmp_ugt(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_ugt: ; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa0, fa1 -; RV32IF-NEXT: beqz a0, .LBB10_2 +; RV32IF-NEXT: flt.s a0, fa1, fa0 +; RV32IF-NEXT: bnez a0, .LBB10_2 ; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB10_2: # %if.then @@ -583,8 +583,8 @@ ; ; RV64IF-LABEL: br_fcmp_ugt: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa0, fa1 -; RV64IF-NEXT: beqz a0, .LBB10_2 +; RV64IF-NEXT: flt.s a0, fa1, fa0 +; RV64IF-NEXT: bnez a0, .LBB10_2 ; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB10_2: # %if.then @@ -594,8 +594,8 @@ ; ; RV32IZFINX-LABEL: br_fcmp_ugt: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: fle.s a0, a0, a1 -; RV32IZFINX-NEXT: beqz a0, .LBB10_2 +; RV32IZFINX-NEXT: flt.s a0, a1, a0 +; RV32IZFINX-NEXT: bnez a0, .LBB10_2 ; RV32IZFINX-NEXT: # %bb.1: # %if.else ; RV32IZFINX-NEXT: ret ; RV32IZFINX-NEXT: .LBB10_2: # %if.then @@ -605,8 +605,8 @@ ; ; RV64IZFINX-LABEL: br_fcmp_ugt: ; RV64IZFINX: # %bb.0: -; RV64IZFINX-NEXT: fle.s a0, a0, a1 -; RV64IZFINX-NEXT: beqz a0, .LBB10_2 +; RV64IZFINX-NEXT: flt.s a0, a1, a0 +; RV64IZFINX-NEXT: bnez a0, .LBB10_2 ; RV64IZFINX-NEXT: # %bb.1: # %if.else ; RV64IZFINX-NEXT: ret ; RV64IZFINX-NEXT: .LBB10_2: # %if.then @@ -625,8 +625,8 @@ define void @br_fcmp_uge(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_uge: ; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa0, fa1 -; RV32IF-NEXT: beqz a0, .LBB11_2 +; RV32IF-NEXT: fle.s a0, fa1, fa0 +; RV32IF-NEXT: bnez a0, .LBB11_2 ; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB11_2: # %if.then @@ -636,8 +636,8 @@ ; ; RV64IF-LABEL: br_fcmp_uge: ; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa0, fa1 -; RV64IF-NEXT: beqz a0, .LBB11_2 +; RV64IF-NEXT: fle.s a0, fa1, fa0 +; RV64IF-NEXT: bnez a0, .LBB11_2 ; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB11_2: # %if.then @@ -647,8 +647,8 @@ ; ; RV32IZFINX-LABEL: br_fcmp_uge: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: flt.s a0, a0, a1 -; RV32IZFINX-NEXT: beqz a0, .LBB11_2 +; RV32IZFINX-NEXT: fle.s a0, a1, a0 +; RV32IZFINX-NEXT: bnez a0, .LBB11_2 ; RV32IZFINX-NEXT: # %bb.1: # %if.else ; RV32IZFINX-NEXT: ret ; RV32IZFINX-NEXT: .LBB11_2: # %if.then @@ -658,8 +658,8 @@ ; ; RV64IZFINX-LABEL: br_fcmp_uge: ; RV64IZFINX: # %bb.0: -; RV64IZFINX-NEXT: flt.s a0, a0, a1 -; RV64IZFINX-NEXT: beqz a0, .LBB11_2 +; RV64IZFINX-NEXT: fle.s a0, a1, a0 +; RV64IZFINX-NEXT: bnez a0, .LBB11_2 ; RV64IZFINX-NEXT: # %bb.1: # %if.else ; RV64IZFINX-NEXT: ret ; RV64IZFINX-NEXT: .LBB11_2: # %if.then @@ -678,8 +678,8 @@ define void @br_fcmp_ult(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_ult: ; RV32IF: # %bb.0: -; RV32IF-NEXT: fle.s a0, fa1, fa0 -; RV32IF-NEXT: beqz a0, .LBB12_2 +; RV32IF-NEXT: flt.s a0, fa0, fa1 +; RV32IF-NEXT: bnez a0, .LBB12_2 ; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB12_2: # %if.then @@ -689,8 +689,8 @@ ; ; RV64IF-LABEL: br_fcmp_ult: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fle.s a0, fa1, fa0 -; RV64IF-NEXT: beqz a0, .LBB12_2 +; RV64IF-NEXT: flt.s a0, fa0, fa1 +; RV64IF-NEXT: bnez a0, .LBB12_2 ; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB12_2: # %if.then @@ -700,8 +700,8 @@ ; ; RV32IZFINX-LABEL: br_fcmp_ult: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: fle.s a0, a1, a0 -; RV32IZFINX-NEXT: beqz a0, .LBB12_2 +; RV32IZFINX-NEXT: flt.s a0, a0, a1 +; RV32IZFINX-NEXT: bnez a0, .LBB12_2 ; RV32IZFINX-NEXT: # %bb.1: # %if.else ; RV32IZFINX-NEXT: ret ; RV32IZFINX-NEXT: .LBB12_2: # %if.then @@ -711,8 +711,8 @@ ; ; RV64IZFINX-LABEL: br_fcmp_ult: ; RV64IZFINX: # %bb.0: -; RV64IZFINX-NEXT: fle.s a0, a1, a0 -; RV64IZFINX-NEXT: beqz a0, .LBB12_2 +; RV64IZFINX-NEXT: flt.s a0, a0, a1 +; RV64IZFINX-NEXT: bnez a0, .LBB12_2 ; RV64IZFINX-NEXT: # %bb.1: # %if.else ; RV64IZFINX-NEXT: ret ; RV64IZFINX-NEXT: .LBB12_2: # %if.then @@ -731,8 +731,8 @@ define void @br_fcmp_ule(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_ule: ; RV32IF: # %bb.0: -; RV32IF-NEXT: flt.s a0, fa1, fa0 -; RV32IF-NEXT: beqz a0, .LBB13_2 +; RV32IF-NEXT: fle.s a0, fa0, fa1 +; RV32IF-NEXT: bnez a0, .LBB13_2 ; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB13_2: # %if.then @@ -742,8 +742,8 @@ ; ; RV64IF-LABEL: br_fcmp_ule: ; RV64IF: # %bb.0: -; RV64IF-NEXT: flt.s a0, fa1, fa0 -; RV64IF-NEXT: beqz a0, .LBB13_2 +; RV64IF-NEXT: fle.s a0, fa0, fa1 +; RV64IF-NEXT: bnez a0, .LBB13_2 ; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB13_2: # %if.then @@ -753,8 +753,8 @@ ; ; RV32IZFINX-LABEL: br_fcmp_ule: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: flt.s a0, a1, a0 -; RV32IZFINX-NEXT: beqz a0, .LBB13_2 +; RV32IZFINX-NEXT: fle.s a0, a0, a1 +; RV32IZFINX-NEXT: bnez a0, .LBB13_2 ; RV32IZFINX-NEXT: # %bb.1: # %if.else ; RV32IZFINX-NEXT: ret ; RV32IZFINX-NEXT: .LBB13_2: # %if.then @@ -764,8 +764,8 @@ ; ; RV64IZFINX-LABEL: br_fcmp_ule: ; RV64IZFINX: # %bb.0: -; RV64IZFINX-NEXT: flt.s a0, a1, a0 -; RV64IZFINX-NEXT: beqz a0, .LBB13_2 +; RV64IZFINX-NEXT: fle.s a0, a0, a1 +; RV64IZFINX-NEXT: bnez a0, .LBB13_2 ; RV64IZFINX-NEXT: # %bb.1: # %if.else ; RV64IZFINX-NEXT: ret ; RV64IZFINX-NEXT: .LBB13_2: # %if.then diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll --- a/llvm/test/CodeGen/RISCV/float-convert.ll +++ b/llvm/test/CodeGen/RISCV/float-convert.ll @@ -620,11 +620,11 @@ ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 -; RV32IF-NEXT: fle.s s0, fa5, fa0 +; RV32IF-NEXT: flt.s s0, fa0, fa5 ; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a2, 524288 -; RV32IF-NEXT: beqz s0, .LBB12_2 +; RV32IF-NEXT: bnez s0, .LBB12_2 ; RV32IF-NEXT: # %bb.1: # %start ; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB12_2: # %start @@ -639,8 +639,8 @@ ; RV32IF-NEXT: neg a4, a1 ; RV32IF-NEXT: and a1, a4, a2 ; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: neg a3, s0 -; RV32IF-NEXT: and a0, a3, a0 +; RV32IF-NEXT: addi s0, s0, -1 +; RV32IF-NEXT: and a0, s0, a0 ; RV32IF-NEXT: or a0, a2, a0 ; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -666,12 +666,12 @@ ; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: mv s0, a0 ; RV32IZFINX-NEXT: lui a0, 913408 -; RV32IZFINX-NEXT: fle.s s1, a0, s0 +; RV32IZFINX-NEXT: flt.s s1, s0, a0 ; RV32IZFINX-NEXT: mv a0, s0 ; RV32IZFINX-NEXT: call __fixsfdi@plt ; RV32IZFINX-NEXT: lui a4, 524288 ; RV32IZFINX-NEXT: lui a2, 524288 -; RV32IZFINX-NEXT: beqz s1, .LBB12_2 +; RV32IZFINX-NEXT: bnez s1, .LBB12_2 ; RV32IZFINX-NEXT: # %bb.1: # %start ; RV32IZFINX-NEXT: mv a2, a1 ; RV32IZFINX-NEXT: .LBB12_2: # %start @@ -685,8 +685,8 @@ ; RV32IZFINX-NEXT: feq.s a1, s0, s0 ; RV32IZFINX-NEXT: neg a4, a1 ; RV32IZFINX-NEXT: and a1, a4, a2 -; RV32IZFINX-NEXT: neg a2, s1 -; RV32IZFINX-NEXT: and a0, a2, a0 +; RV32IZFINX-NEXT: addi s1, s1, -1 +; RV32IZFINX-NEXT: and a0, s1, a0 ; RV32IZFINX-NEXT: neg a2, a3 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: and a0, a4, a0 @@ -866,8 +866,8 @@ ; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.w.x fa5, zero -; RV32IF-NEXT: fle.s a0, fa5, fa0 -; RV32IF-NEXT: neg s0, a0 +; RV32IF-NEXT: flt.s a0, fa0, fa5 +; RV32IF-NEXT: addi s0, a0, -1 ; RV32IF-NEXT: call __fixunssfdi@plt ; RV32IF-NEXT: lui a2, %hi(.LCPI14_0) ; RV32IF-NEXT: flw fa5, %lo(.LCPI14_0)(a2) @@ -899,8 +899,8 @@ ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: mv s0, a0 -; RV32IZFINX-NEXT: fle.s a0, zero, a0 -; RV32IZFINX-NEXT: neg s1, a0 +; RV32IZFINX-NEXT: flt.s a0, a0, zero +; RV32IZFINX-NEXT: addi s1, a0, -1 ; RV32IZFINX-NEXT: mv a0, s0 ; RV32IZFINX-NEXT: call __fixunssfdi@plt ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI14_0) diff --git a/llvm/test/CodeGen/RISCV/float-fcmp.ll b/llvm/test/CodeGen/RISCV/float-fcmp.ll --- a/llvm/test/CodeGen/RISCV/float-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/float-fcmp.ll @@ -388,14 +388,12 @@ define i32 @fcmp_ugt(float %a, float %b) nounwind { ; CHECKIF-LABEL: fcmp_ugt: ; CHECKIF: # %bb.0: -; CHECKIF-NEXT: fle.s a0, fa0, fa1 -; CHECKIF-NEXT: xori a0, a0, 1 +; CHECKIF-NEXT: flt.s a0, fa1, fa0 ; CHECKIF-NEXT: ret ; ; CHECKIZFINX-LABEL: fcmp_ugt: ; CHECKIZFINX: # %bb.0: -; CHECKIZFINX-NEXT: fle.s a0, a0, a1 -; CHECKIZFINX-NEXT: xori a0, a0, 1 +; CHECKIZFINX-NEXT: flt.s a0, a1, a0 ; CHECKIZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ugt: @@ -425,14 +423,12 @@ define i32 @fcmp_uge(float %a, float %b) nounwind { ; CHECKIF-LABEL: fcmp_uge: ; CHECKIF: # %bb.0: -; CHECKIF-NEXT: flt.s a0, fa0, fa1 -; CHECKIF-NEXT: xori a0, a0, 1 +; CHECKIF-NEXT: fle.s a0, fa1, fa0 ; CHECKIF-NEXT: ret ; ; CHECKIZFINX-LABEL: fcmp_uge: ; CHECKIZFINX: # %bb.0: -; CHECKIZFINX-NEXT: flt.s a0, a0, a1 -; CHECKIZFINX-NEXT: xori a0, a0, 1 +; CHECKIZFINX-NEXT: fle.s a0, a1, a0 ; CHECKIZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_uge: @@ -464,14 +460,12 @@ define i32 @fcmp_ult(float %a, float %b) nounwind { ; CHECKIF-LABEL: fcmp_ult: ; CHECKIF: # %bb.0: -; CHECKIF-NEXT: fle.s a0, fa1, fa0 -; CHECKIF-NEXT: xori a0, a0, 1 +; CHECKIF-NEXT: flt.s a0, fa0, fa1 ; CHECKIF-NEXT: ret ; ; CHECKIZFINX-LABEL: fcmp_ult: ; CHECKIZFINX: # %bb.0: -; CHECKIZFINX-NEXT: fle.s a0, a1, a0 -; CHECKIZFINX-NEXT: xori a0, a0, 1 +; CHECKIZFINX-NEXT: flt.s a0, a0, a1 ; CHECKIZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ult: @@ -501,14 +495,12 @@ define i32 @fcmp_ule(float %a, float %b) nounwind { ; CHECKIF-LABEL: fcmp_ule: ; CHECKIF: # %bb.0: -; CHECKIF-NEXT: flt.s a0, fa1, fa0 -; CHECKIF-NEXT: xori a0, a0, 1 +; CHECKIF-NEXT: fle.s a0, fa0, fa1 ; CHECKIF-NEXT: ret ; ; CHECKIZFINX-LABEL: fcmp_ule: ; CHECKIZFINX: # %bb.0: -; CHECKIZFINX-NEXT: flt.s a0, a1, a0 -; CHECKIZFINX-NEXT: xori a0, a0, 1 +; CHECKIZFINX-NEXT: fle.s a0, a0, a1 ; CHECKIZFINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ule: diff --git a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll --- a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll @@ -51,12 +51,12 @@ ; RV32IF-NEXT: .LBB1_2: ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 -; RV32IF-NEXT: fle.s s0, fa5, fs0 +; RV32IF-NEXT: flt.s s0, fs0, fa5 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a2, 524288 -; RV32IF-NEXT: beqz s0, .LBB1_4 +; RV32IF-NEXT: bnez s0, .LBB1_4 ; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB1_4: @@ -70,8 +70,8 @@ ; RV32IF-NEXT: feq.s a1, fs0, fs0 ; RV32IF-NEXT: neg a4, a1 ; RV32IF-NEXT: and a1, a4, a2 -; RV32IF-NEXT: neg a2, s0 -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: addi s0, s0, -1 +; RV32IF-NEXT: and a0, s0, a0 ; RV32IF-NEXT: neg a2, a3 ; RV32IF-NEXT: or a0, a2, a0 ; RV32IF-NEXT: and a0, a4, a0 @@ -95,8 +95,6 @@ ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: mv s0, a0 ; RV32IZFINX-NEXT: lui a0, 307200 ; RV32IZFINX-NEXT: fabs.s a1, s0 @@ -107,22 +105,22 @@ ; RV32IZFINX-NEXT: fcvt.s.w a0, a0, rdn ; RV32IZFINX-NEXT: fsgnj.s s0, a0, s0 ; RV32IZFINX-NEXT: .LBB1_2: -; RV32IZFINX-NEXT: lui a0, 913408 -; RV32IZFINX-NEXT: fle.s s1, a0, s0 -; RV32IZFINX-NEXT: neg s2, s1 ; RV32IZFINX-NEXT: mv a0, s0 ; RV32IZFINX-NEXT: call __fixsfdi@plt -; RV32IZFINX-NEXT: lui a2, %hi(.LCPI1_0) -; RV32IZFINX-NEXT: lw a2, %lo(.LCPI1_0)(a2) -; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: lui a2, 913408 +; RV32IZFINX-NEXT: lui a3, %hi(.LCPI1_0) +; RV32IZFINX-NEXT: lw a3, %lo(.LCPI1_0)(a3) +; RV32IZFINX-NEXT: flt.s a6, s0, a2 +; RV32IZFINX-NEXT: addi a2, a6, -1 +; RV32IZFINX-NEXT: and a0, a2, a0 +; RV32IZFINX-NEXT: flt.s a4, a3, s0 ; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 ; RV32IZFINX-NEXT: lui a3, 524288 -; RV32IZFINX-NEXT: beqz s1, .LBB1_4 +; RV32IZFINX-NEXT: bnez a6, .LBB1_4 ; RV32IZFINX-NEXT: # %bb.3: ; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB1_4: @@ -134,8 +132,6 @@ ; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret ; @@ -180,8 +176,7 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -193,22 +188,21 @@ ; RV32IF-NEXT: fcvt.s.w fa5, a0, rdn ; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0 ; RV32IF-NEXT: .LBB3_2: -; RV32IF-NEXT: fmv.w.x fa5, zero -; RV32IF-NEXT: fle.s a0, fa5, fs0 -; RV32IF-NEXT: neg s0, a0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: fmv.w.x fa5, zero ; RV32IF-NEXT: lui a2, %hi(.LCPI3_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI3_0)(a2) -; RV32IF-NEXT: and a0, s0, a0 -; RV32IF-NEXT: flt.s a2, fa5, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: and a1, s0, a1 -; RV32IF-NEXT: or a1, a2, a1 +; RV32IF-NEXT: flw fa4, %lo(.LCPI3_0)(a2) +; RV32IF-NEXT: flt.s a2, fs0, fa5 +; RV32IF-NEXT: addi a2, a2, -1 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: flt.s a3, fa4, fs0 +; RV32IF-NEXT: neg a3, a3 +; RV32IF-NEXT: or a0, a3, a0 +; RV32IF-NEXT: and a1, a2, a1 +; RV32IF-NEXT: or a1, a3, a1 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -226,7 +220,6 @@ ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: mv s0, a0 ; RV32IZFINX-NEXT: lui a0, 307200 ; RV32IZFINX-NEXT: fabs.s a1, s0 @@ -237,21 +230,20 @@ ; RV32IZFINX-NEXT: fcvt.s.w a0, a0, rdn ; RV32IZFINX-NEXT: fsgnj.s s0, a0, s0 ; RV32IZFINX-NEXT: .LBB3_2: -; RV32IZFINX-NEXT: fle.s a0, zero, s0 -; RV32IZFINX-NEXT: neg s1, a0 ; RV32IZFINX-NEXT: mv a0, s0 ; RV32IZFINX-NEXT: call __fixunssfdi@plt ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI3_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI3_0)(a2) -; RV32IZFINX-NEXT: and a0, s1, a0 +; RV32IZFINX-NEXT: flt.s a3, s0, zero +; RV32IZFINX-NEXT: addi a3, a3, -1 +; RV32IZFINX-NEXT: and a0, a3, a0 ; RV32IZFINX-NEXT: flt.s a2, a2, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: or a0, a2, a0 -; RV32IZFINX-NEXT: and a1, s1, a1 +; RV32IZFINX-NEXT: and a1, a3, a1 ; RV32IZFINX-NEXT: or a1, a2, a1 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret ; @@ -311,12 +303,12 @@ ; RV32IF-NEXT: .LBB5_2: ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 -; RV32IF-NEXT: fle.s s0, fa5, fs0 +; RV32IF-NEXT: flt.s s0, fs0, fa5 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a2, 524288 -; RV32IF-NEXT: beqz s0, .LBB5_4 +; RV32IF-NEXT: bnez s0, .LBB5_4 ; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB5_4: @@ -330,8 +322,8 @@ ; RV32IF-NEXT: feq.s a1, fs0, fs0 ; RV32IF-NEXT: neg a4, a1 ; RV32IF-NEXT: and a1, a4, a2 -; RV32IF-NEXT: neg a2, s0 -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: addi s0, s0, -1 +; RV32IF-NEXT: and a0, s0, a0 ; RV32IF-NEXT: neg a2, a3 ; RV32IF-NEXT: or a0, a2, a0 ; RV32IF-NEXT: and a0, a4, a0 @@ -355,8 +347,6 @@ ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: mv s0, a0 ; RV32IZFINX-NEXT: lui a0, 307200 ; RV32IZFINX-NEXT: fabs.s a1, s0 @@ -367,22 +357,22 @@ ; RV32IZFINX-NEXT: fcvt.s.w a0, a0, rup ; RV32IZFINX-NEXT: fsgnj.s s0, a0, s0 ; RV32IZFINX-NEXT: .LBB5_2: -; RV32IZFINX-NEXT: lui a0, 913408 -; RV32IZFINX-NEXT: fle.s s1, a0, s0 -; RV32IZFINX-NEXT: neg s2, s1 ; RV32IZFINX-NEXT: mv a0, s0 ; RV32IZFINX-NEXT: call __fixsfdi@plt -; RV32IZFINX-NEXT: lui a2, %hi(.LCPI5_0) -; RV32IZFINX-NEXT: lw a2, %lo(.LCPI5_0)(a2) -; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: lui a2, 913408 +; RV32IZFINX-NEXT: lui a3, %hi(.LCPI5_0) +; RV32IZFINX-NEXT: lw a3, %lo(.LCPI5_0)(a3) +; RV32IZFINX-NEXT: flt.s a6, s0, a2 +; RV32IZFINX-NEXT: addi a2, a6, -1 +; RV32IZFINX-NEXT: and a0, a2, a0 +; RV32IZFINX-NEXT: flt.s a4, a3, s0 ; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 ; RV32IZFINX-NEXT: lui a3, 524288 -; RV32IZFINX-NEXT: beqz s1, .LBB5_4 +; RV32IZFINX-NEXT: bnez a6, .LBB5_4 ; RV32IZFINX-NEXT: # %bb.3: ; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB5_4: @@ -394,8 +384,6 @@ ; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret ; @@ -440,8 +428,7 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -453,22 +440,21 @@ ; RV32IF-NEXT: fcvt.s.w fa5, a0, rup ; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0 ; RV32IF-NEXT: .LBB7_2: -; RV32IF-NEXT: fmv.w.x fa5, zero -; RV32IF-NEXT: fle.s a0, fa5, fs0 -; RV32IF-NEXT: neg s0, a0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: fmv.w.x fa5, zero ; RV32IF-NEXT: lui a2, %hi(.LCPI7_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI7_0)(a2) -; RV32IF-NEXT: and a0, s0, a0 -; RV32IF-NEXT: flt.s a2, fa5, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: and a1, s0, a1 -; RV32IF-NEXT: or a1, a2, a1 +; RV32IF-NEXT: flw fa4, %lo(.LCPI7_0)(a2) +; RV32IF-NEXT: flt.s a2, fs0, fa5 +; RV32IF-NEXT: addi a2, a2, -1 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: flt.s a3, fa4, fs0 +; RV32IF-NEXT: neg a3, a3 +; RV32IF-NEXT: or a0, a3, a0 +; RV32IF-NEXT: and a1, a2, a1 +; RV32IF-NEXT: or a1, a3, a1 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -486,7 +472,6 @@ ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: mv s0, a0 ; RV32IZFINX-NEXT: lui a0, 307200 ; RV32IZFINX-NEXT: fabs.s a1, s0 @@ -497,21 +482,20 @@ ; RV32IZFINX-NEXT: fcvt.s.w a0, a0, rup ; RV32IZFINX-NEXT: fsgnj.s s0, a0, s0 ; RV32IZFINX-NEXT: .LBB7_2: -; RV32IZFINX-NEXT: fle.s a0, zero, s0 -; RV32IZFINX-NEXT: neg s1, a0 ; RV32IZFINX-NEXT: mv a0, s0 ; RV32IZFINX-NEXT: call __fixunssfdi@plt ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI7_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI7_0)(a2) -; RV32IZFINX-NEXT: and a0, s1, a0 +; RV32IZFINX-NEXT: flt.s a3, s0, zero +; RV32IZFINX-NEXT: addi a3, a3, -1 +; RV32IZFINX-NEXT: and a0, a3, a0 ; RV32IZFINX-NEXT: flt.s a2, a2, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: or a0, a2, a0 -; RV32IZFINX-NEXT: and a1, s1, a1 +; RV32IZFINX-NEXT: and a1, a3, a1 ; RV32IZFINX-NEXT: or a1, a2, a1 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret ; @@ -571,12 +555,12 @@ ; RV32IF-NEXT: .LBB9_2: ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 -; RV32IF-NEXT: fle.s s0, fa5, fs0 +; RV32IF-NEXT: flt.s s0, fs0, fa5 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a2, 524288 -; RV32IF-NEXT: beqz s0, .LBB9_4 +; RV32IF-NEXT: bnez s0, .LBB9_4 ; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB9_4: @@ -590,8 +574,8 @@ ; RV32IF-NEXT: feq.s a1, fs0, fs0 ; RV32IF-NEXT: neg a4, a1 ; RV32IF-NEXT: and a1, a4, a2 -; RV32IF-NEXT: neg a2, s0 -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: addi s0, s0, -1 +; RV32IF-NEXT: and a0, s0, a0 ; RV32IF-NEXT: neg a2, a3 ; RV32IF-NEXT: or a0, a2, a0 ; RV32IF-NEXT: and a0, a4, a0 @@ -615,8 +599,6 @@ ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: mv s0, a0 ; RV32IZFINX-NEXT: lui a0, 307200 ; RV32IZFINX-NEXT: fabs.s a1, s0 @@ -627,22 +609,22 @@ ; RV32IZFINX-NEXT: fcvt.s.w a0, a0, rtz ; RV32IZFINX-NEXT: fsgnj.s s0, a0, s0 ; RV32IZFINX-NEXT: .LBB9_2: -; RV32IZFINX-NEXT: lui a0, 913408 -; RV32IZFINX-NEXT: fle.s s1, a0, s0 -; RV32IZFINX-NEXT: neg s2, s1 ; RV32IZFINX-NEXT: mv a0, s0 ; RV32IZFINX-NEXT: call __fixsfdi@plt -; RV32IZFINX-NEXT: lui a2, %hi(.LCPI9_0) -; RV32IZFINX-NEXT: lw a2, %lo(.LCPI9_0)(a2) -; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: lui a2, 913408 +; RV32IZFINX-NEXT: lui a3, %hi(.LCPI9_0) +; RV32IZFINX-NEXT: lw a3, %lo(.LCPI9_0)(a3) +; RV32IZFINX-NEXT: flt.s a6, s0, a2 +; RV32IZFINX-NEXT: addi a2, a6, -1 +; RV32IZFINX-NEXT: and a0, a2, a0 +; RV32IZFINX-NEXT: flt.s a4, a3, s0 ; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 ; RV32IZFINX-NEXT: lui a3, 524288 -; RV32IZFINX-NEXT: beqz s1, .LBB9_4 +; RV32IZFINX-NEXT: bnez a6, .LBB9_4 ; RV32IZFINX-NEXT: # %bb.3: ; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB9_4: @@ -654,8 +636,6 @@ ; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret ; @@ -700,8 +680,7 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -713,22 +692,21 @@ ; RV32IF-NEXT: fcvt.s.w fa5, a0, rtz ; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0 ; RV32IF-NEXT: .LBB11_2: -; RV32IF-NEXT: fmv.w.x fa5, zero -; RV32IF-NEXT: fle.s a0, fa5, fs0 -; RV32IF-NEXT: neg s0, a0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: fmv.w.x fa5, zero ; RV32IF-NEXT: lui a2, %hi(.LCPI11_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI11_0)(a2) -; RV32IF-NEXT: and a0, s0, a0 -; RV32IF-NEXT: flt.s a2, fa5, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: and a1, s0, a1 -; RV32IF-NEXT: or a1, a2, a1 +; RV32IF-NEXT: flw fa4, %lo(.LCPI11_0)(a2) +; RV32IF-NEXT: flt.s a2, fs0, fa5 +; RV32IF-NEXT: addi a2, a2, -1 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: flt.s a3, fa4, fs0 +; RV32IF-NEXT: neg a3, a3 +; RV32IF-NEXT: or a0, a3, a0 +; RV32IF-NEXT: and a1, a2, a1 +; RV32IF-NEXT: or a1, a3, a1 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -746,7 +724,6 @@ ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: mv s0, a0 ; RV32IZFINX-NEXT: lui a0, 307200 ; RV32IZFINX-NEXT: fabs.s a1, s0 @@ -757,21 +734,20 @@ ; RV32IZFINX-NEXT: fcvt.s.w a0, a0, rtz ; RV32IZFINX-NEXT: fsgnj.s s0, a0, s0 ; RV32IZFINX-NEXT: .LBB11_2: -; RV32IZFINX-NEXT: fle.s a0, zero, s0 -; RV32IZFINX-NEXT: neg s1, a0 ; RV32IZFINX-NEXT: mv a0, s0 ; RV32IZFINX-NEXT: call __fixunssfdi@plt ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI11_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI11_0)(a2) -; RV32IZFINX-NEXT: and a0, s1, a0 +; RV32IZFINX-NEXT: flt.s a3, s0, zero +; RV32IZFINX-NEXT: addi a3, a3, -1 +; RV32IZFINX-NEXT: and a0, a3, a0 ; RV32IZFINX-NEXT: flt.s a2, a2, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: or a0, a2, a0 -; RV32IZFINX-NEXT: and a1, s1, a1 +; RV32IZFINX-NEXT: and a1, a3, a1 ; RV32IZFINX-NEXT: or a1, a2, a1 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret ; @@ -831,12 +807,12 @@ ; RV32IF-NEXT: .LBB13_2: ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 -; RV32IF-NEXT: fle.s s0, fa5, fs0 +; RV32IF-NEXT: flt.s s0, fs0, fa5 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a2, 524288 -; RV32IF-NEXT: beqz s0, .LBB13_4 +; RV32IF-NEXT: bnez s0, .LBB13_4 ; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB13_4: @@ -850,8 +826,8 @@ ; RV32IF-NEXT: feq.s a1, fs0, fs0 ; RV32IF-NEXT: neg a4, a1 ; RV32IF-NEXT: and a1, a4, a2 -; RV32IF-NEXT: neg a2, s0 -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: addi s0, s0, -1 +; RV32IF-NEXT: and a0, s0, a0 ; RV32IF-NEXT: neg a2, a3 ; RV32IF-NEXT: or a0, a2, a0 ; RV32IF-NEXT: and a0, a4, a0 @@ -875,8 +851,6 @@ ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: mv s0, a0 ; RV32IZFINX-NEXT: lui a0, 307200 ; RV32IZFINX-NEXT: fabs.s a1, s0 @@ -887,22 +861,22 @@ ; RV32IZFINX-NEXT: fcvt.s.w a0, a0, rmm ; RV32IZFINX-NEXT: fsgnj.s s0, a0, s0 ; RV32IZFINX-NEXT: .LBB13_2: -; RV32IZFINX-NEXT: lui a0, 913408 -; RV32IZFINX-NEXT: fle.s s1, a0, s0 -; RV32IZFINX-NEXT: neg s2, s1 ; RV32IZFINX-NEXT: mv a0, s0 ; RV32IZFINX-NEXT: call __fixsfdi@plt -; RV32IZFINX-NEXT: lui a2, %hi(.LCPI13_0) -; RV32IZFINX-NEXT: lw a2, %lo(.LCPI13_0)(a2) -; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: lui a2, 913408 +; RV32IZFINX-NEXT: lui a3, %hi(.LCPI13_0) +; RV32IZFINX-NEXT: lw a3, %lo(.LCPI13_0)(a3) +; RV32IZFINX-NEXT: flt.s a6, s0, a2 +; RV32IZFINX-NEXT: addi a2, a6, -1 +; RV32IZFINX-NEXT: and a0, a2, a0 +; RV32IZFINX-NEXT: flt.s a4, a3, s0 ; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 ; RV32IZFINX-NEXT: lui a3, 524288 -; RV32IZFINX-NEXT: beqz s1, .LBB13_4 +; RV32IZFINX-NEXT: bnez a6, .LBB13_4 ; RV32IZFINX-NEXT: # %bb.3: ; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB13_4: @@ -914,8 +888,6 @@ ; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret ; @@ -960,8 +932,7 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -973,22 +944,21 @@ ; RV32IF-NEXT: fcvt.s.w fa5, a0, rmm ; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0 ; RV32IF-NEXT: .LBB15_2: -; RV32IF-NEXT: fmv.w.x fa5, zero -; RV32IF-NEXT: fle.s a0, fa5, fs0 -; RV32IF-NEXT: neg s0, a0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: fmv.w.x fa5, zero ; RV32IF-NEXT: lui a2, %hi(.LCPI15_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI15_0)(a2) -; RV32IF-NEXT: and a0, s0, a0 -; RV32IF-NEXT: flt.s a2, fa5, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: and a1, s0, a1 -; RV32IF-NEXT: or a1, a2, a1 +; RV32IF-NEXT: flw fa4, %lo(.LCPI15_0)(a2) +; RV32IF-NEXT: flt.s a2, fs0, fa5 +; RV32IF-NEXT: addi a2, a2, -1 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: flt.s a3, fa4, fs0 +; RV32IF-NEXT: neg a3, a3 +; RV32IF-NEXT: or a0, a3, a0 +; RV32IF-NEXT: and a1, a2, a1 +; RV32IF-NEXT: or a1, a3, a1 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -1006,7 +976,6 @@ ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: mv s0, a0 ; RV32IZFINX-NEXT: lui a0, 307200 ; RV32IZFINX-NEXT: fabs.s a1, s0 @@ -1017,21 +986,20 @@ ; RV32IZFINX-NEXT: fcvt.s.w a0, a0, rmm ; RV32IZFINX-NEXT: fsgnj.s s0, a0, s0 ; RV32IZFINX-NEXT: .LBB15_2: -; RV32IZFINX-NEXT: fle.s a0, zero, s0 -; RV32IZFINX-NEXT: neg s1, a0 ; RV32IZFINX-NEXT: mv a0, s0 ; RV32IZFINX-NEXT: call __fixunssfdi@plt ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI15_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI15_0)(a2) -; RV32IZFINX-NEXT: and a0, s1, a0 +; RV32IZFINX-NEXT: flt.s a3, s0, zero +; RV32IZFINX-NEXT: addi a3, a3, -1 +; RV32IZFINX-NEXT: and a0, a3, a0 ; RV32IZFINX-NEXT: flt.s a2, a2, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: or a0, a2, a0 -; RV32IZFINX-NEXT: and a1, s1, a1 +; RV32IZFINX-NEXT: and a1, a3, a1 ; RV32IZFINX-NEXT: or a1, a2, a1 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret ; @@ -1091,12 +1059,12 @@ ; RV32IF-NEXT: .LBB17_2: ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 -; RV32IF-NEXT: fle.s s0, fa5, fs0 +; RV32IF-NEXT: flt.s s0, fs0, fa5 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a2, 524288 -; RV32IF-NEXT: beqz s0, .LBB17_4 +; RV32IF-NEXT: bnez s0, .LBB17_4 ; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB17_4: @@ -1110,8 +1078,8 @@ ; RV32IF-NEXT: feq.s a1, fs0, fs0 ; RV32IF-NEXT: neg a4, a1 ; RV32IF-NEXT: and a1, a4, a2 -; RV32IF-NEXT: neg a2, s0 -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: addi s0, s0, -1 +; RV32IF-NEXT: and a0, s0, a0 ; RV32IF-NEXT: neg a2, a3 ; RV32IF-NEXT: or a0, a2, a0 ; RV32IF-NEXT: and a0, a4, a0 @@ -1135,8 +1103,6 @@ ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: mv s0, a0 ; RV32IZFINX-NEXT: lui a0, 307200 ; RV32IZFINX-NEXT: fabs.s a1, s0 @@ -1147,22 +1113,22 @@ ; RV32IZFINX-NEXT: fcvt.s.w a0, a0, rne ; RV32IZFINX-NEXT: fsgnj.s s0, a0, s0 ; RV32IZFINX-NEXT: .LBB17_2: -; RV32IZFINX-NEXT: lui a0, 913408 -; RV32IZFINX-NEXT: fle.s s1, a0, s0 -; RV32IZFINX-NEXT: neg s2, s1 ; RV32IZFINX-NEXT: mv a0, s0 ; RV32IZFINX-NEXT: call __fixsfdi@plt -; RV32IZFINX-NEXT: lui a2, %hi(.LCPI17_0) -; RV32IZFINX-NEXT: lw a2, %lo(.LCPI17_0)(a2) -; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: lui a2, 913408 +; RV32IZFINX-NEXT: lui a3, %hi(.LCPI17_0) +; RV32IZFINX-NEXT: lw a3, %lo(.LCPI17_0)(a3) +; RV32IZFINX-NEXT: flt.s a6, s0, a2 +; RV32IZFINX-NEXT: addi a2, a6, -1 +; RV32IZFINX-NEXT: and a0, a2, a0 +; RV32IZFINX-NEXT: flt.s a4, a3, s0 ; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 ; RV32IZFINX-NEXT: lui a3, 524288 -; RV32IZFINX-NEXT: beqz s1, .LBB17_4 +; RV32IZFINX-NEXT: bnez a6, .LBB17_4 ; RV32IZFINX-NEXT: # %bb.3: ; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB17_4: @@ -1174,8 +1140,6 @@ ; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret ; @@ -1220,8 +1184,7 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -1233,22 +1196,21 @@ ; RV32IF-NEXT: fcvt.s.w fa5, a0, rne ; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0 ; RV32IF-NEXT: .LBB19_2: -; RV32IF-NEXT: fmv.w.x fa5, zero -; RV32IF-NEXT: fle.s a0, fa5, fs0 -; RV32IF-NEXT: neg s0, a0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixunssfdi@plt +; RV32IF-NEXT: fmv.w.x fa5, zero ; RV32IF-NEXT: lui a2, %hi(.LCPI19_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI19_0)(a2) -; RV32IF-NEXT: and a0, s0, a0 -; RV32IF-NEXT: flt.s a2, fa5, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: and a1, s0, a1 -; RV32IF-NEXT: or a1, a2, a1 +; RV32IF-NEXT: flw fa4, %lo(.LCPI19_0)(a2) +; RV32IF-NEXT: flt.s a2, fs0, fa5 +; RV32IF-NEXT: addi a2, a2, -1 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: flt.s a3, fa4, fs0 +; RV32IF-NEXT: neg a3, a3 +; RV32IF-NEXT: or a0, a3, a0 +; RV32IF-NEXT: and a1, a2, a1 +; RV32IF-NEXT: or a1, a3, a1 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -1266,7 +1228,6 @@ ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: mv s0, a0 ; RV32IZFINX-NEXT: lui a0, 307200 ; RV32IZFINX-NEXT: fabs.s a1, s0 @@ -1277,21 +1238,20 @@ ; RV32IZFINX-NEXT: fcvt.s.w a0, a0, rne ; RV32IZFINX-NEXT: fsgnj.s s0, a0, s0 ; RV32IZFINX-NEXT: .LBB19_2: -; RV32IZFINX-NEXT: fle.s a0, zero, s0 -; RV32IZFINX-NEXT: neg s1, a0 ; RV32IZFINX-NEXT: mv a0, s0 ; RV32IZFINX-NEXT: call __fixunssfdi@plt ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI19_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI19_0)(a2) -; RV32IZFINX-NEXT: and a0, s1, a0 +; RV32IZFINX-NEXT: flt.s a3, s0, zero +; RV32IZFINX-NEXT: addi a3, a3, -1 +; RV32IZFINX-NEXT: and a0, a3, a0 ; RV32IZFINX-NEXT: flt.s a2, a2, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: or a0, a2, a0 -; RV32IZFINX-NEXT: and a1, s1, a1 +; RV32IZFINX-NEXT: and a1, a3, a1 ; RV32IZFINX-NEXT: or a1, a2, a1 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: addi sp, sp, 16 ; RV32IZFINX-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll --- a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll @@ -222,8 +222,8 @@ define float @select_fcmp_ugt(float %a, float %b) nounwind { ; CHECK-LABEL: select_fcmp_ugt: ; CHECK: # %bb.0: -; CHECK-NEXT: fle.s a0, fa0, fa1 -; CHECK-NEXT: beqz a0, .LBB9_2 +; CHECK-NEXT: flt.s a0, fa1, fa0 +; CHECK-NEXT: bnez a0, .LBB9_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: fmv.s fa0, fa1 ; CHECK-NEXT: .LBB9_2: @@ -231,8 +231,8 @@ ; ; CHECKZFINX-LABEL: select_fcmp_ugt: ; CHECKZFINX: # %bb.0: -; CHECKZFINX-NEXT: fle.s a2, a0, a1 -; CHECKZFINX-NEXT: beqz a2, .LBB9_2 +; CHECKZFINX-NEXT: flt.s a2, a1, a0 +; CHECKZFINX-NEXT: bnez a2, .LBB9_2 ; CHECKZFINX-NEXT: # %bb.1: ; CHECKZFINX-NEXT: mv a0, a1 ; CHECKZFINX-NEXT: .LBB9_2: @@ -245,8 +245,8 @@ define float @select_fcmp_uge(float %a, float %b) nounwind { ; CHECK-LABEL: select_fcmp_uge: ; CHECK: # %bb.0: -; CHECK-NEXT: flt.s a0, fa0, fa1 -; CHECK-NEXT: beqz a0, .LBB10_2 +; CHECK-NEXT: fle.s a0, fa1, fa0 +; CHECK-NEXT: bnez a0, .LBB10_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: fmv.s fa0, fa1 ; CHECK-NEXT: .LBB10_2: @@ -254,8 +254,8 @@ ; ; CHECKZFINX-LABEL: select_fcmp_uge: ; CHECKZFINX: # %bb.0: -; CHECKZFINX-NEXT: flt.s a2, a0, a1 -; CHECKZFINX-NEXT: beqz a2, .LBB10_2 +; CHECKZFINX-NEXT: fle.s a2, a1, a0 +; CHECKZFINX-NEXT: bnez a2, .LBB10_2 ; CHECKZFINX-NEXT: # %bb.1: ; CHECKZFINX-NEXT: mv a0, a1 ; CHECKZFINX-NEXT: .LBB10_2: @@ -268,8 +268,8 @@ define float @select_fcmp_ult(float %a, float %b) nounwind { ; CHECK-LABEL: select_fcmp_ult: ; CHECK: # %bb.0: -; CHECK-NEXT: fle.s a0, fa1, fa0 -; CHECK-NEXT: beqz a0, .LBB11_2 +; CHECK-NEXT: flt.s a0, fa0, fa1 +; CHECK-NEXT: bnez a0, .LBB11_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: fmv.s fa0, fa1 ; CHECK-NEXT: .LBB11_2: @@ -277,8 +277,8 @@ ; ; CHECKZFINX-LABEL: select_fcmp_ult: ; CHECKZFINX: # %bb.0: -; CHECKZFINX-NEXT: fle.s a2, a1, a0 -; CHECKZFINX-NEXT: beqz a2, .LBB11_2 +; CHECKZFINX-NEXT: flt.s a2, a0, a1 +; CHECKZFINX-NEXT: bnez a2, .LBB11_2 ; CHECKZFINX-NEXT: # %bb.1: ; CHECKZFINX-NEXT: mv a0, a1 ; CHECKZFINX-NEXT: .LBB11_2: @@ -291,8 +291,8 @@ define float @select_fcmp_ule(float %a, float %b) nounwind { ; CHECK-LABEL: select_fcmp_ule: ; CHECK: # %bb.0: -; CHECK-NEXT: flt.s a0, fa1, fa0 -; CHECK-NEXT: beqz a0, .LBB12_2 +; CHECK-NEXT: fle.s a0, fa0, fa1 +; CHECK-NEXT: bnez a0, .LBB12_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: fmv.s fa0, fa1 ; CHECK-NEXT: .LBB12_2: @@ -300,8 +300,8 @@ ; ; CHECKZFINX-LABEL: select_fcmp_ule: ; CHECKZFINX: # %bb.0: -; CHECKZFINX-NEXT: flt.s a2, a1, a0 -; CHECKZFINX-NEXT: beqz a2, .LBB12_2 +; CHECKZFINX-NEXT: fle.s a2, a0, a1 +; CHECKZFINX-NEXT: bnez a2, .LBB12_2 ; CHECKZFINX-NEXT: # %bb.1: ; CHECKZFINX-NEXT: mv a0, a1 ; CHECKZFINX-NEXT: .LBB12_2: @@ -421,14 +421,14 @@ define signext i32 @select_fcmp_uge_negone_zero(float %a, float %b) nounwind { ; CHECK-LABEL: select_fcmp_uge_negone_zero: ; CHECK: # %bb.0: -; CHECK-NEXT: fle.s a0, fa0, fa1 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: flt.s a0, fa1, fa0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret ; ; CHECKZFINX-LABEL: select_fcmp_uge_negone_zero: ; CHECKZFINX: # %bb.0: -; CHECKZFINX-NEXT: fle.s a0, a0, a1 -; CHECKZFINX-NEXT: addi a0, a0, -1 +; CHECKZFINX-NEXT: flt.s a0, a1, a0 +; CHECKZFINX-NEXT: neg a0, a0 ; CHECKZFINX-NEXT: ret %1 = fcmp ugt float %a, %b %2 = select i1 %1, i32 -1, i32 0 @@ -438,14 +438,16 @@ define signext i32 @select_fcmp_uge_1_2(float %a, float %b) nounwind { ; CHECK-LABEL: select_fcmp_uge_1_2: ; CHECK: # %bb.0: -; CHECK-NEXT: fle.s a0, fa0, fa1 -; CHECK-NEXT: addi a0, a0, 1 +; CHECK-NEXT: flt.s a0, fa1, fa0 +; CHECK-NEXT: li a1, 2 +; CHECK-NEXT: sub a0, a1, a0 ; CHECK-NEXT: ret ; ; CHECKZFINX-LABEL: select_fcmp_uge_1_2: ; CHECKZFINX: # %bb.0: -; CHECKZFINX-NEXT: fle.s a0, a0, a1 -; CHECKZFINX-NEXT: addi a0, a0, 1 +; CHECKZFINX-NEXT: flt.s a0, a1, a0 +; CHECKZFINX-NEXT: li a1, 2 +; CHECKZFINX-NEXT: sub a0, a1, a0 ; CHECKZFINX-NEXT: ret %1 = fcmp ugt float %a, %b %2 = select i1 %1, i32 1, i32 2 diff --git a/llvm/test/CodeGen/RISCV/half-br-fcmp.ll b/llvm/test/CodeGen/RISCV/half-br-fcmp.ll --- a/llvm/test/CodeGen/RISCV/half-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/half-br-fcmp.ll @@ -1116,8 +1116,8 @@ define void @br_fcmp_ugt(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_ugt: ; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: fle.h a0, fa0, fa1 -; RV32IZFH-NEXT: beqz a0, .LBB10_2 +; RV32IZFH-NEXT: flt.h a0, fa1, fa0 +; RV32IZFH-NEXT: bnez a0, .LBB10_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB10_2: # %if.then @@ -1127,8 +1127,8 @@ ; ; RV64IZFH-LABEL: br_fcmp_ugt: ; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: fle.h a0, fa0, fa1 -; RV64IZFH-NEXT: beqz a0, .LBB10_2 +; RV64IZFH-NEXT: flt.h a0, fa1, fa0 +; RV64IZFH-NEXT: bnez a0, .LBB10_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB10_2: # %if.then @@ -1138,8 +1138,8 @@ ; ; RV32IZHINX-LABEL: br_fcmp_ugt: ; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: fle.h a0, a0, a1 -; RV32IZHINX-NEXT: beqz a0, .LBB10_2 +; RV32IZHINX-NEXT: flt.h a0, a1, a0 +; RV32IZHINX-NEXT: bnez a0, .LBB10_2 ; RV32IZHINX-NEXT: # %bb.1: # %if.else ; RV32IZHINX-NEXT: ret ; RV32IZHINX-NEXT: .LBB10_2: # %if.then @@ -1149,8 +1149,8 @@ ; ; RV64IZHINX-LABEL: br_fcmp_ugt: ; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: fle.h a0, a0, a1 -; RV64IZHINX-NEXT: beqz a0, .LBB10_2 +; RV64IZHINX-NEXT: flt.h a0, a1, a0 +; RV64IZHINX-NEXT: bnez a0, .LBB10_2 ; RV64IZHINX-NEXT: # %bb.1: # %if.else ; RV64IZHINX-NEXT: ret ; RV64IZHINX-NEXT: .LBB10_2: # %if.then @@ -1160,10 +1160,10 @@ ; ; RV32IZFHMIN-LABEL: br_fcmp_ugt: ; RV32IZFHMIN: # %bb.0: -; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa1 -; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa0 -; RV32IZFHMIN-NEXT: fle.s a0, fa4, fa5 -; RV32IZFHMIN-NEXT: beqz a0, .LBB10_2 +; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa1 +; RV32IZFHMIN-NEXT: flt.s a0, fa4, fa5 +; RV32IZFHMIN-NEXT: bnez a0, .LBB10_2 ; RV32IZFHMIN-NEXT: # %bb.1: # %if.else ; RV32IZFHMIN-NEXT: ret ; RV32IZFHMIN-NEXT: .LBB10_2: # %if.then @@ -1173,10 +1173,10 @@ ; ; RV64IZFHMIN-LABEL: br_fcmp_ugt: ; RV64IZFHMIN: # %bb.0: -; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1 -; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0 -; RV64IZFHMIN-NEXT: fle.s a0, fa4, fa5 -; RV64IZFHMIN-NEXT: beqz a0, .LBB10_2 +; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa1 +; RV64IZFHMIN-NEXT: flt.s a0, fa4, fa5 +; RV64IZFHMIN-NEXT: bnez a0, .LBB10_2 ; RV64IZFHMIN-NEXT: # %bb.1: # %if.else ; RV64IZFHMIN-NEXT: ret ; RV64IZFHMIN-NEXT: .LBB10_2: # %if.then @@ -1186,10 +1186,10 @@ ; ; RV32IZHINXMIN-LABEL: br_fcmp_ugt: ; RV32IZHINXMIN: # %bb.0: -; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-NEXT: fle.s a0, a0, a1 -; RV32IZHINXMIN-NEXT: beqz a0, .LBB10_2 +; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1 +; RV32IZHINXMIN-NEXT: flt.s a0, a1, a0 +; RV32IZHINXMIN-NEXT: bnez a0, .LBB10_2 ; RV32IZHINXMIN-NEXT: # %bb.1: # %if.else ; RV32IZHINXMIN-NEXT: ret ; RV32IZHINXMIN-NEXT: .LBB10_2: # %if.then @@ -1199,10 +1199,10 @@ ; ; RV64IZHINXMIN-LABEL: br_fcmp_ugt: ; RV64IZHINXMIN: # %bb.0: -; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-NEXT: fle.s a0, a0, a1 -; RV64IZHINXMIN-NEXT: beqz a0, .LBB10_2 +; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1 +; RV64IZHINXMIN-NEXT: flt.s a0, a1, a0 +; RV64IZHINXMIN-NEXT: bnez a0, .LBB10_2 ; RV64IZHINXMIN-NEXT: # %bb.1: # %if.else ; RV64IZHINXMIN-NEXT: ret ; RV64IZHINXMIN-NEXT: .LBB10_2: # %if.then @@ -1221,8 +1221,8 @@ define void @br_fcmp_uge(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_uge: ; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: flt.h a0, fa0, fa1 -; RV32IZFH-NEXT: beqz a0, .LBB11_2 +; RV32IZFH-NEXT: fle.h a0, fa1, fa0 +; RV32IZFH-NEXT: bnez a0, .LBB11_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB11_2: # %if.then @@ -1232,8 +1232,8 @@ ; ; RV64IZFH-LABEL: br_fcmp_uge: ; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: flt.h a0, fa0, fa1 -; RV64IZFH-NEXT: beqz a0, .LBB11_2 +; RV64IZFH-NEXT: fle.h a0, fa1, fa0 +; RV64IZFH-NEXT: bnez a0, .LBB11_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB11_2: # %if.then @@ -1243,8 +1243,8 @@ ; ; RV32IZHINX-LABEL: br_fcmp_uge: ; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: flt.h a0, a0, a1 -; RV32IZHINX-NEXT: beqz a0, .LBB11_2 +; RV32IZHINX-NEXT: fle.h a0, a1, a0 +; RV32IZHINX-NEXT: bnez a0, .LBB11_2 ; RV32IZHINX-NEXT: # %bb.1: # %if.else ; RV32IZHINX-NEXT: ret ; RV32IZHINX-NEXT: .LBB11_2: # %if.then @@ -1254,8 +1254,8 @@ ; ; RV64IZHINX-LABEL: br_fcmp_uge: ; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: flt.h a0, a0, a1 -; RV64IZHINX-NEXT: beqz a0, .LBB11_2 +; RV64IZHINX-NEXT: fle.h a0, a1, a0 +; RV64IZHINX-NEXT: bnez a0, .LBB11_2 ; RV64IZHINX-NEXT: # %bb.1: # %if.else ; RV64IZHINX-NEXT: ret ; RV64IZHINX-NEXT: .LBB11_2: # %if.then @@ -1265,10 +1265,10 @@ ; ; RV32IZFHMIN-LABEL: br_fcmp_uge: ; RV32IZFHMIN: # %bb.0: -; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa1 -; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa0 -; RV32IZFHMIN-NEXT: flt.s a0, fa4, fa5 -; RV32IZFHMIN-NEXT: beqz a0, .LBB11_2 +; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa1 +; RV32IZFHMIN-NEXT: fle.s a0, fa4, fa5 +; RV32IZFHMIN-NEXT: bnez a0, .LBB11_2 ; RV32IZFHMIN-NEXT: # %bb.1: # %if.else ; RV32IZFHMIN-NEXT: ret ; RV32IZFHMIN-NEXT: .LBB11_2: # %if.then @@ -1278,10 +1278,10 @@ ; ; RV64IZFHMIN-LABEL: br_fcmp_uge: ; RV64IZFHMIN: # %bb.0: -; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1 -; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0 -; RV64IZFHMIN-NEXT: flt.s a0, fa4, fa5 -; RV64IZFHMIN-NEXT: beqz a0, .LBB11_2 +; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa1 +; RV64IZFHMIN-NEXT: fle.s a0, fa4, fa5 +; RV64IZFHMIN-NEXT: bnez a0, .LBB11_2 ; RV64IZFHMIN-NEXT: # %bb.1: # %if.else ; RV64IZFHMIN-NEXT: ret ; RV64IZFHMIN-NEXT: .LBB11_2: # %if.then @@ -1291,10 +1291,10 @@ ; ; RV32IZHINXMIN-LABEL: br_fcmp_uge: ; RV32IZHINXMIN: # %bb.0: -; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV32IZHINXMIN-NEXT: flt.s a0, a0, a1 -; RV32IZHINXMIN-NEXT: beqz a0, .LBB11_2 +; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1 +; RV32IZHINXMIN-NEXT: fle.s a0, a1, a0 +; RV32IZHINXMIN-NEXT: bnez a0, .LBB11_2 ; RV32IZHINXMIN-NEXT: # %bb.1: # %if.else ; RV32IZHINXMIN-NEXT: ret ; RV32IZHINXMIN-NEXT: .LBB11_2: # %if.then @@ -1304,10 +1304,10 @@ ; ; RV64IZHINXMIN-LABEL: br_fcmp_uge: ; RV64IZHINXMIN: # %bb.0: -; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; RV64IZHINXMIN-NEXT: flt.s a0, a0, a1 -; RV64IZHINXMIN-NEXT: beqz a0, .LBB11_2 +; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1 +; RV64IZHINXMIN-NEXT: fle.s a0, a1, a0 +; RV64IZHINXMIN-NEXT: bnez a0, .LBB11_2 ; RV64IZHINXMIN-NEXT: # %bb.1: # %if.else ; RV64IZHINXMIN-NEXT: ret ; RV64IZHINXMIN-NEXT: .LBB11_2: # %if.then @@ -1326,8 +1326,8 @@ define void @br_fcmp_ult(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_ult: ; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: fle.h a0, fa1, fa0 -; RV32IZFH-NEXT: beqz a0, .LBB12_2 +; RV32IZFH-NEXT: flt.h a0, fa0, fa1 +; RV32IZFH-NEXT: bnez a0, .LBB12_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB12_2: # %if.then @@ -1337,8 +1337,8 @@ ; ; RV64IZFH-LABEL: br_fcmp_ult: ; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: fle.h a0, fa1, fa0 -; RV64IZFH-NEXT: beqz a0, .LBB12_2 +; RV64IZFH-NEXT: flt.h a0, fa0, fa1 +; RV64IZFH-NEXT: bnez a0, .LBB12_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB12_2: # %if.then @@ -1348,8 +1348,8 @@ ; ; RV32IZHINX-LABEL: br_fcmp_ult: ; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: fle.h a0, a1, a0 -; RV32IZHINX-NEXT: beqz a0, .LBB12_2 +; RV32IZHINX-NEXT: flt.h a0, a0, a1 +; RV32IZHINX-NEXT: bnez a0, .LBB12_2 ; RV32IZHINX-NEXT: # %bb.1: # %if.else ; RV32IZHINX-NEXT: ret ; RV32IZHINX-NEXT: .LBB12_2: # %if.then @@ -1359,8 +1359,8 @@ ; ; RV64IZHINX-LABEL: br_fcmp_ult: ; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: fle.h a0, a1, a0 -; RV64IZHINX-NEXT: beqz a0, .LBB12_2 +; RV64IZHINX-NEXT: flt.h a0, a0, a1 +; RV64IZHINX-NEXT: bnez a0, .LBB12_2 ; RV64IZHINX-NEXT: # %bb.1: # %if.else ; RV64IZHINX-NEXT: ret ; RV64IZHINX-NEXT: .LBB12_2: # %if.then @@ -1370,10 +1370,10 @@ ; ; RV32IZFHMIN-LABEL: br_fcmp_ult: ; RV32IZFHMIN: # %bb.0: -; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 -; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa1 -; RV32IZFHMIN-NEXT: fle.s a0, fa4, fa5 -; RV32IZFHMIN-NEXT: beqz a0, .LBB12_2 +; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa1 +; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa0 +; RV32IZFHMIN-NEXT: flt.s a0, fa4, fa5 +; RV32IZFHMIN-NEXT: bnez a0, .LBB12_2 ; RV32IZFHMIN-NEXT: # %bb.1: # %if.else ; RV32IZFHMIN-NEXT: ret ; RV32IZFHMIN-NEXT: .LBB12_2: # %if.then @@ -1383,10 +1383,10 @@ ; ; RV64IZFHMIN-LABEL: br_fcmp_ult: ; RV64IZFHMIN: # %bb.0: -; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 -; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa1 -; RV64IZFHMIN-NEXT: fle.s a0, fa4, fa5 -; RV64IZFHMIN-NEXT: beqz a0, .LBB12_2 +; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1 +; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0 +; RV64IZFHMIN-NEXT: flt.s a0, fa4, fa5 +; RV64IZFHMIN-NEXT: bnez a0, .LBB12_2 ; RV64IZFHMIN-NEXT: # %bb.1: # %if.else ; RV64IZFHMIN-NEXT: ret ; RV64IZFHMIN-NEXT: .LBB12_2: # %if.then @@ -1396,10 +1396,10 @@ ; ; RV32IZHINXMIN-LABEL: br_fcmp_ult: ; RV32IZHINXMIN: # %bb.0: -; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 ; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1 -; RV32IZHINXMIN-NEXT: fle.s a0, a1, a0 -; RV32IZHINXMIN-NEXT: beqz a0, .LBB12_2 +; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 +; RV32IZHINXMIN-NEXT: flt.s a0, a0, a1 +; RV32IZHINXMIN-NEXT: bnez a0, .LBB12_2 ; RV32IZHINXMIN-NEXT: # %bb.1: # %if.else ; RV32IZHINXMIN-NEXT: ret ; RV32IZHINXMIN-NEXT: .LBB12_2: # %if.then @@ -1409,10 +1409,10 @@ ; ; RV64IZHINXMIN-LABEL: br_fcmp_ult: ; RV64IZHINXMIN: # %bb.0: -; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 ; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1 -; RV64IZHINXMIN-NEXT: fle.s a0, a1, a0 -; RV64IZHINXMIN-NEXT: beqz a0, .LBB12_2 +; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 +; RV64IZHINXMIN-NEXT: flt.s a0, a0, a1 +; RV64IZHINXMIN-NEXT: bnez a0, .LBB12_2 ; RV64IZHINXMIN-NEXT: # %bb.1: # %if.else ; RV64IZHINXMIN-NEXT: ret ; RV64IZHINXMIN-NEXT: .LBB12_2: # %if.then @@ -1431,8 +1431,8 @@ define void @br_fcmp_ule(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_ule: ; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: flt.h a0, fa1, fa0 -; RV32IZFH-NEXT: beqz a0, .LBB13_2 +; RV32IZFH-NEXT: fle.h a0, fa0, fa1 +; RV32IZFH-NEXT: bnez a0, .LBB13_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB13_2: # %if.then @@ -1442,8 +1442,8 @@ ; ; RV64IZFH-LABEL: br_fcmp_ule: ; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: flt.h a0, fa1, fa0 -; RV64IZFH-NEXT: beqz a0, .LBB13_2 +; RV64IZFH-NEXT: fle.h a0, fa0, fa1 +; RV64IZFH-NEXT: bnez a0, .LBB13_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB13_2: # %if.then @@ -1453,8 +1453,8 @@ ; ; RV32IZHINX-LABEL: br_fcmp_ule: ; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: flt.h a0, a1, a0 -; RV32IZHINX-NEXT: beqz a0, .LBB13_2 +; RV32IZHINX-NEXT: fle.h a0, a0, a1 +; RV32IZHINX-NEXT: bnez a0, .LBB13_2 ; RV32IZHINX-NEXT: # %bb.1: # %if.else ; RV32IZHINX-NEXT: ret ; RV32IZHINX-NEXT: .LBB13_2: # %if.then @@ -1464,8 +1464,8 @@ ; ; RV64IZHINX-LABEL: br_fcmp_ule: ; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: flt.h a0, a1, a0 -; RV64IZHINX-NEXT: beqz a0, .LBB13_2 +; RV64IZHINX-NEXT: fle.h a0, a0, a1 +; RV64IZHINX-NEXT: bnez a0, .LBB13_2 ; RV64IZHINX-NEXT: # %bb.1: # %if.else ; RV64IZHINX-NEXT: ret ; RV64IZHINX-NEXT: .LBB13_2: # %if.then @@ -1475,10 +1475,10 @@ ; ; RV32IZFHMIN-LABEL: br_fcmp_ule: ; RV32IZFHMIN: # %bb.0: -; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 -; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa1 -; RV32IZFHMIN-NEXT: flt.s a0, fa4, fa5 -; RV32IZFHMIN-NEXT: beqz a0, .LBB13_2 +; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa1 +; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa0 +; RV32IZFHMIN-NEXT: fle.s a0, fa4, fa5 +; RV32IZFHMIN-NEXT: bnez a0, .LBB13_2 ; RV32IZFHMIN-NEXT: # %bb.1: # %if.else ; RV32IZFHMIN-NEXT: ret ; RV32IZFHMIN-NEXT: .LBB13_2: # %if.then @@ -1488,10 +1488,10 @@ ; ; RV64IZFHMIN-LABEL: br_fcmp_ule: ; RV64IZFHMIN: # %bb.0: -; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 -; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa1 -; RV64IZFHMIN-NEXT: flt.s a0, fa4, fa5 -; RV64IZFHMIN-NEXT: beqz a0, .LBB13_2 +; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1 +; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0 +; RV64IZFHMIN-NEXT: fle.s a0, fa4, fa5 +; RV64IZFHMIN-NEXT: bnez a0, .LBB13_2 ; RV64IZFHMIN-NEXT: # %bb.1: # %if.else ; RV64IZFHMIN-NEXT: ret ; RV64IZFHMIN-NEXT: .LBB13_2: # %if.then @@ -1501,10 +1501,10 @@ ; ; RV32IZHINXMIN-LABEL: br_fcmp_ule: ; RV32IZHINXMIN: # %bb.0: -; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 ; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1 -; RV32IZHINXMIN-NEXT: flt.s a0, a1, a0 -; RV32IZHINXMIN-NEXT: beqz a0, .LBB13_2 +; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 +; RV32IZHINXMIN-NEXT: fle.s a0, a0, a1 +; RV32IZHINXMIN-NEXT: bnez a0, .LBB13_2 ; RV32IZHINXMIN-NEXT: # %bb.1: # %if.else ; RV32IZHINXMIN-NEXT: ret ; RV32IZHINXMIN-NEXT: .LBB13_2: # %if.then @@ -1514,10 +1514,10 @@ ; ; RV64IZHINXMIN-LABEL: br_fcmp_ule: ; RV64IZHINXMIN: # %bb.0: -; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 ; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1 -; RV64IZHINXMIN-NEXT: flt.s a0, a1, a0 -; RV64IZHINXMIN-NEXT: beqz a0, .LBB13_2 +; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 +; RV64IZHINXMIN-NEXT: fle.s a0, a0, a1 +; RV64IZHINXMIN-NEXT: bnez a0, .LBB13_2 ; RV64IZHINXMIN-NEXT: # %bb.1: # %if.else ; RV64IZHINXMIN-NEXT: ret ; RV64IZHINXMIN-NEXT: .LBB13_2: # %if.then diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll --- a/llvm/test/CodeGen/RISCV/half-convert.ll +++ b/llvm/test/CodeGen/RISCV/half-convert.ll @@ -1625,12 +1625,12 @@ ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 -; RV32IZFH-NEXT: fle.s s0, fa5, fs0 +; RV32IZFH-NEXT: flt.s s0, fs0, fa5 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a2, 524288 -; RV32IZFH-NEXT: beqz s0, .LBB10_2 +; RV32IZFH-NEXT: bnez s0, .LBB10_2 ; RV32IZFH-NEXT: # %bb.1: # %start ; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB10_2: # %start @@ -1645,8 +1645,8 @@ ; RV32IZFH-NEXT: neg a4, a1 ; RV32IZFH-NEXT: and a1, a4, a2 ; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: neg a3, s0 -; RV32IZFH-NEXT: and a0, a3, a0 +; RV32IZFH-NEXT: addi s0, s0, -1 +; RV32IZFH-NEXT: and a0, s0, a0 ; RV32IZFH-NEXT: or a0, a2, a0 ; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1673,12 +1673,12 @@ ; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IDZFH-NEXT: lui a0, 913408 ; RV32IDZFH-NEXT: fmv.w.x fa5, a0 -; RV32IDZFH-NEXT: fle.s s0, fa5, fs0 +; RV32IDZFH-NEXT: flt.s s0, fs0, fa5 ; RV32IDZFH-NEXT: fmv.s fa0, fs0 ; RV32IDZFH-NEXT: call __fixsfdi@plt ; RV32IDZFH-NEXT: lui a4, 524288 ; RV32IDZFH-NEXT: lui a2, 524288 -; RV32IDZFH-NEXT: beqz s0, .LBB10_2 +; RV32IDZFH-NEXT: bnez s0, .LBB10_2 ; RV32IDZFH-NEXT: # %bb.1: # %start ; RV32IDZFH-NEXT: mv a2, a1 ; RV32IDZFH-NEXT: .LBB10_2: # %start @@ -1693,8 +1693,8 @@ ; RV32IDZFH-NEXT: neg a4, a1 ; RV32IDZFH-NEXT: and a1, a4, a2 ; RV32IDZFH-NEXT: neg a2, a3 -; RV32IDZFH-NEXT: neg a3, s0 -; RV32IDZFH-NEXT: and a0, a3, a0 +; RV32IDZFH-NEXT: addi s0, s0, -1 +; RV32IDZFH-NEXT: and a0, s0, a0 ; RV32IDZFH-NEXT: or a0, a2, a0 ; RV32IDZFH-NEXT: and a0, a4, a0 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1727,8 +1727,8 @@ ; RV32IZHINX-NEXT: flt.s s1, a1, s0 ; RV32IZHINX-NEXT: neg s2, s1 ; RV32IZHINX-NEXT: lui a0, 913408 -; RV32IZHINX-NEXT: fle.s s3, a0, s0 -; RV32IZHINX-NEXT: neg s4, s3 +; RV32IZHINX-NEXT: flt.s s3, s0, a0 +; RV32IZHINX-NEXT: addi s4, s3, -1 ; RV32IZHINX-NEXT: mv a0, s0 ; RV32IZHINX-NEXT: call __fixsfdi@plt ; RV32IZHINX-NEXT: and a0, s4, a0 @@ -1737,7 +1737,7 @@ ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a4, 524288 ; RV32IZHINX-NEXT: lui a3, 524288 -; RV32IZHINX-NEXT: beqz s3, .LBB10_2 +; RV32IZHINX-NEXT: bnez s3, .LBB10_2 ; RV32IZHINX-NEXT: # %bb.1: # %start ; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB10_2: # %start @@ -1780,8 +1780,8 @@ ; RV32IZDINXZHINX-NEXT: flt.s s1, a1, s0 ; RV32IZDINXZHINX-NEXT: neg s2, s1 ; RV32IZDINXZHINX-NEXT: lui a0, 913408 -; RV32IZDINXZHINX-NEXT: fle.s s3, a0, s0 -; RV32IZDINXZHINX-NEXT: neg s4, s3 +; RV32IZDINXZHINX-NEXT: flt.s s3, s0, a0 +; RV32IZDINXZHINX-NEXT: addi s4, s3, -1 ; RV32IZDINXZHINX-NEXT: mv a0, s0 ; RV32IZDINXZHINX-NEXT: call __fixsfdi@plt ; RV32IZDINXZHINX-NEXT: and a0, s4, a0 @@ -1790,7 +1790,7 @@ ; RV32IZDINXZHINX-NEXT: neg a2, a2 ; RV32IZDINXZHINX-NEXT: lui a4, 524288 ; RV32IZDINXZHINX-NEXT: lui a3, 524288 -; RV32IZDINXZHINX-NEXT: beqz s3, .LBB10_2 +; RV32IZDINXZHINX-NEXT: bnez s3, .LBB10_2 ; RV32IZDINXZHINX-NEXT: # %bb.1: # %start ; RV32IZDINXZHINX-NEXT: mv a3, a1 ; RV32IZDINXZHINX-NEXT: .LBB10_2: # %start @@ -1928,12 +1928,12 @@ ; RV32IFZFHMIN-NEXT: fcvt.s.h fs0, fa0 ; RV32IFZFHMIN-NEXT: lui a0, 913408 ; RV32IFZFHMIN-NEXT: fmv.w.x fa5, a0 -; RV32IFZFHMIN-NEXT: fle.s s0, fa5, fs0 +; RV32IFZFHMIN-NEXT: flt.s s0, fs0, fa5 ; RV32IFZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IFZFHMIN-NEXT: call __fixsfdi@plt ; RV32IFZFHMIN-NEXT: lui a4, 524288 ; RV32IFZFHMIN-NEXT: lui a2, 524288 -; RV32IFZFHMIN-NEXT: beqz s0, .LBB10_2 +; RV32IFZFHMIN-NEXT: bnez s0, .LBB10_2 ; RV32IFZFHMIN-NEXT: # %bb.1: # %start ; RV32IFZFHMIN-NEXT: mv a2, a1 ; RV32IFZFHMIN-NEXT: .LBB10_2: # %start @@ -1948,8 +1948,8 @@ ; RV32IFZFHMIN-NEXT: neg a4, a1 ; RV32IFZFHMIN-NEXT: and a1, a4, a2 ; RV32IFZFHMIN-NEXT: neg a2, a3 -; RV32IFZFHMIN-NEXT: neg a3, s0 -; RV32IFZFHMIN-NEXT: and a0, a3, a0 +; RV32IFZFHMIN-NEXT: addi s0, s0, -1 +; RV32IFZFHMIN-NEXT: and a0, s0, a0 ; RV32IFZFHMIN-NEXT: or a0, a2, a0 ; RV32IFZFHMIN-NEXT: and a0, a4, a0 ; RV32IFZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1977,12 +1977,12 @@ ; RV32IDZFHMIN-NEXT: fcvt.s.h fs0, fa0 ; RV32IDZFHMIN-NEXT: lui a0, 913408 ; RV32IDZFHMIN-NEXT: fmv.w.x fa5, a0 -; RV32IDZFHMIN-NEXT: fle.s s0, fa5, fs0 +; RV32IDZFHMIN-NEXT: flt.s s0, fs0, fa5 ; RV32IDZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IDZFHMIN-NEXT: call __fixsfdi@plt ; RV32IDZFHMIN-NEXT: lui a4, 524288 ; RV32IDZFHMIN-NEXT: lui a2, 524288 -; RV32IDZFHMIN-NEXT: beqz s0, .LBB10_2 +; RV32IDZFHMIN-NEXT: bnez s0, .LBB10_2 ; RV32IDZFHMIN-NEXT: # %bb.1: # %start ; RV32IDZFHMIN-NEXT: mv a2, a1 ; RV32IDZFHMIN-NEXT: .LBB10_2: # %start @@ -1997,8 +1997,8 @@ ; RV32IDZFHMIN-NEXT: neg a4, a1 ; RV32IDZFHMIN-NEXT: and a1, a4, a2 ; RV32IDZFHMIN-NEXT: neg a2, a3 -; RV32IDZFHMIN-NEXT: neg a3, s0 -; RV32IDZFHMIN-NEXT: and a0, a3, a0 +; RV32IDZFHMIN-NEXT: addi s0, s0, -1 +; RV32IDZFHMIN-NEXT: and a0, s0, a0 ; RV32IDZFHMIN-NEXT: or a0, a2, a0 ; RV32IDZFHMIN-NEXT: and a0, a4, a0 ; RV32IDZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -2022,8 +2022,8 @@ ; CHECK32-IZHINXMIN-NEXT: flt.s s1, a1, s0 ; CHECK32-IZHINXMIN-NEXT: neg s2, s1 ; CHECK32-IZHINXMIN-NEXT: lui a0, 913408 -; CHECK32-IZHINXMIN-NEXT: fle.s s3, a0, s0 -; CHECK32-IZHINXMIN-NEXT: neg s4, s3 +; CHECK32-IZHINXMIN-NEXT: flt.s s3, s0, a0 +; CHECK32-IZHINXMIN-NEXT: addi s4, s3, -1 ; CHECK32-IZHINXMIN-NEXT: mv a0, s0 ; CHECK32-IZHINXMIN-NEXT: call __fixsfdi@plt ; CHECK32-IZHINXMIN-NEXT: and a0, s4, a0 @@ -2032,7 +2032,7 @@ ; CHECK32-IZHINXMIN-NEXT: neg a2, a2 ; CHECK32-IZHINXMIN-NEXT: lui a4, 524288 ; CHECK32-IZHINXMIN-NEXT: lui a3, 524288 -; CHECK32-IZHINXMIN-NEXT: beqz s3, .LBB10_2 +; CHECK32-IZHINXMIN-NEXT: bnez s3, .LBB10_2 ; CHECK32-IZHINXMIN-NEXT: # %bb.1: # %start ; CHECK32-IZHINXMIN-NEXT: mv a3, a1 ; CHECK32-IZHINXMIN-NEXT: .LBB10_2: # %start @@ -2076,8 +2076,8 @@ ; CHECK32-IZDINXZHINXMIN-NEXT: flt.s s1, a1, s0 ; CHECK32-IZDINXZHINXMIN-NEXT: neg s2, s1 ; CHECK32-IZDINXZHINXMIN-NEXT: lui a0, 913408 -; CHECK32-IZDINXZHINXMIN-NEXT: fle.s s3, a0, s0 -; CHECK32-IZDINXZHINXMIN-NEXT: neg s4, s3 +; CHECK32-IZDINXZHINXMIN-NEXT: flt.s s3, s0, a0 +; CHECK32-IZDINXZHINXMIN-NEXT: addi s4, s3, -1 ; CHECK32-IZDINXZHINXMIN-NEXT: mv a0, s0 ; CHECK32-IZDINXZHINXMIN-NEXT: call __fixsfdi@plt ; CHECK32-IZDINXZHINXMIN-NEXT: and a0, s4, a0 @@ -2086,7 +2086,7 @@ ; CHECK32-IZDINXZHINXMIN-NEXT: neg a2, a2 ; CHECK32-IZDINXZHINXMIN-NEXT: lui a4, 524288 ; CHECK32-IZDINXZHINXMIN-NEXT: lui a3, 524288 -; CHECK32-IZDINXZHINXMIN-NEXT: beqz s3, .LBB10_2 +; CHECK32-IZDINXZHINXMIN-NEXT: bnez s3, .LBB10_2 ; CHECK32-IZDINXZHINXMIN-NEXT: # %bb.1: # %start ; CHECK32-IZDINXZHINXMIN-NEXT: mv a3, a1 ; CHECK32-IZDINXZHINXMIN-NEXT: .LBB10_2: # %start @@ -2262,8 +2262,8 @@ ; RV32IZFH-NEXT: flt.s a0, fa5, fa0 ; RV32IZFH-NEXT: neg s0, a0 ; RV32IZFH-NEXT: fmv.w.x fa5, zero -; RV32IZFH-NEXT: fle.s a0, fa5, fa0 -; RV32IZFH-NEXT: neg s1, a0 +; RV32IZFH-NEXT: flt.s a0, fa0, fa5 +; RV32IZFH-NEXT: addi s1, a0, -1 ; RV32IZFH-NEXT: call __fixunssfdi@plt ; RV32IZFH-NEXT: and a0, s1, a0 ; RV32IZFH-NEXT: or a0, s0, a0 @@ -2296,8 +2296,8 @@ ; RV32IDZFH-NEXT: flt.s a0, fa5, fa0 ; RV32IDZFH-NEXT: neg s0, a0 ; RV32IDZFH-NEXT: fmv.w.x fa5, zero -; RV32IDZFH-NEXT: fle.s a0, fa5, fa0 -; RV32IDZFH-NEXT: neg s1, a0 +; RV32IDZFH-NEXT: flt.s a0, fa0, fa5 +; RV32IDZFH-NEXT: addi s1, a0, -1 ; RV32IDZFH-NEXT: call __fixunssfdi@plt ; RV32IDZFH-NEXT: and a0, s1, a0 ; RV32IDZFH-NEXT: or a0, s0, a0 @@ -2329,8 +2329,8 @@ ; RV32IZHINX-NEXT: fcvt.s.h a0, a0 ; RV32IZHINX-NEXT: flt.s a1, a1, a0 ; RV32IZHINX-NEXT: neg s0, a1 -; RV32IZHINX-NEXT: fle.s a1, zero, a0 -; RV32IZHINX-NEXT: neg s1, a1 +; RV32IZHINX-NEXT: flt.s a1, a0, zero +; RV32IZHINX-NEXT: addi s1, a1, -1 ; RV32IZHINX-NEXT: call __fixunssfdi@plt ; RV32IZHINX-NEXT: and a0, s1, a0 ; RV32IZHINX-NEXT: or a0, s0, a0 @@ -2362,8 +2362,8 @@ ; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 ; RV32IZDINXZHINX-NEXT: flt.s a1, a1, a0 ; RV32IZDINXZHINX-NEXT: neg s0, a1 -; RV32IZDINXZHINX-NEXT: fle.s a1, zero, a0 -; RV32IZDINXZHINX-NEXT: neg s1, a1 +; RV32IZDINXZHINX-NEXT: flt.s a1, a0, zero +; RV32IZDINXZHINX-NEXT: addi s1, a1, -1 ; RV32IZDINXZHINX-NEXT: call __fixunssfdi@plt ; RV32IZDINXZHINX-NEXT: and a0, s1, a0 ; RV32IZDINXZHINX-NEXT: or a0, s0, a0 @@ -2460,8 +2460,8 @@ ; CHECK32-IZFHMIN-NEXT: flt.s a0, fa5, fa0 ; CHECK32-IZFHMIN-NEXT: neg s0, a0 ; CHECK32-IZFHMIN-NEXT: fmv.w.x fa5, zero -; CHECK32-IZFHMIN-NEXT: fle.s a0, fa5, fa0 -; CHECK32-IZFHMIN-NEXT: neg s1, a0 +; CHECK32-IZFHMIN-NEXT: flt.s a0, fa0, fa5 +; CHECK32-IZFHMIN-NEXT: addi s1, a0, -1 ; CHECK32-IZFHMIN-NEXT: call __fixunssfdi@plt ; CHECK32-IZFHMIN-NEXT: and a0, s1, a0 ; CHECK32-IZFHMIN-NEXT: or a0, s0, a0 @@ -2494,8 +2494,8 @@ ; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0 ; CHECK32-IZHINXMIN-NEXT: flt.s a1, a1, a0 ; CHECK32-IZHINXMIN-NEXT: neg s0, a1 -; CHECK32-IZHINXMIN-NEXT: fle.s a1, zero, a0 -; CHECK32-IZHINXMIN-NEXT: neg s1, a1 +; CHECK32-IZHINXMIN-NEXT: flt.s a1, a0, zero +; CHECK32-IZHINXMIN-NEXT: addi s1, a1, -1 ; CHECK32-IZHINXMIN-NEXT: call __fixunssfdi@plt ; CHECK32-IZHINXMIN-NEXT: and a0, s1, a0 ; CHECK32-IZHINXMIN-NEXT: or a0, s0, a0 @@ -2528,8 +2528,8 @@ ; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 ; CHECK32-IZDINXZHINXMIN-NEXT: flt.s a1, a1, a0 ; CHECK32-IZDINXZHINXMIN-NEXT: neg s0, a1 -; CHECK32-IZDINXZHINXMIN-NEXT: fle.s a1, zero, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: neg s1, a1 +; CHECK32-IZDINXZHINXMIN-NEXT: flt.s a1, a0, zero +; CHECK32-IZDINXZHINXMIN-NEXT: addi s1, a1, -1 ; CHECK32-IZDINXZHINXMIN-NEXT: call __fixunssfdi@plt ; CHECK32-IZDINXZHINXMIN-NEXT: and a0, s1, a0 ; CHECK32-IZDINXZHINXMIN-NEXT: or a0, s0, a0 diff --git a/llvm/test/CodeGen/RISCV/half-fcmp.ll b/llvm/test/CodeGen/RISCV/half-fcmp.ll --- a/llvm/test/CodeGen/RISCV/half-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/half-fcmp.ll @@ -532,56 +532,49 @@ define i32 @fcmp_ugt(half %a, half %b) nounwind { ; CHECKIZFH-LABEL: fcmp_ugt: ; CHECKIZFH: # %bb.0: -; CHECKIZFH-NEXT: fle.h a0, fa0, fa1 -; CHECKIZFH-NEXT: xori a0, a0, 1 +; CHECKIZFH-NEXT: flt.h a0, fa1, fa0 ; CHECKIZFH-NEXT: ret ; ; CHECKIZHINX-LABEL: fcmp_ugt: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: fle.h a0, a0, a1 -; CHECKIZHINX-NEXT: xori a0, a0, 1 +; CHECKIZHINX-NEXT: flt.h a0, a1, a0 ; CHECKIZHINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ugt: ; RV32I: # %bb.0: -; RV32I-NEXT: fmv.h.x fa5, a1 -; RV32I-NEXT: fmv.h.x fa4, a0 -; RV32I-NEXT: fle.h a0, fa4, fa5 -; RV32I-NEXT: xori a0, a0, 1 +; RV32I-NEXT: fmv.h.x fa5, a0 +; RV32I-NEXT: fmv.h.x fa4, a1 +; RV32I-NEXT: flt.h a0, fa4, fa5 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fcmp_ugt: ; RV64I: # %bb.0: -; RV64I-NEXT: fmv.h.x fa5, a1 -; RV64I-NEXT: fmv.h.x fa4, a0 -; RV64I-NEXT: fle.h a0, fa4, fa5 -; RV64I-NEXT: xori a0, a0, 1 +; RV64I-NEXT: fmv.h.x fa5, a0 +; RV64I-NEXT: fmv.h.x fa4, a1 +; RV64I-NEXT: flt.h a0, fa4, fa5 ; RV64I-NEXT: ret ; ; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ugt: ; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: -; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1 -; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0 -; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fle.s a0, fa4, fa5 -; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1 +; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa0 +; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa1 +; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a0, fa4, fa5 ; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret ; ; CHECKIZFHMIN-LABEL: fcmp_ugt: ; CHECKIZFHMIN: # %bb.0: -; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0 -; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1 +; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a1 +; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a0 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 -; CHECKIZFHMIN-NEXT: fle.s a0, fa5, fa4 -; CHECKIZFHMIN-NEXT: xori a0, a0, 1 +; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4 ; CHECKIZFHMIN-NEXT: ret ; ; CHECKIZHINXMIN-LABEL: fcmp_ugt: ; CHECKIZHINXMIN: # %bb.0: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECKIZHINXMIN-NEXT: fle.s a0, a0, a1 -; CHECKIZHINXMIN-NEXT: xori a0, a0, 1 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 +; CHECKIZHINXMIN-NEXT: flt.s a0, a1, a0 ; CHECKIZHINXMIN-NEXT: ret %1 = fcmp ugt half %a, %b %2 = zext i1 %1 to i32 @@ -591,56 +584,49 @@ define i32 @fcmp_uge(half %a, half %b) nounwind { ; CHECKIZFH-LABEL: fcmp_uge: ; CHECKIZFH: # %bb.0: -; CHECKIZFH-NEXT: flt.h a0, fa0, fa1 -; CHECKIZFH-NEXT: xori a0, a0, 1 +; CHECKIZFH-NEXT: fle.h a0, fa1, fa0 ; CHECKIZFH-NEXT: ret ; ; CHECKIZHINX-LABEL: fcmp_uge: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: flt.h a0, a0, a1 -; CHECKIZHINX-NEXT: xori a0, a0, 1 +; CHECKIZHINX-NEXT: fle.h a0, a1, a0 ; CHECKIZHINX-NEXT: ret ; ; RV32I-LABEL: fcmp_uge: ; RV32I: # %bb.0: -; RV32I-NEXT: fmv.h.x fa5, a1 -; RV32I-NEXT: fmv.h.x fa4, a0 -; RV32I-NEXT: flt.h a0, fa4, fa5 -; RV32I-NEXT: xori a0, a0, 1 +; RV32I-NEXT: fmv.h.x fa5, a0 +; RV32I-NEXT: fmv.h.x fa4, a1 +; RV32I-NEXT: fle.h a0, fa4, fa5 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fcmp_uge: ; RV64I: # %bb.0: -; RV64I-NEXT: fmv.h.x fa5, a1 -; RV64I-NEXT: fmv.h.x fa4, a0 -; RV64I-NEXT: flt.h a0, fa4, fa5 -; RV64I-NEXT: xori a0, a0, 1 +; RV64I-NEXT: fmv.h.x fa5, a0 +; RV64I-NEXT: fmv.h.x fa4, a1 +; RV64I-NEXT: fle.h a0, fa4, fa5 ; RV64I-NEXT: ret ; ; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_uge: ; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: -; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1 -; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0 -; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a0, fa4, fa5 -; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1 +; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa0 +; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa1 +; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fle.s a0, fa4, fa5 ; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret ; ; CHECKIZFHMIN-LABEL: fcmp_uge: ; CHECKIZFHMIN: # %bb.0: -; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0 -; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1 +; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a1 +; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a0 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 -; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4 -; CHECKIZFHMIN-NEXT: xori a0, a0, 1 +; CHECKIZFHMIN-NEXT: fle.s a0, fa5, fa4 ; CHECKIZFHMIN-NEXT: ret ; ; CHECKIZHINXMIN-LABEL: fcmp_uge: ; CHECKIZHINXMIN: # %bb.0: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECKIZHINXMIN-NEXT: flt.s a0, a0, a1 -; CHECKIZHINXMIN-NEXT: xori a0, a0, 1 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 +; CHECKIZHINXMIN-NEXT: fle.s a0, a1, a0 ; CHECKIZHINXMIN-NEXT: ret %1 = fcmp uge half %a, %b %2 = zext i1 %1 to i32 @@ -650,56 +636,49 @@ define i32 @fcmp_ult(half %a, half %b) nounwind { ; CHECKIZFH-LABEL: fcmp_ult: ; CHECKIZFH: # %bb.0: -; CHECKIZFH-NEXT: fle.h a0, fa1, fa0 -; CHECKIZFH-NEXT: xori a0, a0, 1 +; CHECKIZFH-NEXT: flt.h a0, fa0, fa1 ; CHECKIZFH-NEXT: ret ; ; CHECKIZHINX-LABEL: fcmp_ult: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: fle.h a0, a1, a0 -; CHECKIZHINX-NEXT: xori a0, a0, 1 +; CHECKIZHINX-NEXT: flt.h a0, a0, a1 ; CHECKIZHINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ult: ; RV32I: # %bb.0: -; RV32I-NEXT: fmv.h.x fa5, a0 -; RV32I-NEXT: fmv.h.x fa4, a1 -; RV32I-NEXT: fle.h a0, fa4, fa5 -; RV32I-NEXT: xori a0, a0, 1 +; RV32I-NEXT: fmv.h.x fa5, a1 +; RV32I-NEXT: fmv.h.x fa4, a0 +; RV32I-NEXT: flt.h a0, fa4, fa5 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fcmp_ult: ; RV64I: # %bb.0: -; RV64I-NEXT: fmv.h.x fa5, a0 -; RV64I-NEXT: fmv.h.x fa4, a1 -; RV64I-NEXT: fle.h a0, fa4, fa5 -; RV64I-NEXT: xori a0, a0, 1 +; RV64I-NEXT: fmv.h.x fa5, a1 +; RV64I-NEXT: fmv.h.x fa4, a0 +; RV64I-NEXT: flt.h a0, fa4, fa5 ; RV64I-NEXT: ret ; ; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ult: ; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: -; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa0 -; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa1 -; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fle.s a0, fa4, fa5 -; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1 +; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1 +; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0 +; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a0, fa4, fa5 ; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret ; ; CHECKIZFHMIN-LABEL: fcmp_ult: ; CHECKIZFHMIN: # %bb.0: -; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a1 -; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a0 +; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0 +; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 -; CHECKIZFHMIN-NEXT: fle.s a0, fa5, fa4 -; CHECKIZFHMIN-NEXT: xori a0, a0, 1 +; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4 ; CHECKIZFHMIN-NEXT: ret ; ; CHECKIZHINXMIN-LABEL: fcmp_ult: ; CHECKIZHINXMIN: # %bb.0: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 -; CHECKIZHINXMIN-NEXT: fle.s a0, a1, a0 -; CHECKIZHINXMIN-NEXT: xori a0, a0, 1 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 +; CHECKIZHINXMIN-NEXT: flt.s a0, a0, a1 ; CHECKIZHINXMIN-NEXT: ret %1 = fcmp ult half %a, %b %2 = zext i1 %1 to i32 @@ -709,56 +688,49 @@ define i32 @fcmp_ule(half %a, half %b) nounwind { ; CHECKIZFH-LABEL: fcmp_ule: ; CHECKIZFH: # %bb.0: -; CHECKIZFH-NEXT: flt.h a0, fa1, fa0 -; CHECKIZFH-NEXT: xori a0, a0, 1 +; CHECKIZFH-NEXT: fle.h a0, fa0, fa1 ; CHECKIZFH-NEXT: ret ; ; CHECKIZHINX-LABEL: fcmp_ule: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: flt.h a0, a1, a0 -; CHECKIZHINX-NEXT: xori a0, a0, 1 +; CHECKIZHINX-NEXT: fle.h a0, a0, a1 ; CHECKIZHINX-NEXT: ret ; ; RV32I-LABEL: fcmp_ule: ; RV32I: # %bb.0: -; RV32I-NEXT: fmv.h.x fa5, a0 -; RV32I-NEXT: fmv.h.x fa4, a1 -; RV32I-NEXT: flt.h a0, fa4, fa5 -; RV32I-NEXT: xori a0, a0, 1 +; RV32I-NEXT: fmv.h.x fa5, a1 +; RV32I-NEXT: fmv.h.x fa4, a0 +; RV32I-NEXT: fle.h a0, fa4, fa5 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fcmp_ule: ; RV64I: # %bb.0: -; RV64I-NEXT: fmv.h.x fa5, a0 -; RV64I-NEXT: fmv.h.x fa4, a1 -; RV64I-NEXT: flt.h a0, fa4, fa5 -; RV64I-NEXT: xori a0, a0, 1 +; RV64I-NEXT: fmv.h.x fa5, a1 +; RV64I-NEXT: fmv.h.x fa4, a0 +; RV64I-NEXT: fle.h a0, fa4, fa5 ; RV64I-NEXT: ret ; ; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ule: ; CHECKIZFHMIN-ILP32F-LP64F: # %bb.0: -; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa0 -; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa1 -; CHECKIZFHMIN-ILP32F-LP64F-NEXT: flt.s a0, fa4, fa5 -; CHECKIZFHMIN-ILP32F-LP64F-NEXT: xori a0, a0, 1 +; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa5, fa1 +; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fcvt.s.h fa4, fa0 +; CHECKIZFHMIN-ILP32F-LP64F-NEXT: fle.s a0, fa4, fa5 ; CHECKIZFHMIN-ILP32F-LP64F-NEXT: ret ; ; CHECKIZFHMIN-LABEL: fcmp_ule: ; CHECKIZFHMIN: # %bb.0: -; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a1 -; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a0 +; CHECKIZFHMIN-NEXT: fmv.h.x fa5, a0 +; CHECKIZFHMIN-NEXT: fmv.h.x fa4, a1 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa4 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5 -; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4 -; CHECKIZFHMIN-NEXT: xori a0, a0, 1 +; CHECKIZFHMIN-NEXT: fle.s a0, fa5, fa4 ; CHECKIZFHMIN-NEXT: ret ; ; CHECKIZHINXMIN-LABEL: fcmp_ule: ; CHECKIZHINXMIN: # %bb.0: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 -; CHECKIZHINXMIN-NEXT: flt.s a0, a1, a0 -; CHECKIZHINXMIN-NEXT: xori a0, a0, 1 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 +; CHECKIZHINXMIN-NEXT: fle.s a0, a0, a1 ; CHECKIZHINXMIN-NEXT: ret %1 = fcmp ule half %a, %b %2 = zext i1 %1 to i32 diff --git a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll --- a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll @@ -112,12 +112,12 @@ ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 -; RV32IZFH-NEXT: fle.s s0, fa5, fs0 +; RV32IZFH-NEXT: flt.s s0, fs0, fa5 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a2, 524288 -; RV32IZFH-NEXT: beqz s0, .LBB1_4 +; RV32IZFH-NEXT: bnez s0, .LBB1_4 ; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB1_4: @@ -131,8 +131,8 @@ ; RV32IZFH-NEXT: feq.s a1, fs0, fs0 ; RV32IZFH-NEXT: neg a4, a1 ; RV32IZFH-NEXT: and a1, a4, a2 -; RV32IZFH-NEXT: neg a2, s0 -; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: addi s0, s0, -1 +; RV32IZFH-NEXT: and a0, s0, a0 ; RV32IZFH-NEXT: neg a2, a3 ; RV32IZFH-NEXT: or a0, a2, a0 ; RV32IZFH-NEXT: and a0, a4, a0 @@ -156,8 +156,6 @@ ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI1_0) ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI1_0)(a1) ; RV32IZHINX-NEXT: fabs.h a2, a0 @@ -169,22 +167,22 @@ ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 ; RV32IZHINX-NEXT: .LBB1_2: ; RV32IZHINX-NEXT: fcvt.s.h s0, a0 -; RV32IZHINX-NEXT: lui a0, 913408 -; RV32IZHINX-NEXT: fle.s s1, a0, s0 -; RV32IZHINX-NEXT: neg s2, s1 ; RV32IZHINX-NEXT: mv a0, s0 ; RV32IZHINX-NEXT: call __fixsfdi@plt -; RV32IZHINX-NEXT: lui a2, %hi(.LCPI1_1) -; RV32IZHINX-NEXT: lw a2, %lo(.LCPI1_1)(a2) -; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: lui a2, 913408 +; RV32IZHINX-NEXT: lui a3, %hi(.LCPI1_1) +; RV32IZHINX-NEXT: lw a3, %lo(.LCPI1_1)(a3) +; RV32IZHINX-NEXT: flt.s a6, s0, a2 +; RV32IZHINX-NEXT: addi a2, a6, -1 +; RV32IZHINX-NEXT: and a0, a2, a0 +; RV32IZHINX-NEXT: flt.s a4, a3, s0 ; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 ; RV32IZHINX-NEXT: lui a3, 524288 -; RV32IZHINX-NEXT: beqz s1, .LBB1_4 +; RV32IZHINX-NEXT: bnez a6, .LBB1_4 ; RV32IZHINX-NEXT: # %bb.3: ; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB1_4: @@ -196,8 +194,6 @@ ; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret ; @@ -241,12 +237,12 @@ ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 -; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 +; RV32IZFHMIN-NEXT: flt.s s0, fs0, fa5 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi@plt ; RV32IZFHMIN-NEXT: lui a4, 524288 ; RV32IZFHMIN-NEXT: lui a2, 524288 -; RV32IZFHMIN-NEXT: beqz s0, .LBB1_4 +; RV32IZFHMIN-NEXT: bnez s0, .LBB1_4 ; RV32IZFHMIN-NEXT: # %bb.3: ; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB1_4: @@ -260,8 +256,8 @@ ; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 ; RV32IZFHMIN-NEXT: neg a4, a1 ; RV32IZFHMIN-NEXT: and a1, a4, a2 -; RV32IZFHMIN-NEXT: neg a2, s0 -; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: addi s0, s0, -1 +; RV32IZFHMIN-NEXT: and a0, s0, a0 ; RV32IZFHMIN-NEXT: neg a2, a3 ; RV32IZFHMIN-NEXT: or a0, a2, a0 ; RV32IZFHMIN-NEXT: and a0, a4, a0 @@ -308,39 +304,39 @@ ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 -; RV32IZHINXMIN-NEXT: lui a0, 913408 -; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 -; RV32IZHINXMIN-NEXT: neg s2, s1 ; RV32IZHINXMIN-NEXT: mv a0, s0 ; RV32IZHINXMIN-NEXT: call __fixsfdi@plt -; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI1_0) -; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI1_0)(a2) -; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: lui a2, 913408 +; RV32IZHINXMIN-NEXT: lui a3, %hi(.LCPI1_0) +; RV32IZHINXMIN-NEXT: lw a3, %lo(.LCPI1_0)(a3) +; RV32IZHINXMIN-NEXT: flt.s a6, s0, a2 +; RV32IZHINXMIN-NEXT: addi a2, a6, -1 +; RV32IZHINXMIN-NEXT: and a0, a2, a0 +; RV32IZHINXMIN-NEXT: flt.s a4, a3, s0 ; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 ; RV32IZHINXMIN-NEXT: lui a3, 524288 -; RV32IZHINXMIN-NEXT: beqz s1, .LBB1_4 -; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a3, a1 -; RV32IZHINXMIN-NEXT: .LBB1_4: -; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a4, .LBB1_6 -; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a3, a5, -1 +; RV32IZHINXMIN-NEXT: beqz a6, .LBB1_5 +; RV32IZHINXMIN-NEXT: # %bb.3: +; RV32IZHINXMIN-NEXT: and a0, a2, a0 +; RV32IZHINXMIN-NEXT: bnez a4, .LBB1_6 +; RV32IZHINXMIN-NEXT: .LBB1_4: +; RV32IZHINXMIN-NEXT: and a1, a2, a3 +; RV32IZHINXMIN-NEXT: ret +; RV32IZHINXMIN-NEXT: .LBB1_5: +; RV32IZHINXMIN-NEXT: mv a3, a1 +; RV32IZHINXMIN-NEXT: and a0, a2, a0 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB1_4 ; RV32IZHINXMIN-NEXT: .LBB1_6: +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; @@ -512,8 +508,7 @@ ; RV32IZFH: # %bb.0: ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: lui a0, %hi(.LCPI3_0) ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI3_0)(a0) ; RV32IZFH-NEXT: fabs.h fa4, fa0 @@ -525,22 +520,21 @@ ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 ; RV32IZFH-NEXT: .LBB3_2: ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 -; RV32IZFH-NEXT: fmv.w.x fa5, zero -; RV32IZFH-NEXT: fle.s a0, fa5, fs0 -; RV32IZFH-NEXT: neg s0, a0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixunssfdi@plt +; RV32IZFH-NEXT: fmv.w.x fa5, zero ; RV32IZFH-NEXT: lui a2, %hi(.LCPI3_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI3_1)(a2) -; RV32IZFH-NEXT: and a0, s0, a0 -; RV32IZFH-NEXT: flt.s a2, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: and a1, s0, a1 -; RV32IZFH-NEXT: or a1, a2, a1 +; RV32IZFH-NEXT: flw fa4, %lo(.LCPI3_1)(a2) +; RV32IZFH-NEXT: flt.s a2, fs0, fa5 +; RV32IZFH-NEXT: addi a2, a2, -1 +; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: flt.s a3, fa4, fs0 +; RV32IZFH-NEXT: neg a3, a3 +; RV32IZFH-NEXT: or a0, a3, a0 +; RV32IZFH-NEXT: and a1, a2, a1 +; RV32IZFH-NEXT: or a1, a3, a1 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; @@ -558,7 +552,6 @@ ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI3_0) ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI3_0)(a1) ; RV32IZHINX-NEXT: fabs.h a2, a0 @@ -570,21 +563,20 @@ ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 ; RV32IZHINX-NEXT: .LBB3_2: ; RV32IZHINX-NEXT: fcvt.s.h s0, a0 -; RV32IZHINX-NEXT: fle.s a0, zero, s0 -; RV32IZHINX-NEXT: neg s1, a0 ; RV32IZHINX-NEXT: mv a0, s0 ; RV32IZHINX-NEXT: call __fixunssfdi@plt ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI3_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI3_1)(a2) -; RV32IZHINX-NEXT: and a0, s1, a0 +; RV32IZHINX-NEXT: flt.s a3, s0, zero +; RV32IZHINX-NEXT: addi a3, a3, -1 +; RV32IZHINX-NEXT: and a0, a3, a0 ; RV32IZHINX-NEXT: flt.s a2, a2, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: or a0, a2, a0 -; RV32IZHINX-NEXT: and a1, s1, a1 +; RV32IZHINX-NEXT: and a1, a3, a1 ; RV32IZHINX-NEXT: or a1, a2, a1 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret ; @@ -622,26 +614,24 @@ ; RV32IZFHMIN-NEXT: .LBB3_2: ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 -; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero -; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s0, a0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixunssfdi@plt +; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI3_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI3_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s0, a0 -; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: and a1, s0, a1 -; RV32IZFHMIN-NEXT: or a1, a2, a1 +; RV32IZFHMIN-NEXT: flw fa4, %lo(.LCPI3_0)(a2) +; RV32IZFHMIN-NEXT: flt.s a2, fs0, fa5 +; RV32IZFHMIN-NEXT: addi a2, a2, -1 +; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: flt.s a3, fa4, fs0 +; RV32IZFHMIN-NEXT: neg a3, a3 +; RV32IZFHMIN-NEXT: or a0, a3, a0 +; RV32IZFHMIN-NEXT: and a1, a2, a1 +; RV32IZFHMIN-NEXT: or a1, a3, a1 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret ; @@ -682,24 +672,22 @@ ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 -; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 -; RV32IZHINXMIN-NEXT: neg s1, a0 ; RV32IZHINXMIN-NEXT: mv a0, s0 ; RV32IZHINXMIN-NEXT: call __fixunssfdi@plt ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI3_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI3_0)(a2) -; RV32IZHINXMIN-NEXT: and a0, s1, a0 +; RV32IZHINXMIN-NEXT: flt.s a3, s0, zero +; RV32IZHINXMIN-NEXT: addi a3, a3, -1 +; RV32IZHINXMIN-NEXT: and a0, a3, a0 ; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 -; RV32IZHINXMIN-NEXT: and a1, s1, a1 +; RV32IZHINXMIN-NEXT: and a1, a3, a1 ; RV32IZHINXMIN-NEXT: or a1, a2, a1 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-NEXT: ret ; @@ -824,12 +812,12 @@ ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 -; RV32IZFH-NEXT: fle.s s0, fa5, fs0 +; RV32IZFH-NEXT: flt.s s0, fs0, fa5 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a2, 524288 -; RV32IZFH-NEXT: beqz s0, .LBB5_4 +; RV32IZFH-NEXT: bnez s0, .LBB5_4 ; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB5_4: @@ -843,8 +831,8 @@ ; RV32IZFH-NEXT: feq.s a1, fs0, fs0 ; RV32IZFH-NEXT: neg a4, a1 ; RV32IZFH-NEXT: and a1, a4, a2 -; RV32IZFH-NEXT: neg a2, s0 -; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: addi s0, s0, -1 +; RV32IZFH-NEXT: and a0, s0, a0 ; RV32IZFH-NEXT: neg a2, a3 ; RV32IZFH-NEXT: or a0, a2, a0 ; RV32IZFH-NEXT: and a0, a4, a0 @@ -868,8 +856,6 @@ ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI5_0) ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI5_0)(a1) ; RV32IZHINX-NEXT: fabs.h a2, a0 @@ -881,22 +867,22 @@ ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 ; RV32IZHINX-NEXT: .LBB5_2: ; RV32IZHINX-NEXT: fcvt.s.h s0, a0 -; RV32IZHINX-NEXT: lui a0, 913408 -; RV32IZHINX-NEXT: fle.s s1, a0, s0 -; RV32IZHINX-NEXT: neg s2, s1 ; RV32IZHINX-NEXT: mv a0, s0 ; RV32IZHINX-NEXT: call __fixsfdi@plt -; RV32IZHINX-NEXT: lui a2, %hi(.LCPI5_1) -; RV32IZHINX-NEXT: lw a2, %lo(.LCPI5_1)(a2) -; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: lui a2, 913408 +; RV32IZHINX-NEXT: lui a3, %hi(.LCPI5_1) +; RV32IZHINX-NEXT: lw a3, %lo(.LCPI5_1)(a3) +; RV32IZHINX-NEXT: flt.s a6, s0, a2 +; RV32IZHINX-NEXT: addi a2, a6, -1 +; RV32IZHINX-NEXT: and a0, a2, a0 +; RV32IZHINX-NEXT: flt.s a4, a3, s0 ; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 ; RV32IZHINX-NEXT: lui a3, 524288 -; RV32IZHINX-NEXT: beqz s1, .LBB5_4 +; RV32IZHINX-NEXT: bnez a6, .LBB5_4 ; RV32IZHINX-NEXT: # %bb.3: ; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB5_4: @@ -908,8 +894,6 @@ ; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret ; @@ -953,12 +937,12 @@ ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 -; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 +; RV32IZFHMIN-NEXT: flt.s s0, fs0, fa5 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi@plt ; RV32IZFHMIN-NEXT: lui a4, 524288 ; RV32IZFHMIN-NEXT: lui a2, 524288 -; RV32IZFHMIN-NEXT: beqz s0, .LBB5_4 +; RV32IZFHMIN-NEXT: bnez s0, .LBB5_4 ; RV32IZFHMIN-NEXT: # %bb.3: ; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB5_4: @@ -972,8 +956,8 @@ ; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 ; RV32IZFHMIN-NEXT: neg a4, a1 ; RV32IZFHMIN-NEXT: and a1, a4, a2 -; RV32IZFHMIN-NEXT: neg a2, s0 -; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: addi s0, s0, -1 +; RV32IZFHMIN-NEXT: and a0, s0, a0 ; RV32IZFHMIN-NEXT: neg a2, a3 ; RV32IZFHMIN-NEXT: or a0, a2, a0 ; RV32IZFHMIN-NEXT: and a0, a4, a0 @@ -1020,39 +1004,39 @@ ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 -; RV32IZHINXMIN-NEXT: lui a0, 913408 -; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 -; RV32IZHINXMIN-NEXT: neg s2, s1 ; RV32IZHINXMIN-NEXT: mv a0, s0 ; RV32IZHINXMIN-NEXT: call __fixsfdi@plt -; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI5_0) -; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI5_0)(a2) -; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: lui a2, 913408 +; RV32IZHINXMIN-NEXT: lui a3, %hi(.LCPI5_0) +; RV32IZHINXMIN-NEXT: lw a3, %lo(.LCPI5_0)(a3) +; RV32IZHINXMIN-NEXT: flt.s a6, s0, a2 +; RV32IZHINXMIN-NEXT: addi a2, a6, -1 +; RV32IZHINXMIN-NEXT: and a0, a2, a0 +; RV32IZHINXMIN-NEXT: flt.s a4, a3, s0 ; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 ; RV32IZHINXMIN-NEXT: lui a3, 524288 -; RV32IZHINXMIN-NEXT: beqz s1, .LBB5_4 -; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a3, a1 -; RV32IZHINXMIN-NEXT: .LBB5_4: -; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a4, .LBB5_6 -; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a3, a5, -1 +; RV32IZHINXMIN-NEXT: beqz a6, .LBB5_5 +; RV32IZHINXMIN-NEXT: # %bb.3: +; RV32IZHINXMIN-NEXT: and a0, a2, a0 +; RV32IZHINXMIN-NEXT: bnez a4, .LBB5_6 +; RV32IZHINXMIN-NEXT: .LBB5_4: +; RV32IZHINXMIN-NEXT: and a1, a2, a3 +; RV32IZHINXMIN-NEXT: ret +; RV32IZHINXMIN-NEXT: .LBB5_5: +; RV32IZHINXMIN-NEXT: mv a3, a1 +; RV32IZHINXMIN-NEXT: and a0, a2, a0 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB5_4 ; RV32IZHINXMIN-NEXT: .LBB5_6: +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; @@ -1224,8 +1208,7 @@ ; RV32IZFH: # %bb.0: ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: lui a0, %hi(.LCPI7_0) ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI7_0)(a0) ; RV32IZFH-NEXT: fabs.h fa4, fa0 @@ -1237,22 +1220,21 @@ ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 ; RV32IZFH-NEXT: .LBB7_2: ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 -; RV32IZFH-NEXT: fmv.w.x fa5, zero -; RV32IZFH-NEXT: fle.s a0, fa5, fs0 -; RV32IZFH-NEXT: neg s0, a0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixunssfdi@plt +; RV32IZFH-NEXT: fmv.w.x fa5, zero ; RV32IZFH-NEXT: lui a2, %hi(.LCPI7_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI7_1)(a2) -; RV32IZFH-NEXT: and a0, s0, a0 -; RV32IZFH-NEXT: flt.s a2, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: and a1, s0, a1 -; RV32IZFH-NEXT: or a1, a2, a1 +; RV32IZFH-NEXT: flw fa4, %lo(.LCPI7_1)(a2) +; RV32IZFH-NEXT: flt.s a2, fs0, fa5 +; RV32IZFH-NEXT: addi a2, a2, -1 +; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: flt.s a3, fa4, fs0 +; RV32IZFH-NEXT: neg a3, a3 +; RV32IZFH-NEXT: or a0, a3, a0 +; RV32IZFH-NEXT: and a1, a2, a1 +; RV32IZFH-NEXT: or a1, a3, a1 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; @@ -1270,7 +1252,6 @@ ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI7_0) ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI7_0)(a1) ; RV32IZHINX-NEXT: fabs.h a2, a0 @@ -1282,21 +1263,20 @@ ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 ; RV32IZHINX-NEXT: .LBB7_2: ; RV32IZHINX-NEXT: fcvt.s.h s0, a0 -; RV32IZHINX-NEXT: fle.s a0, zero, s0 -; RV32IZHINX-NEXT: neg s1, a0 ; RV32IZHINX-NEXT: mv a0, s0 ; RV32IZHINX-NEXT: call __fixunssfdi@plt ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI7_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI7_1)(a2) -; RV32IZHINX-NEXT: and a0, s1, a0 +; RV32IZHINX-NEXT: flt.s a3, s0, zero +; RV32IZHINX-NEXT: addi a3, a3, -1 +; RV32IZHINX-NEXT: and a0, a3, a0 ; RV32IZHINX-NEXT: flt.s a2, a2, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: or a0, a2, a0 -; RV32IZHINX-NEXT: and a1, s1, a1 +; RV32IZHINX-NEXT: and a1, a3, a1 ; RV32IZHINX-NEXT: or a1, a2, a1 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret ; @@ -1334,26 +1314,24 @@ ; RV32IZFHMIN-NEXT: .LBB7_2: ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 -; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero -; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s0, a0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixunssfdi@plt +; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI7_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI7_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s0, a0 -; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: and a1, s0, a1 -; RV32IZFHMIN-NEXT: or a1, a2, a1 +; RV32IZFHMIN-NEXT: flw fa4, %lo(.LCPI7_0)(a2) +; RV32IZFHMIN-NEXT: flt.s a2, fs0, fa5 +; RV32IZFHMIN-NEXT: addi a2, a2, -1 +; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: flt.s a3, fa4, fs0 +; RV32IZFHMIN-NEXT: neg a3, a3 +; RV32IZFHMIN-NEXT: or a0, a3, a0 +; RV32IZFHMIN-NEXT: and a1, a2, a1 +; RV32IZFHMIN-NEXT: or a1, a3, a1 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret ; @@ -1394,24 +1372,22 @@ ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 -; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 -; RV32IZHINXMIN-NEXT: neg s1, a0 ; RV32IZHINXMIN-NEXT: mv a0, s0 ; RV32IZHINXMIN-NEXT: call __fixunssfdi@plt ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI7_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI7_0)(a2) -; RV32IZHINXMIN-NEXT: and a0, s1, a0 +; RV32IZHINXMIN-NEXT: flt.s a3, s0, zero +; RV32IZHINXMIN-NEXT: addi a3, a3, -1 +; RV32IZHINXMIN-NEXT: and a0, a3, a0 ; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 -; RV32IZHINXMIN-NEXT: and a1, s1, a1 +; RV32IZHINXMIN-NEXT: and a1, a3, a1 ; RV32IZHINXMIN-NEXT: or a1, a2, a1 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-NEXT: ret ; @@ -1536,12 +1512,12 @@ ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 -; RV32IZFH-NEXT: fle.s s0, fa5, fs0 +; RV32IZFH-NEXT: flt.s s0, fs0, fa5 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a2, 524288 -; RV32IZFH-NEXT: beqz s0, .LBB9_4 +; RV32IZFH-NEXT: bnez s0, .LBB9_4 ; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB9_4: @@ -1555,8 +1531,8 @@ ; RV32IZFH-NEXT: feq.s a1, fs0, fs0 ; RV32IZFH-NEXT: neg a4, a1 ; RV32IZFH-NEXT: and a1, a4, a2 -; RV32IZFH-NEXT: neg a2, s0 -; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: addi s0, s0, -1 +; RV32IZFH-NEXT: and a0, s0, a0 ; RV32IZFH-NEXT: neg a2, a3 ; RV32IZFH-NEXT: or a0, a2, a0 ; RV32IZFH-NEXT: and a0, a4, a0 @@ -1580,8 +1556,6 @@ ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI9_0) ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI9_0)(a1) ; RV32IZHINX-NEXT: fabs.h a2, a0 @@ -1593,22 +1567,22 @@ ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 ; RV32IZHINX-NEXT: .LBB9_2: ; RV32IZHINX-NEXT: fcvt.s.h s0, a0 -; RV32IZHINX-NEXT: lui a0, 913408 -; RV32IZHINX-NEXT: fle.s s1, a0, s0 -; RV32IZHINX-NEXT: neg s2, s1 ; RV32IZHINX-NEXT: mv a0, s0 ; RV32IZHINX-NEXT: call __fixsfdi@plt -; RV32IZHINX-NEXT: lui a2, %hi(.LCPI9_1) -; RV32IZHINX-NEXT: lw a2, %lo(.LCPI9_1)(a2) -; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: lui a2, 913408 +; RV32IZHINX-NEXT: lui a3, %hi(.LCPI9_1) +; RV32IZHINX-NEXT: lw a3, %lo(.LCPI9_1)(a3) +; RV32IZHINX-NEXT: flt.s a6, s0, a2 +; RV32IZHINX-NEXT: addi a2, a6, -1 +; RV32IZHINX-NEXT: and a0, a2, a0 +; RV32IZHINX-NEXT: flt.s a4, a3, s0 ; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 ; RV32IZHINX-NEXT: lui a3, 524288 -; RV32IZHINX-NEXT: beqz s1, .LBB9_4 +; RV32IZHINX-NEXT: bnez a6, .LBB9_4 ; RV32IZHINX-NEXT: # %bb.3: ; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB9_4: @@ -1620,8 +1594,6 @@ ; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret ; @@ -1665,12 +1637,12 @@ ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 -; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 +; RV32IZFHMIN-NEXT: flt.s s0, fs0, fa5 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi@plt ; RV32IZFHMIN-NEXT: lui a4, 524288 ; RV32IZFHMIN-NEXT: lui a2, 524288 -; RV32IZFHMIN-NEXT: beqz s0, .LBB9_4 +; RV32IZFHMIN-NEXT: bnez s0, .LBB9_4 ; RV32IZFHMIN-NEXT: # %bb.3: ; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB9_4: @@ -1684,8 +1656,8 @@ ; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 ; RV32IZFHMIN-NEXT: neg a4, a1 ; RV32IZFHMIN-NEXT: and a1, a4, a2 -; RV32IZFHMIN-NEXT: neg a2, s0 -; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: addi s0, s0, -1 +; RV32IZFHMIN-NEXT: and a0, s0, a0 ; RV32IZFHMIN-NEXT: neg a2, a3 ; RV32IZFHMIN-NEXT: or a0, a2, a0 ; RV32IZFHMIN-NEXT: and a0, a4, a0 @@ -1732,39 +1704,39 @@ ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 -; RV32IZHINXMIN-NEXT: lui a0, 913408 -; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 -; RV32IZHINXMIN-NEXT: neg s2, s1 ; RV32IZHINXMIN-NEXT: mv a0, s0 ; RV32IZHINXMIN-NEXT: call __fixsfdi@plt -; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI9_0) -; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI9_0)(a2) -; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: lui a2, 913408 +; RV32IZHINXMIN-NEXT: lui a3, %hi(.LCPI9_0) +; RV32IZHINXMIN-NEXT: lw a3, %lo(.LCPI9_0)(a3) +; RV32IZHINXMIN-NEXT: flt.s a6, s0, a2 +; RV32IZHINXMIN-NEXT: addi a2, a6, -1 +; RV32IZHINXMIN-NEXT: and a0, a2, a0 +; RV32IZHINXMIN-NEXT: flt.s a4, a3, s0 ; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 ; RV32IZHINXMIN-NEXT: lui a3, 524288 -; RV32IZHINXMIN-NEXT: beqz s1, .LBB9_4 -; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a3, a1 -; RV32IZHINXMIN-NEXT: .LBB9_4: -; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a4, .LBB9_6 -; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a3, a5, -1 +; RV32IZHINXMIN-NEXT: beqz a6, .LBB9_5 +; RV32IZHINXMIN-NEXT: # %bb.3: +; RV32IZHINXMIN-NEXT: and a0, a2, a0 +; RV32IZHINXMIN-NEXT: bnez a4, .LBB9_6 +; RV32IZHINXMIN-NEXT: .LBB9_4: +; RV32IZHINXMIN-NEXT: and a1, a2, a3 +; RV32IZHINXMIN-NEXT: ret +; RV32IZHINXMIN-NEXT: .LBB9_5: +; RV32IZHINXMIN-NEXT: mv a3, a1 +; RV32IZHINXMIN-NEXT: and a0, a2, a0 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB9_4 ; RV32IZHINXMIN-NEXT: .LBB9_6: +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; @@ -1936,8 +1908,7 @@ ; RV32IZFH: # %bb.0: ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: lui a0, %hi(.LCPI11_0) ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI11_0)(a0) ; RV32IZFH-NEXT: fabs.h fa4, fa0 @@ -1949,22 +1920,21 @@ ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 ; RV32IZFH-NEXT: .LBB11_2: ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 -; RV32IZFH-NEXT: fmv.w.x fa5, zero -; RV32IZFH-NEXT: fle.s a0, fa5, fs0 -; RV32IZFH-NEXT: neg s0, a0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixunssfdi@plt +; RV32IZFH-NEXT: fmv.w.x fa5, zero ; RV32IZFH-NEXT: lui a2, %hi(.LCPI11_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI11_1)(a2) -; RV32IZFH-NEXT: and a0, s0, a0 -; RV32IZFH-NEXT: flt.s a2, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: and a1, s0, a1 -; RV32IZFH-NEXT: or a1, a2, a1 +; RV32IZFH-NEXT: flw fa4, %lo(.LCPI11_1)(a2) +; RV32IZFH-NEXT: flt.s a2, fs0, fa5 +; RV32IZFH-NEXT: addi a2, a2, -1 +; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: flt.s a3, fa4, fs0 +; RV32IZFH-NEXT: neg a3, a3 +; RV32IZFH-NEXT: or a0, a3, a0 +; RV32IZFH-NEXT: and a1, a2, a1 +; RV32IZFH-NEXT: or a1, a3, a1 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; @@ -1982,7 +1952,6 @@ ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI11_0) ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI11_0)(a1) ; RV32IZHINX-NEXT: fabs.h a2, a0 @@ -1994,21 +1963,20 @@ ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 ; RV32IZHINX-NEXT: .LBB11_2: ; RV32IZHINX-NEXT: fcvt.s.h s0, a0 -; RV32IZHINX-NEXT: fle.s a0, zero, s0 -; RV32IZHINX-NEXT: neg s1, a0 ; RV32IZHINX-NEXT: mv a0, s0 ; RV32IZHINX-NEXT: call __fixunssfdi@plt ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI11_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI11_1)(a2) -; RV32IZHINX-NEXT: and a0, s1, a0 +; RV32IZHINX-NEXT: flt.s a3, s0, zero +; RV32IZHINX-NEXT: addi a3, a3, -1 +; RV32IZHINX-NEXT: and a0, a3, a0 ; RV32IZHINX-NEXT: flt.s a2, a2, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: or a0, a2, a0 -; RV32IZHINX-NEXT: and a1, s1, a1 +; RV32IZHINX-NEXT: and a1, a3, a1 ; RV32IZHINX-NEXT: or a1, a2, a1 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret ; @@ -2046,26 +2014,24 @@ ; RV32IZFHMIN-NEXT: .LBB11_2: ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 -; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero -; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s0, a0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixunssfdi@plt +; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI11_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI11_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s0, a0 -; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: and a1, s0, a1 -; RV32IZFHMIN-NEXT: or a1, a2, a1 +; RV32IZFHMIN-NEXT: flw fa4, %lo(.LCPI11_0)(a2) +; RV32IZFHMIN-NEXT: flt.s a2, fs0, fa5 +; RV32IZFHMIN-NEXT: addi a2, a2, -1 +; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: flt.s a3, fa4, fs0 +; RV32IZFHMIN-NEXT: neg a3, a3 +; RV32IZFHMIN-NEXT: or a0, a3, a0 +; RV32IZFHMIN-NEXT: and a1, a2, a1 +; RV32IZFHMIN-NEXT: or a1, a3, a1 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret ; @@ -2106,24 +2072,22 @@ ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 -; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 -; RV32IZHINXMIN-NEXT: neg s1, a0 ; RV32IZHINXMIN-NEXT: mv a0, s0 ; RV32IZHINXMIN-NEXT: call __fixunssfdi@plt ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI11_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI11_0)(a2) -; RV32IZHINXMIN-NEXT: and a0, s1, a0 +; RV32IZHINXMIN-NEXT: flt.s a3, s0, zero +; RV32IZHINXMIN-NEXT: addi a3, a3, -1 +; RV32IZHINXMIN-NEXT: and a0, a3, a0 ; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 -; RV32IZHINXMIN-NEXT: and a1, s1, a1 +; RV32IZHINXMIN-NEXT: and a1, a3, a1 ; RV32IZHINXMIN-NEXT: or a1, a2, a1 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-NEXT: ret ; @@ -2248,12 +2212,12 @@ ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 -; RV32IZFH-NEXT: fle.s s0, fa5, fs0 +; RV32IZFH-NEXT: flt.s s0, fs0, fa5 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a2, 524288 -; RV32IZFH-NEXT: beqz s0, .LBB13_4 +; RV32IZFH-NEXT: bnez s0, .LBB13_4 ; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB13_4: @@ -2267,8 +2231,8 @@ ; RV32IZFH-NEXT: feq.s a1, fs0, fs0 ; RV32IZFH-NEXT: neg a4, a1 ; RV32IZFH-NEXT: and a1, a4, a2 -; RV32IZFH-NEXT: neg a2, s0 -; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: addi s0, s0, -1 +; RV32IZFH-NEXT: and a0, s0, a0 ; RV32IZFH-NEXT: neg a2, a3 ; RV32IZFH-NEXT: or a0, a2, a0 ; RV32IZFH-NEXT: and a0, a4, a0 @@ -2292,8 +2256,6 @@ ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI13_0) ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI13_0)(a1) ; RV32IZHINX-NEXT: fabs.h a2, a0 @@ -2305,22 +2267,22 @@ ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 ; RV32IZHINX-NEXT: .LBB13_2: ; RV32IZHINX-NEXT: fcvt.s.h s0, a0 -; RV32IZHINX-NEXT: lui a0, 913408 -; RV32IZHINX-NEXT: fle.s s1, a0, s0 -; RV32IZHINX-NEXT: neg s2, s1 ; RV32IZHINX-NEXT: mv a0, s0 ; RV32IZHINX-NEXT: call __fixsfdi@plt -; RV32IZHINX-NEXT: lui a2, %hi(.LCPI13_1) -; RV32IZHINX-NEXT: lw a2, %lo(.LCPI13_1)(a2) -; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: lui a2, 913408 +; RV32IZHINX-NEXT: lui a3, %hi(.LCPI13_1) +; RV32IZHINX-NEXT: lw a3, %lo(.LCPI13_1)(a3) +; RV32IZHINX-NEXT: flt.s a6, s0, a2 +; RV32IZHINX-NEXT: addi a2, a6, -1 +; RV32IZHINX-NEXT: and a0, a2, a0 +; RV32IZHINX-NEXT: flt.s a4, a3, s0 ; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 ; RV32IZHINX-NEXT: lui a3, 524288 -; RV32IZHINX-NEXT: beqz s1, .LBB13_4 +; RV32IZHINX-NEXT: bnez a6, .LBB13_4 ; RV32IZHINX-NEXT: # %bb.3: ; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB13_4: @@ -2332,8 +2294,6 @@ ; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret ; @@ -2377,12 +2337,12 @@ ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 -; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 +; RV32IZFHMIN-NEXT: flt.s s0, fs0, fa5 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi@plt ; RV32IZFHMIN-NEXT: lui a4, 524288 ; RV32IZFHMIN-NEXT: lui a2, 524288 -; RV32IZFHMIN-NEXT: beqz s0, .LBB13_4 +; RV32IZFHMIN-NEXT: bnez s0, .LBB13_4 ; RV32IZFHMIN-NEXT: # %bb.3: ; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB13_4: @@ -2396,8 +2356,8 @@ ; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 ; RV32IZFHMIN-NEXT: neg a4, a1 ; RV32IZFHMIN-NEXT: and a1, a4, a2 -; RV32IZFHMIN-NEXT: neg a2, s0 -; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: addi s0, s0, -1 +; RV32IZFHMIN-NEXT: and a0, s0, a0 ; RV32IZFHMIN-NEXT: neg a2, a3 ; RV32IZFHMIN-NEXT: or a0, a2, a0 ; RV32IZFHMIN-NEXT: and a0, a4, a0 @@ -2444,39 +2404,39 @@ ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 -; RV32IZHINXMIN-NEXT: lui a0, 913408 -; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 -; RV32IZHINXMIN-NEXT: neg s2, s1 ; RV32IZHINXMIN-NEXT: mv a0, s0 ; RV32IZHINXMIN-NEXT: call __fixsfdi@plt -; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI13_0) -; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI13_0)(a2) -; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: lui a2, 913408 +; RV32IZHINXMIN-NEXT: lui a3, %hi(.LCPI13_0) +; RV32IZHINXMIN-NEXT: lw a3, %lo(.LCPI13_0)(a3) +; RV32IZHINXMIN-NEXT: flt.s a6, s0, a2 +; RV32IZHINXMIN-NEXT: addi a2, a6, -1 +; RV32IZHINXMIN-NEXT: and a0, a2, a0 +; RV32IZHINXMIN-NEXT: flt.s a4, a3, s0 ; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 ; RV32IZHINXMIN-NEXT: lui a3, 524288 -; RV32IZHINXMIN-NEXT: beqz s1, .LBB13_4 -; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a3, a1 -; RV32IZHINXMIN-NEXT: .LBB13_4: -; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a4, .LBB13_6 -; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a3, a5, -1 +; RV32IZHINXMIN-NEXT: beqz a6, .LBB13_5 +; RV32IZHINXMIN-NEXT: # %bb.3: +; RV32IZHINXMIN-NEXT: and a0, a2, a0 +; RV32IZHINXMIN-NEXT: bnez a4, .LBB13_6 +; RV32IZHINXMIN-NEXT: .LBB13_4: +; RV32IZHINXMIN-NEXT: and a1, a2, a3 +; RV32IZHINXMIN-NEXT: ret +; RV32IZHINXMIN-NEXT: .LBB13_5: +; RV32IZHINXMIN-NEXT: mv a3, a1 +; RV32IZHINXMIN-NEXT: and a0, a2, a0 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB13_4 ; RV32IZHINXMIN-NEXT: .LBB13_6: +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; @@ -2648,8 +2608,7 @@ ; RV32IZFH: # %bb.0: ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: lui a0, %hi(.LCPI15_0) ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI15_0)(a0) ; RV32IZFH-NEXT: fabs.h fa4, fa0 @@ -2661,22 +2620,21 @@ ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 ; RV32IZFH-NEXT: .LBB15_2: ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 -; RV32IZFH-NEXT: fmv.w.x fa5, zero -; RV32IZFH-NEXT: fle.s a0, fa5, fs0 -; RV32IZFH-NEXT: neg s0, a0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixunssfdi@plt +; RV32IZFH-NEXT: fmv.w.x fa5, zero ; RV32IZFH-NEXT: lui a2, %hi(.LCPI15_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI15_1)(a2) -; RV32IZFH-NEXT: and a0, s0, a0 -; RV32IZFH-NEXT: flt.s a2, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: and a1, s0, a1 -; RV32IZFH-NEXT: or a1, a2, a1 +; RV32IZFH-NEXT: flw fa4, %lo(.LCPI15_1)(a2) +; RV32IZFH-NEXT: flt.s a2, fs0, fa5 +; RV32IZFH-NEXT: addi a2, a2, -1 +; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: flt.s a3, fa4, fs0 +; RV32IZFH-NEXT: neg a3, a3 +; RV32IZFH-NEXT: or a0, a3, a0 +; RV32IZFH-NEXT: and a1, a2, a1 +; RV32IZFH-NEXT: or a1, a3, a1 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; @@ -2694,7 +2652,6 @@ ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI15_0) ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI15_0)(a1) ; RV32IZHINX-NEXT: fabs.h a2, a0 @@ -2706,21 +2663,20 @@ ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 ; RV32IZHINX-NEXT: .LBB15_2: ; RV32IZHINX-NEXT: fcvt.s.h s0, a0 -; RV32IZHINX-NEXT: fle.s a0, zero, s0 -; RV32IZHINX-NEXT: neg s1, a0 ; RV32IZHINX-NEXT: mv a0, s0 ; RV32IZHINX-NEXT: call __fixunssfdi@plt ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI15_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI15_1)(a2) -; RV32IZHINX-NEXT: and a0, s1, a0 +; RV32IZHINX-NEXT: flt.s a3, s0, zero +; RV32IZHINX-NEXT: addi a3, a3, -1 +; RV32IZHINX-NEXT: and a0, a3, a0 ; RV32IZHINX-NEXT: flt.s a2, a2, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: or a0, a2, a0 -; RV32IZHINX-NEXT: and a1, s1, a1 +; RV32IZHINX-NEXT: and a1, a3, a1 ; RV32IZHINX-NEXT: or a1, a2, a1 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret ; @@ -2758,26 +2714,24 @@ ; RV32IZFHMIN-NEXT: .LBB15_2: ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 -; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero -; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s0, a0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixunssfdi@plt +; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI15_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI15_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s0, a0 -; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: and a1, s0, a1 -; RV32IZFHMIN-NEXT: or a1, a2, a1 +; RV32IZFHMIN-NEXT: flw fa4, %lo(.LCPI15_0)(a2) +; RV32IZFHMIN-NEXT: flt.s a2, fs0, fa5 +; RV32IZFHMIN-NEXT: addi a2, a2, -1 +; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: flt.s a3, fa4, fs0 +; RV32IZFHMIN-NEXT: neg a3, a3 +; RV32IZFHMIN-NEXT: or a0, a3, a0 +; RV32IZFHMIN-NEXT: and a1, a2, a1 +; RV32IZFHMIN-NEXT: or a1, a3, a1 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret ; @@ -2818,24 +2772,22 @@ ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 -; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 -; RV32IZHINXMIN-NEXT: neg s1, a0 ; RV32IZHINXMIN-NEXT: mv a0, s0 ; RV32IZHINXMIN-NEXT: call __fixunssfdi@plt ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI15_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI15_0)(a2) -; RV32IZHINXMIN-NEXT: and a0, s1, a0 +; RV32IZHINXMIN-NEXT: flt.s a3, s0, zero +; RV32IZHINXMIN-NEXT: addi a3, a3, -1 +; RV32IZHINXMIN-NEXT: and a0, a3, a0 ; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 -; RV32IZHINXMIN-NEXT: and a1, s1, a1 +; RV32IZHINXMIN-NEXT: and a1, a3, a1 ; RV32IZHINXMIN-NEXT: or a1, a2, a1 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-NEXT: ret ; @@ -2960,12 +2912,12 @@ ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 -; RV32IZFH-NEXT: fle.s s0, fa5, fs0 +; RV32IZFH-NEXT: flt.s s0, fs0, fa5 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a2, 524288 -; RV32IZFH-NEXT: beqz s0, .LBB17_4 +; RV32IZFH-NEXT: bnez s0, .LBB17_4 ; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB17_4: @@ -2979,8 +2931,8 @@ ; RV32IZFH-NEXT: feq.s a1, fs0, fs0 ; RV32IZFH-NEXT: neg a4, a1 ; RV32IZFH-NEXT: and a1, a4, a2 -; RV32IZFH-NEXT: neg a2, s0 -; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: addi s0, s0, -1 +; RV32IZFH-NEXT: and a0, s0, a0 ; RV32IZFH-NEXT: neg a2, a3 ; RV32IZFH-NEXT: or a0, a2, a0 ; RV32IZFH-NEXT: and a0, a4, a0 @@ -3004,8 +2956,6 @@ ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI17_0) ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI17_0)(a1) ; RV32IZHINX-NEXT: fabs.h a2, a0 @@ -3017,22 +2967,22 @@ ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 ; RV32IZHINX-NEXT: .LBB17_2: ; RV32IZHINX-NEXT: fcvt.s.h s0, a0 -; RV32IZHINX-NEXT: lui a0, 913408 -; RV32IZHINX-NEXT: fle.s s1, a0, s0 -; RV32IZHINX-NEXT: neg s2, s1 ; RV32IZHINX-NEXT: mv a0, s0 ; RV32IZHINX-NEXT: call __fixsfdi@plt -; RV32IZHINX-NEXT: lui a2, %hi(.LCPI17_1) -; RV32IZHINX-NEXT: lw a2, %lo(.LCPI17_1)(a2) -; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: lui a2, 913408 +; RV32IZHINX-NEXT: lui a3, %hi(.LCPI17_1) +; RV32IZHINX-NEXT: lw a3, %lo(.LCPI17_1)(a3) +; RV32IZHINX-NEXT: flt.s a6, s0, a2 +; RV32IZHINX-NEXT: addi a2, a6, -1 +; RV32IZHINX-NEXT: and a0, a2, a0 +; RV32IZHINX-NEXT: flt.s a4, a3, s0 ; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 ; RV32IZHINX-NEXT: lui a3, 524288 -; RV32IZHINX-NEXT: beqz s1, .LBB17_4 +; RV32IZHINX-NEXT: bnez a6, .LBB17_4 ; RV32IZHINX-NEXT: # %bb.3: ; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB17_4: @@ -3044,8 +2994,6 @@ ; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret ; @@ -3089,12 +3037,12 @@ ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 -; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 +; RV32IZFHMIN-NEXT: flt.s s0, fs0, fa5 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi@plt ; RV32IZFHMIN-NEXT: lui a4, 524288 ; RV32IZFHMIN-NEXT: lui a2, 524288 -; RV32IZFHMIN-NEXT: beqz s0, .LBB17_4 +; RV32IZFHMIN-NEXT: bnez s0, .LBB17_4 ; RV32IZFHMIN-NEXT: # %bb.3: ; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB17_4: @@ -3108,8 +3056,8 @@ ; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 ; RV32IZFHMIN-NEXT: neg a4, a1 ; RV32IZFHMIN-NEXT: and a1, a4, a2 -; RV32IZFHMIN-NEXT: neg a2, s0 -; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: addi s0, s0, -1 +; RV32IZFHMIN-NEXT: and a0, s0, a0 ; RV32IZFHMIN-NEXT: neg a2, a3 ; RV32IZFHMIN-NEXT: or a0, a2, a0 ; RV32IZFHMIN-NEXT: and a0, a4, a0 @@ -3156,39 +3104,39 @@ ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 -; RV32IZHINXMIN-NEXT: lui a0, 913408 -; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0 -; RV32IZHINXMIN-NEXT: neg s2, s1 ; RV32IZHINXMIN-NEXT: mv a0, s0 ; RV32IZHINXMIN-NEXT: call __fixsfdi@plt -; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI17_0) -; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI17_0)(a2) -; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: lui a2, 913408 +; RV32IZHINXMIN-NEXT: lui a3, %hi(.LCPI17_0) +; RV32IZHINXMIN-NEXT: lw a3, %lo(.LCPI17_0)(a3) +; RV32IZHINXMIN-NEXT: flt.s a6, s0, a2 +; RV32IZHINXMIN-NEXT: addi a2, a6, -1 +; RV32IZHINXMIN-NEXT: and a0, a2, a0 +; RV32IZHINXMIN-NEXT: flt.s a4, a3, s0 ; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 ; RV32IZHINXMIN-NEXT: lui a3, 524288 -; RV32IZHINXMIN-NEXT: beqz s1, .LBB17_4 -; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a3, a1 -; RV32IZHINXMIN-NEXT: .LBB17_4: -; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a4, .LBB17_6 -; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a3, a5, -1 +; RV32IZHINXMIN-NEXT: beqz a6, .LBB17_5 +; RV32IZHINXMIN-NEXT: # %bb.3: +; RV32IZHINXMIN-NEXT: and a0, a2, a0 +; RV32IZHINXMIN-NEXT: bnez a4, .LBB17_6 +; RV32IZHINXMIN-NEXT: .LBB17_4: +; RV32IZHINXMIN-NEXT: and a1, a2, a3 +; RV32IZHINXMIN-NEXT: ret +; RV32IZHINXMIN-NEXT: .LBB17_5: +; RV32IZHINXMIN-NEXT: mv a3, a1 +; RV32IZHINXMIN-NEXT: and a0, a2, a0 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB17_4 ; RV32IZHINXMIN-NEXT: .LBB17_6: +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; @@ -3360,8 +3308,7 @@ ; RV32IZFH: # %bb.0: ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: lui a0, %hi(.LCPI19_0) ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI19_0)(a0) ; RV32IZFH-NEXT: fabs.h fa4, fa0 @@ -3373,22 +3320,21 @@ ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 ; RV32IZFH-NEXT: .LBB19_2: ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 -; RV32IZFH-NEXT: fmv.w.x fa5, zero -; RV32IZFH-NEXT: fle.s a0, fa5, fs0 -; RV32IZFH-NEXT: neg s0, a0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixunssfdi@plt +; RV32IZFH-NEXT: fmv.w.x fa5, zero ; RV32IZFH-NEXT: lui a2, %hi(.LCPI19_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI19_1)(a2) -; RV32IZFH-NEXT: and a0, s0, a0 -; RV32IZFH-NEXT: flt.s a2, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: and a1, s0, a1 -; RV32IZFH-NEXT: or a1, a2, a1 +; RV32IZFH-NEXT: flw fa4, %lo(.LCPI19_1)(a2) +; RV32IZFH-NEXT: flt.s a2, fs0, fa5 +; RV32IZFH-NEXT: addi a2, a2, -1 +; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: flt.s a3, fa4, fs0 +; RV32IZFH-NEXT: neg a3, a3 +; RV32IZFH-NEXT: or a0, a3, a0 +; RV32IZFH-NEXT: and a1, a2, a1 +; RV32IZFH-NEXT: or a1, a3, a1 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; @@ -3406,7 +3352,6 @@ ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI19_0) ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI19_0)(a1) ; RV32IZHINX-NEXT: fabs.h a2, a0 @@ -3418,21 +3363,20 @@ ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0 ; RV32IZHINX-NEXT: .LBB19_2: ; RV32IZHINX-NEXT: fcvt.s.h s0, a0 -; RV32IZHINX-NEXT: fle.s a0, zero, s0 -; RV32IZHINX-NEXT: neg s1, a0 ; RV32IZHINX-NEXT: mv a0, s0 ; RV32IZHINX-NEXT: call __fixunssfdi@plt ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI19_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI19_1)(a2) -; RV32IZHINX-NEXT: and a0, s1, a0 +; RV32IZHINX-NEXT: flt.s a3, s0, zero +; RV32IZHINX-NEXT: addi a3, a3, -1 +; RV32IZHINX-NEXT: and a0, a3, a0 ; RV32IZHINX-NEXT: flt.s a2, a2, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: or a0, a2, a0 -; RV32IZHINX-NEXT: and a1, s1, a1 +; RV32IZHINX-NEXT: and a1, a3, a1 ; RV32IZHINX-NEXT: or a1, a2, a1 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 ; RV32IZHINX-NEXT: ret ; @@ -3470,26 +3414,24 @@ ; RV32IZFHMIN-NEXT: .LBB19_2: ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 -; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero -; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s0, a0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixunssfdi@plt +; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI19_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI19_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s0, a0 -; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: and a1, s0, a1 -; RV32IZFHMIN-NEXT: or a1, a2, a1 +; RV32IZFHMIN-NEXT: flw fa4, %lo(.LCPI19_0)(a2) +; RV32IZFHMIN-NEXT: flt.s a2, fs0, fa5 +; RV32IZFHMIN-NEXT: addi a2, a2, -1 +; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: flt.s a3, fa4, fs0 +; RV32IZFHMIN-NEXT: neg a3, a3 +; RV32IZFHMIN-NEXT: or a0, a3, a0 +; RV32IZFHMIN-NEXT: and a1, a2, a1 +; RV32IZFHMIN-NEXT: or a1, a3, a1 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: ret ; @@ -3530,24 +3472,22 @@ ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0 -; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0 -; RV32IZHINXMIN-NEXT: neg s1, a0 ; RV32IZHINXMIN-NEXT: mv a0, s0 ; RV32IZHINXMIN-NEXT: call __fixunssfdi@plt ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI19_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI19_0)(a2) -; RV32IZHINXMIN-NEXT: and a0, s1, a0 +; RV32IZHINXMIN-NEXT: flt.s a3, s0, zero +; RV32IZHINXMIN-NEXT: addi a3, a3, -1 +; RV32IZHINXMIN-NEXT: and a0, a3, a0 ; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 -; RV32IZHINXMIN-NEXT: and a1, s1, a1 +; RV32IZHINXMIN-NEXT: and a1, a3, a1 ; RV32IZHINXMIN-NEXT: or a1, a2, a1 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 ; RV32IZHINXMIN-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/half-select-fcmp.ll b/llvm/test/CodeGen/RISCV/half-select-fcmp.ll --- a/llvm/test/CodeGen/RISCV/half-select-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/half-select-fcmp.ll @@ -444,8 +444,8 @@ define half @select_fcmp_ugt(half %a, half %b) nounwind { ; CHECK-LABEL: select_fcmp_ugt: ; CHECK: # %bb.0: -; CHECK-NEXT: fle.h a0, fa0, fa1 -; CHECK-NEXT: beqz a0, .LBB9_2 +; CHECK-NEXT: flt.h a0, fa1, fa0 +; CHECK-NEXT: bnez a0, .LBB9_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: fmv.h fa0, fa1 ; CHECK-NEXT: .LBB9_2: @@ -453,8 +453,8 @@ ; ; CHECKIZHINX-LABEL: select_fcmp_ugt: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: fle.h a2, a0, a1 -; CHECKIZHINX-NEXT: beqz a2, .LBB9_2 +; CHECKIZHINX-NEXT: flt.h a2, a1, a0 +; CHECKIZHINX-NEXT: bnez a2, .LBB9_2 ; CHECKIZHINX-NEXT: # %bb.1: ; CHECKIZHINX-NEXT: mv a0, a1 ; CHECKIZHINX-NEXT: .LBB9_2: @@ -491,8 +491,8 @@ define half @select_fcmp_uge(half %a, half %b) nounwind { ; CHECK-LABEL: select_fcmp_uge: ; CHECK: # %bb.0: -; CHECK-NEXT: flt.h a0, fa0, fa1 -; CHECK-NEXT: beqz a0, .LBB10_2 +; CHECK-NEXT: fle.h a0, fa1, fa0 +; CHECK-NEXT: bnez a0, .LBB10_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: fmv.h fa0, fa1 ; CHECK-NEXT: .LBB10_2: @@ -500,8 +500,8 @@ ; ; CHECKIZHINX-LABEL: select_fcmp_uge: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: flt.h a2, a0, a1 -; CHECKIZHINX-NEXT: beqz a2, .LBB10_2 +; CHECKIZHINX-NEXT: fle.h a2, a1, a0 +; CHECKIZHINX-NEXT: bnez a2, .LBB10_2 ; CHECKIZHINX-NEXT: # %bb.1: ; CHECKIZHINX-NEXT: mv a0, a1 ; CHECKIZHINX-NEXT: .LBB10_2: @@ -538,8 +538,8 @@ define half @select_fcmp_ult(half %a, half %b) nounwind { ; CHECK-LABEL: select_fcmp_ult: ; CHECK: # %bb.0: -; CHECK-NEXT: fle.h a0, fa1, fa0 -; CHECK-NEXT: beqz a0, .LBB11_2 +; CHECK-NEXT: flt.h a0, fa0, fa1 +; CHECK-NEXT: bnez a0, .LBB11_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: fmv.h fa0, fa1 ; CHECK-NEXT: .LBB11_2: @@ -547,8 +547,8 @@ ; ; CHECKIZHINX-LABEL: select_fcmp_ult: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: fle.h a2, a1, a0 -; CHECKIZHINX-NEXT: beqz a2, .LBB11_2 +; CHECKIZHINX-NEXT: flt.h a2, a0, a1 +; CHECKIZHINX-NEXT: bnez a2, .LBB11_2 ; CHECKIZHINX-NEXT: # %bb.1: ; CHECKIZHINX-NEXT: mv a0, a1 ; CHECKIZHINX-NEXT: .LBB11_2: @@ -585,8 +585,8 @@ define half @select_fcmp_ule(half %a, half %b) nounwind { ; CHECK-LABEL: select_fcmp_ule: ; CHECK: # %bb.0: -; CHECK-NEXT: flt.h a0, fa1, fa0 -; CHECK-NEXT: beqz a0, .LBB12_2 +; CHECK-NEXT: fle.h a0, fa0, fa1 +; CHECK-NEXT: bnez a0, .LBB12_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: fmv.h fa0, fa1 ; CHECK-NEXT: .LBB12_2: @@ -594,8 +594,8 @@ ; ; CHECKIZHINX-LABEL: select_fcmp_ule: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: flt.h a2, a1, a0 -; CHECKIZHINX-NEXT: beqz a2, .LBB12_2 +; CHECKIZHINX-NEXT: fle.h a2, a0, a1 +; CHECKIZHINX-NEXT: bnez a2, .LBB12_2 ; CHECKIZHINX-NEXT: # %bb.1: ; CHECKIZHINX-NEXT: mv a0, a1 ; CHECKIZHINX-NEXT: .LBB12_2: @@ -840,30 +840,30 @@ define signext i32 @select_fcmp_uge_negone_zero(half %a, half %b) nounwind { ; CHECK-LABEL: select_fcmp_uge_negone_zero: ; CHECK: # %bb.0: -; CHECK-NEXT: fle.h a0, fa0, fa1 -; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: flt.h a0, fa1, fa0 +; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret ; ; CHECKIZHINX-LABEL: select_fcmp_uge_negone_zero: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: fle.h a0, a0, a1 -; CHECKIZHINX-NEXT: addi a0, a0, -1 +; CHECKIZHINX-NEXT: flt.h a0, a1, a0 +; CHECKIZHINX-NEXT: neg a0, a0 ; CHECKIZHINX-NEXT: ret ; ; CHECKIZFHMIN-LABEL: select_fcmp_uge_negone_zero: ; CHECKIZFHMIN: # %bb.0: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 -; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0 -; CHECKIZFHMIN-NEXT: fle.s a0, fa4, fa5 -; CHECKIZFHMIN-NEXT: addi a0, a0, -1 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa1 +; CHECKIZFHMIN-NEXT: flt.s a0, fa4, fa5 +; CHECKIZFHMIN-NEXT: neg a0, a0 ; CHECKIZFHMIN-NEXT: ret ; ; CHECKIZHINXMIN-LABEL: select_fcmp_uge_negone_zero: ; CHECKIZHINXMIN: # %bb.0: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECKIZHINXMIN-NEXT: fle.s a0, a0, a1 -; CHECKIZHINXMIN-NEXT: addi a0, a0, -1 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 +; CHECKIZHINXMIN-NEXT: flt.s a0, a1, a0 +; CHECKIZHINXMIN-NEXT: neg a0, a0 ; CHECKIZHINXMIN-NEXT: ret %1 = fcmp ugt half %a, %b %2 = select i1 %1, i32 -1, i32 0 @@ -873,30 +873,34 @@ define signext i32 @select_fcmp_uge_1_2(half %a, half %b) nounwind { ; CHECK-LABEL: select_fcmp_uge_1_2: ; CHECK: # %bb.0: -; CHECK-NEXT: fle.h a0, fa0, fa1 -; CHECK-NEXT: addi a0, a0, 1 +; CHECK-NEXT: flt.h a0, fa1, fa0 +; CHECK-NEXT: li a1, 2 +; CHECK-NEXT: sub a0, a1, a0 ; CHECK-NEXT: ret ; ; CHECKIZHINX-LABEL: select_fcmp_uge_1_2: ; CHECKIZHINX: # %bb.0: -; CHECKIZHINX-NEXT: fle.h a0, a0, a1 -; CHECKIZHINX-NEXT: addi a0, a0, 1 +; CHECKIZHINX-NEXT: flt.h a0, a1, a0 +; CHECKIZHINX-NEXT: li a1, 2 +; CHECKIZHINX-NEXT: sub a0, a1, a0 ; CHECKIZHINX-NEXT: ret ; ; CHECKIZFHMIN-LABEL: select_fcmp_uge_1_2: ; CHECKIZFHMIN: # %bb.0: -; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 -; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0 -; CHECKIZFHMIN-NEXT: fle.s a0, fa4, fa5 -; CHECKIZFHMIN-NEXT: addi a0, a0, 1 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa1 +; CHECKIZFHMIN-NEXT: flt.s a0, fa4, fa5 +; CHECKIZFHMIN-NEXT: li a1, 2 +; CHECKIZFHMIN-NEXT: sub a0, a1, a0 ; CHECKIZFHMIN-NEXT: ret ; ; CHECKIZHINXMIN-LABEL: select_fcmp_uge_1_2: ; CHECKIZHINXMIN: # %bb.0: -; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECKIZHINXMIN-NEXT: fle.s a0, a0, a1 -; CHECKIZHINXMIN-NEXT: addi a0, a0, 1 +; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 +; CHECKIZHINXMIN-NEXT: flt.s a0, a1, a0 +; CHECKIZHINXMIN-NEXT: li a1, 2 +; CHECKIZHINXMIN-NEXT: sub a0, a1, a0 ; CHECKIZHINXMIN-NEXT: ret %1 = fcmp ugt half %a, %b %2 = select i1 %1, i32 1, i32 2 diff --git a/llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll b/llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll --- a/llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll +++ b/llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll @@ -234,10 +234,9 @@ ; ; CHECK-RV64IF-LABEL: flo: ; CHECK-RV64IF: # %bb.0: -; CHECK-RV64IF-NEXT: fle.s a0, fa0, fa1 -; CHECK-RV64IF-NEXT: fle.s a1, fa0, fa2 -; CHECK-RV64IF-NEXT: and a0, a0, a1 -; CHECK-RV64IF-NEXT: xori a0, a0, 1 +; CHECK-RV64IF-NEXT: flt.s a0, fa1, fa0 +; CHECK-RV64IF-NEXT: flt.s a1, fa2, fa0 +; CHECK-RV64IF-NEXT: or a0, a0, a1 ; CHECK-RV64IF-NEXT: ret %l0 = fcmp ult float %a, %c %l1 = fcmp ult float %b, %c