Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -25815,7 +25815,111 @@ } } - return SDValue(); + // Avoid producing TBL and TBL2 instructions if we don't know + // SVE register size or minimal is unequal to maximum size. + if (!MinSVESize) + return SDValue(); + + EVT VTOp1 = Op.getOperand(0).getValueType(); + unsigned BitsPerElt = VTOp1.getVectorElementType().getSizeInBits(); + unsigned IndexLen = MinSVESize / BitsPerElt; + unsigned NumElts = VTOp1.getVectorNumElements(); + unsigned MaskSize = ShuffleMask.size(); + unsigned MaxOffset; + + switch (BitsPerElt) { + default: + llvm_unreachable("unexpected element type for vector"); + case 8: + MaxOffset = std::numeric_limits::max(); + break; + case 16: + MaxOffset = std::numeric_limits::max(); + break; + case 32: + case 64: + MaxOffset = std::numeric_limits::max(); + break; + } + // In case if the hardware is not able to represent vector type in + // a scalable register. + if (NumElts > IndexLen || (MaskSize != NumElts && (2 * NumElts > IndexLen)) || + isZerosVector(Op1.getNode()) || isZerosVector(Op2.getNode())) + return SDValue(); + + bool Op1IsUnused = false; + bool Op2IsUnused = false; + if (llvm::all_of(ShuffleMask, + [&NumElts](unsigned Val) { return Val < NumElts; })) + Op2IsUnused = true; + + if (llvm::all_of(ShuffleMask, + [&NumElts](unsigned Val) { return Val >= NumElts; })) { + Op1IsUnused = true; + std::swap(Op1, Op2); + } + + // Ignore two operands case if not SVE2 and all indexes numbers + // could be represented. + if (Op2IsUnused || Op1IsUnused || + // For 8-bit elements and 1024-bit SVE registers and MaxOffset equals + // to 255, this might point to the last element of in the second operand + // of the shufflevector, thus we are rejecting this transform. + (Subtarget->hasSVE2() && IndexLen < (MaxOffset / 2) && + MinSVESize == MaxSVESize)) { + + unsigned FillElements = IndexLen - NumElts; + EVT MaskEltType = EVT::getIntegerVT(*DAG.getContext(), BitsPerElt); + EVT MaskType = EVT::getVectorVT(*DAG.getContext(), MaskEltType, IndexLen); + + SmallVector TBLMask; + assert(NumElts == ShuffleMask.size() && "Incorrect mask"); + for (int Val : ShuffleMask) { + unsigned Offset = Val; + if (Op1IsUnused) + Offset = Offset < NumElts ? Offset + NumElts : Offset - NumElts; + // Filling up the remaining positions of the mask with MaxOffset because + // for one byte per element and maximum possible 2048-bits register size + // this is the last range value. + else if (Op2IsUnused && Offset >= NumElts) + Offset = MaxOffset; + else + // If we refer to the second operand then we have to add elements number + // in hardware register minus number of elements in a type. + if (!Op2IsUnused && !Op1IsUnused && Offset > NumElts) + Offset += IndexLen - NumElts; + TBLMask.push_back(DAG.getConstant(Offset, DL, MVT::i64)); + } + // It is still better to fill TBL mask to the actual hardware supported + // size with out of index elements. + for (unsigned i = 0; i < FillElements; ++i) + TBLMask.push_back(DAG.getConstant(MaxOffset, DL, MVT::i64)); + + EVT MaskContainerVT = getContainerForFixedLengthVector(DAG, MaskType); + SDValue VecMask = + DAG.getBuildVector(MaskType, DL, ArrayRef(TBLMask.data(), IndexLen)); + SDValue SVEMask = convertToScalableVector(DAG, MaskContainerVT, VecMask); + + SDValue Shuffle; + if (Op1IsUnused || Op2IsUnused) { + Shuffle = convertFromScalableVector( + DAG, VT, + DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, ContainerVT, + DAG.getConstant(Intrinsic::aarch64_sve_tbl, DL, MVT::i32), + Op1, SVEMask)); + } else { + if (Subtarget->hasSVE2()) { + Shuffle = convertFromScalableVector( + DAG, VT, + DAG.getNode( + ISD::INTRINSIC_WO_CHAIN, DL, ContainerVT, + DAG.getConstant(Intrinsic::aarch64_sve_tbl2, DL, MVT::i32), Op1, + Op2, SVEMask)); + } + } + return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle); + } else + return SDValue(); } SDValue AArch64TargetLowering::getSVESafeBitCast(EVT VT, SDValue Op, Index: llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll =================================================================== --- llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll +++ llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll @@ -194,28 +194,13 @@ define void @test_rev_elts_fail(ptr %a) #1 { ; CHECK-LABEL: test_rev_elts_fail: ; CHECK: // %bb.0: -; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill -; CHECK-NEXT: sub x9, sp, #48 -; CHECK-NEXT: mov x29, sp -; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0 -; CHECK-NEXT: .cfi_def_cfa w29, 16 -; CHECK-NEXT: .cfi_offset w30, -8 -; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: adrp x8, .LCPI11_0 +; CHECK-NEXT: add x8, x8, :lo12:.LCPI11_0 ; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] -; CHECK-NEXT: mov z1.d, z0.d[2] -; CHECK-NEXT: fmov x11, d0 -; CHECK-NEXT: fmov x8, d1 -; CHECK-NEXT: mov z1.d, z0.d[3] -; CHECK-NEXT: fmov x9, d1 -; CHECK-NEXT: mov x10, v0.d[1] -; CHECK-NEXT: stp x9, x8, [sp, #16] -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: stp x10, x11, [sp] -; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8] +; CHECK-NEXT: ld1d { z1.d }, p0/z, [x8] +; CHECK-NEXT: tbl z0.d, { z0.d }, z1.d ; CHECK-NEXT: st1d { z0.d }, p0, [x0] -; CHECK-NEXT: mov sp, x29 -; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ret %tmp1 = load <4 x i64>, ptr %a %tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> undef, <4 x i32> @@ -260,39 +245,26 @@ ; sve-vector-bits-min=256, sve-vector-bits-max is not set, REV inst can't be generated. define void @test_revv8i32(ptr %a) #0 { -; CHECK-LABEL: test_revv8i32: -; CHECK: // %bb.0: -; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill -; CHECK-NEXT: sub x9, sp, #48 -; CHECK-NEXT: mov x29, sp -; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0 -; CHECK-NEXT: .cfi_def_cfa w29, 16 -; CHECK-NEXT: .cfi_offset w30, -8 -; CHECK-NEXT: .cfi_offset w29, -16 -; CHECK-NEXT: ptrue p0.s, vl8 -; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] -; CHECK-NEXT: mov w8, v0.s[1] -; CHECK-NEXT: fmov w10, s0 -; CHECK-NEXT: mov w9, v0.s[2] -; CHECK-NEXT: mov w11, v0.s[3] -; CHECK-NEXT: mov z1.s, z0.s[4] -; CHECK-NEXT: mov z2.s, z0.s[5] -; CHECK-NEXT: mov z3.s, z0.s[6] -; CHECK-NEXT: mov z0.s, z0.s[7] -; CHECK-NEXT: stp w8, w10, [sp, #24] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: stp w11, w9, [sp, #16] -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: fmov w11, s0 -; CHECK-NEXT: stp w8, w10, [sp, #8] -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: stp w11, w9, [sp] -; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8] -; CHECK-NEXT: st1w { z0.s }, p0, [x0] -; CHECK-NEXT: mov sp, x29 -; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload -; CHECK-NEXT: ret +; VBITS_GE_256-LABEL: test_revv8i32: +; VBITS_GE_256: // %bb.0: +; VBITS_GE_256-NEXT: ptrue p0.s, vl8 +; VBITS_GE_256-NEXT: index z1.s, #7, #-1 +; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0] +; VBITS_GE_256-NEXT: tbl z0.s, { z0.s }, z1.s +; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0] +; VBITS_GE_256-NEXT: ret +; +; VBITS_GE_512-LABEL: test_revv8i32: +; VBITS_GE_512: // %bb.0: +; VBITS_GE_512-NEXT: adrp x8, .LCPI14_0 +; VBITS_GE_512-NEXT: add x8, x8, :lo12:.LCPI14_0 +; VBITS_GE_512-NEXT: ptrue p0.s, vl8 +; VBITS_GE_512-NEXT: ptrue p1.s, vl16 +; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0] +; VBITS_GE_512-NEXT: ld1w { z1.s }, p1/z, [x8] +; VBITS_GE_512-NEXT: tbl z0.s, { z0.s }, z1.s +; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0] +; VBITS_GE_512-NEXT: ret %tmp1 = load <8 x i32>, ptr %a %tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> store <8 x i32> %tmp2, ptr %a @@ -379,60 +351,13 @@ define void @test_rev_fail(ptr %a) #1 { ; CHECK-LABEL: test_rev_fail: ; CHECK: // %bb.0: -; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill -; CHECK-NEXT: sub x9, sp, #48 -; CHECK-NEXT: mov x29, sp -; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0 -; CHECK-NEXT: .cfi_def_cfa w29, 16 -; CHECK-NEXT: .cfi_offset w30, -8 -; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: adrp x8, .LCPI20_0 +; CHECK-NEXT: add x8, x8, :lo12:.LCPI20_0 ; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] -; CHECK-NEXT: mov z1.h, z0.h[8] -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov w9, s1 -; CHECK-NEXT: mov z4.h, z0.h[11] -; CHECK-NEXT: mov z5.h, z0.h[12] -; CHECK-NEXT: mov z2.h, z0.h[9] -; CHECK-NEXT: strh w8, [sp, #14] -; CHECK-NEXT: fmov w8, s4 -; CHECK-NEXT: mov z3.h, z0.h[10] -; CHECK-NEXT: strh w9, [sp, #30] -; CHECK-NEXT: fmov w9, s5 -; CHECK-NEXT: mov z16.h, z0.h[15] -; CHECK-NEXT: fmov w11, s2 -; CHECK-NEXT: fmov w12, s3 -; CHECK-NEXT: strh w8, [sp, #24] -; CHECK-NEXT: fmov w8, s16 -; CHECK-NEXT: mov z6.h, z0.h[13] -; CHECK-NEXT: mov z7.h, z0.h[14] -; CHECK-NEXT: umov w10, v0.h[1] -; CHECK-NEXT: strh w9, [sp, #22] -; CHECK-NEXT: umov w9, v0.h[2] -; CHECK-NEXT: strh w11, [sp, #28] -; CHECK-NEXT: fmov w11, s6 -; CHECK-NEXT: strh w12, [sp, #26] -; CHECK-NEXT: fmov w12, s7 -; CHECK-NEXT: strh w8, [sp, #16] -; CHECK-NEXT: umov w8, v0.h[5] -; CHECK-NEXT: strh w10, [sp, #12] -; CHECK-NEXT: strh w11, [sp, #20] -; CHECK-NEXT: umov w11, v0.h[3] -; CHECK-NEXT: strh w12, [sp, #18] -; CHECK-NEXT: umov w12, v0.h[4] -; CHECK-NEXT: umov w10, v0.h[6] -; CHECK-NEXT: strh w9, [sp, #10] -; CHECK-NEXT: umov w9, v0.h[7] -; CHECK-NEXT: strh w8, [sp, #4] -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: strh w11, [sp, #8] -; CHECK-NEXT: strh w12, [sp, #6] -; CHECK-NEXT: strh w10, [sp, #2] -; CHECK-NEXT: strh w9, [sp] -; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8] +; CHECK-NEXT: ld1h { z1.h }, p0/z, [x8] +; CHECK-NEXT: tbl z0.h, { z0.h }, z1.h ; CHECK-NEXT: st1h { z0.h }, p0, [x0] -; CHECK-NEXT: mov sp, x29 -; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ret %tmp1 = load <16 x i16>, ptr %a %tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> Index: llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll =================================================================== --- llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll +++ llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll @@ -937,4 +937,69 @@ ret void } +define void @shuffle_v4f64_tbl_op1(ptr %a, ptr %b) #1 { +; CHECK:.LCPI42_0: +; CHECK-NEXT: .xword 1 +; CHECK-NEXT: .xword 3 +; CHECK-NEXT: .xword 2 +; CHECK-NEXT: .xword 0 +; CHECK-LABEL: shuffle_v4f64_tbl_op1: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI42_0 +; CHECK-NEXT: add x8, x8, :lo12:.LCPI42_0 +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] +; CHECK-NEXT: ld1d { z1.d }, p0/z, [x8] +; CHECK-NEXT: tbl z0.d, { z0.d }, z1.d +; CHECK-NEXT: st1d { z0.d }, p0, [x0] +; CHECK-NEXT: ret + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b + %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> + store <4 x double> %ret, ptr %a + ret void +} + +define void @shuffle_v4f64_tbl_op2(ptr %a, ptr %b) #1 { +; CHECK:.LCPI43_0: +; CHECK-NEXT: .xword 1 +; CHECK-NEXT: .xword 3 +; CHECK-NEXT: .xword 2 +; CHECK-NEXT: .xword 0 +; CHECK-LABEL: shuffle_v4f64_tbl_op2: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI43_0 +; CHECK-NEXT: add x8, x8, :lo12:.LCPI43_0 +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1] +; CHECK-NEXT: ld1d { z1.d }, p0/z, [x8] +; CHECK-NEXT: tbl z0.d, { z0.d }, z1.d +; CHECK-NEXT: st1d { z0.d }, p0, [x0] +; CHECK-NEXT: ret + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b + %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> + store <4 x double> %ret, ptr %a + ret void +} + +define void @shuffle_v4f64_tbl2(ptr %a, ptr %b) #2 { +; CHECK-LABEL: shuffle_v4f64_tbl2: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: index z2.d, #2, #1 +; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] +; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1] +; CHECK-NEXT: tbl z0.d, { z0.d, z1.d }, z2.d +; CHECK-NEXT: st1d { z0.d }, p0, [x0] +; CHECK-NEXT: ret + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b + %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> + store <4 x double> %ret, ptr %a + ret void +} + attributes #0 = { "target-features"="+sve" } +attributes #1 = { "target-features"="+sve" vscale_range(2,2) } +attributes #2 = { "target-features"="+sve2" vscale_range(2,2) } Index: llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll =================================================================== --- llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll +++ llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll @@ -379,3 +379,372 @@ store <4 x double> %ret, ptr %a ret void } + +; CHECK: .LCPI23_0: +; CHECK-NEXT: .hword 10 +; CHECK-NEXT: .hword 1 +; CHECK-NEXT: .hword 3 +; CHECK-NEXT: .hword 4 +; CHECK-NEXT: .hword 65535 +; CHECK-NEXT: .hword 65535 +; CHECK-NEXT: .hword 65535 +; CHECK-NEXT: .hword 65535 +define <4 x i16> @sve2_shuffle_v4i16_tbl2(ptr %a, ptr %b) #1 { +; CHECK-LABEL: sve2_shuffle_v4i16_tbl2: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI23_0 +; CHECK-NEXT: ldr d0, [x0] +; CHECK-NEXT: ldr d1, [x1] +; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI23_0] +; CHECK-NEXT: tbl z0.h, { z0.h, z1.h }, z2.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %op1 = load <4 x i16>, ptr %a + %op2 = load <4 x i16>, ptr %b + %1 = shufflevector <4 x i16> %op1, <4 x i16> %op2, <4 x i32> + ret <4 x i16> %1 +} + +; CHECK: .LCPI24_0: +; CHECK-NEXT: .hword 0 +; CHECK-NEXT: .hword 3 +; CHECK-NEXT: .hword 7 +; CHECK-NEXT: .hword 7 +; CHECK-NEXT: .hword 15 +; CHECK-NEXT: .hword 0 +; CHECK-NEXT: .hword 0 +; CHECK-NEXT: .hword 1 +define <8 x i16> @sve2_shuffle_v8i16_tbl2(ptr %a, ptr %b) #1 { +; CHECK-LABEL: sve2_shuffle_v8i16_tbl2: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI24_0 +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldr q1, [x1] +; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI24_0] +; CHECK-NEXT: tbl z0.h, { z0.h, z1.h }, z2.h +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %op1 = load <8 x i16>, ptr %a + %op2 = load <8 x i16>, ptr %b + %1 = shufflevector <8 x i16> %op1, <8 x i16> %op2, <8 x i32> + ret <8 x i16> %1 +} + +; CHECK: .LCPI25_0: +; CHECK-NEXT: .hword 0 +; CHECK-NEXT: .hword 3 +; CHECK-NEXT: .hword 7 +; CHECK-NEXT: .hword 7 +; CHECK-NEXT: .hword 1 +; CHECK-NEXT: .hword 0 +; CHECK-NEXT: .hword 0 +; CHECK-NEXT: .hword 1 +define <8 x i16> @sve2_shuffle_v8i16_tbl_op1(ptr %a, ptr %b) #1 { +; CHECK-LABEL: sve2_shuffle_v8i16_tbl_op1: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI25_0 +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI25_0] +; CHECK-NEXT: tbl z0.h, { z0.h }, z1.h +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %op1 = load <8 x i16>, ptr %a + %op2 = load <8 x i16>, ptr %b + %1 = shufflevector <8 x i16> %op1, <8 x i16> %op2, <8 x i32> + ret <8 x i16> %1 +} + +; CHECK: .LCPI26_0: +; CHECK-NEXT: .hword 2 +; CHECK-NEXT: .hword 5 +; CHECK-NEXT: .hword 2 +; CHECK-NEXT: .hword 3 +; CHECK-NEXT: .hword 7 +; CHECK-NEXT: .hword 3 +; CHECK-NEXT: .hword 3 +; CHECK-NEXT: .hword 2 +define <8 x i16> @sve2_shuffle_v8i16_tbl_op2(ptr %a, ptr %b) #1 { +; CHECK-LABEL: sve2_shuffle_v8i16_tbl_op2: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI26_0 +; CHECK-NEXT: ldr q0, [x1] +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI26_0] +; CHECK-NEXT: tbl z0.h, { z0.h }, z1.h +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %op1 = load <8 x i16>, ptr %a + %op2 = load <8 x i16>, ptr %b + %1 = shufflevector <8 x i16> %op1, <8 x i16> %op2, <8 x i32> + ret <8 x i16> %1 +} + +; CHECK: .LCPI27_0: +; CHECK-NEXT: .word 0 +; CHECK-NEXT: .word 3 +; CHECK-NEXT: .word 5 +; CHECK-NEXT: .word 1 +define <4 x float> @sve2_shuffle_v4f32_tbl2_op2(ptr %a, ptr %b) #1 { +; CHECK-LABEL: sve2_shuffle_v4f32_tbl2_op2: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI27_0 +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldr q1, [x1] +; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI27_0] +; CHECK-NEXT: tbl z0.s, { z0.s, z1.s }, z2.s +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %op1 = load <4 x float>, ptr %a + %op2 = load <4 x float>, ptr %b + %1 = shufflevector <4 x float> %op1, <4 x float> %op2, <4 x i32> + ret <4 x float> %1 +} + +; CHECK: .LCPI28_0: +; CHECK-NEXT: .word 0 +; CHECK-NEXT: .word 3 +; CHECK-NEXT: .word 2 +; CHECK-NEXT: .word 1 +define <4 x float> @sve2_shuffle_v4f32_tbl_op1(ptr %a, ptr %b) #1 { +; CHECK-LABEL: sve2_shuffle_v4f32_tbl_op1: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI28_0 +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI28_0] +; CHECK-NEXT: tbl z0.s, { z0.s }, z1.s +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %op1 = load <4 x float>, ptr %a + %op2 = load <4 x float>, ptr %b + %1 = shufflevector <4 x float> %op1, <4 x float> %op2, <4 x i32> + ret <4 x float> %1 +} + +; CHECK: .LCPI29_0: +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 3 +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 255 +; CHECK-NEXT: .byte 255 +define <8 x i8> @shuffle_index_size_acceptable_op2(ptr %a, ptr %b) #2 { +; CHECK-LABEL: shuffle_index_size_acceptable_op2: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI29_0 +; CHECK-NEXT: add x8, x8, :lo12:.LCPI29_0 +; CHECK-NEXT: ptrue p0.b +; CHECK-NEXT: ldr d0, [x1] +; CHECK-NEXT: ld1b { z1.b }, p0/z, [x8] +; CHECK-NEXT: tbl z0.b, { z0.b }, z1.b +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %op1 = load <8 x i8>, ptr %a + %op2 = load <8 x i8>, ptr %b + %1 = shufflevector <8 x i8> %op1, <8 x i8> %op2, <8 x i32> + ret <8 x i8> %1 +} + +; CHECK: .LCPI30_0: +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 3 +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 5 +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 255 +; CHECK-NEXT: .byte 255 +define <8 x i8> @shuffle_index_size_acceptable_op1(ptr %a, ptr %b) #2 { +; CHECK-LABEL: shuffle_index_size_acceptable_op1: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI30_0 +; CHECK-NEXT: add x8, x8, :lo12:.LCPI30_0 +; CHECK-NEXT: ptrue p0.b +; CHECK-NEXT: ldr d0, [x0] +; CHECK-NEXT: ld1b { z1.b }, p0/z, [x8] +; CHECK-NEXT: tbl z0.b, { z0.b }, z1.b +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %op1 = load <8 x i8>, ptr %a + %op2 = load <8 x i8>, ptr %b + %1 = shufflevector <8 x i8> %op1, <8 x i8> %op2, <8 x i32> + ret <8 x i8> %1 +} + +; CHECK: .LCPI31_0: +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 17 +; CHECK-NEXT: .byte 18 +; CHECK-NEXT: .byte 19 +; CHECK-NEXT: .byte 20 +; CHECK-NEXT: .byte 20 +; CHECK-NEXT: .byte 22 +; CHECK-NEXT: .byte 23 +; CHECK-NEXT: .byte 255 +; CHECK-NEXT: .byte 255 +define <8 x i8> @shuffle_index_size_acceptable_op_both(ptr %a, ptr %b) #1 { +; CHECK-LABEL: shuffle_index_size_acceptable_op_both: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI31_0 +; CHECK-NEXT: ldr d0, [x0] +; CHECK-NEXT: ldr d1, [x1] +; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI31_0] +; CHECK-NEXT: tbl z0.b, { z0.b, z1.b }, z2.b +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %op1 = load <8 x i8>, ptr %a + %op2 = load <8 x i8>, ptr %b + %1 = shufflevector <8 x i8> %op1, <8 x i8> %op2, <8 x i32> + ret <8 x i8> %1 +} + +define <8 x i8> @shuffle_index_size_unacceptable_op_both(ptr %a, ptr %b) #3 { +; CHECK-LABEL: shuffle_index_size_unacceptable_op_both: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr d0, [x1] +; CHECK-NEXT: ldr d1, [x0] +; CHECK-NEXT: mov z2.b, z0.b[7] +; CHECK-NEXT: fmov w8, s2 +; CHECK-NEXT: mov z2.b, z0.b[6] +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: mov z2.b, z0.b[4] +; CHECK-NEXT: fmov w10, s2 +; CHECK-NEXT: mov z2.b, z0.b[3] +; CHECK-NEXT: strb w8, [sp, #15] +; CHECK-NEXT: fmov w8, s2 +; CHECK-NEXT: mov z2.b, z0.b[2] +; CHECK-NEXT: mov z0.b, z0.b[1] +; CHECK-NEXT: mov z1.b, z1.b[1] +; CHECK-NEXT: strb w9, [sp, #14] +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: strb w10, [sp, #13] +; CHECK-NEXT: strb w10, [sp, #12] +; CHECK-NEXT: fmov w10, s0 +; CHECK-NEXT: strb w8, [sp, #11] +; CHECK-NEXT: fmov w8, s1 +; CHECK-NEXT: strb w9, [sp, #10] +; CHECK-NEXT: strb w10, [sp, #9] +; CHECK-NEXT: strb w8, [sp, #8] +; CHECK-NEXT: ldr d0, [sp, #8] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %op1 = load <8 x i8>, ptr %a + %op2 = load <8 x i8>, ptr %b + %1 = shufflevector <8 x i8> %op1, <8 x i8> %op2, <8 x i32> + ret <8 x i8> %1 +} + +; CHECK: .LCPI33_0: +; CHECK-NEXT: .hword 1 +; CHECK-NEXT: .hword 129 +; CHECK-NEXT: .hword 130 +; CHECK-NEXT: .hword 131 +; CHECK-NEXT: .hword 132 +; CHECK-NEXT: .hword 132 +; CHECK-NEXT: .hword 134 +; CHECK-NEXT: .hword 135 +; CHECK-NEXT: .hword 65535 +; CHECK-NEXT: .hword 65535 +define <8 x i16> @shuffle_index_size_acceptable_i16_op_both(ptr %a, ptr %b) #3 { +; CHECK-LABEL: shuffle_index_size_acceptable_i16_op_both: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI33_0 +; CHECK-NEXT: add x8, x8, :lo12:.LCPI33_0 +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldr q1, [x1] +; CHECK-NEXT: ld1h { z2.h }, p0/z, [x8] +; CHECK-NEXT: tbl z0.h, { z0.h, z1.h }, z2.h +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %op1 = load <8 x i16>, ptr %a + %op2 = load <8 x i16>, ptr %b + %1 = shufflevector <8 x i16> %op1, <8 x i16> %op2, <8 x i32> + ret <8 x i16> %1 +} + +define <16 x double> @shuffle_doublemask_size_unacceptable_form(ptr %a, ptr %b) #1 { +; CHECK-LABEL: shuffle_doublemask_size_unacceptable_form: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q5, q3, [x0, #16] +; CHECK-NEXT: index z0.d, #3, #-2 +; CHECK-NEXT: index z6.d, #0, #3 +; CHECK-NEXT: ldr q2, [x0] +; CHECK-NEXT: ldr q17, [x1, #48] +; CHECK-NEXT: mov z16.d, z3.d[1] +; CHECK-NEXT: mov z4.d, z2.d +; CHECK-NEXT: tbl z1.d, { z2.d, z3.d }, z0.d +; CHECK-NEXT: tbl z0.d, { z4.d, z5.d }, z6.d +; CHECK-NEXT: tbl z7.d, { z16.d, z17.d }, z6.d +; CHECK-NEXT: mov z3.d, z1.d +; CHECK-NEXT: mov z5.d, z1.d +; CHECK-NEXT: mov z2.d, z0.d +; CHECK-NEXT: mov z4.d, z0.d +; CHECK-NEXT: mov z6.d, z0.d +; CHECK-NEXT: // kill: def $q7 killed $q7 killed $z7 +; CHECK-NEXT: ret + %op1 = load <8 x double>, ptr %a + %op2 = load <8 x double>, ptr %b + %1 = shufflevector <8 x double> %op1, <8 x double> %op2, <16 x i32> + ret <16 x double> %1 +} + +; CHECK: .LCPI35_0: +; CHECK-NEXT: .hword 1 +; CHECK-NEXT: .hword 11 +; CHECK-NEXT: .hword 10 +; CHECK-NEXT: .hword 3 +; CHECK-NEXT: .hword 0 +; CHECK-NEXT: .hword 0 +; CHECK-NEXT: .hword 0 +; CHECK-NEXT: .hword 8 +define <8 x i16> @shuffle_doublemask_size_acceptable_i16_op_both(ptr %a, ptr %b) #1 { +; CHECK-LABEL: shuffle_doublemask_size_acceptable_i16_op_both: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI35_0 +; CHECK-NEXT: ldr d0, [x0] +; CHECK-NEXT: ldr d1, [x1] +; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI35_0] +; CHECK-NEXT: tbl z0.h, { z0.h, z1.h }, z2.h +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %op1 = load <4 x i16>, ptr %a + %op2 = load <4 x i16>, ptr %b + %1 = shufflevector <4 x i16> %op1, <4 x i16> %op2, <8 x i32> + ret <8 x i16> %1 +} + +; CHECK: .LCPI36_0: +; CHECK-NEXT: .word 0 +; CHECK-NEXT: .word 1 +; CHECK-NEXT: .word 1 +; CHECK-NEXT: .word 2 +; CHECK-NEXT: .word 4294967295 +; CHECK-NEXT: .word 4294967295 +define <4 x float> @shuffle_halfmask_size_acceptable_float_op_one(ptr %ptr1, ptr %ptr2) #2 { +; CHECK-LABEL: shuffle_halfmask_size_acceptable_float_op_one: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI36_0 +; CHECK-NEXT: add x8, x8, :lo12:.LCPI36_0 +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8] +; CHECK-NEXT: ldr q1, [x0] +; CHECK-NEXT: tbl z0.s, { z1.s }, z0.s +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %a = load <8 x float>, ptr %ptr1 + %b = load <8 x float>, ptr %ptr2 + %1 = shufflevector <8 x float> %a, <8 x float> %b, <4 x i32> + ret <4 x float> %1 +} + +attributes #0 = { "target-features"="+sve" } +attributes #1 = { "target-features"="+sve2" vscale_range(1,1) } +attributes #2 = { "target-features"="+sve2" vscale_range(8,8) } +attributes #3 = { "target-features"="+sve2" vscale_range(16,16) }