diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -5644,9 +5644,12 @@ } const Value *llvm::getUnderlyingObject(const Value *V, unsigned MaxLookup) { + DenseMap Visited; std::function Visit = [&](const Value *Root, unsigned Count) { const Value *V = Root; + if (Visited.contains(V)) + return Visited.at(V); if (!V->getType()->isPointerTy() || (MaxLookup != 0 && Count == MaxLookup)) return V; @@ -5664,11 +5667,22 @@ V = GA->getAliasee(); } else { if (auto *PHI = dyn_cast(V)) { - // Look through single-arg phi nodes created by LCSSA. - if (PHI->getNumIncomingValues() == 1) { - V = PHI->getIncomingValue(0); - return Visit(V, Count + 1); + // We can look through Phi's if each incoming value has the same + // underlying object, or is the phi itself. + Visited[Root] = Root; + const Value *NewUnderlying = Root; + for (const Value *IncomingValue : PHI->incoming_values()) { + if (IncomingValue == Root) + continue; + const Value *IncomingUnderlying = Visit(IncomingValue, Count + 1); + if (NewUnderlying == Root) + NewUnderlying = IncomingUnderlying; + else if (NewUnderlying != IncomingUnderlying) + // There are >=2 possible underlying objects. We cannot + // determine a new underlying object. + return V; } + V = NewUnderlying; } else if (auto *Call = dyn_cast(V)) { // CaptureTracking can know about special capturing properties of // some intrinsics like launder.invariant.group, that can't be @@ -5684,10 +5698,11 @@ return Visit(RP, Count + 1); } } - + Visited[Root] = V; return V; } assert(V->getType()->isPointerTy() && "Unexpected operand type!"); + Visited[Root] = V; return Visit(V, Count + 1); }; diff --git a/llvm/test/Analysis/BasicAA/recphi.ll b/llvm/test/Analysis/BasicAA/recphi.ll --- a/llvm/test/Analysis/BasicAA/recphi.ll +++ b/llvm/test/Analysis/BasicAA/recphi.ll @@ -41,11 +41,11 @@ ; CHECK: MustAlias: i32* %tab, [2 x i32]* %tab ; CHECK: MustAlias: i32* %tab, i8* %tab ; CHECK: NoAlias: i32* %arrayidx, i32* %tab -; CHECK: MayAlias: i32* %incdec.ptr.i, [2 x i32]* %tab +; CHECK: PartialAlias: i32* %incdec.ptr.i, [2 x i32]* %tab ; CHECK: NoAlias: i32* %incdec.ptr.i, i8* %tab ; CHECK: MayAlias: i32* %arrayidx, i32* %incdec.ptr.i ; CHECK: NoAlias: i32* %incdec.ptr.i, i32* %tab -; CHECK: MayAlias: i32* %p.addr.05.i, [2 x i32]* %tab +; CHECK: PartialAlias: i32* %p.addr.05.i, [2 x i32]* %tab ; CHECK: MayAlias: i32* %p.addr.05.i, i8* %tab ; CHECK: MayAlias: i32* %arrayidx, i32* %p.addr.05.i ; CHECK: MayAlias: i32* %p.addr.05.i, i32* %tab @@ -95,11 +95,11 @@ ; CHECK: PartialAlias (off -36): i32* %arrayidx1, [10 x i32]* %tab ; CHECK: NoAlias: i32* %arrayidx1, i8* %tab ; CHECK: NoAlias: i32* %arrayidx1, i32* %tab -; CHECK: MayAlias: i32* %incdec.ptr.i, [10 x i32]* %tab +; CHECK: PartialAlias: i32* %incdec.ptr.i, [10 x i32]* %tab ; CHECK: MayAlias: i32* %incdec.ptr.i, i8* %tab ; CHECK: MayAlias: i32* %incdec.ptr.i, i32* %tab ; CHECK: MayAlias: i32* %arrayidx1, i32* %incdec.ptr.i -; CHECK: MayAlias: i32* %p.addr.05.i, [10 x i32]* %tab +; CHECK: PartialAlias: i32* %p.addr.05.i, [10 x i32]* %tab ; CHECK: MayAlias: i32* %p.addr.05.i, i8* %tab ; CHECK: MayAlias: i32* %p.addr.05.i, i32* %tab ; CHECK: MayAlias: i32* %arrayidx1, i32* %p.addr.05.i diff --git a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll --- a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll @@ -424,8 +424,8 @@ ; CHECK-NEXT: mov w8, wzr ; CHECK-NEXT: b .LBB5_7 ; CHECK-NEXT: .LBB5_3: -; CHECK-NEXT: mov w8, wzr -; CHECK-NEXT: b .LBB5_9 +; CHECK-NEXT: mov w0, wzr +; CHECK-NEXT: ret ; CHECK-NEXT: .LBB5_4: // %vector.ph ; CHECK-NEXT: and x11, x10, #0xfffffff0 ; CHECK-NEXT: add x8, x0, #8 diff --git a/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll b/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll --- a/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll +++ b/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll @@ -17,8 +17,6 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnone %lim) { ; ENABLE-LABEL: wrongUseOfPostDominate: ; ENABLE: @ %bb.0: @ %entry -; ENABLE-NEXT: .save {r11, lr} -; ENABLE-NEXT: push {r11, lr} ; ENABLE-NEXT: cmn r1, #1 ; ENABLE-NEXT: ble .LBB0_7 ; ENABLE-NEXT: @ %bb.1: @ %while.cond.preheader @@ -26,8 +24,8 @@ ; ENABLE-NEXT: beq .LBB0_6 ; ENABLE-NEXT: @ %bb.2: @ %while.cond.preheader ; ENABLE-NEXT: cmp r0, r2 -; ENABLE-NEXT: pophs {r11, pc} -; ENABLE-NEXT: .LBB0_3: @ %while.body.preheader +; ENABLE-NEXT: bhs .LBB0_6 +; ENABLE-NEXT: @ %bb.3: @ %while.body.preheader ; ENABLE-NEXT: movw r12, :lower16:skip ; ENABLE-NEXT: sub r1, r1, #1 ; ENABLE-NEXT: movt r12, :upper16:skip @@ -38,70 +36,73 @@ ; ENABLE-NEXT: add r0, r0, r3 ; ENABLE-NEXT: sub r3, r1, #1 ; ENABLE-NEXT: cmp r3, r1 -; ENABLE-NEXT: bhs .LBB0_6 -; ENABLE-NEXT: @ %bb.5: @ %while.body +; ENABLE-NEXT: bxhs lr +; ENABLE-NEXT: .LBB0_5: @ %while.body ; ENABLE-NEXT: @ in Loop: Header=BB0_4 Depth=1 ; ENABLE-NEXT: cmp r0, r2 ; ENABLE-NEXT: mov r1, r3 ; ENABLE-NEXT: blo .LBB0_4 ; ENABLE-NEXT: .LBB0_6: @ %if.end29 -; ENABLE-NEXT: pop {r11, pc} -; ENABLE-NEXT: .LBB0_7: @ %while.cond2.outer +; ENABLE-NEXT: bx lr +; ENABLE-NEXT: .LBB0_7: +; ENABLE-NEXT: .save {r11, lr} +; ENABLE-NEXT: push {r11, lr} +; ENABLE-NEXT: .LBB0_8: @ %while.cond2.outer ; ENABLE-NEXT: @ =>This Loop Header: Depth=1 -; ENABLE-NEXT: @ Child Loop BB0_8 Depth 2 -; ENABLE-NEXT: @ Child Loop BB0_15 Depth 2 +; ENABLE-NEXT: @ Child Loop BB0_9 Depth 2 +; ENABLE-NEXT: @ Child Loop BB0_16 Depth 2 ; ENABLE-NEXT: mov r3, r0 -; ENABLE-NEXT: .LBB0_8: @ %while.cond2 -; ENABLE-NEXT: @ Parent Loop BB0_7 Depth=1 +; ENABLE-NEXT: .LBB0_9: @ %while.cond2 +; ENABLE-NEXT: @ Parent Loop BB0_8 Depth=1 ; ENABLE-NEXT: @ => This Inner Loop Header: Depth=2 ; ENABLE-NEXT: add r1, r1, #1 ; ENABLE-NEXT: cmp r1, #1 -; ENABLE-NEXT: beq .LBB0_18 -; ENABLE-NEXT: @ %bb.9: @ %while.body4 -; ENABLE-NEXT: @ in Loop: Header=BB0_8 Depth=2 +; ENABLE-NEXT: beq .LBB0_19 +; ENABLE-NEXT: @ %bb.10: @ %while.body4 +; ENABLE-NEXT: @ in Loop: Header=BB0_9 Depth=2 ; ENABLE-NEXT: cmp r3, r2 -; ENABLE-NEXT: bls .LBB0_8 -; ENABLE-NEXT: @ %bb.10: @ %if.then7 -; ENABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1 +; ENABLE-NEXT: bls .LBB0_9 +; ENABLE-NEXT: @ %bb.11: @ %if.then7 +; ENABLE-NEXT: @ in Loop: Header=BB0_8 Depth=1 ; ENABLE-NEXT: mov r0, r3 ; ENABLE-NEXT: ldrb r12, [r0, #-1]! ; ENABLE-NEXT: sxtb lr, r12 ; ENABLE-NEXT: cmn lr, #1 -; ENABLE-NEXT: bgt .LBB0_7 -; ENABLE-NEXT: @ %bb.11: @ %if.then7 -; ENABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1 +; ENABLE-NEXT: bgt .LBB0_8 +; ENABLE-NEXT: @ %bb.12: @ %if.then7 +; ENABLE-NEXT: @ in Loop: Header=BB0_8 Depth=1 ; ENABLE-NEXT: cmp r0, r2 -; ENABLE-NEXT: bls .LBB0_7 -; ENABLE-NEXT: @ %bb.12: @ %land.rhs14.preheader -; ENABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1 -; ENABLE-NEXT: cmn lr, #1 -; ENABLE-NEXT: bgt .LBB0_7 +; ENABLE-NEXT: bls .LBB0_8 ; ENABLE-NEXT: @ %bb.13: @ %land.rhs14.preheader -; ENABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1 +; ENABLE-NEXT: @ in Loop: Header=BB0_8 Depth=1 +; ENABLE-NEXT: cmn lr, #1 +; ENABLE-NEXT: bgt .LBB0_8 +; ENABLE-NEXT: @ %bb.14: @ %land.rhs14.preheader +; ENABLE-NEXT: @ in Loop: Header=BB0_8 Depth=1 ; ENABLE-NEXT: cmp r12, #191 -; ENABLE-NEXT: bhi .LBB0_7 -; ENABLE-NEXT: @ %bb.14: @ %while.body24.preheader -; ENABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1 +; ENABLE-NEXT: bhi .LBB0_8 +; ENABLE-NEXT: @ %bb.15: @ %while.body24.preheader +; ENABLE-NEXT: @ in Loop: Header=BB0_8 Depth=1 ; ENABLE-NEXT: sub r3, r3, #2 -; ENABLE-NEXT: .LBB0_15: @ %while.body24 -; ENABLE-NEXT: @ Parent Loop BB0_7 Depth=1 +; ENABLE-NEXT: .LBB0_16: @ %while.body24 +; ENABLE-NEXT: @ Parent Loop BB0_8 Depth=1 ; ENABLE-NEXT: @ => This Inner Loop Header: Depth=2 ; ENABLE-NEXT: mov r0, r3 ; ENABLE-NEXT: cmp r3, r2 -; ENABLE-NEXT: bls .LBB0_7 -; ENABLE-NEXT: @ %bb.16: @ %while.body24.land.rhs14_crit_edge -; ENABLE-NEXT: @ in Loop: Header=BB0_15 Depth=2 +; ENABLE-NEXT: bls .LBB0_8 +; ENABLE-NEXT: @ %bb.17: @ %while.body24.land.rhs14_crit_edge +; ENABLE-NEXT: @ in Loop: Header=BB0_16 Depth=2 ; ENABLE-NEXT: mov r3, r0 ; ENABLE-NEXT: ldrsb lr, [r3], #-1 ; ENABLE-NEXT: cmn lr, #1 ; ENABLE-NEXT: uxtb r12, lr -; ENABLE-NEXT: bgt .LBB0_7 -; ENABLE-NEXT: @ %bb.17: @ %while.body24.land.rhs14_crit_edge -; ENABLE-NEXT: @ in Loop: Header=BB0_15 Depth=2 +; ENABLE-NEXT: bgt .LBB0_8 +; ENABLE-NEXT: @ %bb.18: @ %while.body24.land.rhs14_crit_edge +; ENABLE-NEXT: @ in Loop: Header=BB0_16 Depth=2 ; ENABLE-NEXT: cmp r12, #192 -; ENABLE-NEXT: blo .LBB0_15 -; ENABLE-NEXT: b .LBB0_7 -; ENABLE-NEXT: .LBB0_18: +; ENABLE-NEXT: blo .LBB0_16 +; ENABLE-NEXT: b .LBB0_8 +; ENABLE-NEXT: .LBB0_19: ; ENABLE-NEXT: mov r0, r3 ; ENABLE-NEXT: pop {r11, pc} ; diff --git a/llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll b/llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll --- a/llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll +++ b/llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll @@ -224,14 +224,15 @@ ; CHECK-NEXT: vldrb.u8 q0, [r12], #16 ; CHECK-NEXT: vstrb.8 q0, [r4], #16 ; CHECK-NEXT: letp lr, .LBB10_2 -; CHECK-NEXT: .LBB10_3: @ %for.body +; CHECK-NEXT: .LBB10_3: @ %prehead +; CHECK-NEXT: pop.w {r4, lr} +; CHECK-NEXT: .LBB10_4: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldrb r3, [r0], #1 ; CHECK-NEXT: subs r2, #2 ; CHECK-NEXT: strb r3, [r1], #1 -; CHECK-NEXT: bne .LBB10_3 -; CHECK-NEXT: @ %bb.4: -; CHECK-NEXT: pop.w {r4, lr} +; CHECK-NEXT: bne .LBB10_4 +; CHECK-NEXT: @ %bb.5: @ %for.cond.cleanup ; CHECK-NEXT: bx lr entry: %cmp6 = icmp slt i32 %n, 0 diff --git a/llvm/test/Transforms/InstCombine/ptr-replace-alloca.ll b/llvm/test/Transforms/InstCombine/ptr-replace-alloca.ll --- a/llvm/test/Transforms/InstCombine/ptr-replace-alloca.ll +++ b/llvm/test/Transforms/InstCombine/ptr-replace-alloca.ll @@ -15,9 +15,7 @@ ; CHECK: else: ; CHECK-NEXT: br label [[SINK]] ; CHECK: sink: -; CHECK-NEXT: [[PTR1:%.*]] = phi ptr [ getelementptr inbounds ([32 x i8], ptr @g1, i64 0, i64 2), [[IF]] ], [ getelementptr inbounds ([32 x i8], ptr @g1, i64 0, i64 1), [[ELSE]] ] -; CHECK-NEXT: [[LOAD:%.*]] = load i8, ptr [[PTR1]], align 1 -; CHECK-NEXT: ret i8 [[LOAD]] +; CHECK-NEXT: ret i8 0 ; entry: %alloca = alloca [32 x i8], align 4, addrspace(1) @@ -114,13 +112,11 @@ ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[BB_0:%.*]] ; CHECK: bb.0: -; CHECK-NEXT: [[PTR1:%.*]] = phi ptr [ getelementptr inbounds ([32 x i8], ptr @g1, i64 0, i64 1), [[ENTRY:%.*]] ], [ getelementptr inbounds ([32 x i8], ptr @g1, i64 0, i64 2), [[BB_1:%.*]] ] -; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB_1]], label [[EXIT:%.*]] +; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB_1:%.*]], label [[EXIT:%.*]] ; CHECK: bb.1: ; CHECK-NEXT: br label [[BB_0]] ; CHECK: exit: -; CHECK-NEXT: [[LOAD:%.*]] = load i8, ptr [[PTR1]], align 1 -; CHECK-NEXT: ret i8 [[LOAD]] +; CHECK-NEXT: ret i8 0 ; entry: %alloca = alloca [32 x i8], align 4, addrspace(1) @@ -171,13 +167,11 @@ ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[BB_0:%.*]] ; CHECK: bb.0: -; CHECK-NEXT: [[PTR1:%.*]] = phi ptr [ getelementptr inbounds ([32 x i8], ptr @g1, i64 0, i64 1), [[ENTRY:%.*]] ], [ getelementptr inbounds ([32 x i8], ptr @g1, i64 0, i64 2), [[BB_1:%.*]] ] -; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB_1]], label [[EXIT:%.*]] +; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB_1:%.*]], label [[EXIT:%.*]] ; CHECK: bb.1: ; CHECK-NEXT: br label [[BB_0]] ; CHECK: exit: -; CHECK-NEXT: [[LOAD:%.*]] = load i8, ptr [[PTR1]], align 1 -; CHECK-NEXT: ret i8 [[LOAD]] +; CHECK-NEXT: ret i8 0 ; entry: %alloca = alloca [32 x i8], align 4, addrspace(1) @@ -288,9 +282,7 @@ ; CHECK: if: ; CHECK-NEXT: br label [[JOIN]] ; CHECK: join: -; CHECK-NEXT: [[PHI1:%.*]] = phi ptr addrspace(1) [ @g2, [[IF]] ], [ getelementptr inbounds ([32 x i8], ptr addrspace(1) @g2, i64 0, i64 2), [[ENTRY:%.*]] ] -; CHECK-NEXT: [[V:%.*]] = load i32, ptr addrspace(1) [[PHI1]], align 4 -; CHECK-NEXT: ret i32 [[V]] +; CHECK-NEXT: ret i32 0 ; entry: %a = alloca [32 x i8] diff --git a/llvm/test/Transforms/LoopVectorize/ARM/pointer_iv.ll b/llvm/test/Transforms/LoopVectorize/ARM/pointer_iv.ll --- a/llvm/test/Transforms/LoopVectorize/ARM/pointer_iv.ll +++ b/llvm/test/Transforms/LoopVectorize/ARM/pointer_iv.ll @@ -62,8 +62,8 @@ ; CHECK-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[STRIDED_VEC]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr [[NEXT_GEP4]], align 4 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 -; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], 996 -; CHECK-NEXT: br i1 [[TMP4]], label [[FOR_BODY:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 996 +; CHECK-NEXT: br i1 [[TMP3]], label [[FOR_BODY:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] ; CHECK: for.body: ; CHECK-NEXT: [[A_ADDR_09:%.*]] = phi ptr [ [[ADD_PTR:%.*]], [[FOR_BODY]] ], [ [[IND_END]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[I_08:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 996, [[VECTOR_BODY]] ] @@ -881,62 +881,31 @@ define hidden void @mult_ptr_iv(ptr noalias nocapture readonly %x, ptr noalias nocapture %z) { ; CHECK-LABEL: @mult_ptr_iv( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, ptr [[Z:%.*]], i32 3000 -; CHECK-NEXT: [[UGLYGEP1:%.*]] = getelementptr i8, ptr [[X:%.*]], i32 3000 -; CHECK-NEXT: [[BOUND0:%.*]] = icmp ugt ptr [[UGLYGEP1]], [[Z]] -; CHECK-NEXT: [[BOUND1:%.*]] = icmp ugt ptr [[UGLYGEP]], [[X]] -; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] -; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[FOR_BODY:%.*]], label [[VECTOR_PH:%.*]] -; CHECK: vector.ph: -; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[X]], i32 3000 -; CHECK-NEXT: [[IND_END2:%.*]] = getelementptr i8, ptr [[Z]], i32 3000 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: -; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[X]], [[VECTOR_PH]] ], [ [[PTR_IND:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[POINTER_PHI5:%.*]] = phi ptr [ [[Z]], [[VECTOR_PH]] ], [ [[PTR_IND6:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[PTR_IND:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[POINTER_PHI4:%.*]] = phi ptr [ [[Z:%.*]], [[ENTRY]] ], [ [[PTR_IND5:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[POINTER_PHI]], <4 x i32> -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[POINTER_PHI5]], <4 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[POINTER_PHI4]], <4 x i32> ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, <4 x ptr> [[TMP0]], i32 1 -; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> [[TMP0]], i32 1, <4 x i1> , <4 x i8> poison), !alias.scope !28 +; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> [[TMP0]], i32 1, <4 x i1> , <4 x i8> poison) ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, <4 x ptr> [[TMP0]], i32 2 -; CHECK-NEXT: [[WIDE_MASKED_GATHER7:%.*]] = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> [[TMP2]], i32 1, <4 x i1> , <4 x i8> poison), !alias.scope !28 -; CHECK-NEXT: [[WIDE_MASKED_GATHER8:%.*]] = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> [[TMP3]], i32 1, <4 x i1> , <4 x i8> poison), !alias.scope !28 +; CHECK-NEXT: [[WIDE_MASKED_GATHER6:%.*]] = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> [[TMP2]], i32 1, <4 x i1> , <4 x i8> poison) +; CHECK-NEXT: [[WIDE_MASKED_GATHER7:%.*]] = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> [[TMP3]], i32 1, <4 x i1> , <4 x i8> poison) ; CHECK-NEXT: [[TMP4:%.*]] = mul <4 x i8> [[WIDE_MASKED_GATHER]], -; CHECK-NEXT: [[TMP5:%.*]] = mul <4 x i8> [[WIDE_MASKED_GATHER]], [[WIDE_MASKED_GATHER7]] -; CHECK-NEXT: [[TMP6:%.*]] = mul <4 x i8> [[WIDE_MASKED_GATHER]], [[WIDE_MASKED_GATHER8]] +; CHECK-NEXT: [[TMP5:%.*]] = mul <4 x i8> [[WIDE_MASKED_GATHER]], [[WIDE_MASKED_GATHER6]] +; CHECK-NEXT: [[TMP6:%.*]] = mul <4 x i8> [[WIDE_MASKED_GATHER]], [[WIDE_MASKED_GATHER7]] ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, <4 x ptr> [[TMP1]], i32 1 -; CHECK-NEXT: call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> [[TMP4]], <4 x ptr> [[TMP1]], i32 1, <4 x i1> ), !alias.scope !31, !noalias !28 +; CHECK-NEXT: call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> [[TMP4]], <4 x ptr> [[TMP1]], i32 1, <4 x i1> ) ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, <4 x ptr> [[TMP1]], i32 2 -; CHECK-NEXT: call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> [[TMP5]], <4 x ptr> [[TMP7]], i32 1, <4 x i1> ), !alias.scope !31, !noalias !28 -; CHECK-NEXT: call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> [[TMP6]], <4 x ptr> [[TMP8]], i32 1, <4 x i1> ), !alias.scope !31, !noalias !28 +; CHECK-NEXT: call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> [[TMP5]], <4 x ptr> [[TMP7]], i32 1, <4 x i1> ) +; CHECK-NEXT: call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> [[TMP6]], <4 x ptr> [[TMP8]], i32 1, <4 x i1> ) ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; CHECK-NEXT: [[PTR_IND]] = getelementptr i8, ptr [[POINTER_PHI]], i32 12 -; CHECK-NEXT: [[PTR_IND6]] = getelementptr i8, ptr [[POINTER_PHI5]], i32 12 +; CHECK-NEXT: [[PTR_IND5]] = getelementptr i8, ptr [[POINTER_PHI4]], i32 12 ; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1000 -; CHECK-NEXT: br i1 [[TMP9]], label [[END:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP33:![0-9]+]] -; CHECK: for.body: -; CHECK-NEXT: [[X_ADDR_050:%.*]] = phi ptr [ [[INCDEC_PTR2:%.*]], [[FOR_BODY]] ], [ [[X]], [[ENTRY:%.*]] ] -; CHECK-NEXT: [[Z_ADDR_049:%.*]] = phi ptr [ [[INCDEC_PTR34:%.*]], [[FOR_BODY]] ], [ [[Z]], [[ENTRY]] ] -; CHECK-NEXT: [[I_048:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ] -; CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i8, ptr [[X_ADDR_050]], i32 1 -; CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr [[X_ADDR_050]], align 1 -; CHECK-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds i8, ptr [[X_ADDR_050]], i32 2 -; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr [[INCDEC_PTR]], align 1 -; CHECK-NEXT: [[INCDEC_PTR2]] = getelementptr inbounds i8, ptr [[X_ADDR_050]], i32 3 -; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[INCDEC_PTR1]], align 1 -; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[TMP10]], 10 -; CHECK-NEXT: [[MUL1:%.*]] = mul i8 [[TMP10]], [[TMP11]] -; CHECK-NEXT: [[MUL2:%.*]] = mul i8 [[TMP10]], [[TMP12]] -; CHECK-NEXT: [[INCDEC_PTR32:%.*]] = getelementptr inbounds i8, ptr [[Z_ADDR_049]], i32 1 -; CHECK-NEXT: store i8 [[MUL]], ptr [[Z_ADDR_049]], align 1 -; CHECK-NEXT: [[INCDEC_PTR33:%.*]] = getelementptr inbounds i8, ptr [[Z_ADDR_049]], i32 2 -; CHECK-NEXT: store i8 [[MUL1]], ptr [[INCDEC_PTR32]], align 1 -; CHECK-NEXT: [[INCDEC_PTR34]] = getelementptr inbounds i8, ptr [[Z_ADDR_049]], i32 3 -; CHECK-NEXT: store i8 [[MUL2]], ptr [[INCDEC_PTR33]], align 1 -; CHECK-NEXT: [[INC]] = add nuw i32 [[I_048]], 1 -; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], 1000 -; CHECK-NEXT: br i1 [[EXITCOND]], label [[END]], label [[FOR_BODY]], !llvm.loop [[LOOP34:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP9]], label [[END:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP28:![0-9]+]] ; CHECK: end: ; CHECK-NEXT: ret void ;