diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -442,14 +442,14 @@ } } -multiclass VALU_IV_V_X_I funct6, Operand optype = simm5> { +multiclass VALU_IV_V_X_I funct6> { def V : VALUVV, Sched<[WriteVIALUV_WorstCase, ReadVIALUV_WorstCase, ReadVIALUV_WorstCase, ReadVMask]>; def X : VALUVX, Sched<[WriteVIALUX_WorstCase, ReadVIALUV_WorstCase, ReadVIALUX_WorstCase, ReadVMask]>; - def I : VALUVI, + def I : VALUVI, Sched<[WriteVIALUI_WorstCase, ReadVIALUV_WorstCase, ReadVMask]>; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td @@ -139,7 +139,7 @@ defm VROL_V : VALU_IV_V_X<"vrol", 0b010101>; defm VROR_V : VROR_IV_V_X_I<"vror", 0b010100>; let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in - defm VWSLL_V : VALU_IV_V_X_I<"vwsll", 0b110101, uimm5>; + defm VWSLL_V : VSHT_IV_V_X_I<"vwsll", 0b110101>; } // Predicates = [HasStdExtZvbb] let Predicates = [HasStdExtZvbc] in {