Index: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrMemory.td =================================================================== --- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrMemory.td +++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrMemory.td @@ -25,59 +25,63 @@ let Defs = [ARGUMENTS] in { // Basic load. -def LOAD_I32 : I<(outs I32:$dst), (ins I32:$addr), - [(set I32:$dst, (load I32:$addr))], - "i32.load\t$dst, $addr">; -def LOAD_I64 : I<(outs I64:$dst), (ins I32:$addr), - [(set I64:$dst, (load I32:$addr))], - "i64.load\t$dst, $addr">; -def LOAD_F32 : I<(outs F32:$dst), (ins I32:$addr), - [(set F32:$dst, (load I32:$addr))], - "f32.load\t$dst, $addr">; -def LOAD_F64 : I<(outs F64:$dst), (ins I32:$addr), - [(set F64:$dst, (load I32:$addr))], - "f64.load\t$dst, $addr">; +def LOAD_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [], + "i32.load\t$dst, $off($addr)">; +def LOAD_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [], + "i64.load\t$dst, $off($addr)">; +def LOAD_F32 : I<(outs F32:$dst), (ins I32:$off, I32:$addr), [], + "f32.load\t$dst, $off($addr)">; +def LOAD_F64 : I<(outs F64:$dst), (ins I32:$off, I32:$addr), [], + "f64.load\t$dst, $off($addr)">; // Extending load. -def LOAD8_S_I32 : I<(outs I32:$dst), (ins I32:$addr), - [(set I32:$dst, (sextloadi8 I32:$addr))], - "i32.load8_s\t$dst, $addr">; -def LOAD8_U_I32 : I<(outs I32:$dst), (ins I32:$addr), - [(set I32:$dst, (zextloadi8 I32:$addr))], - "i32.load8_u\t$dst, $addr">; -def LOAD16_S_I32 : I<(outs I32:$dst), (ins I32:$addr), - [(set I32:$dst, (sextloadi16 I32:$addr))], - "i32.load16_s\t$dst, $addr">; -def LOAD16_U_I32 : I<(outs I32:$dst), (ins I32:$addr), - [(set I32:$dst, (zextloadi16 I32:$addr))], - "i32.load16_u\t$dst, $addr">; -def LOAD8_S_I64 : I<(outs I64:$dst), (ins I32:$addr), - [(set I64:$dst, (sextloadi8 I32:$addr))], - "i64.load8_s\t$dst, $addr">; -def LOAD8_U_I64 : I<(outs I64:$dst), (ins I32:$addr), - [(set I64:$dst, (zextloadi8 I32:$addr))], - "i64.load8_u\t$dst, $addr">; -def LOAD16_S_I64 : I<(outs I64:$dst), (ins I32:$addr), - [(set I64:$dst, (sextloadi16 I32:$addr))], - "i64.load16_s\t$dst, $addr">; -def LOAD16_U_I64 : I<(outs I64:$dst), (ins I32:$addr), - [(set I64:$dst, (zextloadi16 I32:$addr))], - "i64.load16_u\t$dst, $addr">; -def LOAD32_S_I64 : I<(outs I64:$dst), (ins I32:$addr), - [(set I64:$dst, (sextloadi32 I32:$addr))], - "i64.load32_s\t$dst, $addr">; -def LOAD32_U_I64 : I<(outs I64:$dst), (ins I32:$addr), - [(set I64:$dst, (zextloadi32 I32:$addr))], - "i64.load32_u\t$dst, $addr">; +def LOAD8_S_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [], + "i32.load8_s\t$dst, $off($addr)">; +def LOAD8_U_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [], + "i32.load8_u\t$dst, $off($addr)">; +def LOAD16_S_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [], + "i32.load16_s\t$dst, $off($addr)">; +def LOAD16_U_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [], + "i32.load16_u\t$dst, $off($addr)">; +def LOAD8_S_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [], + "i64.load8_s\t$dst, $off($addr)">; +def LOAD8_U_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [], + "i64.load8_u\t$dst, $off($addr)">; +def LOAD16_S_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [], + "i64.load16_s\t$dst, $off($addr)">; +def LOAD16_U_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [], + "i64.load16_u\t$dst, $off($addr)">; +def LOAD32_S_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [], + "i64.load32_s\t$dst, $off($addr)">; +def LOAD32_U_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [], + "i64.load32_u\t$dst, $off($addr)">; } // Defs = [ARGUMENTS] +// Select loads with no constant offset. +def : Pat<(i32 (load I32:$addr)), (LOAD_I32 0, $addr)>; +def : Pat<(i64 (load I32:$addr)), (LOAD_I64 0, $addr)>; +def : Pat<(f32 (load I32:$addr)), (LOAD_F32 0, $addr)>; +def : Pat<(f64 (load I32:$addr)), (LOAD_F64 0, $addr)>; + +// Select extending loads with no constant offset. +def : Pat<(i32 (sextloadi8 I32:$addr)), (LOAD8_S_I32 0, $addr)>; +def : Pat<(i32 (zextloadi8 I32:$addr)), (LOAD8_U_I32 0, $addr)>; +def : Pat<(i32 (sextloadi16 I32:$addr)), (LOAD16_S_I32 0, $addr)>; +def : Pat<(i32 (zextloadi16 I32:$addr)), (LOAD16_U_I32 0, $addr)>; +def : Pat<(i64 (sextloadi8 I32:$addr)), (LOAD8_S_I64 0, $addr)>; +def : Pat<(i64 (zextloadi8 I32:$addr)), (LOAD8_U_I64 0, $addr)>; +def : Pat<(i64 (sextloadi16 I32:$addr)), (LOAD16_S_I64 0, $addr)>; +def : Pat<(i64 (zextloadi16 I32:$addr)), (LOAD16_U_I64 0, $addr)>; +def : Pat<(i64 (sextloadi32 I32:$addr)), (LOAD32_S_I64 0, $addr)>; +def : Pat<(i64 (zextloadi32 I32:$addr)), (LOAD32_U_I64 0, $addr)>; + // "Don't care" extending load become zero-extending load. -def : Pat<(i32 (extloadi8 I32:$addr)), (LOAD8_U_I32 $addr)>; -def : Pat<(i32 (extloadi16 I32:$addr)), (LOAD16_U_I32 $addr)>; -def : Pat<(i64 (extloadi8 I32:$addr)), (LOAD8_U_I64 $addr)>; -def : Pat<(i64 (extloadi16 I32:$addr)), (LOAD16_U_I64 $addr)>; -def : Pat<(i64 (extloadi32 I32:$addr)), (LOAD32_U_I64 $addr)>; +def : Pat<(i32 (extloadi8 I32:$addr)), (LOAD8_U_I32 0, $addr)>; +def : Pat<(i32 (extloadi16 I32:$addr)), (LOAD16_U_I32 0, $addr)>; +def : Pat<(i64 (extloadi8 I32:$addr)), (LOAD8_U_I64 0, $addr)>; +def : Pat<(i64 (extloadi16 I32:$addr)), (LOAD16_U_I64 0, $addr)>; +def : Pat<(i64 (extloadi32 I32:$addr)), (LOAD32_U_I64 0, $addr)>; let Defs = [ARGUMENTS] in { @@ -87,48 +91,55 @@ // instruction definition patterns that don't reference all of the output // operands. // Note: WebAssembly inverts SelectionDAG's usual operand order. -def STORE_I32 : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [], - "i32.store\t$dst, $addr, $val">; -def STORE_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [], - "i64.store\t$dst, $addr, $val">; -def STORE_F32 : I<(outs F32:$dst), (ins I32:$addr, F32:$val), [], - "f32.store\t$dst, $addr, $val">; -def STORE_F64 : I<(outs F64:$dst), (ins I32:$addr, F64:$val), [], - "f64.store\t$dst, $addr, $val">; +def STORE_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr, I32:$val), [], + "i32.store\t$dst, $off($addr), $val">; +def STORE_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr, I64:$val), [], + "i64.store\t$dst, $off($addr), $val">; +def STORE_F32 : I<(outs F32:$dst), (ins I32:$off, I32:$addr, F32:$val), [], + "f32.store\t$dst, $off($addr), $val">; +def STORE_F64 : I<(outs F64:$dst), (ins I32:$off, I32:$addr, F64:$val), [], + "f64.store\t$dst, $off($addr), $val">; } // Defs = [ARGUMENTS] -def : Pat<(store I32:$val, I32:$addr), (STORE_I32 I32:$addr, I32:$val)>; -def : Pat<(store I64:$val, I32:$addr), (STORE_I64 I32:$addr, I64:$val)>; -def : Pat<(store F32:$val, I32:$addr), (STORE_F32 I32:$addr, F32:$val)>; -def : Pat<(store F64:$val, I32:$addr), (STORE_F64 I32:$addr, F64:$val)>; +def : Pat<(store I32:$val, I32:$addr), (STORE_I32 0, I32:$addr, I32:$val)>; +def : Pat<(store I64:$val, I32:$addr), (STORE_I64 0, I32:$addr, I64:$val)>; +def : Pat<(store F32:$val, I32:$addr), (STORE_F32 0, I32:$addr, F32:$val)>; +def : Pat<(store F64:$val, I32:$addr), (STORE_F64 0, I32:$addr, F64:$val)>; + +// FIXME: This pattern matches an immediate to actually use the offset field +// in the store instruction; however only unsigned offsets are supported in +// wasm, so we need to constrain the immediate we match. This may require +// custom code rather than a simple pattern. +// def : Pat<(store I32:$val, (add I32:$addr, (i32 imm:$off))), +// (STORE_I32 imm:$off, I32:$addr, I32:$val)>; let Defs = [ARGUMENTS] in { // Truncating store. -def STORE8_I32 : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [], - "i32.store8\t$dst, $addr, $val">; -def STORE16_I32 : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [], - "i32.store16\t$dst, $addr, $val">; -def STORE8_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [], - "i64.store8\t$dst, $addr, $val">; -def STORE16_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [], - "i64.store16\t$dst, $addr, $val">; -def STORE32_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [], - "i64.store32\t$dst, $addr, $val">; +def STORE8_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr, I32:$val), [], + "i32.store8\t$dst, $off($addr), $val">; +def STORE16_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr, I32:$val), [], + "i32.store16\t$dst, $off($addr), $val">; +def STORE8_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr, I64:$val), [], + "i64.store8\t$dst, $off($addr), $val">; +def STORE16_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr, I64:$val), [], + "i64.store16\t$dst, $off($addr), $val">; +def STORE32_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr, I64:$val), [], + "i64.store32\t$dst, $off($addr), $val">; } // Defs = [ARGUMENTS] def : Pat<(truncstorei8 I32:$val, I32:$addr), - (STORE8_I32 I32:$addr, I32:$val)>; + (STORE8_I32 0, I32:$addr, I32:$val)>; def : Pat<(truncstorei16 I32:$val, I32:$addr), - (STORE16_I32 I32:$addr, I32:$val)>; + (STORE16_I32 0, I32:$addr, I32:$val)>; def : Pat<(truncstorei8 I64:$val, I32:$addr), - (STORE8_I64 I32:$addr, I64:$val)>; + (STORE8_I64 0, I32:$addr, I64:$val)>; def : Pat<(truncstorei16 I64:$val, I32:$addr), - (STORE16_I64 I32:$addr, I64:$val)>; + (STORE16_I64 0, I32:$addr, I64:$val)>; def : Pat<(truncstorei32 I64:$val, I32:$addr), - (STORE32_I64 I32:$addr, I64:$val)>; + (STORE32_I64 0, I32:$addr, I64:$val)>; let Defs = [ARGUMENTS] in { Index: llvm/trunk/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp =================================================================== --- llvm/trunk/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp +++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp @@ -88,7 +88,7 @@ case WebAssembly::STORE_I32: case WebAssembly::STORE_I64: unsigned ToReg = MI.getOperand(0).getReg(); - unsigned FromReg = MI.getOperand(2).getReg(); + unsigned FromReg = MI.getOperand(3).getReg(); for (auto I = MRI.use_begin(FromReg), E = MRI.use_end(); I != E;) { MachineOperand &O = *I++; MachineInstr *Where = O.getParent(); Index: llvm/trunk/test/CodeGen/WebAssembly/cfg-stackify.ll =================================================================== --- llvm/trunk/test/CodeGen/WebAssembly/cfg-stackify.ll +++ llvm/trunk/test/CodeGen/WebAssembly/cfg-stackify.ll @@ -184,7 +184,7 @@ ; CHECK-LABEL: minimal_loop: ; CHECK-NOT: br ; CHECK: BB7_1: -; CHECK: i32.store $discard=, $0, $pop{{[0-9]+}}{{$}} +; CHECK: i32.store $discard=, 0($0), $pop{{[0-9]+}}{{$}} ; CHECK: br BB7_1{{$}} ; CHECK: BB7_2: define i32 @minimal_loop(i32* %p) { Index: llvm/trunk/test/CodeGen/WebAssembly/global.ll =================================================================== --- llvm/trunk/test/CodeGen/WebAssembly/global.ll +++ llvm/trunk/test/CodeGen/WebAssembly/global.ll @@ -11,7 +11,7 @@ ; CHECK: foo: ; CHECK: i32.const $push0=, answer{{$}} -; CHECK-NEXT: i32.load $push1=, $pop0{{$}} +; CHECK-NEXT: i32.load $push1=, 0($pop0){{$}} ; CHECK-NEXT: return $pop1{{$}} define i32 @foo() { %a = load i32, i32* @answer Index: llvm/trunk/test/CodeGen/WebAssembly/load-ext.ll =================================================================== --- llvm/trunk/test/CodeGen/WebAssembly/load-ext.ll +++ llvm/trunk/test/CodeGen/WebAssembly/load-ext.ll @@ -6,7 +6,7 @@ target triple = "wasm32-unknown-unknown" ; CHECK-LABEL: sext_i8_i32: -; CHECK: i32.load8_s $push0=, $0{{$}} +; CHECK: i32.load8_s $push0=, 0($0){{$}} ; CHECK-NEXT: return $pop0{{$}} define i32 @sext_i8_i32(i8 *%p) { %v = load i8, i8* %p @@ -15,7 +15,7 @@ } ; CHECK-LABEL: zext_i8_i32: -; CHECK: i32.load8_u $push0=, $0{{$}} +; CHECK: i32.load8_u $push0=, 0($0){{$}} ; CHECK-NEXT: return $pop0{{$}} define i32 @zext_i8_i32(i8 *%p) { %v = load i8, i8* %p @@ -24,7 +24,7 @@ } ; CHECK-LABEL: sext_i16_i32: -; CHECK: i32.load16_s $push0=, $0{{$}} +; CHECK: i32.load16_s $push0=, 0($0){{$}} ; CHECK-NEXT: return $pop0{{$}} define i32 @sext_i16_i32(i16 *%p) { %v = load i16, i16* %p @@ -33,7 +33,7 @@ } ; CHECK-LABEL: zext_i16_i32: -; CHECK: i32.load16_u $push0=, $0{{$}} +; CHECK: i32.load16_u $push0=, 0($0){{$}} ; CHECK-NEXT: return $pop0{{$}} define i32 @zext_i16_i32(i16 *%p) { %v = load i16, i16* %p @@ -42,7 +42,7 @@ } ; CHECK-LABEL: sext_i8_i64: -; CHECK: i64.load8_s $push0=, $0{{$}} +; CHECK: i64.load8_s $push0=, 0($0){{$}} ; CHECK-NEXT: return $pop0{{$}} define i64 @sext_i8_i64(i8 *%p) { %v = load i8, i8* %p @@ -51,7 +51,7 @@ } ; CHECK-LABEL: zext_i8_i64: -; CHECK: i64.load8_u $push0=, $0{{$}} +; CHECK: i64.load8_u $push0=, 0($0){{$}} ; CHECK-NEXT: return $pop0{{$}} define i64 @zext_i8_i64(i8 *%p) { %v = load i8, i8* %p @@ -60,7 +60,7 @@ } ; CHECK-LABEL: sext_i16_i64: -; CHECK: i64.load16_s $push0=, $0{{$}} +; CHECK: i64.load16_s $push0=, 0($0){{$}} ; CHECK-NEXT: return $pop0{{$}} define i64 @sext_i16_i64(i16 *%p) { %v = load i16, i16* %p @@ -69,7 +69,7 @@ } ; CHECK-LABEL: zext_i16_i64: -; CHECK: i64.load16_u $push0=, $0{{$}} +; CHECK: i64.load16_u $push0=, 0($0){{$}} ; CHECK-NEXT: return $pop0{{$}} define i64 @zext_i16_i64(i16 *%p) { %v = load i16, i16* %p @@ -78,7 +78,7 @@ } ; CHECK-LABEL: sext_i32_i64: -; CHECK: i64.load32_s $push0=, $0{{$}} +; CHECK: i64.load32_s $push0=, 0($0){{$}} ; CHECK-NEXT: return $pop0{{$}} define i64 @sext_i32_i64(i32 *%p) { %v = load i32, i32* %p @@ -87,7 +87,7 @@ } ; CHECK-LABEL: zext_i32_i64: -; CHECK: i64.load32_u $push0=, $0{{$}} +; CHECK: i64.load32_u $push0=, 0($0){{$}} ; CHECK: return $pop0{{$}} define i64 @zext_i32_i64(i32 *%p) { %v = load i32, i32* %p Index: llvm/trunk/test/CodeGen/WebAssembly/load-store-i1.ll =================================================================== --- llvm/trunk/test/CodeGen/WebAssembly/load-store-i1.ll +++ llvm/trunk/test/CodeGen/WebAssembly/load-store-i1.ll @@ -6,7 +6,7 @@ target triple = "wasm32-unknown-unknown" ; CHECK-LABEL: load_u_i1_i32: -; CHECK: i32.load8_u $push[[NUM0:[0-9]+]]=, $0{{$}} +; CHECK: i32.load8_u $push[[NUM0:[0-9]+]]=, 0($0){{$}} ; CHECK-NEXT: return $pop[[NUM0]]{{$}} define i32 @load_u_i1_i32(i1* %p) { %v = load i1, i1* %p @@ -15,7 +15,7 @@ } ; CHECK-LABEL: load_s_i1_i32: -; CHECK: i32.load8_u $push[[NUM0:[0-9]+]]=, $0{{$}} +; CHECK: i32.load8_u $push[[NUM0:[0-9]+]]=, 0($0){{$}} ; CHECK-NEXT: i32.const $[[NUM1:[0-9]+]]=, 31{{$}} ; CHECK-NEXT: shl $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $[[NUM1]]{{$}} ; CHECK-NEXT: shr_s $push[[NUM3:[0-9]+]]=, $pop[[NUM2]], $[[NUM1]]{{$}} @@ -27,7 +27,7 @@ } ; CHECK-LABEL: load_u_i1_i64: -; CHECK: i64.load8_u $push[[NUM0:[0-9]+]]=, $0{{$}} +; CHECK: i64.load8_u $push[[NUM0:[0-9]+]]=, 0($0){{$}} ; CHECK-NEXT: return $pop[[NUM0]]{{$}} define i64 @load_u_i1_i64(i1* %p) { %v = load i1, i1* %p @@ -36,7 +36,7 @@ } ; CHECK-LABEL: load_s_i1_i64: -; CHECK: i64.load8_u $push[[NUM0:[0-9]+]]=, $0{{$}} +; CHECK: i64.load8_u $push[[NUM0:[0-9]+]]=, 0($0){{$}} ; CHECK-NEXT: i64.const $[[NUM1:[0-9]+]]=, 63{{$}} ; CHECK-NEXT: shl $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $[[NUM1]]{{$}} ; CHECK-NEXT: shr_s $push[[NUM3:[0-9]+]]=, $pop[[NUM2]], $[[NUM1]]{{$}} @@ -50,7 +50,7 @@ ; CHECK-LABEL: store_i32_i1: ; CHECK: i32.const $push[[NUM0:[0-9]+]]=, 1{{$}} ; CHECK-NEXT: i32.and $push[[NUM1:[0-9]+]]=, $1, $pop[[NUM0]]{{$}} -; CHECK-NEXT: i32.store8 $discard=, $0, $pop[[NUM1]]{{$}} +; CHECK-NEXT: i32.store8 $discard=, 0($0), $pop[[NUM1]]{{$}} define void @store_i32_i1(i1* %p, i32 %v) { %t = trunc i32 %v to i1 store i1 %t, i1* %p @@ -60,7 +60,7 @@ ; CHECK-LABEL: store_i64_i1: ; CHECK: i64.const $push[[NUM0:[0-9]+]]=, 1{{$}} ; CHECK-NEXT: i64.and $push[[NUM1:[0-9]+]]=, $1, $pop[[NUM0]]{{$}} -; CHECK-NEXT: i64.store8 $discard=, $0, $pop[[NUM1]]{{$}} +; CHECK-NEXT: i64.store8 $discard=, 0($0), $pop[[NUM1]]{{$}} define void @store_i64_i1(i1* %p, i64 %v) { %t = trunc i64 %v to i1 store i1 %t, i1* %p Index: llvm/trunk/test/CodeGen/WebAssembly/load.ll =================================================================== --- llvm/trunk/test/CodeGen/WebAssembly/load.ll +++ llvm/trunk/test/CodeGen/WebAssembly/load.ll @@ -8,7 +8,7 @@ ; CHECK-LABEL: ldi32: ; CHECK-NEXT: .param i32{{$}} ; CHECK-NEXT: .result i32{{$}} -; CHECK-NEXT: i32.load $push[[NUM:[0-9]+]]=, $0{{$}} +; CHECK-NEXT: i32.load $push[[NUM:[0-9]+]]=, 0($0){{$}} ; CHECK-NEXT: return $pop[[NUM]]{{$}} define i32 @ldi32(i32 *%p) { %v = load i32, i32* %p @@ -18,7 +18,7 @@ ; CHECK-LABEL: ldi64: ; CHECK-NEXT: .param i32{{$}} ; CHECK-NEXT: .result i64{{$}} -; CHECK-NEXT: i64.load $push[[NUM:[0-9]+]]=, $0{{$}} +; CHECK-NEXT: i64.load $push[[NUM:[0-9]+]]=, 0($0){{$}} ; CHECK-NEXT: return $pop[[NUM]]{{$}} define i64 @ldi64(i64 *%p) { %v = load i64, i64* %p @@ -28,7 +28,7 @@ ; CHECK-LABEL: ldf32: ; CHECK-NEXT: .param i32{{$}} ; CHECK-NEXT: .result f32{{$}} -; CHECK-NEXT: f32.load $push[[NUM:[0-9]+]]=, $0{{$}} +; CHECK-NEXT: f32.load $push[[NUM:[0-9]+]]=, 0($0){{$}} ; CHECK-NEXT: return $pop[[NUM]]{{$}} define float @ldf32(float *%p) { %v = load float, float* %p @@ -38,7 +38,7 @@ ; CHECK-LABEL: ldf64: ; CHECK-NEXT: .param i32{{$}} ; CHECK-NEXT: .result f64{{$}} -; CHECK-NEXT: f64.load $push[[NUM:[0-9]+]]=, $0{{$}} +; CHECK-NEXT: f64.load $push[[NUM:[0-9]+]]=, 0($0){{$}} ; CHECK-NEXT: return $pop[[NUM]]{{$}} define double @ldf64(double *%p) { %v = load double, double* %p Index: llvm/trunk/test/CodeGen/WebAssembly/store-results.ll =================================================================== --- llvm/trunk/test/CodeGen/WebAssembly/store-results.ll +++ llvm/trunk/test/CodeGen/WebAssembly/store-results.ll @@ -9,7 +9,7 @@ ; CHECK-LABEL: single_block: ; CHECK-NOT: .local ; CHECK: i32.const $push{{[0-9]+}}=, 0 -; CHECK: i32.store $push[[STORE:[0-9]+]]=, $0, $pop{{[0-9]+}} +; CHECK: i32.store $push[[STORE:[0-9]+]]=, 0($0), $pop{{[0-9]+}} ; CHECK: return $pop[[STORE]]{{$}} define i32 @single_block(i32* %p) { entry: @@ -26,7 +26,7 @@ @pos = global %class.Vec3 zeroinitializer, align 4 ; CHECK-LABEL: foo: -; CHECK: i32.store $discard=, $pop0, $0 +; CHECK: i32.store $discard=, 0($pop0), $0 define void @foo() { for.body.i: br label %for.body5.i @@ -44,7 +44,7 @@ } ; CHECK-LABEL: bar: -; CHECK: i32.store $discard=, $0, $pop0 +; CHECK: i32.store $discard=, 0($0), $pop0 define void @bar() { for.body.i: br label %for.body5.i Index: llvm/trunk/test/CodeGen/WebAssembly/store-trunc.ll =================================================================== --- llvm/trunk/test/CodeGen/WebAssembly/store-trunc.ll +++ llvm/trunk/test/CodeGen/WebAssembly/store-trunc.ll @@ -6,7 +6,7 @@ target triple = "wasm32-unknown-unknown" ; CHECK-LABEL: trunc_i8_i32: -; CHECK: i32.store8 $discard=, $0, $1{{$}} +; CHECK: i32.store8 $discard=, 0($0), $1{{$}} define void @trunc_i8_i32(i8 *%p, i32 %v) { %t = trunc i32 %v to i8 store i8 %t, i8* %p @@ -14,7 +14,7 @@ } ; CHECK-LABEL: trunc_i16_i32: -; CHECK: i32.store16 $discard=, $0, $1{{$}} +; CHECK: i32.store16 $discard=, 0($0), $1{{$}} define void @trunc_i16_i32(i16 *%p, i32 %v) { %t = trunc i32 %v to i16 store i16 %t, i16* %p @@ -22,7 +22,7 @@ } ; CHECK-LABEL: trunc_i8_i64: -; CHECK: i64.store8 $discard=, $0, $1{{$}} +; CHECK: i64.store8 $discard=, 0($0), $1{{$}} define void @trunc_i8_i64(i8 *%p, i64 %v) { %t = trunc i64 %v to i8 store i8 %t, i8* %p @@ -30,7 +30,7 @@ } ; CHECK-LABEL: trunc_i16_i64: -; CHECK: i64.store16 $discard=, $0, $1{{$}} +; CHECK: i64.store16 $discard=, 0($0), $1{{$}} define void @trunc_i16_i64(i16 *%p, i64 %v) { %t = trunc i64 %v to i16 store i16 %t, i16* %p @@ -38,7 +38,7 @@ } ; CHECK-LABEL: trunc_i32_i64: -; CHECK: i64.store32 $discard=, $0, $1{{$}} +; CHECK: i64.store32 $discard=, 0($0), $1{{$}} define void @trunc_i32_i64(i32 *%p, i64 %v) { %t = trunc i64 %v to i32 store i32 %t, i32* %p Index: llvm/trunk/test/CodeGen/WebAssembly/store.ll =================================================================== --- llvm/trunk/test/CodeGen/WebAssembly/store.ll +++ llvm/trunk/test/CodeGen/WebAssembly/store.ll @@ -7,7 +7,7 @@ ; CHECK-LABEL: sti32: ; CHECK-NEXT: .param i32, i32{{$}} -; CHECK-NEXT: i32.store $discard=, $0, $1{{$}} +; CHECK-NEXT: i32.store $discard=, 0($0), $1{{$}} ; CHECK-NEXT: return{{$}} define void @sti32(i32 *%p, i32 %v) { store i32 %v, i32* %p @@ -16,7 +16,7 @@ ; CHECK-LABEL: sti64: ; CHECK-NEXT: .param i32, i64{{$}} -; CHECK-NEXT: i64.store $discard=, $0, $1{{$}} +; CHECK-NEXT: i64.store $discard=, 0($0), $1{{$}} ; CHECK-NEXT: return{{$}} define void @sti64(i64 *%p, i64 %v) { store i64 %v, i64* %p @@ -25,7 +25,7 @@ ; CHECK-LABEL: stf32: ; CHECK-NEXT: .param i32, f32{{$}} -; CHECK-NEXT: f32.store $discard=, $0, $1{{$}} +; CHECK-NEXT: f32.store $discard=, 0($0), $1{{$}} ; CHECK-NEXT: return{{$}} define void @stf32(float *%p, float %v) { store float %v, float* %p @@ -34,7 +34,7 @@ ; CHECK-LABEL: stf64: ; CHECK-NEXT: .param i32, f64{{$}} -; CHECK-NEXT: f64.store $discard=, $0, $1{{$}} +; CHECK-NEXT: f64.store $discard=, 0($0), $1{{$}} ; CHECK-NEXT: return{{$}} define void @stf64(double *%p, double %v) { store double %v, double* %p Index: llvm/trunk/test/CodeGen/WebAssembly/varargs.ll =================================================================== --- llvm/trunk/test/CodeGen/WebAssembly/varargs.ll +++ llvm/trunk/test/CodeGen/WebAssembly/varargs.ll @@ -32,8 +32,8 @@ ; CHECK-LABEL: copy: ; CHECK-NEXT: .param i32, i32{{$}} -; CHECK-NEXT: i32.load $push0=, $1{{$}} -; CHECK-NEXT: i32.store $discard=, $0, $pop0{{$}} +; CHECK-NEXT: i32.load $push0=, 0($1){{$}} +; CHECK-NEXT: i32.store $discard=, 0($0), $pop0{{$}} ; CHECK-NEXT: return{{$}} define void @copy(i8** %ap, i8** %bp) { entry: @@ -49,11 +49,11 @@ ; CHECK-NEXT: .param i32{{$}} ; CHECK-NEXT: .result i32{{$}} ; CHECK-NEXT: .local i32{{$}} -; CHECK-NEXT: i32.load $1=, $0{{$}} +; CHECK-NEXT: i32.load $1=, 0($0){{$}} ; CHECK-NEXT: i32.const $push0=, 4{{$}} ; CHECK-NEXT: i32.add $push1=, $1, $pop0{{$}} -; CHECK-NEXT: i32.store $discard=, $0, $pop1{{$}} -; CHECK-NEXT: i32.load $push2=, $1{{$}} +; CHECK-NEXT: i32.store $discard=, 0($0), $pop1{{$}} +; CHECK-NEXT: i32.load $push2=, 0($1){{$}} ; CHECK-NEXT: return $pop2{{$}} define i8 @arg_i8(i8** %ap) { entry: @@ -67,15 +67,15 @@ ; CHECK-NEXT: .param i32{{$}} ; CHECK-NEXT: .result i32{{$}} ; CHECK-NEXT: .local i32{{$}} -; CHECK-NEXT: i32.load $push0=, $0{{$}} +; CHECK-NEXT: i32.load $push0=, 0($0){{$}} ; CHECK-NEXT: i32.const $push1=, 3{{$}} ; CHECK-NEXT: i32.add $push2=, $pop0, $pop1{{$}} ; CHECK-NEXT: i32.const $push3=, -4{{$}} ; CHECK-NEXT: i32.and $1=, $pop2, $pop3{{$}} ; CHECK-NEXT: i32.const $push4=, 4{{$}} ; CHECK-NEXT: i32.add $push5=, $1, $pop4{{$}} -; CHECK-NEXT: i32.store $discard=, $0, $pop5{{$}} -; CHECK-NEXT: i32.load $push6=, $1{{$}} +; CHECK-NEXT: i32.store $discard=, 0($0), $pop5{{$}} +; CHECK-NEXT: i32.load $push6=, 0($1){{$}} ; CHECK-NEXT: return $pop6{{$}} define i32 @arg_i32(i8** %ap) { entry: