diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -50,7 +50,7 @@ // Crypto has been split up and any combination is now valid (see the // crypto definitions above). Also, crypto is now context sensitive: // it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. -// Therefore, we rely on Clang, the user interacing tool, to pass on the +// Therefore, we rely on Clang, the user interfacing tool, to pass on the // appropriate crypto options. But here in the backend, crypto has very little // meaning anymore. We kept the Crypto definition here for backward // compatibility, and now imply features SHA2 and AES, which was the @@ -745,6 +745,7 @@ include "AArch64SchedTSV110.td" include "AArch64SchedAmpere1.td" include "AArch64SchedNeoverseN2.td" +include "AArch64SchedNeoverseV2.td" def TuneA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", "Cortex-A35 ARM processors">; @@ -1392,7 +1393,7 @@ ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>; def : ProcessorModel<"neoverse-v1", NeoverseN2Model, ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>; -def : ProcessorModel<"neoverse-v2", NeoverseN2Model, +def : ProcessorModel<"neoverse-v2", NeoverseV2Model, ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>; def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3, [TuneExynosM3]>; diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -114,6 +114,9 @@ /// Returns whether the instruction is FP or NEON. static bool isFpOrNEON(const MachineInstr &MI); + /// Returns whether the instruction is in H form (16 bit operands) + static bool isHForm(const MachineInstr &MI); + /// Returns whether the instruction is in Q form (128 bit operands) static bool isQForm(const MachineInstr &MI); diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -3256,6 +3256,20 @@ return MF ? MF->getRegInfo().getRegClassOrNull(Reg) : nullptr; } +bool AArch64InstrInfo::isHForm(const MachineInstr &MI) { + auto IsHFPR = [&](const MachineOperand &Op) { + if (!Op.isReg()) + return false; + auto Reg = Op.getReg(); + if (Reg.isPhysical()) + return AArch64::FPR16RegClass.contains(Reg); + const TargetRegisterClass *TRC = ::getRegClass(MI, Reg); + return TRC == &AArch64::FPR16RegClass || + TRC == &AArch64::FPR16_loRegClass; + }; + return llvm::any_of(MI.operands(), IsHFPR); +} + bool AArch64InstrInfo::isQForm(const MachineInstr &MI) { auto IsQFPR = [&](const MachineOperand &Op) { if (!Op.isReg()) diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td @@ -0,0 +1,2814 @@ +//=- AArch64SchedNeoverseV2.td - NeoverseV2 Scheduling Defs --*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the scheduling model for the Arm Neoverse V2 processors. +// All information is taken from the V2 Software Optimisation guide: +// +// https://developer.arm.com/documentation/PJDOC-466751330-593177/r0p2 +// +//===----------------------------------------------------------------------===// + +def NeoverseV2Model : SchedMachineModel { + let IssueWidth = 16; // Micro-ops dispatched at a time. + let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer. NOTE: Copied from N2. + let LoadLatency = 4; // Optimistic load latency. + let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2. + let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57. + let CompleteModel = 1; + + list UnsupportedFeatures = !listconcat(SMEUnsupported.F, + [HasSVE2p1]); +} + +//===----------------------------------------------------------------------===// +// Define each kind of processor resource and number available on Neoverse V2. +// Instructions are first fetched and then decoded into internal macro-ops +// (MOPs). From there, the MOPs proceed through register renaming and dispatch +// stages. A MOP can be split into two micro-ops further down the pipeline +// after the decode stage. Once dispatched, micro-ops wait for their operands +// and issue out-of-order to one of seventeen issue pipelines. Each issue +// pipeline can accept one micro-op per cycle. + +let SchedModel = NeoverseV2Model in { + +// Define the (17) issue ports. +def V2UnitB : ProcResource<2>; // Branch 0/1 +def V2UnitS0 : ProcResource<1>; // Integer single-cycle 0 +def V2UnitS1 : ProcResource<1>; // Integer single-cycle 1 +def V2UnitS2 : ProcResource<1>; // Integer single-cycle 2 +def V2UnitS3 : ProcResource<1>; // Integer single-cycle 3 +def V2UnitM0 : ProcResource<1>; // Integer single/multicycle 0 +def V2UnitM1 : ProcResource<1>; // Integer single/multicycle 1 +def V2UnitV0 : ProcResource<1>; // FP/ASIMD 0 +def V2UnitV1 : ProcResource<1>; // FP/ASIMD 1 +def V2UnitV2 : ProcResource<1>; // FP/ASIMD 2 +def V2UnitV3 : ProcResource<1>; // FP/ASIMD 3 +def V2UnitL01 : ProcResource<2>; // Load/Store 0/1 +def V2UnitL2 : ProcResource<1>; // Load 2 +def V2UnitD : ProcResource<2>; // Store data 0/1 + +def V2UnitR : ProcResGroup<[V2UnitS0, V2UnitS1]>; // Integer single-cycle 0/1 +def V2UnitS : ProcResGroup<[V2UnitS0, V2UnitS1, V2UnitS2, V2UnitS3]>; // Integer single-cycle 0/1/2/3 +def V2UnitF : ProcResGroup<[V2UnitS0, V2UnitS1, V2UnitM0, V2UnitM1]>; // Integer single-cycle 0/1 and single/multicycle 0/1 +def V2UnitI : ProcResGroup<[V2UnitS0, V2UnitS1, V2UnitS2, V2UnitS3, V2UnitM0, V2UnitM1]>; // Integer single-cycle 0/1/2/3 and single/multicycle 0/1 +def V2UnitM : ProcResGroup<[V2UnitM0, V2UnitM1]>; // Integer single/multicycle 0/1 +def V2UnitL : ProcResGroup<[V2UnitL01, V2UnitL2]>; // Load/Store 0/1 and Load 2 +def V2UnitV : ProcResGroup<[V2UnitV0, V2UnitV1, V2UnitV2, V2UnitV3]>; // FP/ASIMD 0/1/2/3 +def V2UnitV01 : ProcResGroup<[V2UnitV0, V2UnitV1]>; // FP/ASIMD 0/1 +def V2UnitV02 : ProcResGroup<[V2UnitV0, V2UnitV2]>; // FP/ASIMD 0/2 +def V2UnitV13 : ProcResGroup<[V2UnitV1, V2UnitV3]>; // FP/ASIMD 1/3 +def V2UnitV23 : ProcResGroup<[V2UnitV2, V2UnitV3]>; // FP/ASIMD 2/3 + +// Define commonly used read types. + +// No forwarding is provided for these types. +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + +// NOTE: Copied from N2. +def : WriteRes { let Unsupported = 1; } +def : WriteRes { let Latency = 1; } +def : WriteRes { let Latency = 1; } +def : WriteRes { let Latency = 4; } + +//===----------------------------------------------------------------------===// +// Define customized scheduler read/write types specific to the Neoverse V2. + +//===----------------------------------------------------------------------===// +// Define generic 1 micro-op types + +def V2Write_1cyc_1B : SchedWriteRes<[V2UnitB]> { let Latency = 1; } +def V2Write_1cyc_1F : SchedWriteRes<[V2UnitF]> { let Latency = 1; } +def V2Write_1cyc_1I : SchedWriteRes<[V2UnitI]> { let Latency = 1; } +def V2Write_1cyc_1M : SchedWriteRes<[V2UnitM]> { let Latency = 1; } +def V2Write_1cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 1; } +def V2Write_1cyc_1L01 : SchedWriteRes<[V2UnitL01]> { let Latency = 1; } +def V2Write_2cyc_1M : SchedWriteRes<[V2UnitM]> { let Latency = 2; } +def V2Write_3cyc_1M : SchedWriteRes<[V2UnitM]> { let Latency = 3; } +def V2Write_2cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 2; } +def V2Write_3cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 3; } +def V2Write_5cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 5; } +def V2Write_12cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 12; + let ResourceCycles = [12]; } +def V2Write_20cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 20; + let ResourceCycles = [20]; } +def V2Write_4cyc_1L : SchedWriteRes<[V2UnitL]> { let Latency = 4; } +def V2Write_6cyc_1L : SchedWriteRes<[V2UnitL]> { let Latency = 6; } +def V2Write_2cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 2; } +def V2Write_2cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 2; } +def V2Write_2cyc_1V01 : SchedWriteRes<[V2UnitV01]> { let Latency = 2; } +def V2Write_2cyc_1V23 : SchedWriteRes<[V2UnitV23]> { let Latency = 2; } +def V2Write_3cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 3; } +def V2Write_3cyc_1V01 : SchedWriteRes<[V2UnitV01]> { let Latency = 3; + let ResourceCycles = [2]; } +def V2Write_3cyc_1V23 : SchedWriteRes<[V2UnitV23]> { let Latency = 3; } +def V2Write_4cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 4; } +def V2Write_5cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 5; } +def V2Write_6cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 6; } +def V2Write_12cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 12; } +def V2Write_3cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 3; } +def V2Write_3cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 3; } +def V2Write_4cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 4; } +def V2Write_4cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 4; } +def V2Write_7cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 7; + let ResourceCycles = [7]; } +def V2Write_7cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 7; + let ResourceCycles = [2]; } +def V2Write_9cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 9; } +def V2Write_9cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 9; + let ResourceCycles = [2]; } +def V2Write_10cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 10; } +def V2Write_10cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 10; + let ResourceCycles = [2]; } +def V2Write_12cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 12; + let ResourceCycles = [11]; } +def V2Write_13cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 13; } +def V2Write_15cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 15; } +def V2Write_15cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 15; + let ResourceCycles = [8]; } +def V2Write_16cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 16; } +def V2Write_16cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 16; + let ResourceCycles = [8]; } +def V2Write_20cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 20; + let ResourceCycles = [20]; } +def V2Write_2cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 2; } +def V2Write_2cyc_1V13 : SchedWriteRes<[V2UnitV13]> { let Latency = 2; } +def V2Write_3cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 3; } +def V2Write_4cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 4; } +def V2Write_4cyc_1V13 : SchedWriteRes<[V2UnitV13]> { let Latency = 4; } +def V2Write_6cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 6; } +def V2Write_10cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 10; } +def V2Write_6cyc_1L01 : SchedWriteRes<[V2UnitL01]> { let Latency = 6; } + +//===----------------------------------------------------------------------===// +// Define generic 2 micro-op types + +def V2Write_1cyc_1B_1R : SchedWriteRes<[V2UnitB, V2UnitR]> { + let Latency = 1; + let NumMicroOps = 2; +} + +def V2Write_6cyc_1M0_1B : SchedWriteRes<[V2UnitM0, V2UnitB]> { + let Latency = 6; + let NumMicroOps = 2; +} + +def V2Write_9cyc_1M0_1L : SchedWriteRes<[V2UnitM0, V2UnitL]> { + let Latency = 9; + let NumMicroOps = 2; +} + +def V2Write_3cyc_1I_1M : SchedWriteRes<[V2UnitI, V2UnitM]> { + let Latency = 3; + let NumMicroOps = 2; +} + +def V2Write_1cyc_2M : SchedWriteRes<[V2UnitM, V2UnitM]> { + let Latency = 1; + let NumMicroOps = 2; +} + +def V2Write_3cyc_2M : SchedWriteRes<[V2UnitM, V2UnitM]> { + let Latency = 3; + let NumMicroOps = 2; +} + +def V2Write_4cyc_2M : SchedWriteRes<[V2UnitM, V2UnitM]> { + let Latency = 4; + let NumMicroOps = 2; +} + +def V2Write_5cyc_1L_1F : SchedWriteRes<[V2UnitL, V2UnitF]> { + let Latency = 5; + let NumMicroOps = 2; +} + +def V2Write_6cyc_1I_1L : SchedWriteRes<[V2UnitI, V2UnitL]> { + let Latency = 6; + let NumMicroOps = 2; +} + +def V2Write_7cyc_1F_1L : SchedWriteRes<[V2UnitF, V2UnitL]> { + let Latency = 7; + let NumMicroOps = 2; +} + +def V2Write_7cyc_1I_1L : SchedWriteRes<[V2UnitI, V2UnitL]> { + let Latency = 7; + let NumMicroOps = 2; +} + +def V2Write_1cyc_1L01_1D : SchedWriteRes<[V2UnitL01, V2UnitD]> { + let Latency = 1; + let NumMicroOps = 2; +} + +def V2Write_5cyc_1M0_1V : SchedWriteRes<[V2UnitM0, V2UnitV]> { + let Latency = 5; + let NumMicroOps = 2; +} + +def V2Write_2cyc_1L01_1V01 : SchedWriteRes<[V2UnitL01, V2UnitV01]> { + let Latency = 2; + let NumMicroOps = 2; +} + +def V2Write_2cyc_1L01_1V : SchedWriteRes<[V2UnitL01, V2UnitV]> { + let Latency = 2; + let NumMicroOps = 2; +} + +def V2Write_2cyc_2V01 : SchedWriteRes<[V2UnitV01, V2UnitV01]> { + let Latency = 2; + let NumMicroOps = 2; +} + +def V2Write_4cyc_2V01 : SchedWriteRes<[V2UnitV01, V2UnitV01]> { + let Latency = 4; + let NumMicroOps = 2; +} + +def V2Write_4cyc_1L01_1V01 : SchedWriteRes<[V2UnitL01, V2UnitV01]> { + let Latency = 4; + let NumMicroOps = 2; +} + +def V2Write_4cyc_1V13_1V : SchedWriteRes<[V2UnitV13, V2UnitV]> { + let Latency = 4; + let NumMicroOps = 2; +} + +def V2Write_4cyc_2V0 : SchedWriteRes<[V2UnitV0, V2UnitV0]> { + let Latency = 4; + let NumMicroOps = 2; +} + +def V2Write_4cyc_2V02 : SchedWriteRes<[V2UnitV02, V2UnitV02]> { + let Latency = 4; + let NumMicroOps = 2; +} + +def V2Write_4cyc_2V : SchedWriteRes<[V2UnitV, V2UnitV]> { + let Latency = 4; + let NumMicroOps = 2; +} + +def V2Write_6cyc_2V : SchedWriteRes<[V2UnitV, V2UnitV]> { + let Latency = 6; + let NumMicroOps = 2; +} + +def V2Write_6cyc_2L : SchedWriteRes<[V2UnitL, V2UnitL]> { + let Latency = 6; + let NumMicroOps = 2; +} + +def V2Write_8cyc_1L_1V : SchedWriteRes<[V2UnitL, V2UnitV]> { + let Latency = 8; + let NumMicroOps = 2; +} + +def V2Write_4cyc_1L01_1V : SchedWriteRes<[V2UnitL01, V2UnitV]> { + let Latency = 4; + let NumMicroOps = 2; +} + +def V2Write_3cyc_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> { + let Latency = 3; + let NumMicroOps = 2; +} + +def V2Write_4cyc_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> { + let Latency = 4; + let NumMicroOps = 2; +} + +def V2Write_1cyc_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> { + let Latency = 1; + let NumMicroOps = 2; +} + +def V2Write_2cyc_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> { + let Latency = 2; + let NumMicroOps = 2; +} + +def V2Write_6cyc_2V1 : SchedWriteRes<[V2UnitV1, V2UnitV1]> { + let Latency = 6; + let NumMicroOps = 2; +} + +def V2Write_4cyc_1V0_1M0 : SchedWriteRes<[V2UnitV0, V2UnitM0]> { + let Latency = 4; + let NumMicroOps = 2; +} + +def V2Write_5cyc_1V0_1M0 : SchedWriteRes<[V2UnitV0, V2UnitM0]> { + let Latency = 5; + let NumMicroOps = 2; +} + +def V2Write_5cyc_2V0 : SchedWriteRes<[V2UnitV0, V2UnitV0]> { + let Latency = 5; + let NumMicroOps = 2; +} + +def V2Write_5cyc_2V02 : SchedWriteRes<[V2UnitV02, V2UnitV02]> { + let Latency = 5; + let NumMicroOps = 2; +} + +def V2Write_6cyc_1V1_1M0 : SchedWriteRes<[V2UnitV1, V2UnitM0]> { + let Latency = 6; + let NumMicroOps = 2; +} + +def V2Write_7cyc_1M0_1V02 : SchedWriteRes<[V2UnitM0, V2UnitV02]> { + let Latency = 7; + let NumMicroOps = 2; +} + +def V2Write_2cyc_1V0_1M : SchedWriteRes<[V2UnitV0, V2UnitM]> { + let Latency = 2; + let NumMicroOps = 2; +} + +def V2Write_3cyc_1V0_1M : SchedWriteRes<[V2UnitV0, V2UnitM]> { + let Latency = 3; + let NumMicroOps = 2; +} + +def V2Write_6cyc_1V_1V13 : SchedWriteRes<[V2UnitV, V2UnitV13]> { + let Latency = 6; + let NumMicroOps = 2; +} + +def V2Write_6cyc_1L_1M : SchedWriteRes<[V2UnitL, V2UnitM]> { + let Latency = 6; + let NumMicroOps = 2; +} + +def V2Write_6cyc_1L_1S : SchedWriteRes<[V2UnitL, V2UnitS]> { + let Latency = 6; + let NumMicroOps = 2; +} + +def V2Write_4cyc_2V13 : SchedWriteRes<[V2UnitV13, V2UnitV13]> { + let Latency = 4; + let NumMicroOps = 2; +} + +def V2Write_8cyc_1M0_1V01 : SchedWriteRes<[V2UnitM0, V2UnitV01]> { + let Latency = 8; + let NumMicroOps = 2; +} + +//===----------------------------------------------------------------------===// +// Define generic 3 micro-op types + +def V2Write_1cyc_1L01_1D_1I : SchedWriteRes<[V2UnitL01, V2UnitD, V2UnitI]> { + let Latency = 1; + let NumMicroOps = 3; +} + +def V2Write_2cyc_1L01_1V01_1I : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitI]> { + let Latency = 2; + let NumMicroOps = 3; +} + +def V2Write_2cyc_1L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01]> { + let Latency = 2; + let NumMicroOps = 3; +} + +def V2Write_4cyc_1L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01]> { + let Latency = 4; + let NumMicroOps = 3; +} + +def V2Write_9cyc_1L_2V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV]> { + let Latency = 9; + let NumMicroOps = 3; +} + +def V2Write_4cyc_3V01 : SchedWriteRes<[V2UnitV01, V2UnitV01, V2UnitV01]> { + let Latency = 4; + let NumMicroOps = 3; +} + +def V2Write_7cyc_1M_1M0_1V : SchedWriteRes<[V2UnitM, V2UnitM0, V2UnitV]> { + let Latency = 7; + let NumMicroOps = 3; +} + +def V2Write_2cyc_1L01_1S_1V : SchedWriteRes<[V2UnitL01, V2UnitS, V2UnitV]> { + let Latency = 2; + let NumMicroOps = 3; +} + +def V2Write_2cyc_1L01_1S_1V01 : SchedWriteRes<[V2UnitL01, V2UnitS, V2UnitV01]> { + let Latency = 2; + let NumMicroOps = 3; +} + +def V2Write_6cyc_3L : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL]> { + let Latency = 6; + let NumMicroOps = 3; +} + +def V2Write_6cyc_3V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV]> { + let Latency = 6; + let NumMicroOps = 3; +} + +def V2Write_8cyc_1L_2V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV]> { + let Latency = 8; + let NumMicroOps = 3; +} + +//===----------------------------------------------------------------------===// +// Define generic 4 micro-op types + +def V2Write_2cyc_1L01_2V01_1I : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01, + V2UnitI]> { + let Latency = 2; + let NumMicroOps = 4; +} + +def V2Write_2cyc_2L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, + V2UnitV01, V2UnitV01]> { + let Latency = 2; + let NumMicroOps = 4; +} + +def V2Write_4cyc_2L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, + V2UnitV01, V2UnitV01]> { + let Latency = 4; + let NumMicroOps = 4; +} + +def V2Write_5cyc_1I_3L : SchedWriteRes<[V2UnitI, V2UnitL, V2UnitL, V2UnitL]> { + let Latency = 5; + let NumMicroOps = 4; +} + +def V2Write_9cyc_2L_2V1 : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV1, + V2UnitV1]> { + let Latency = 9; + let NumMicroOps = 4; +} + +def V2Write_6cyc_4V0 : SchedWriteRes<[V2UnitV0, V2UnitV0, V2UnitV0, V2UnitV0]> { + let Latency = 6; + let NumMicroOps = 4; +} + +def V2Write_8cyc_4V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, V2UnitV]> { + let Latency = 8; + let NumMicroOps = 4; +} + +def V2Write_6cyc_2V_2V13 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV13, + V2UnitV13]> { + let Latency = 6; + let NumMicroOps = 4; +} + +def V2Write_8cyc_2V_2V13 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV13, + V2UnitV13]> { + let Latency = 8; + let NumMicroOps = 4; +} + +def V2Write_6cyc_4V02 : SchedWriteRes<[V2UnitV02, V2UnitV02, V2UnitV02, + V2UnitV02]> { + let Latency = 6; + let NumMicroOps = 4; +} + +def V2Write_6cyc_4V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, V2UnitV]> { + let Latency = 6; + let NumMicroOps = 4; +} + +def V2Write_8cyc_2L_2V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, V2UnitV]> { + let Latency = 8; + let NumMicroOps = 4; +} + +def V2Write_9cyc_2L_2V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, V2UnitV]> { + let Latency = 9; + let NumMicroOps = 4; +} + +def V2Write_2cyc_2L01_2V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV, + V2UnitV]> { + let Latency = 2; + let NumMicroOps = 4; +} + +def V2Write_4cyc_2L01_2V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV, + V2UnitV]> { + let Latency = 4; + let NumMicroOps = 4; +} + +def V2Write_8cyc_2M0_2V02 : SchedWriteRes<[V2UnitM0, V2UnitM0, V2UnitV02, + V2UnitV02]> { + let Latency = 8; + let NumMicroOps = 4; +} + +def V2Write_8cyc_2V_2V1 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV1, + V2UnitV1]> { + let Latency = 8; + let NumMicroOps = 4; +} + +def V2Write_4cyc_2M0_2M : SchedWriteRes<[V2UnitM0, V2UnitM0, V2UnitM, + V2UnitM]> { + let Latency = 4; + let NumMicroOps = 4; +} + +def V2Write_5cyc_2M0_2M : SchedWriteRes<[V2UnitM0, V2UnitM0, V2UnitM, + V2UnitM]> { + let Latency = 5; + let NumMicroOps = 4; +} + +def V2Write_6cyc_2I_2L : SchedWriteRes<[V2UnitI, V2UnitI, V2UnitL, V2UnitL]> { + let Latency = 6; + let NumMicroOps = 4; +} + +def V2Write_7cyc_4L : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL]> { + let Latency = 7; + let NumMicroOps = 4; +} + +def V2Write_6cyc_1L01_3V01 : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01, + V2UnitV01]> { + let Latency = 6; + let NumMicroOps = 4; +} + +//===----------------------------------------------------------------------===// +// Define generic 5 micro-op types + +def V2Write_2cyc_1L01_2V01_2I : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01, + V2UnitI, V2UnitI]> { + let Latency = 2; + let NumMicroOps = 5; +} + +def V2Write_8cyc_2L_3V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, V2UnitV, + V2UnitV]> { + let Latency = 8; + let NumMicroOps = 5; +} + +def V2Write_9cyc_1L_4V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV, V2UnitV, + V2UnitV]> { + let Latency = 9; + let NumMicroOps = 5; +} + +def V2Write_10cyc_1L_4V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV, V2UnitV, + V2UnitV]> { + let Latency = 10; + let NumMicroOps = 5; +} + +def V2Write_6cyc_5V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, V2UnitV, + V2UnitV]> { + let Latency = 6; + let NumMicroOps = 5; +} + +//===----------------------------------------------------------------------===// +// Define generic 6 micro-op types + +def V2Write_8cyc_3L_3V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, + V2UnitV, V2UnitV, V2UnitV]> { + let Latency = 8; + let NumMicroOps = 6; +} + +def V2Write_9cyc_3L_3V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, + V2UnitV, V2UnitV, V2UnitV]> { + let Latency = 9; + let NumMicroOps = 6; +} + +def V2Write_9cyc_2L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, + V2UnitV, V2UnitV, V2UnitV]> { + let Latency = 9; + let NumMicroOps = 6; +} + +def V2Write_9cyc_2L_2V_2S : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, + V2UnitV, V2UnitS, V2UnitS]> { + let Latency = 9; + let NumMicroOps = 6; +} + +def V2Write_9cyc_2V_4V13 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV13, + V2UnitV13, V2UnitV13, V2UnitV13]> { + let Latency = 9; + let NumMicroOps = 6; +} + +def V2Write_2cyc_3L01_3V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitV, V2UnitV, V2UnitV]> { + let Latency = 2; + let NumMicroOps = 6; +} + +def V2Write_4cyc_2L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV01, + V2UnitV01, V2UnitV01, V2UnitV01]> { + let Latency = 4; + let NumMicroOps = 6; +} + +def V2Write_5cyc_2L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV01, + V2UnitV01, V2UnitV01, V2UnitV01]> { + let Latency = 5; + let NumMicroOps = 6; +} + +def V2Write_2cyc_3L01_3V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitV01, V2UnitV01, V2UnitV01]> { + let Latency = 2; + let NumMicroOps = 6; +} + +def V2Write_4cyc_2L01_2S_2V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitS, + V2UnitS, V2UnitV01, V2UnitV01]> { + let Latency = 4; + let NumMicroOps = 6; +} + +//===----------------------------------------------------------------------===// +// Define generic 7 micro-op types + +def V2Write_8cyc_3L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, + V2UnitV, V2UnitV, V2UnitV, V2UnitV]> { + let Latency = 8; + let NumMicroOps = 7; +} + +//===----------------------------------------------------------------------===// +// Define generic 8 micro-op types + +def V2Write_2cyc_4L01_4V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitV, V2UnitV, V2UnitV, + V2UnitV]> { + let Latency = 2; + let NumMicroOps = 8; +} + +def V2Write_2cyc_4L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01]> { + let Latency = 2; + let NumMicroOps = 8; +} + +def V2Write_4cyc_4L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01]> { + let Latency = 4; + let NumMicroOps = 8; +} + +def V2Write_6cyc_2L01_6V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV01, + V2UnitV01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01]> { + let Latency = 6; + let NumMicroOps = 8; +} + +def V2Write_8cyc_4L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL, + V2UnitV, V2UnitV, V2UnitV, V2UnitV]> { + let Latency = 8; + let NumMicroOps = 8; +} + +//===----------------------------------------------------------------------===// +// Define generic 9 micro-op types + +def V2Write_6cyc_3L01_6V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitV01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, V2UnitV01]> { + let Latency = 6; + let NumMicroOps = 9; +} + +def V2Write_10cyc_1L_8V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV, V2UnitV, + V2UnitV, V2UnitV, V2UnitV, V2UnitV, + V2UnitV]> { + let Latency = 10; + let NumMicroOps = 9; +} + +def V2Write_10cyc_3V_3L_3S : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, + V2UnitL, V2UnitL, V2UnitL, + V2UnitS, V2UnitS, V2UnitS]> { + let Latency = 10; + let NumMicroOps = 9; +} + +//===----------------------------------------------------------------------===// +// Define generic 10 micro-op types + +def V2Write_9cyc_6L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL, + V2UnitL, V2UnitL, V2UnitV, V2UnitV, + V2UnitV, V2UnitV]> { + let Latency = 9; + let NumMicroOps = 10; +} + +//===----------------------------------------------------------------------===// +// Define generic 12 micro-op types + +def V2Write_5cyc_4L01_8V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, V2UnitV01]> { + let Latency = 5; + let NumMicroOps = 12; +} + +def V2Write_9cyc_4L_8V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, + V2UnitL, V2UnitV, V2UnitV, + V2UnitV, V2UnitV, V2UnitV, + V2UnitV, V2UnitV, V2UnitV]> { + let Latency = 9; + let NumMicroOps = 12; +} + +def V2Write_10cyc_4L_8V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, + V2UnitL, V2UnitV, V2UnitV, + V2UnitV, V2UnitV, V2UnitV, + V2UnitV, V2UnitV, V2UnitV]> { + let Latency = 10; + let NumMicroOps = 12; +} + +//===----------------------------------------------------------------------===// +// Define generic 16 micro-op types + +def V2Write_7cyc_4L01_12V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, V2UnitV01, + V2UnitV01]> { + let Latency = 7; + let NumMicroOps = 16; +} + +def V2Write_10cyc_4L_8V_4S : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, + V2UnitL, V2UnitV, V2UnitV, + V2UnitV, V2UnitV, V2UnitV, + V2UnitV, V2UnitV, V2UnitV, + V2UnitS, V2UnitS, V2UnitS, + V2UnitS]> { + let Latency = 10; + let NumMicroOps = 16; +} + +//===----------------------------------------------------------------------===// +// Define generic 18 micro-op types + +def V2Write_7cyc_9L01_9V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitV01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, V2UnitV01]> { + let Latency = 7; + let NumMicroOps = 18; +} + +//===----------------------------------------------------------------------===// +// Define generic 27 micro-op types + +def V2Write_7cyc_9L01_9S_9V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitS, V2UnitS, V2UnitS, + V2UnitS, V2UnitS, V2UnitS, + V2UnitS, V2UnitS, V2UnitS, + V2UnitV01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, + V2UnitV01]> { + let Latency = 7; + let NumMicroOps = 27; +} + +//===----------------------------------------------------------------------===// +// Define generic 36 micro-op types + +def V2Write_11cyc_18L01_18V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, V2UnitL01, + V2UnitV01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, + V2UnitV01]> { + let Latency = 11; + let NumMicroOps = 36; +} + +//===----------------------------------------------------------------------===// +// Define generic 54 micro-op types + +def V2Write_11cyc_18L01_18S_18V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, + V2UnitL01, V2UnitL01, + V2UnitS, V2UnitS, V2UnitS, + V2UnitS, V2UnitS, V2UnitS, + V2UnitS, V2UnitS, V2UnitS, + V2UnitS, V2UnitS, V2UnitS, + V2UnitS, V2UnitS, V2UnitS, + V2UnitS, V2UnitS, V2UnitS, + V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01, + V2UnitV01, V2UnitV01]> { + let Latency = 11; + let NumMicroOps = 54; +} + +//===----------------------------------------------------------------------===// +// Define predicate-controlled types + +def V2Write_ArithI : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def V2Write_ArithF : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def V2Write_Logical : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def V2Write_Extr : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def V2Write_LdrHQ : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def V2Write_StrHQ : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def V2Write_2or3cyc_1M : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def V2Write_3or4cyc_2M : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def V2Write_1or2cyc_1M0 : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def V2Write_2or3cyc_1M0 : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def V2Write_1or2cyc_1M0_1M : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def V2Write_3or4cyc_1M0_1M : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def V2Write_4or5cyc_2M0_2M : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def V2Write_4or5cyc_1V0_1M0 : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def V2Write_2or3cyc_1V0_1M : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def V2Write_IncDec : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +//===----------------------------------------------------------------------===// +// Define forwarded types + +// NOTE: SOG, p. 16, n. 2: Accumulator forwarding is not supported for +// consumers of 64 bit multiply high operations? +def V2Wr_IM : SchedWriteRes<[V2UnitM]> { let Latency = 2; } +def V2Wr_IMA : SchedWriteRes<[V2UnitM0]> { let Latency = 2; } +def V2Wr_IMUL : SchedWriteVariant<[ + SchedVar, + SchedVar]>; +def V2Rd_IMA : SchedReadAdvance<1, [V2Wr_IMA]>; + +def V2Wr_FMA : SchedWriteRes<[V2UnitV]> { let Latency = 4; } +def V2Rd_FMA : SchedReadAdvance<2, [WriteFMul, V2Wr_FMA]>; + +def V2Wr_VA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; } +def V2Rd_VA : SchedReadAdvance<3, [V2Wr_VA]>; + +def V2Wr_VDOT : SchedWriteRes<[V2UnitV]> { let Latency = 3; } +def V2Rd_VDOT : SchedReadAdvance<2, [V2Wr_VDOT]>; + +def V2Wr_VMMA : SchedWriteRes<[V2UnitV]> { let Latency = 3; } +def V2Rd_VMMA : SchedReadAdvance<2, [V2Wr_VMMA]>; + +def V2Wr_VMA : SchedWriteRes<[V2UnitV02]> { let Latency = 4; } +def V2Rd_VMA : SchedReadAdvance<3, [V2Wr_VMA]>; + +def V2Wr_VMAH : SchedWriteRes<[V2UnitV02, V2UnitV02]> { let Latency = 4; } +def V2Rd_VMAH : SchedReadAdvance<2, [V2Wr_VMAH]>; + +def V2Wr_VMAL : SchedWriteRes<[V2UnitV02]> { let Latency = 4; } +def V2Rd_VMAL : SchedReadAdvance<3, [V2Wr_VMAL]>; + +def V2Wr_VPA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; } +def V2Rd_VPA : SchedReadAdvance<3, [V2Wr_VPA]>; + +def V2Wr_VSA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; } +def V2Rd_VSA : SchedReadAdvance<3, [V2Wr_VSA]>; + +def V2Wr_VFCMA : SchedWriteRes<[V2UnitV]> { let Latency = 4; } +def V2Rd_VFCMA : SchedReadAdvance<2, [V2Wr_VFCMA]>; + +def V2Wr_VFM : SchedWriteRes<[V2UnitV]> { let Latency = 3; } +def V2Wr_VFMA : SchedWriteRes<[V2UnitV]> { let Latency = 4; } +def V2Rd_VFMA : SchedReadAdvance<2, [V2Wr_VFM, V2Wr_VFMA]>; + +def V2Wr_VFMAL : SchedWriteRes<[V2UnitV]> { let Latency = 4; } +def V2Rd_VFMAL : SchedReadAdvance<2, [V2Wr_VFMAL]>; + +def V2Wr_VBFDOT : SchedWriteRes<[V2UnitV]> { let Latency = 5; } +def V2Rd_VBFDOT : SchedReadAdvance<2, [V2Wr_VBFDOT]>; +def V2Wr_VBFMMA : SchedWriteRes<[V2UnitV]> { let Latency = 6; } +def V2Rd_VBFMMA : SchedReadAdvance<2, [V2Wr_VBFMMA]>; +def V2Wr_VBFMAL : SchedWriteRes<[V2UnitV]> { let Latency = 5; } +def V2Rd_VBFMAL : SchedReadAdvance<3, [V2Wr_VBFMAL]>; + +def V2Wr_CRC : SchedWriteRes<[V2UnitM0]> { let Latency = 2; } +def V2Rd_CRC : SchedReadAdvance<1, [V2Wr_CRC]>; + +def V2Wr_ZA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; } +def V2Rd_ZA : SchedReadAdvance<3, [V2Wr_ZA]>; +def V2Wr_ZPA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; } +def V2Rd_ZPA : SchedReadAdvance<3, [V2Wr_ZPA]>; +def V2Wr_ZSA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; } +def V2Rd_ZSA : SchedReadAdvance<3, [V2Wr_ZSA]>; + +def V2Wr_ZDOTB : SchedWriteRes<[V2UnitV]> { let Latency = 3; } +def V2Rd_ZDOTB : SchedReadAdvance<2, [V2Wr_ZDOTB]>; +def V2Wr_ZDOTH : SchedWriteRes<[V2UnitV02]> { let Latency = 4; } +def V2Rd_ZDOTH : SchedReadAdvance<3, [V2Wr_ZDOTH]>; + +// NOTE: SOG p. 43: Complex multiply-add B, H, S element size: How to reduce +// throughput to 1 in case of forwarding? +def V2Wr_ZCMABHS : SchedWriteRes<[V2UnitV02]> { let Latency = 4; } +def V2Rd_ZCMABHS : SchedReadAdvance<3, [V2Wr_ZCMABHS]>; +def V2Wr_ZCMAD : SchedWriteRes<[V2UnitV02, V2UnitV02]> { let Latency = 5; } +def V2Rd_ZCMAD : SchedReadAdvance<2, [V2Wr_ZCMAD]>; + +def V2Wr_ZMMA : SchedWriteRes<[V2UnitV]> { let Latency = 3; } +def V2Rd_ZMMA : SchedReadAdvance<2, [V2Wr_ZMMA]>; + +def V2Wr_ZMABHS : SchedWriteRes<[V2UnitV02, V2UnitV02]> { let Latency = 4; } +def V2Rd_ZMABHS : SchedReadAdvance<3, [V2Wr_ZMABHS]>; +def V2Wr_ZMAD : SchedWriteRes<[V2UnitV02, V2UnitV02]> { let Latency = 5; } +def V2Rd_ZMAD : SchedReadAdvance<2, [V2Wr_ZMAD]>; + +def V2Wr_ZMAL : SchedWriteRes<[V2UnitV02]> { let Latency = 4; } +def V2Rd_ZMAL : SchedReadAdvance<3, [V2Wr_ZMAL]>; + +def V2Wr_ZMASQL : SchedWriteRes<[V2UnitV02]> { let Latency = 4; } +def V2Wr_ZMASQBHS : SchedWriteRes<[V2UnitV02]> { let Latency = 4; } +def V2Wr_ZMASQD : SchedWriteRes<[V2UnitV02, V2UnitV02]> { let Latency = 5; } +def V2Rd_ZMASQ : SchedReadAdvance<2, [V2Wr_ZMASQL, V2Wr_ZMASQBHS, + V2Wr_ZMASQD]>; + +def V2Wr_ZFCMA : SchedWriteRes<[V2UnitV]> { let Latency = 5; } +def V2Rd_ZFCMA : SchedReadAdvance<3, [V2Wr_ZFCMA]>; + +def V2Wr_ZFMA : SchedWriteRes<[V2UnitV]> { let Latency = 4; } +def V2Rd_ZFMA : SchedReadAdvance<2, [V2Wr_ZFMA]>; + +def V2Wr_ZFMAL : SchedWriteRes<[V2UnitV]> { let Latency = 4; } +def V2Rd_ZFMAL : SchedReadAdvance<2, [V2Wr_ZFMAL]>; + +def V2Wr_ZBFDOT : SchedWriteRes<[V2UnitV]> { let Latency = 5; } +def V2Rd_ZBFDOT : SchedReadAdvance<2, [V2Wr_ZBFDOT]>; +def V2Wr_ZBFMMA : SchedWriteRes<[V2UnitV]> { let Latency = 6; } +def V2Rd_ZBFMMA : SchedReadAdvance<2, [V2Wr_ZBFMMA]>; +def V2Wr_ZBFMAL : SchedWriteRes<[V2UnitV]> { let Latency = 5; } +def V2Rd_ZBFMAL : SchedReadAdvance<3, [V2Wr_ZBFMAL]>; + +//===----------------------------------------------------------------------===// +// Define types with long resource cycles (rc) + +def V2Write_6cyc_1V1_5rc : SchedWriteRes<[V2UnitV1]> { let Latency = 6; let ResourceCycles = [ 5]; } +def V2Write_7cyc_1V02_7rc : SchedWriteRes<[V2UnitV02]> { let Latency = 7; let ResourceCycles = [ 7]; } +def V2Write_10cyc_1V02_5rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ResourceCycles = [ 5]; } +def V2Write_10cyc_1V02_9rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ResourceCycles = [ 9]; } +def V2Write_10cyc_1V02_10rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ResourceCycles = [10]; } +def V2Write_10cyc_1V0_9rc : SchedWriteRes<[V2UnitV0]> { let Latency = 10; let ResourceCycles = [ 9]; } +def V2Write_10cyc_1V1_9rc : SchedWriteRes<[V2UnitV1]> { let Latency = 10; let ResourceCycles = [ 9]; } +def V2Write_13cyc_1V0_12rc : SchedWriteRes<[V2UnitV0]> { let Latency = 13; let ResourceCycles = [12]; } +def V2Write_13cyc_1V02_12rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ResourceCycles = [12]; } +def V2Write_13cyc_1V02_13rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ResourceCycles = [13]; } +def V2Write_15cyc_1V02_14rc : SchedWriteRes<[V2UnitV02]> { let Latency = 15; let ResourceCycles = [14]; } +def V2Write_16cyc_1V02_15rc : SchedWriteRes<[V2UnitV02]> { let Latency = 16; let ResourceCycles = [15]; } +def V2Write_16cyc_1V0_14rc : SchedWriteRes<[V2UnitV0]> { let Latency = 16; let ResourceCycles = [14]; } + +// Miscellaneous +// ----------------------------------------------------------------------------- + +def : InstRW<[WriteI], (instrs COPY)>; + +// §3.3 Branch instructions +// ----------------------------------------------------------------------------- + +// Branch, immed +// Compare and branch +def : SchedAlias; + +// Branch, register +def : SchedAlias; + +// Branch and link, immed +// Branch and link, register +def : InstRW<[V2Write_1cyc_1B_1R], (instrs BL, BLR)>; + +// §3.4 Arithmetic and Logical Instructions +// ----------------------------------------------------------------------------- + +// ALU, basic +// ALU, basic, flagset +def : SchedAlias; +def : InstRW<[V2Write_1cyc_1F], + (instregex "^(ADC|SBC)S[WX]r$")>; + +// ALU, extend and shift +def : SchedAlias; + +// Arithmetic, LSL shift, shift <= 4 +// Arithmetic, flagset, LSL shift, shift <= 4 +// Arithmetic, LSR/ASR/ROR shift or LSL shift > 4 +def : SchedAlias; +def : InstRW<[V2Write_ArithF], + (instregex "^(ADD|SUB)S[WX]rs$")>; + +// Arithmetic, immediate to logical address tag +def : InstRW<[V2Write_2cyc_1M], (instrs ADDG, SUBG)>; + +// Convert floating-point condition flags +// Flag manipulation instructions +def : WriteRes { let Latency = 1; } + +// Insert Random Tags +def : InstRW<[V2Write_2cyc_1M], (instrs IRG, IRGstack)>; + +// Insert Tag Mask +// Subtract Pointer +// Subtract Pointer, flagset +def : InstRW<[V2Write_1cyc_1I], (instrs GMI, SUBP, SUBPS)>; + +// Logical, shift, no flagset +def : InstRW<[V2Write_1cyc_1I], + (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>; + +// Logical, shift, flagset +def : InstRW<[V2Write_Logical], (instregex "^(AND|BIC)S[WX]rs$")>; + +// Move and shift instructions +// ----------------------------------------------------------------------------- + +def : SchedAlias; + +// §3.5 Divide and multiply instructions +// ----------------------------------------------------------------------------- + +// SDIV, UDIV +def : SchedAlias; +def : SchedAlias; + +def : SchedAlias; +def : SchedAlias; + +// Multiply +// Multiply accumulate, W-form +// Multiply accumulate, X-form +def : InstRW<[V2Wr_IMUL, ReadIM, ReadIM, V2Rd_IMA], + (instregex "^M(ADD|SUB)[WX]rrr$")>; + +// Multiply accumulate long +// Multiply long +def : InstRW<[V2Wr_IMUL, ReadIM, ReadIM, V2Rd_IMA], + (instregex "^(S|U)M(ADD|SUB)Lrrr$")>; + +// Multiply high +def : InstRW<[V2Write_3cyc_1M], (instrs SMULHrr, UMULHrr)>; + +// Pointer Authentication Instructions (v8.3 PAC) +// ----------------------------------------------------------------------------- + +// Authenticate data address +// Authenticate instruction address +// Compute pointer authentication code for data address +// Compute pointer authentication code, using generic key +// Compute pointer authentication code for instruction address +def : InstRW<[V2Write_5cyc_1M0], (instregex "^AUT", "^PAC")>; + +// Branch and link, register, with pointer authentication +// Branch, register, with pointer authentication +// Branch, return, with pointer authentication +def : InstRW<[V2Write_6cyc_1M0_1B], (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ, BRAA, + BRAAZ, BRAB, BRABZ, RETAA, RETAB, + ERETAA, ERETAB)>; + + +// Load register, with pointer authentication +def : InstRW<[V2Write_9cyc_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>; + +// Strip pointer authentication code +def : InstRW<[V2Write_2cyc_1M0], (instrs XPACD, XPACI, XPACLRI)>; + +// Miscellaneous data-processing instructions +// ----------------------------------------------------------------------------- + +// Address generation +def : InstRW<[V2Write_1cyc_1F], (instrs ADR, ADRP)>; + +// Bitfield extract, one reg +// Bitfield extract, two regs +def : SchedAlias; +def : InstRW<[V2Write_Extr], (instrs EXTRWrri, EXTRXrri)>; + +// Bitfield move, basic +def : SchedAlias; + +// Bitfield move, insert +def : InstRW<[V2Write_2cyc_1M], (instregex "^BFM[WX]ri$")>; + +// Load instructions +// ----------------------------------------------------------------------------- + +// NOTE: SOG p. 19: Throughput of LDN?P X-form should be 2, but reported as 3. + +def : SchedAlias; +def : SchedAlias; + +// Load register, literal +def : InstRW<[V2Write_5cyc_1L_1F], (instrs LDRWl, LDRXl, LDRSWl, PRFMl)>; + +// Load pair, signed immed offset, signed words +def : InstRW<[V2Write_5cyc_1I_3L, WriteLDHi], (instrs LDPSWi)>; + +// Load pair, immed post-index or immed pre-index, signed words +def : InstRW<[V2Write_5cyc_1I_3L, WriteLDHi, WriteAdr], + (instregex "^LDPSW(post|pre)$")>; + +// Store instructions +// ----------------------------------------------------------------------------- + +// NOTE: SOG, p. 20: Unsure if STRH uses pipeline I. + +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; +def : SchedAlias; // copied from A57. + +// Tag load instructions +// ----------------------------------------------------------------------------- + +// Load allocation tag +// Load multiple allocation tags +def : InstRW<[V2Write_4cyc_1L], (instrs LDG, LDGM)>; + +// Tag store instructions +// ----------------------------------------------------------------------------- + +// Store allocation tags to one or two granules, post-index +// Store allocation tags to one or two granules, pre-index +// Store allocation tag to one or two granules, zeroing, post-index +// Store Allocation Tag to one or two granules, zeroing, pre-index +// Store allocation tag and reg pair to memory, post-Index +// Store allocation tag and reg pair to memory, pre-Index +def : InstRW<[V2Write_1cyc_1L01_1D_1I], (instrs STGPreIndex, STGPostIndex, + ST2GPreIndex, ST2GPostIndex, + STZGPreIndex, STZGPostIndex, + STZ2GPreIndex, STZ2GPostIndex, + STGPpre, STGPpost)>; + +// Store allocation tags to one or two granules, signed offset +// Store allocation tag to two granules, zeroing, signed offset +// Store allocation tag and reg pair to memory, signed offset +// Store multiple allocation tags +def : InstRW<[V2Write_1cyc_1L01_1D], (instrs STGi, ST2Gi, STZGi, + STZ2Gi, STGPi, STGM, STZGM)>; + +// FP data processing instructions +// ----------------------------------------------------------------------------- + +// FP absolute value +// FP arithmetic +// FP min/max +// FP negate +// FP select +def : SchedAlias; + +// FP compare +def : SchedAlias; + +// FP divide, square root +def : SchedAlias; + +// FP divide, H-form +def : InstRW<[V2Write_7cyc_1V02], (instrs FDIVHrr)>; +// FP divide, S-form +def : InstRW<[V2Write_10cyc_1V02], (instrs FDIVSrr)>; +// FP divide, D-form +def : InstRW<[V2Write_15cyc_1V02], (instrs FDIVDrr)>; + +// FP square root, H-form +def : InstRW<[V2Write_7cyc_1V02], (instrs FSQRTHr)>; +// FP square root, S-form +def : InstRW<[V2Write_9cyc_1V02], (instrs FSQRTSr)>; +// FP square root, D-form +def : InstRW<[V2Write_16cyc_1V02], (instrs FSQRTDr)>; + +// FP multiply +def : WriteRes { let Latency = 3; } + +// FP multiply accumulate +def : InstRW<[V2Wr_FMA, ReadDefault, ReadDefault, V2Rd_FMA], + (instregex "^FN?M(ADD|SUB)[HSD]rrr$")>; + +// FP round to integral +def : InstRW<[V2Write_3cyc_1V02], (instregex "^FRINT[AIMNPXZ][HSD]r$", + "^FRINT(32|64)[XZ][SD]r$")>; + +// FP miscellaneous instructions +// ----------------------------------------------------------------------------- + +// FP convert, from gen to vec reg +def : InstRW<[V2Write_3cyc_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>; + +// FP convert, from vec to gen reg +def : InstRW<[V2Write_3cyc_1V01], + (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]ri?$")>; + +// FP convert, Javascript from vec to gen reg +def : SchedAlias; + +// FP convert, from vec to vec reg +def : InstRW<[V2Write_3cyc_1V02], (instrs FCVTSHr, FCVTDHr, FCVTHSr, FCVTDSr, + FCVTHDr, FCVTSDr, FCVTXNv1i64)>; + +// FP move, immed +// FP move, register +def : SchedAlias; + +// FP transfer, from gen to low half of vec reg +def : InstRW<[V2Write_3cyc_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>; + +// FP transfer, from gen to high half of vec reg +def : InstRW<[V2Write_5cyc_1M0_1V], (instrs FMOVXDHighr)>; + +// FP transfer, from vec to gen reg +def : SchedAlias; + +// FP load instructions +// ----------------------------------------------------------------------------- + +// Load vector reg, literal, S/D/Q forms +def : InstRW<[V2Write_7cyc_1F_1L], (instregex "^LDR[SDQ]l$")>; + +// Load vector reg, unscaled immed +def : InstRW<[V2Write_6cyc_1L], (instregex "^LDUR[BHSDQ]i$")>; + +// Load vector reg, immed post-index +// Load vector reg, immed pre-index +def : InstRW<[V2Write_6cyc_1I_1L, WriteAdr], + (instregex "^LDR[BHSDQ](pre|post)$")>; + +// Load vector reg, unsigned immed +def : InstRW<[V2Write_6cyc_1L], (instregex "^LDR[BHSDQ]ui$")>; + +// Load vector reg, register offset, basic +// Load vector reg, register offset, scale, S/D-form +// Load vector reg, register offset, scale, H/Q-form +// Load vector reg, register offset, extend +// Load vector reg, register offset, extend, scale, S/D-form +// Load vector reg, register offset, extend, scale, H/Q-form +def : InstRW<[V2Write_LdrHQ, ReadAdrBase], (instregex "^LDR[BHSDQ]ro[WX]$")>; + +// Load vector pair, immed offset, S/D-form +def : InstRW<[V2Write_6cyc_1L, WriteLDHi], (instregex "^LDN?P[SD]i$")>; + +// Load vector pair, immed offset, Q-form +def : InstRW<[V2Write_6cyc_2L, WriteLDHi], (instrs LDPQi, LDNPQi)>; + +// Load vector pair, immed post-index, S/D-form +// Load vector pair, immed pre-index, S/D-form +def : InstRW<[V2Write_6cyc_1I_1L, WriteLDHi, WriteAdr], + (instregex "^LDP[SD](pre|post)$")>; + +// Load vector pair, immed post-index, Q-form +// Load vector pair, immed pre-index, Q-form +def : InstRW<[V2Write_6cyc_2I_2L, WriteLDHi, WriteAdr], (instrs LDPQpost, + LDPQpre)>; + +// FP store instructions +// ----------------------------------------------------------------------------- + +// Store vector reg, unscaled immed, B/H/S/D-form +// Store vector reg, unscaled immed, Q-form +def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^STUR[BHSDQ]i$")>; + +// Store vector reg, immed post-index, B/H/S/D-form +// Store vector reg, immed post-index, Q-form +// Store vector reg, immed pre-index, B/H/S/D-form +// Store vector reg, immed pre-index, Q-form +def : InstRW<[WriteAdr, V2Write_2cyc_1L01_1V01_1I], + (instregex "^STR[BHSDQ](pre|post)$")>; + +// Store vector reg, unsigned immed, B/H/S/D-form +// Store vector reg, unsigned immed, Q-form +def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^STR[BHSDQ]ui$")>; + +// Store vector reg, register offset, basic, B/H/S/D-form +// Store vector reg, register offset, basic, Q-form +// Store vector reg, register offset, scale, H-form +// Store vector reg, register offset, scale, S/D-form +// Store vector reg, register offset, scale, Q-form +// Store vector reg, register offset, extend, B/H/S/D-form +// Store vector reg, register offset, extend, Q-form +// Store vector reg, register offset, extend, scale, H-form +// Store vector reg, register offset, extend, scale, S/D-form +// Store vector reg, register offset, extend, scale, Q-form +def : InstRW<[V2Write_StrHQ, ReadAdrBase], + (instregex "^STR[BHSDQ]ro[WX]$")>; + +// Store vector pair, immed offset, S-form +// Store vector pair, immed offset, D-form +def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^STN?P[SD]i$")>; + +// Store vector pair, immed offset, Q-form +def : InstRW<[V2Write_2cyc_1L01_2V01], (instrs STPQi, STNPQi)>; + +// Store vector pair, immed post-index, S-form +// Store vector pair, immed post-index, D-form +// Store vector pair, immed pre-index, S-form +// Store vector pair, immed pre-index, D-form +def : InstRW<[WriteAdr, V2Write_2cyc_1L01_1V01_1I], + (instregex "^STP[SD](pre|post)$")>; + +// Store vector pair, immed post-index, Q-form +def : InstRW<[V2Write_2cyc_1L01_2V01_1I], (instrs STPQpost)>; + +// Store vector pair, immed pre-index, Q-form +def : InstRW<[V2Write_2cyc_1L01_2V01_2I], (instrs STPQpre)>; + +// ASIMD integer instructions +// ----------------------------------------------------------------------------- + +// ASIMD absolute diff +// ASIMD absolute diff long +// ASIMD arith, basic +// ASIMD arith, complex +// ASIMD arith, pair-wise +// ASIMD compare +// ASIMD logical +// ASIMD max/min, basic and pair-wise +def : SchedAlias; +def : SchedAlias; + +// ASIMD absolute diff accum +// ASIMD absolute diff accum long +def : InstRW<[V2Wr_VA, V2Rd_VA], (instregex "^[SU]ABAL?v")>; + +// ASIMD arith, reduce, 4H/4S +def : InstRW<[V2Write_2cyc_1V13], (instregex "^(ADDV|[SU]ADDLV)v4(i16|i32)v$")>; + +// ASIMD arith, reduce, 8B/8H +def : InstRW<[V2Write_4cyc_1V13_1V], + (instregex "^(ADDV|[SU]ADDLV)v8(i8|i16)v$")>; + +// ASIMD arith, reduce, 16B +def : InstRW<[V2Write_4cyc_2V13], (instregex "^(ADDV|[SU]ADDLV)v16i8v$")>; + +// ASIMD dot product +// ASIMD dot product using signed and unsigned integers +def : InstRW<[V2Wr_VDOT, V2Rd_VDOT], + (instregex "^([SU]|SU|US)DOT(lane)?(v8|v16)i8$")>; + +// ASIMD matrix multiply-accumulate +def : InstRW<[V2Wr_VMMA, V2Rd_VMMA], (instrs SMMLA, UMMLA, USMMLA)>; + +// ASIMD max/min, reduce, 4H/4S +def : InstRW<[V2Write_2cyc_1V13], (instregex "^[SU](MAX|MIN)Vv4i16v$", + "^[SU](MAX|MIN)Vv4i32v$")>; + +// ASIMD max/min, reduce, 8B/8H +def : InstRW<[V2Write_4cyc_1V13_1V], (instregex "^[SU](MAX|MIN)Vv8i8v$", + "^[SU](MAX|MIN)Vv8i16v$")>; + +// ASIMD max/min, reduce, 16B +def : InstRW<[V2Write_4cyc_2V13], (instregex "[SU](MAX|MIN)Vv16i8v$")>; + +// ASIMD multiply +def : InstRW<[V2Write_4cyc_1V02], (instregex "^MULv", "^SQ(R)?DMULHv")>; + +// ASIMD multiply accumulate +def : InstRW<[V2Wr_VMA, V2Rd_VMA], (instregex "^MLAv", "^MLSv")>; + +// ASIMD multiply accumulate high +def : InstRW<[V2Wr_VMAH, V2Rd_VMAH], (instregex "^SQRDMLAHv", "^SQRDMLSHv")>; + +// ASIMD multiply accumulate long +def : InstRW<[V2Wr_VMAL, V2Rd_VMAL], (instregex "^[SU]MLALv", "^[SU]MLSLv")>; + +// ASIMD multiply accumulate saturating long +def : InstRW<[V2Write_4cyc_1V02], (instregex "^SQDML[AS]L[iv]")>; + +// ASIMD multiply/multiply long (8x8) polynomial, D-form +// ASIMD multiply/multiply long (8x8) polynomial, Q-form +def : InstRW<[V2Write_3cyc_1V23], (instregex "^PMULL?(v8i8|v16i8)$")>; + +// ASIMD multiply long +def : InstRW<[V2Write_3cyc_1V02], (instregex "^[SU]MULLv", "^SQDMULL[iv]")>; + +// ASIMD pairwise add and accumulate long +def : InstRW<[V2Wr_VPA, V2Rd_VPA], (instregex "^[SU]ADALPv")>; + +// ASIMD shift accumulate +def : InstRW<[V2Wr_VSA, V2Rd_VSA], (instregex "^[SU]SRA[dv]", "^[SU]RSRA[dv]")>; + +// ASIMD shift by immed, basic +def : InstRW<[V2Write_2cyc_1V13], (instregex "^SHL[dv]", "^SHLLv", "^SHRNv", + "^SSHLLv", "^SSHR[dv]", "^USHLLv", + "^USHR[dv]")>; + +// ASIMD shift by immed and insert, basic +def : InstRW<[V2Write_2cyc_1V13], (instregex "^SLI[dv]", "^SRI[dv]")>; + +// ASIMD shift by immed, complex +def : InstRW<[V2Write_4cyc_1V13], + (instregex "^RSHRNv", "^SQRSHRU?N[bhsv]", "^(SQSHLU?|UQSHL)[bhsd]$", + "^(SQSHLU?|UQSHL)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)_shift$", + "^SQSHRU?N[bhsv]", "^SRSHR[dv]", "^UQRSHRN[bhsv]", + "^UQSHRN[bhsv]", "^URSHR[dv]")>; + +// ASIMD shift by register, basic +def : InstRW<[V2Write_2cyc_1V13], (instregex "^[SU]SHLv")>; + +// ASIMD shift by register, complex +def : InstRW<[V2Write_4cyc_1V13], + (instregex "^[SU]RSHLv", "^[SU]QRSHLv", + "^[SU]QSHL(v1i8|v1i16|v1i32|v1i64|v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)$")>; + +// ASIMD floating-point instructions +// ----------------------------------------------------------------------------- + +// ASIMD FP absolute value/difference +// ASIMD FP arith, normal +// ASIMD FP compare +// ASIMD FP complex add +// ASIMD FP max/min, normal +// ASIMD FP max/min, pairwise +// ASIMD FP negate +// Handled by SchedAlias + +// ASIMD FP complex multiply add +def : InstRW<[V2Wr_VFCMA, V2Rd_VFCMA], (instregex "^FCMLAv")>; + +// ASIMD FP convert, long (F16 to F32) +def : InstRW<[V2Write_4cyc_2V02], (instregex "^FCVTL(v4|v8)i16")>; + +// ASIMD FP convert, long (F32 to F64) +def : InstRW<[V2Write_3cyc_1V02], (instregex "^FCVTL(v2|v4)i32")>; + +// ASIMD FP convert, narrow (F32 to F16) +def : InstRW<[V2Write_4cyc_2V02], (instregex "^FCVTN(v4|v8)i16")>; + +// ASIMD FP convert, narrow (F64 to F32) +def : InstRW<[V2Write_3cyc_1V02], (instregex "^FCVTN(v2|v4)i32", + "^FCVTXN(v2|v4)f32")>; + +// ASIMD FP convert, other, D-form F32 and Q-form F64 +def : InstRW<[V2Write_3cyc_1V02], (instregex "^FCVT[AMNPZ][SU]v2f(32|64)$", + "^FCVT[AMNPZ][SU]v1i64$", + "^FCVTZ[SU]d$", + "^[SU]CVTFv2f(32|64)$", + "^[SU]CVTFv1i64$", + "^[SU]CVTFd$")>; + +// ASIMD FP convert, other, D-form F16 and Q-form F32 +def : InstRW<[V2Write_4cyc_2V02], (instregex "^FCVT[AMNPZ][SU]v4f(16|32)$", + "^FCVT[AMNPZ][SU]v1i32$", + "^FCVTZ[SU]s$", + "^[SU]CVTFv4f(16|32)$", + "^[SU]CVTFv1i32$", + "^[SU]CVTFs$")>; + +// ASIMD FP convert, other, Q-form F16 +def : InstRW<[V2Write_6cyc_4V02], (instregex "^FCVT[AMNPZ][SU]v8f16$", + "^FCVT[AMNPZ][SU]v1f16$", + "^FCVTZ[SU]h$", + "^[SU]CVTFv8f16$", + "^[SU]CVTFv1i16$", + "^[SU]CVTFh$")>; + +// ASIMD FP divide, D-form, F16 +def : InstRW<[V2Write_7cyc_1V02_7rc], (instrs FDIVv4f16)>; + +// ASIMD FP divide, D-form, F32 +def : InstRW<[V2Write_10cyc_1V02_5rc], (instrs FDIVv2f32)>; + +// ASIMD FP divide, Q-form, F16 +def : InstRW<[V2Write_13cyc_1V02_13rc], (instrs FDIVv8f16)>; + +// ASIMD FP divide, Q-form, F32 +def : InstRW<[V2Write_10cyc_1V02_10rc], (instrs FDIVv4f32)>; + +// ASIMD FP divide, Q-form, F64 +def : InstRW<[V2Write_15cyc_1V02_14rc], (instrs FDIVv2f64)>; + +// ASIMD FP max/min, reduce, F32 and D-form F16 +def : InstRW<[V2Write_4cyc_2V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>; + +// ASIMD FP max/min, reduce, Q-form F16 +def : InstRW<[V2Write_6cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>; + +// ASIMD FP multiply +def : InstRW<[V2Wr_VFM], (instregex "^FMULv", "^FMULXv")>; + +// ASIMD FP multiply accumulate +def : InstRW<[V2Wr_VFMA, V2Rd_VFMA], (instregex "^FMLAv", "^FMLSv")>; + +// ASIMD FP multiply accumulate long +def : InstRW<[V2Wr_VFMAL, V2Rd_VFMAL], (instregex "^FML[AS]L2?(lane)?v")>; + +// ASIMD FP round, D-form F32 and Q-form F64 +def : InstRW<[V2Write_3cyc_1V02], + (instregex "^FRINT[AIMNPXZ]v2f(32|64)$", + "^FRINT(32|64)[XZ]v2f(32|64)$")>; + +// ASIMD FP round, D-form F16 and Q-form F32 +def : InstRW<[V2Write_4cyc_2V02], + (instregex "^FRINT[AIMNPXZ]v4f(16|32)$", + "^FRINT(32|64)[XZ]v4f32$")>; + +// ASIMD FP round, Q-form F16 +def : InstRW<[V2Write_6cyc_4V02], (instregex "^FRINT[AIMNPXZ]v8f16$")>; + +// ASIMD FP square root, D-form, F16 +def : InstRW<[V2Write_7cyc_1V02_7rc], (instrs FSQRTv4f16)>; + +// ASIMD FP square root, D-form, F32 +def : InstRW<[V2Write_10cyc_1V02_5rc], (instrs FSQRTv2f32)>; + +// ASIMD FP square root, Q-form, F16 +def : InstRW<[V2Write_13cyc_1V02_13rc], (instrs FSQRTv8f16)>; + +// ASIMD FP square root, Q-form, F32 +def : InstRW<[V2Write_10cyc_1V02_9rc], (instrs FSQRTv4f32)>; + +// ASIMD FP square root, Q-form, F64 +def : InstRW<[V2Write_16cyc_1V02_15rc], (instrs FSQRTv2f64)>; + +// ASIMD BFloat16 (BF16) instructions +// ----------------------------------------------------------------------------- + +// ASIMD convert, F32 to BF16 +def : InstRW<[V2Write_4cyc_2V02], (instrs BFCVTN, BFCVTN2)>; + +// ASIMD dot product +def : InstRW<[V2Wr_VBFDOT, V2Rd_VBFDOT], (instrs BFDOTv4bf16, BFDOTv8bf16)>; + +// ASIMD matrix multiply accumulate +def : InstRW<[V2Wr_VBFMMA, V2Rd_VBFMMA], (instrs BFMMLA)>; + +// ASIMD multiply accumulate long +def : InstRW<[V2Wr_VBFMAL, V2Rd_VBFMAL], (instrs BFMLALB, BFMLALBIdx, BFMLALT, + BFMLALTIdx)>; + +// Scalar convert, F32 to BF16 +def : InstRW<[V2Write_3cyc_1V02], (instrs BFCVT)>; + +// ASIMD miscellaneous instructions +// ----------------------------------------------------------------------------- + +// ASIMD bit reverse +// ASIMD bitwise insert +// ASIMD count +// ASIMD duplicate, element +// ASIMD extract +// ASIMD extract narrow +// ASIMD insert, element to element +// ASIMD move, FP immed +// ASIMD move, integer immed +// ASIMD reverse +// ASIMD table lookup extension, 1 table reg +// ASIMD transpose +// ASIMD unzip/zip +// Handled by SchedAlias + +// ASIMD duplicate, gen reg +def : InstRW<[V2Write_3cyc_1M0], (instregex "^DUPv.+gpr")>; + +// ASIMD extract narrow, saturating +def : InstRW<[V2Write_4cyc_1V13], (instregex "^[SU]QXTNv", "^SQXTUNv")>; + +// ASIMD reciprocal and square root estimate, D-form U32 +def : InstRW<[V2Write_3cyc_1V02], (instrs URECPEv2i32, URSQRTEv2i32)>; + +// ASIMD reciprocal and square root estimate, Q-form U32 +def : InstRW<[V2Write_4cyc_2V02], (instrs URECPEv4i32, URSQRTEv4i32)>; + +// ASIMD reciprocal and square root estimate, D-form F32 and scalar forms +def : InstRW<[V2Write_3cyc_1V02], (instrs FRECPEv1f16, FRECPEv1i32, + FRECPEv1i64, FRECPEv2f32, + FRSQRTEv1f16, FRSQRTEv1i32, + FRSQRTEv1i64, FRSQRTEv2f32)>; + +// ASIMD reciprocal and square root estimate, D-form F16 and Q-form F32 +def : InstRW<[V2Write_4cyc_2V02], (instrs FRECPEv4f16, FRECPEv4f32, + FRSQRTEv4f16, FRSQRTEv4f32)>; + +// ASIMD reciprocal and square root estimate, Q-form F16 +def : InstRW<[V2Write_6cyc_4V02], (instrs FRECPEv8f16, FRSQRTEv8f16)>; + +// ASIMD reciprocal exponent +def : InstRW<[V2Write_3cyc_1V02], (instregex "^FRECPXv")>; + +// ASIMD reciprocal step +def : InstRW<[V2Write_4cyc_1V], (instregex "^FRECPS(32|64|v)", + "^FRSQRTS(32|64|v)")>; + +// ASIMD table lookup, 1 or 2 table regs +def : InstRW<[V2Write_2cyc_1V01], (instrs TBLv8i8One, TBLv16i8One, + TBLv8i8Two, TBLv16i8Two)>; + +// ASIMD table lookup, 3 table regs +def : InstRW<[V2Write_4cyc_2V01], (instrs TBLv8i8Three, TBLv16i8Three)>; + +// ASIMD table lookup, 4 table regs +def : InstRW<[V2Write_4cyc_3V01], (instrs TBLv8i8Four, TBLv16i8Four)>; + +// ASIMD table lookup extension, 2 table reg +def : InstRW<[V2Write_4cyc_2V], (instrs TBXv8i8Two, TBXv16i8Two)>; + +// ASIMD table lookup extension, 3 table reg +def : InstRW<[V2Write_6cyc_3V], (instrs TBXv8i8Three, TBXv16i8Three)>; + +// ASIMD table lookup extension, 4 table reg +def : InstRW<[V2Write_6cyc_5V], (instrs TBXv8i8Four, TBXv16i8Four)>; + +// ASIMD transfer, element to gen reg +def : InstRW<[V2Write_2cyc_2V01], (instregex "^[SU]MOVv")>; + +// ASIMD transfer, gen reg to element +def : InstRW<[V2Write_5cyc_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>; + +// ASIMD load instructions +// ----------------------------------------------------------------------------- + +// ASIMD load, 1 element, multiple, 1 reg, D-form +def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1Onev(8b|4h|2s|1d)$")>; +def : InstRW<[V2Write_6cyc_1L, WriteAdr], + (instregex "^LD1Onev(8b|4h|2s|1d)_POST$")>; + +// ASIMD load, 1 element, multiple, 1 reg, Q-form +def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1Onev(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_6cyc_1L, WriteAdr], + (instregex "^LD1Onev(16b|8h|4s|2d)_POST$")>; + +// ASIMD load, 1 element, multiple, 2 reg, D-form +def : InstRW<[V2Write_6cyc_2L], (instregex "^LD1Twov(8b|4h|2s|1d)$")>; +def : InstRW<[V2Write_6cyc_2L, WriteAdr], + (instregex "^LD1Twov(8b|4h|2s|1d)_POST$")>; + +// ASIMD load, 1 element, multiple, 2 reg, Q-form +def : InstRW<[V2Write_6cyc_2L], (instregex "^LD1Twov(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_6cyc_2L, WriteAdr], + (instregex "^LD1Twov(16b|8h|4s|2d)_POST$")>; + +// ASIMD load, 1 element, multiple, 3 reg, D-form +def : InstRW<[V2Write_6cyc_3L], (instregex "^LD1Threev(8b|4h|2s|1d)$")>; +def : InstRW<[V2Write_6cyc_3L, WriteAdr], + (instregex "^LD1Threev(8b|4h|2s|1d)_POST$")>; + +// ASIMD load, 1 element, multiple, 3 reg, Q-form +def : InstRW<[V2Write_6cyc_3L], (instregex "^LD1Threev(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_6cyc_3L, WriteAdr], + (instregex "^LD1Threev(16b|8h|4s|2d)_POST$")>; + +// ASIMD load, 1 element, multiple, 4 reg, D-form +def : InstRW<[V2Write_7cyc_4L], (instregex "^LD1Fourv(8b|4h|2s|1d)$")>; +def : InstRW<[V2Write_7cyc_4L, WriteAdr], + (instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>; + +// ASIMD load, 1 element, multiple, 4 reg, Q-form +def : InstRW<[V2Write_7cyc_4L], (instregex "^LD1Fourv(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_7cyc_4L, WriteAdr], + (instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>; + +// ASIMD load, 1 element, one lane, B/H/S +// ASIMD load, 1 element, one lane, D +def : InstRW<[V2Write_8cyc_1L_1V], (instregex "LD1i(8|16|32|64)$")>; +def : InstRW<[V2Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>; + +// ASIMD load, 1 element, all lanes, D-form, B/H/S +// ASIMD load, 1 element, all lanes, D-form, D +def : InstRW<[V2Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)$")>; +def : InstRW<[V2Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>; + +// ASIMD load, 1 element, all lanes, Q-form +def : InstRW<[V2Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>; + +// ASIMD load, 2 element, multiple, D-form, B/H/S +def : InstRW<[V2Write_8cyc_1L_2V], (instregex "LD2Twov(8b|4h|2s)$")>; +def : InstRW<[V2Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>; + +// ASIMD load, 2 element, multiple, Q-form, B/H/S +// ASIMD load, 2 element, multiple, Q-form, D +def : InstRW<[V2Write_8cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_8cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>; + +// ASIMD load, 2 element, one lane, B/H +// ASIMD load, 2 element, one lane, S +// ASIMD load, 2 element, one lane, D +def : InstRW<[V2Write_8cyc_1L_2V], (instregex "LD2i(8|16|32|64)$")>; +def : InstRW<[V2Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16|32|64)_POST$")>; + +// ASIMD load, 2 element, all lanes, D-form, B/H/S +// ASIMD load, 2 element, all lanes, D-form, D +def : InstRW<[V2Write_8cyc_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)$")>; +def : InstRW<[V2Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>; + +// ASIMD load, 2 element, all lanes, Q-form +def : InstRW<[V2Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>; + +// ASIMD load, 3 element, multiple, D-form, B/H/S +def : InstRW<[V2Write_8cyc_2L_3V], (instregex "LD3Threev(8b|4h|2s)$")>; +def : InstRW<[V2Write_8cyc_2L_3V, WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST$")>; + +// ASIMD load, 3 element, multiple, Q-form, B/H/S +// ASIMD load, 3 element, multiple, Q-form, D +def : InstRW<[V2Write_8cyc_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_8cyc_3L_3V, WriteAdr], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>; + +// ASIMD load, 3 element, one lane, B/H +// ASIMD load, 3 element, one lane, S +// ASIMD load, 3 element, one lane, D +def : InstRW<[V2Write_8cyc_2L_3V], (instregex "LD3i(8|16|32|64)$")>; +def : InstRW<[V2Write_8cyc_2L_3V, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>; + +// ASIMD load, 3 element, all lanes, D-form, B/H/S +// ASIMD load, 3 element, all lanes, D-form, D +def : InstRW<[V2Write_8cyc_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)$")>; +def : InstRW<[V2Write_8cyc_2L_3V, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>; + +// ASIMD load, 3 element, all lanes, Q-form, B/H/S +// ASIMD load, 3 element, all lanes, Q-form, D +def : InstRW<[V2Write_8cyc_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_8cyc_3L_3V, WriteAdr], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>; + +// ASIMD load, 4 element, multiple, D-form, B/H/S +def : InstRW<[V2Write_8cyc_3L_4V], (instregex "LD4Fourv(8b|4h|2s)$")>; +def : InstRW<[V2Write_8cyc_3L_4V, WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST$")>; + +// ASIMD load, 4 element, multiple, Q-form, B/H/S +// ASIMD load, 4 element, multiple, Q-form, D +def : InstRW<[V2Write_9cyc_6L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_9cyc_6L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>; + +// ASIMD load, 4 element, one lane, B/H +// ASIMD load, 4 element, one lane, S +// ASIMD load, 4 element, one lane, D +def : InstRW<[V2Write_8cyc_3L_4V], (instregex "LD4i(8|16|32|64)$")>; +def : InstRW<[V2Write_8cyc_3L_4V, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>; + +// ASIMD load, 4 element, all lanes, D-form, B/H/S +// ASIMD load, 4 element, all lanes, D-form, D +def : InstRW<[V2Write_8cyc_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)$")>; +def : InstRW<[V2Write_8cyc_3L_4V, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>; + +// ASIMD load, 4 element, all lanes, Q-form, B/H/S +// ASIMD load, 4 element, all lanes, Q-form, D +def : InstRW<[V2Write_8cyc_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_8cyc_4L_4V, WriteAdr], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>; + +// ASIMD store instructions +// ----------------------------------------------------------------------------- + +// ASIMD store, 1 element, multiple, 1 reg, D-form +def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "ST1Onev(8b|4h|2s|1d)$")>; +def : InstRW<[V2Write_2cyc_1L01_1V01, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>; + +// ASIMD store, 1 element, multiple, 1 reg, Q-form +def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "ST1Onev(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_2cyc_1L01_1V01, WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>; + +// ASIMD store, 1 element, multiple, 2 reg, D-form +def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "ST1Twov(8b|4h|2s|1d)$")>; +def : InstRW<[V2Write_2cyc_1L01_1V01, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>; + +// ASIMD store, 1 element, multiple, 2 reg, Q-form +def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "ST1Twov(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_2cyc_2L01_2V01, WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>; + +// ASIMD store, 1 element, multiple, 3 reg, D-form +def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "ST1Threev(8b|4h|2s|1d)$")>; +def : InstRW<[V2Write_2cyc_2L01_2V01, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>; + +// ASIMD store, 1 element, multiple, 3 reg, Q-form +def : InstRW<[V2Write_2cyc_3L01_3V01], (instregex "ST1Threev(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_2cyc_3L01_3V01, WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>; + +// ASIMD store, 1 element, multiple, 4 reg, D-form +def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; +def : InstRW<[V2Write_2cyc_2L01_2V01, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>; + +// ASIMD store, 1 element, multiple, 4 reg, Q-form +def : InstRW<[V2Write_2cyc_4L01_4V01], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_2cyc_4L01_4V01, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>; + +// ASIMD store, 1 element, one lane, B/H/S +// ASIMD store, 1 element, one lane, D +def : InstRW<[V2Write_4cyc_1L01_2V01], (instregex "ST1i(8|16|32|64)$")>; +def : InstRW<[V2Write_4cyc_1L01_2V01, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>; + +// ASIMD store, 2 element, multiple, D-form, B/H/S +def : InstRW<[V2Write_4cyc_1L01_2V01], (instregex "ST2Twov(8b|4h|2s)$")>; +def : InstRW<[V2Write_4cyc_1L01_2V01, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>; + +// ASIMD store, 2 element, multiple, Q-form, B/H/S +// ASIMD store, 2 element, multiple, Q-form, D +def : InstRW<[V2Write_4cyc_2L01_4V01], (instregex "ST2Twov(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_4cyc_2L01_4V01, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>; + +// ASIMD store, 2 element, one lane, B/H/S +// ASIMD store, 2 element, one lane, D +def : InstRW<[V2Write_4cyc_1L01_2V01], (instregex "ST2i(8|16|32|64)$")>; +def : InstRW<[V2Write_4cyc_1L01_2V01, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>; + +// ASIMD store, 3 element, multiple, D-form, B/H/S +def : InstRW<[V2Write_5cyc_2L01_4V01], (instregex "ST3Threev(8b|4h|2s)$")>; +def : InstRW<[V2Write_5cyc_2L01_4V01, WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>; + +// ASIMD store, 3 element, multiple, Q-form, B/H/S +// ASIMD store, 3 element, multiple, Q-form, D +def : InstRW<[V2Write_6cyc_3L01_6V01], (instregex "ST3Threev(16b|8h|4s|2d)$")>; +def : InstRW<[V2Write_6cyc_3L01_6V01, WriteAdr], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>; + +// ASIMD store, 3 element, one lane, B/H +// ASIMD store, 3 element, one lane, S +// ASIMD store, 3 element, one lane, D +def : InstRW<[V2Write_5cyc_2L01_4V01], (instregex "ST3i(8|16|32|64)$")>; +def : InstRW<[V2Write_5cyc_2L01_4V01, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>; + +// ASIMD store, 4 element, multiple, D-form, B/H/S +def : InstRW<[V2Write_6cyc_2L01_6V01], (instregex "ST4Fourv(8b|4h|2s)$")>; +def : InstRW<[V2Write_6cyc_2L01_6V01, WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; + +// ASIMD store, 4 element, multiple, Q-form, B/H/S +def : InstRW<[V2Write_7cyc_4L01_12V01], (instregex "ST4Fourv(16b|8h|4s)$")>; +def : InstRW<[V2Write_7cyc_4L01_12V01, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>; + +// ASIMD store, 4 element, multiple, Q-form, D +def : InstRW<[V2Write_5cyc_4L01_8V01], (instregex "ST4Fourv(2d)$")>; +def : InstRW<[V2Write_5cyc_4L01_8V01, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>; + +// ASIMD store, 4 element, one lane, B/H/S +def : InstRW<[V2Write_6cyc_1L01_3V01], (instregex "ST4i(8|16|32)$")>; +def : InstRW<[V2Write_6cyc_1L01_3V01, WriteAdr], (instregex "ST4i(8|16|32)_POST$")>; + +// ASIMD store, 4 element, one lane, D +def : InstRW<[V2Write_4cyc_2L01_4V01], (instregex "ST4i(64)$")>; +def : InstRW<[V2Write_4cyc_2L01_4V01, WriteAdr], (instregex "ST4i(64)_POST$")>; + +// Cryptography extensions +// ----------------------------------------------------------------------------- + +// Crypto AES ops +def : InstRW<[V2Write_2cyc_1V], (instregex "^AES[DE]rr$", "^AESI?MCrr")>; + +// Crypto polynomial (64x64) multiply long +def : InstRW<[V2Write_2cyc_1V], (instrs PMULLv1i64, PMULLv2i64)>; + +// Crypto SHA1 hash acceleration op +// Crypto SHA1 schedule acceleration ops +def : InstRW<[V2Write_2cyc_1V0], (instregex "^SHA1(H|SU0|SU1)")>; + +// Crypto SHA1 hash acceleration ops +// Crypto SHA256 hash acceleration ops +def : InstRW<[V2Write_4cyc_1V0], (instregex "^SHA1[CMP]", "^SHA256H2?")>; + +// Crypto SHA256 schedule acceleration ops +def : InstRW<[V2Write_2cyc_1V0], (instregex "^SHA256SU[01]")>; + +// Crypto SHA512 hash acceleration ops +def : InstRW<[V2Write_2cyc_1V0], (instregex "^SHA512(H|H2|SU0|SU1)")>; + +// Crypto SHA3 ops +def : InstRW<[V2Write_2cyc_1V0], (instrs BCAX, EOR3, RAX1, XAR)>; + +// Crypto SM3 ops +def : InstRW<[V2Write_2cyc_1V0], (instregex "^SM3PARTW[12]$", "^SM3SS1$", + "^SM3TT[12][AB]$")>; + +// Crypto SM4 ops +def : InstRW<[V2Write_4cyc_1V0], (instrs SM4E, SM4ENCKEY)>; + +// CRC +// ----------------------------------------------------------------------------- + +def : InstRW<[V2Wr_CRC, V2Rd_CRC], (instregex "^CRC32")>; + +// SVE Predicate instructions +// ----------------------------------------------------------------------------- + +// Loop control, based on predicate +def : InstRW<[V2Write_2or3cyc_1M], (instrs BRKA_PPmP, BRKA_PPzP, + BRKB_PPmP, BRKB_PPzP)>; + +// Loop control, based on predicate and flag setting +def : InstRW<[V2Write_3or4cyc_2M], (instrs BRKAS_PPzP, BRKBS_PPzP)>; + +// Loop control, propagating +def : InstRW<[V2Write_2or3cyc_1M0], (instrs BRKN_PPzP, BRKPA_PPzPP, + BRKPB_PPzPP)>; + +// Loop control, propagating and flag setting +def : InstRW<[V2Write_3or4cyc_1M0_1M], (instrs BRKNS_PPzP, BRKPAS_PPzPP, + BRKPBS_PPzPP)>; + +// Loop control, based on GPR +def : InstRW<[V2Write_3cyc_2M], + (instregex "^WHILE(GE|GT|HI|HS|LE|LO|LS|LT)_P(WW|XX)_[BHSD]$")>; +def : InstRW<[V2Write_3cyc_2M], (instregex "^WHILE(RW|WR)_PXX_[BHSD]$")>; + +// Loop terminate +def : InstRW<[V2Write_1cyc_2M], (instregex "^CTERM(EQ|NE)_(WW|XX)$")>; + +// Predicate counting scalar +def : InstRW<[V2Write_2cyc_1M], (instrs ADDPL_XXI, ADDVL_XXI, RDVLI_XI)>; +def : InstRW<[V2Write_2cyc_1M], + (instregex "^(CNT|SQDEC|SQINC|UQDEC|UQINC)[BHWD]_XPiI$", + "^SQ(DEC|INC)[BHWD]_XPiWdI$", + "^UQ(DEC|INC)[BHWD]_WPiI$")>; + +// Predicate counting scalar, ALL, {1,2,4} +def : InstRW<[V2Write_IncDec], (instregex "^(DEC|INC)[BHWD]_XPiI$")>; + +// Predicate counting scalar, active predicate +def : InstRW<[V2Write_2cyc_1M], + (instregex "^CNTP_XPP_[BHSD]$", + "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_XP_[BHSD]$", + "^(UQDEC|UQINC)P_WP_[BHSD]$", + "^(SQDEC|SQINC)P_XPWd_[BHSD]$")>; + +// Predicate counting vector, active predicate +def : InstRW<[V2Write_7cyc_1M_1M0_1V], + (instregex "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_ZP_[HSD]$")>; + +// Predicate logical +def : InstRW<[V2Write_1or2cyc_1M0], + (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP$")>; + +// Predicate logical, flag setting +def : InstRW<[V2Write_1or2cyc_1M0_1M], + (instregex "^(ANDS|BICS|EORS|NANDS|NORS|ORNS|ORRS)_PPzPP$")>; + +// Predicate reverse +def : InstRW<[V2Write_2cyc_1M], (instregex "^REV_PP_[BHSD]$")>; + +// Predicate select +def : InstRW<[V2Write_1cyc_1M0], (instrs SEL_PPPP)>; + +// Predicate set +def : InstRW<[V2Write_2cyc_1M], (instregex "^PFALSE$", "^PTRUE_[BHSD]$")>; + +// Predicate set/initialize, set flags +def : InstRW<[V2Write_3cyc_2M], (instregex "^PTRUES_[BHSD]$")>; + +// Predicate find first/next +def : InstRW<[V2Write_2cyc_1M], (instregex "^PFIRST_B$", "^PNEXT_[BHSD]$")>; + +// Predicate test +def : InstRW<[V2Write_1cyc_1M], (instrs PTEST_PP)>; + +// Predicate transpose +def : InstRW<[V2Write_2cyc_1M], (instregex "^TRN[12]_PPP_[BHSD]$")>; + +// Predicate unpack and widen +def : InstRW<[V2Write_2cyc_1M], (instrs PUNPKHI_PP, PUNPKLO_PP)>; + +// Predicate zip/unzip +def : InstRW<[V2Write_2cyc_1M], (instregex "^(ZIP|UZP)[12]_PPP_[BHSD]$")>; + +// SVE integer instructions +// ----------------------------------------------------------------------------- + +// Arithmetic, absolute diff +def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU]ABD_ZPmZ_[BHSD]$", + "^[SU]ABD_ZPZZ_UNDEF_[BHSD]$")>; + +// Arithmetic, absolute diff accum +def : InstRW<[V2Wr_ZA, V2Rd_ZA], (instregex "^[SU]ABA_ZZZ_[BHSD]$")>; + +// Arithmetic, absolute diff accum long +def : InstRW<[V2Wr_ZA, V2Rd_ZA], (instregex "^[SU]ABAL[TB]_ZZZ_[HSD]$")>; + +// Arithmetic, absolute diff long +def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]$")>; + +// Arithmetic, basic +def : InstRW<[V2Write_2cyc_1V], + (instregex "^(ABS|ADD|CNOT|NEG|SUB|SUBR)_ZPmZ_[BHSD]$", + "^(ABS|CNOT|NEG)_ZPmZ_UNDEF_[BHSD]$", + "^(ADD|SUB)_ZZZ_[BHSD]$", + "^(ADD|SUB|SUBR)_ZI_[BHSD]$", + "^ADR_[SU]XTW_ZZZ_D_[0123]$", + "^ADR_LSL_ZZZ_[SD]_[0123]$", + "^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]$", + "^SADDLBT_ZZZ_[HSD]$", + "^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]$", + "^SSUBL(BT|TB)_ZZZ_[HSD]$")>; + +// Arithmetic, complex +def : InstRW<[V2Write_2cyc_1V], + (instregex "^R?(ADD|SUB)HN[BT]_ZZZ_[BHS]$", + "^SQ(ABS|ADD|NEG|SUB|SUBR)_ZPmZ_[BHSD]$", + "^SQ(ABS|NEG)_ZPmZ_UNDEF_[BHSD]$", + "^[SU]Q(ADD|SUB)_ZZZ_[BHSD]$", + "^[SU]Q(ADD|SUB)_ZI_[BHSD]$", + "^(SRH|SUQ|UQ|USQ|URH)ADD_ZPmZ_[BHSD]$", + "^(UQSUB|UQSUBR)_ZPmZ_[BHSD]$")>; + +// Arithmetic, large integer +def : InstRW<[V2Write_2cyc_1V], (instregex "^(AD|SB)CL[BT]_ZZZ_[SD]$")>; + +// Arithmetic, pairwise add +def : InstRW<[V2Write_2cyc_1V], (instregex "^ADDP_ZPmZ_[BHSD]$")>; + +// Arithmetic, pairwise add and accum long +def : InstRW<[V2Wr_ZPA, ReadDefault, V2Rd_ZPA], + (instregex "^[SU]ADALP_ZPmZ_[HSD]$")>; + +// Arithmetic, shift +def : InstRW<[V2Write_2cyc_1V13], + (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]$", + "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]$", + "^(ASR|LSL|LSR)_ZPmI_[BHSD]$", + "^(ASR|LSL|LSR)_ZPmZ_[BHSD]$", + "^(ASR|LSL|LSR)_ZZI_[BHSD]$", + "^(ASR|LSL|LSR)_ZPZ[IZ]_UNDEF_[BHSD]$", + "^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]$")>; + +// Arithmetic, shift and accumulate +def : InstRW<[V2Wr_ZSA, V2Rd_ZSA], (instregex "^[SU]R?SRA_ZZI_[BHSD]$")>; + +// Arithmetic, shift by immediate +def : InstRW<[V2Write_2cyc_1V13], (instregex "^SHRN[BT]_ZZI_[BHS]$", + "^[SU]SHLL[BT]_ZZI_[HSD]$")>; + +// Arithmetic, shift by immediate and insert +def : InstRW<[V2Write_2cyc_1V13], (instregex "^(SLI|SRI)_ZZI_[BHSD]$")>; + +// Arithmetic, shift complex +def : InstRW<[V2Write_4cyc_1V13], + (instregex "^(SQ)?RSHRU?N[BT]_ZZI_[BHS]$", + "^(SQRSHL|SQRSHLR|SQSHL|SQSHLR|UQRSHL|UQRSHLR|UQSHL|UQSHLR)_ZPmZ_[BHSD]$", + "^[SU]QR?SHL_ZPZZ_UNDEF_[BHSD]$", + "^(SQSHL|SQSHLU|UQSHL)_ZPmI_[BHSD]$", + "^SQSHRU?N[BT]_ZZI_[BHS]$", + "^UQR?SHRN[BT]_ZZI_[BHS]$")>; + +// Arithmetic, shift right for divide +def : InstRW<[V2Write_4cyc_1V13], (instregex "^ASRD_ZPmI_[BHSD]$")>; + +// Arithmetic, shift rounding +def : InstRW<[V2Write_4cyc_1V13], (instregex "^[SU]RSHLR?_ZPmZ_[BHSD]$", + "^[SU]RSHL_ZPZZ_UNDEF_[BHSD]$", + "^[SU]RSHR_ZPmI_[BHSD]$")>; + +// Bit manipulation +def : InstRW<[V2Write_6cyc_2V1], (instregex "^(BDEP|BEXT|BGRP)_ZZZ_[BHSD]$")>; + +// Bitwise select +def : InstRW<[V2Write_2cyc_1V], (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ$")>; + +// Count/reverse bits +def : InstRW<[V2Write_2cyc_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]$", + "^(CLS|CLZ|CNT)_ZPmZ_UNDEF_[BHSD]$")>; + +// Broadcast logical bitmask immediate to vector +def : InstRW<[V2Write_2cyc_1V], (instrs DUPM_ZI)>; + +// Compare and set flags +def : InstRW<[V2Write_4or5cyc_1V0_1M0], + (instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]$", + "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]$")>; + +// Complex add +def : InstRW<[V2Write_2cyc_1V], (instregex "^(SQ)?CADD_ZZI_[BHSD]$")>; + +// Complex dot product 8-bit element +def : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instrs CDOT_ZZZ_S, CDOT_ZZZI_S)>; + +// Complex dot product 16-bit element +def : InstRW<[V2Wr_ZDOTH, V2Rd_ZDOTH], (instrs CDOT_ZZZ_D, CDOT_ZZZI_D)>; + +// Complex multiply-add B, H, S element size +def : InstRW<[V2Wr_ZCMABHS, V2Rd_ZCMABHS], (instregex "^CMLA_ZZZ_[BHS]$", + "^CMLA_ZZZI_[HS]$")>; + +// Complex multiply-add D element size +def : InstRW<[V2Wr_ZCMAD, V2Rd_ZCMAD], (instrs CMLA_ZZZ_D)>; + +// Conditional extract operations, scalar form +def : InstRW<[V2Write_8cyc_1M0_1V01], (instregex "^CLAST[AB]_RPZ_[BHSD]$")>; + +// Conditional extract operations, SIMD&FP scalar and vector forms +def : InstRW<[V2Write_3cyc_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]$", + "^COMPACT_ZPZ_[SD]$", + "^SPLICE_ZPZZ?_[BHSD]$")>; + +// Convert to floating point, 64b to float or convert to double +def : InstRW<[V2Write_3cyc_1V02], (instregex "^[SU]CVTF_ZPmZ_Dto[HSD](_UNDEF)?$", + "^[SU]CVTF_ZPmZ_StoD(_UNDEF)?$")>; + +// Convert to floating point, 32b to single or half +def : InstRW<[V2Write_4cyc_2V02], (instregex "^[SU]CVTF_ZPmZ_Sto[HS](_UNDEF)?$")>; + +// Convert to floating point, 16b to half +def : InstRW<[V2Write_6cyc_4V02], (instregex "^[SU]CVTF_ZPmZ_HtoH(_UNDEF)?$")>; + +// Copy, scalar +def : InstRW<[V2Write_5cyc_1M0_1V], (instregex "^CPY_ZPmR_[BHSD]$")>; + +// Copy, scalar SIMD&FP or imm +def : InstRW<[V2Write_2cyc_1V], (instregex "^CPY_ZPm[IV]_[BHSD]$", + "^CPY_ZPzI_[BHSD]$")>; + +// Divides, 32 bit +def : InstRW<[V2Write_12cyc_1V0], (instregex "^[SU]DIVR?_ZPmZ_S$", + "^[SU]DIV_ZPZZ_UNDEF_S$")>; + +// Divides, 64 bit +def : InstRW<[V2Write_20cyc_1V0], (instregex "^[SU]DIVR?_ZPmZ_D$", + "^[SU]DIV_ZPZZ_UNDEF_D$")>; + +// Dot product, 8 bit +def : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instregex "^[SU]DOT_ZZZI?_S$")>; + +// Dot product, 8 bit, using signed and unsigned integers +def : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ)>; + +// Dot product, 16 bit +def : InstRW<[V2Wr_ZDOTH, V2Rd_ZDOTH], (instregex "^[SU]DOT_ZZZI?_D$")>; + +// Duplicate, immediate and indexed form +def : InstRW<[V2Write_2cyc_1V], (instregex "^DUP_ZI_[BHSD]$", + "^DUP_ZZI_[BHSDQ]$")>; + +// Duplicate, scalar form +def : InstRW<[V2Write_3cyc_1M0], (instregex "^DUP_ZR_[BHSD]$")>; + +// Extend, sign or zero +def : InstRW<[V2Write_2cyc_1V13], (instregex "^[SU]XTB_ZPmZ(_UNDEF)?_[HSD]$", + "^[SU]XTH_ZPmZ(_UNDEF)?_[SD]$", + "^[SU]XTW_ZPmZ(_UNDEF)?_[D]$")>; + +// Extract +def : InstRW<[V2Write_2cyc_1V], (instrs EXT_ZZI, EXT_ZZI_B)>; + +// Extract narrow saturating +def : InstRW<[V2Write_4cyc_1V13], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]$", + "^SQXTUN[BT]_ZZ_[BHS]$")>; + +// Extract/insert operation, SIMD and FP scalar form +def : InstRW<[V2Write_3cyc_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]$", + "^INSR_ZV_[BHSD]$")>; + +// Extract/insert operation, scalar +def : InstRW<[V2Write_6cyc_1V1_1M0], (instregex "^LAST[AB]_RPZ_[BHSD]$", + "^INSR_ZR_[BHSD]$")>; + +// Histogram operations +def : InstRW<[V2Write_2cyc_1V], (instregex "^HISTCNT_ZPzZZ_[SD]$", + "^HISTSEG_ZZZ$")>; + +// Horizontal operations, B, H, S form, immediate operands only +def : InstRW<[V2Write_4cyc_1V02], (instregex "^INDEX_II_[BHS]$")>; + +// Horizontal operations, B, H, S form, scalar, immediate operands/ scalar +// operands only / immediate, scalar operands +def : InstRW<[V2Write_7cyc_1M0_1V02], (instregex "^INDEX_(IR|RI|RR)_[BHS]$")>; + +// Horizontal operations, D form, immediate operands only +def : InstRW<[V2Write_5cyc_2V02], (instrs INDEX_II_D)>; + +// Horizontal operations, D form, scalar, immediate operands)/ scalar operands +// only / immediate, scalar operands +def : InstRW<[V2Write_8cyc_2M0_2V02], (instregex "^INDEX_(IR|RI|RR)_D$")>; + +// Logical +def : InstRW<[V2Write_2cyc_1V], + (instregex "^(AND|EOR|ORR)_ZI$", + "^(AND|BIC|EOR|ORR)_ZZZ$", + "^EOR(BT|TB)_ZZZ_[BHSD]$", + "^(AND|BIC|EOR|NOT|ORR)_ZPmZ_[BHSD]$", + "^NOT_ZPmZ_UNDEF_[BHSD]$")>; + +// Max/min, basic and pairwise +def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]$", + "^[SU](MAX|MIN)P?_ZPmZ_[BHSD]$", + "^[SU](MAX|MIN)_ZPZZ_UNDEF_[BHSD]$")>; + +// Matching operations +// FIXME: SOG p. 44, n. 5: If the consuming instruction has a flag source, the +// latency for this instruction is 4 cycles. +def : InstRW<[V2Write_2or3cyc_1V0_1M], (instregex "^N?MATCH_PPzZZ_[BH]$")>; + +// Matrix multiply-accumulate +def : InstRW<[V2Wr_ZMMA, V2Rd_ZMMA], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>; + +// Move prefix +def : InstRW<[V2Write_2cyc_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]$", + "^MOVPRFX_ZZ$")>; + +// Multiply, B, H, S element size +def : InstRW<[V2Write_4cyc_1V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHS]$", + "^MUL_ZPZZ_UNDEF_[BHS]$", + "^[SU]MULH_(ZPmZ|ZZZ)_[BHS]$", + "^[SU]MULH_ZPZZ_UNDEF_[BHS]$")>; + +// Multiply, D element size +def : InstRW<[V2Write_5cyc_2V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_D$", + "^MUL_ZPZZ_UNDEF_D$", + "^[SU]MULH_(ZPmZ|ZZZ)_D$", + "^[SU]MULH_ZPZZ_UNDEF_D$")>; + +// Multiply long +def : InstRW<[V2Write_4cyc_1V02], (instregex "^[SU]MULL[BT]_ZZZI_[SD]$", + "^[SU]MULL[BT]_ZZZ_[HSD]$")>; + +// Multiply accumulate, B, H, S element size +def : InstRW<[V2Wr_ZMABHS, V2Rd_ZMABHS], + (instregex "^ML[AS]_ZZZI_[HS]$", "^ML[AS]_ZPZZZ_UNDEF_[BHS]$")>; +def : InstRW<[V2Wr_ZMABHS, ReadDefault, V2Rd_ZMABHS], + (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_[BHS]$")>; + +// Multiply accumulate, D element size +def : InstRW<[V2Wr_ZMAD, V2Rd_ZMAD], + (instregex "^ML[AS]_ZZZI_D$", "^ML[AS]_ZPZZZ_UNDEF_D$")>; +def : InstRW<[V2Wr_ZMAD, ReadDefault, V2Rd_ZMAD], + (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_D$")>; + +// Multiply accumulate long +def : InstRW<[V2Wr_ZMAL, V2Rd_ZMAL], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]$", + "^[SU]ML[AS]L[BT]_ZZZI_[SD]$")>; + +// Multiply accumulate saturating doubling long regular +def : InstRW<[V2Wr_ZMASQL, V2Rd_ZMASQ], + (instregex "^SQDML[AS]L(B|T|BT)_ZZZ_[HSD]$", + "^SQDML[AS]L[BT]_ZZZI_[SD]$")>; + +// Multiply saturating doubling high, B, H, S element size +def : InstRW<[V2Write_4cyc_1V02], (instregex "^SQDMULH_ZZZ_[BHS]$", + "^SQDMULH_ZZZI_[HS]$")>; + +// Multiply saturating doubling high, D element size +def : InstRW<[V2Write_5cyc_2V02], (instrs SQDMULH_ZZZ_D, SQDMULH_ZZZI_D)>; + +// Multiply saturating doubling long +def : InstRW<[V2Write_4cyc_1V02], (instregex "^SQDMULL[BT]_ZZZ_[HSD]$", + "^SQDMULL[BT]_ZZZI_[SD]$")>; + +// Multiply saturating rounding doubling regular/complex accumulate, B, H, S +// element size +def : InstRW<[V2Wr_ZMASQBHS, V2Rd_ZMASQ], (instregex "^SQRDML[AS]H_ZZZ_[BHS]$", + "^SQRDCMLAH_ZZZ_[BHS]$", + "^SQRDML[AS]H_ZZZI_[HS]$", + "^SQRDCMLAH_ZZZI_[HS]$")>; + +// Multiply saturating rounding doubling regular/complex accumulate, D element +// size +def : InstRW<[V2Wr_ZMASQD, V2Rd_ZMASQ], (instregex "^SQRDML[AS]H_ZZZI?_D$", + "^SQRDCMLAH_ZZZ_D$")>; + +// Multiply saturating rounding doubling regular/complex, B, H, S element size +def : InstRW<[V2Write_4cyc_1V02], (instregex "^SQRDMULH_ZZZ_[BHS]$", + "^SQRDMULH_ZZZI_[HS]$")>; + +// Multiply saturating rounding doubling regular/complex, D element size +def : InstRW<[V2Write_5cyc_2V02], (instregex "^SQRDMULH_ZZZI?_D$")>; + +// Multiply/multiply long, (8x8) polynomial +def : InstRW<[V2Write_2cyc_1V23], (instregex "^PMUL_ZZZ_B$", + "^PMULL[BT]_ZZZ_[HDQ]$")>; + +// Predicate counting vector +def : InstRW<[V2Write_2cyc_1V], (instregex "^([SU]Q)?(DEC|INC)[HWD]_ZPiI$")>; + +// Reciprocal estimate +def : InstRW<[V2Write_4cyc_2V02], (instrs URECPE_ZPmZ_S, URSQRTE_ZPmZ_S, + URECPE_ZPmZ_UNDEF_S, URSQRTE_ZPmZ_UNDEF_S)>; + +// Reduction, arithmetic, B form +def : InstRW<[V2Write_9cyc_2V_4V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>; + +// Reduction, arithmetic, H form +def : InstRW<[V2Write_8cyc_2V_2V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>; + +// Reduction, arithmetic, S form +def : InstRW<[V2Write_6cyc_2V_2V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_S")>; + +// Reduction, arithmetic, D form +def : InstRW<[V2Write_4cyc_2V], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>; + +// Reduction, logical +def : InstRW<[V2Write_6cyc_1V_1V13], (instregex "^(AND|EOR|OR)V_VPZ_[BHSD]$")>; + +// Reverse, vector +def : InstRW<[V2Write_2cyc_1V], (instregex "^REV_ZZ_[BHSD]$", + "^REVB_ZPmZ_[HSD]$", + "^REVH_ZPmZ_[SD]$", + "^REVW_ZPmZ_D$")>; + +// Select, vector form +def : InstRW<[V2Write_2cyc_1V], (instregex "^SEL_ZPZZ_[BHSD]$")>; + +// Table lookup +def : InstRW<[V2Write_2cyc_1V], (instregex "^TBL_ZZZZ?_[BHSD]$")>; + +// Table lookup extension +def : InstRW<[V2Write_2cyc_1V], (instregex "^TBX_ZZZ_[BHSD]$")>; + +// Transpose, vector form +def : InstRW<[V2Write_2cyc_1V], (instregex "^TRN[12]_ZZZ_[BHSDQ]$")>; + +// Unpack and extend +def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU]UNPK(HI|LO)_ZZ_[HSD]$")>; + +// Zip/unzip +def : InstRW<[V2Write_2cyc_1V], (instregex "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]$")>; + +// SVE floating-point instructions +// ----------------------------------------------------------------------------- + +// Floating point absolute value/difference +def : InstRW<[V2Write_2cyc_1V], (instregex "^FAB[SD]_ZPmZ_[HSD]$", + "^FABD_ZPZZ_UNDEF_[HSD]$", + "^FABS_ZPmZ_UNDEF_[HSD]$")>; + +// Floating point arithmetic +def : InstRW<[V2Write_2cyc_1V], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]$", + "^F(ADD|SUB)_ZPZ[IZ]_UNDEF_[HSD]$", + "^FADDP_ZPmZZ_[HSD]$", + "^FNEG_ZPmZ(_UNDEF)?_[HSD]$", + "^FSUBR_ZPm[IZ]_[HSD]$", + "^FSUBR_ZPZI_UNDEF_[HSD]$")>; + +// Floating point associative add, F16 +def : InstRW<[V2Write_10cyc_1V1_9rc], (instrs FADDA_VPZ_H)>; + +// Floating point associative add, F32 +def : InstRW<[V2Write_6cyc_1V1_5rc], (instrs FADDA_VPZ_S)>; + +// Floating point associative add, F64 +def : InstRW<[V2Write_4cyc_1V], (instrs FADDA_VPZ_D)>; + +// Floating point compare +def : InstRW<[V2Write_2cyc_1V0], (instregex "^FACG[ET]_PPzZZ_[HSD]$", + "^FCM(EQ|GE|GT|NE)_PPzZ[0Z]_[HSD]$", + "^FCM(LE|LT)_PPzZ0_[HSD]$", + "^FCMUO_PPzZZ_[HSD]$")>; + +// Floating point complex add +def : InstRW<[V2Write_3cyc_1V], (instregex "^FCADD_ZPmZ_[HSD]$")>; + +// Floating point complex multiply add +def : InstRW<[V2Wr_ZFCMA, ReadDefault, V2Rd_ZFCMA], (instregex "^FCMLA_ZPmZZ_[HSD]$")>; +def : InstRW<[V2Wr_ZFCMA, V2Rd_ZFCMA], (instregex "^FCMLA_ZZZI_[HS]$")>; + +// Floating point convert, long or narrow (F16 to F32 or F32 to F16) +def : InstRW<[V2Write_4cyc_2V02], (instregex "^FCVT_ZPmZ_(HtoS|StoH)(_UNDEF)?$", + "^FCVTLT_ZPmZ_HtoS$", + "^FCVTNT_ZPmZ_StoH$")>; + +// Floating point convert, long or narrow (F16 to F64, F32 to F64, F64 to F32 +// or F64 to F16) +def : InstRW<[V2Write_3cyc_1V02], (instregex "^FCVT_ZPmZ_(HtoD|StoD|DtoS|DtoH)(_UNDEF)?$", + "^FCVTLT_ZPmZ_StoD$", + "^FCVTNT_ZPmZ_DtoS$")>; + +// Floating point convert, round to odd +def : InstRW<[V2Write_3cyc_1V02], (instrs FCVTX_ZPmZ_DtoS, FCVTXNT_ZPmZ_DtoS)>; + +// Floating point base2 log, F16 +def : InstRW<[V2Write_6cyc_4V02], (instrs FLOGB_ZPmZ_H)>; + +// Floating point base2 log, F32 +def : InstRW<[V2Write_4cyc_2V02], (instrs FLOGB_ZPmZ_S)>; + +// Floating point base2 log, F64 +def : InstRW<[V2Write_3cyc_1V02], (instrs FLOGB_ZPmZ_D)>; + +// Floating point convert to integer, F16 +def : InstRW<[V2Write_6cyc_4V02], (instregex "^FCVTZ[SU]_ZPmZ_HtoH(_UNDEF)?$")>; + +// Floating point convert to integer, F32 +def : InstRW<[V2Write_4cyc_2V02], (instregex "^FCVTZ[SU]_ZPmZ_(HtoS|StoS)(_UNDEF)?$")>; + +// Floating point convert to integer, F64 +def : InstRW<[V2Write_3cyc_1V02], + (instregex "^FCVTZ[SU]_ZPmZ_(HtoD|StoD|DtoS|DtoD)(_UNDEF)?$")>; + +// Floating point copy +def : InstRW<[V2Write_2cyc_1V], (instregex "^FCPY_ZPmI_[HSD]$", + "^FDUP_ZI_[HSD]$")>; + +// Floating point divide, F16 +def : InstRW<[V2Write_13cyc_1V02_12rc], (instregex "^FDIVR?_ZPmZ_H$", + "^FDIV_ZPZZ_UNDEF_H$")>; + +// Floating point divide, F32 +def : InstRW<[V2Write_10cyc_1V02_9rc], (instregex "^FDIVR?_ZPmZ_S$", + "^FDIV_ZPZZ_UNDEF_S$")>; + +// Floating point divide, F64 +def : InstRW<[V2Write_15cyc_1V02_14rc], (instregex "^FDIVR?_ZPmZ_D$", + "^FDIV_ZPZZ_UNDEF_D$")>; + +// Floating point min/max pairwise +def : InstRW<[V2Write_2cyc_1V], (instregex "^F(MAX|MIN)(NM)?P_ZPmZZ_[HSD]$")>; + +// Floating point min/max +def : InstRW<[V2Write_2cyc_1V], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]$", + "^F(MAX|MIN)(NM)?_ZPZ[IZ]_UNDEF_[HSD]$")>; + +// Floating point multiply +def : InstRW<[V2Write_3cyc_1V], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]$", + "^FMULX_ZPZZ_UNDEF_[HSD]$", + "^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]$", + "^FMUL_ZPZ[IZ]_UNDEF_[HSD]$")>; + +// Floating point multiply accumulate +def : InstRW<[V2Wr_ZFMA, ReadDefault, V2Rd_ZFMA], + (instregex "^FN?ML[AS]_ZPmZZ_[HSD]$", + "^FN?(MAD|MSB)_ZPmZZ_[HSD]$")>; +def : InstRW<[V2Wr_ZFMA, V2Rd_ZFMA], + (instregex "^FML[AS]_ZZZI_[HSD]$", + "^FN?ML[AS]_ZPZZZ_UNDEF_[HSD]$")>; + +// Floating point multiply add/sub accumulate long +def : InstRW<[V2Wr_ZFMAL, V2Rd_ZFMAL], (instregex "^FML[AS]L[BT]_ZZZI?_SHH$")>; + +// Floating point reciprocal estimate, F16 +def : InstRW<[V2Write_6cyc_4V02], (instrs FRECPE_ZZ_H, FRECPX_ZPmZ_H, + FRSQRTE_ZZ_H, FRECPX_ZPmZ_UNDEF_H)>; + +// Floating point reciprocal estimate, F32 +def : InstRW<[V2Write_4cyc_2V02], (instrs FRECPE_ZZ_S, FRECPX_ZPmZ_S, + FRSQRTE_ZZ_S, FRECPX_ZPmZ_UNDEF_S)>; + +// Floating point reciprocal estimate, F64 +def : InstRW<[V2Write_3cyc_1V02], (instrs FRECPE_ZZ_D, FRECPX_ZPmZ_D, + FRSQRTE_ZZ_D, FRECPX_ZPmZ_UNDEF_D)>; + +// Floating point reciprocal step +def : InstRW<[V2Write_4cyc_1V], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]$")>; + +// Floating point reduction, F16 +def : InstRW<[V2Write_8cyc_4V], + (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_H$")>; + +// Floating point reduction, F32 +def : InstRW<[V2Write_6cyc_3V], + (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_S$")>; + +// Floating point reduction, F64 +def : InstRW<[V2Write_4cyc_2V], + (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_D$")>; + +// Floating point round to integral, F16 +def : InstRW<[V2Write_6cyc_4V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ(_UNDEF)?_H$")>; + +// Floating point round to integral, F32 +def : InstRW<[V2Write_4cyc_2V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ(_UNDEF)?_S$")>; + +// Floating point round to integral, F64 +def : InstRW<[V2Write_3cyc_1V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ(_UNDEF)?_D$")>; + +// Floating point square root, F16 +def : InstRW<[V2Write_13cyc_1V0_12rc], (instrs FSQRT_ZPmZ_H, FSQRT_ZPmZ_UNDEF_H)>; + +// Floating point square root, F32 +def : InstRW<[V2Write_10cyc_1V0_9rc], (instrs FSQRT_ZPmZ_S, FSQRT_ZPmZ_UNDEF_S)>; + +// Floating point square root, F64 +def : InstRW<[V2Write_16cyc_1V0_14rc], (instrs FSQRT_ZPmZ_D, FSQRT_ZPmZ_UNDEF_D)>; + +// Floating point trigonometric exponentiation +def : InstRW<[V2Write_3cyc_1V1], (instregex "^FEXPA_ZZ_[HSD]$")>; + +// Floating point trigonometric multiply add +def : InstRW<[V2Write_4cyc_1V], (instregex "^FTMAD_ZZI_[HSD]$")>; + +// Floating point trigonometric, miscellaneous +def : InstRW<[V2Write_3cyc_1V], (instregex "^FTS(MUL|SEL)_ZZZ_[HSD]$")>; + +// SVE BFloat16 (BF16) instructions +// ----------------------------------------------------------------------------- + +// Convert, F32 to BF16 +def : InstRW<[V2Write_4cyc_1V02], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>; + +// Dot product +def : InstRW<[V2Wr_ZBFDOT, V2Rd_ZBFDOT], (instrs BFDOT_ZZI, BFDOT_ZZZ)>; + +// Matrix multiply accumulate +def : InstRW<[V2Wr_ZBFMMA, V2Rd_ZBFMMA], (instrs BFMMLA_ZZZ)>; + +// Multiply accumulate long +def : InstRW<[V2Wr_ZBFMAL, V2Rd_ZBFMAL], (instregex "^BFMLAL[BT]_ZZZI?$")>; + +// SVE Load instructions +// ----------------------------------------------------------------------------- + +// Load vector +def : InstRW<[V2Write_6cyc_1L], (instrs LDR_ZXI)>; + +// Load predicate +def : InstRW<[V2Write_6cyc_1L_1M], (instrs LDR_PXI)>; + +// Contiguous load, scalar + imm +def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1[BHWD]_IMM_REAL$", + "^LD1S?B_[HSD]_IMM_REAL$", + "^LD1S?H_[SD]_IMM_REAL$", + "^LD1S?W_D_IMM_REAL$" )>; +// Contiguous load, scalar + scalar +def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1[BHWD]$", + "^LD1S?B_[HSD]$", + "^LD1S?H_[SD]$", + "^LD1S?W_D$" )>; + +// Contiguous load broadcast, scalar + imm +def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1R[BHWD]_IMM$", + "^LD1RS?B_[HSD]_IMM$", + "^LD1RS?H_[SD]_IMM$", + "^LD1RW_D_IMM$", + "^LD1RSW_IMM$", + "^LD1RQ_[BHWD]_IMM$")>; + +// Contiguous load broadcast, scalar + scalar +def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1RQ_[BHWD]$")>; + +// Non temporal load, scalar + imm +// Non temporal load, scalar + scalar +def : InstRW<[V2Write_6cyc_1L], (instregex "^LDNT1[BHWD]_ZR[IR]$")>; + +// Non temporal gather load, vector + scalar 32-bit element size +def : InstRW<[V2Write_9cyc_2L_4V], (instregex "^LDNT1[BHW]_ZZR_S_REAL$", + "^LDNT1S[BH]_ZZR_S_REAL$")>; + +// Non temporal gather load, vector + scalar 64-bit element size +def : InstRW<[V2Write_9cyc_2L_2V1], (instregex "^LDNT1S?[BHW]_ZZR_D_REAL$")>; +def : InstRW<[V2Write_9cyc_2L_2V1], (instrs LDNT1D_ZZR_D_REAL)>; + +// Contiguous first faulting load, scalar + scalar +def : InstRW<[V2Write_6cyc_1L_1S], (instregex "^LDFF1[BHWD]_REAL$", + "^LDFF1S?B_[HSD]_REAL$", + "^LDFF1S?H_[SD]_REAL$", + "^LDFF1S?W_D_REAL$")>; + +// Contiguous non faulting load, scalar + imm +def : InstRW<[V2Write_6cyc_1L], (instregex "^LDNF1[BHWD]_IMM_REAL$", + "^LDNF1S?B_[HSD]_IMM_REAL$", + "^LDNF1S?H_[SD]_IMM_REAL$", + "^LDNF1S?W_D_IMM_REAL$")>; + +// Contiguous Load two structures to two vectors, scalar + imm +def : InstRW<[V2Write_8cyc_2L_2V], (instregex "^LD2[BHWD]_IMM$")>; + +// Contiguous Load two structures to two vectors, scalar + scalar +def : InstRW<[V2Write_9cyc_2L_2V_2S], (instregex "^LD2[BHWD]$")>; + +// Contiguous Load three structures to three vectors, scalar + imm +def : InstRW<[V2Write_9cyc_3L_3V], (instregex "^LD3[BHWD]_IMM$")>; + +// Contiguous Load three structures to three vectors, scalar + scalar +def : InstRW<[V2Write_10cyc_3V_3L_3S], (instregex "^LD3[BHWD]$")>; + +// Contiguous Load four structures to four vectors, scalar + imm +def : InstRW<[V2Write_9cyc_4L_8V], (instregex "^LD4[BHWD]_IMM$")>; + +// Contiguous Load four structures to four vectors, scalar + scalar +def : InstRW<[V2Write_10cyc_4L_8V_4S], (instregex "^LD4[BHWD]$")>; + +// Gather load, vector + imm, 32-bit element size +def : InstRW<[V2Write_9cyc_1L_4V], (instregex "^GLD(FF)?1S?[BH]_S_IMM_REAL$", + "^GLD(FF)?1W_IMM_REAL$")>; + +// Gather load, vector + imm, 64-bit element size +def : InstRW<[V2Write_9cyc_1L_4V], (instregex "^GLD(FF)?1S?[BHW]_D_IMM_REAL$", + "^GLD(FF)?1D_IMM_REAL$")>; + +// Gather load, 32-bit scaled offset +def : InstRW<[V2Write_10cyc_1L_8V], + (instregex "^GLD(FF)?1S?H_S_[SU]XTW_SCALED_REAL$", + "^GLD(FF)?1W_[SU]XTW_SCALED_REAL")>; + +// Gather load, 64-bit scaled offset +// NOTE: These instructions are not specified in the SOG. +def : InstRW<[V2Write_10cyc_1L_4V], + (instregex "^GLD(FF)?1S?[HW]_D_([SU]XTW_)?SCALED_REAL$", + "^GLD(FF)?1D_([SU]XTW_)?SCALED_REAL$")>; + +// Gather load, 32-bit unpacked unscaled offset +def : InstRW<[V2Write_9cyc_1L_4V], (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW_REAL$", + "^GLD(FF)?1W_[SU]XTW_REAL$")>; + +// Gather load, 64-bit unpacked unscaled offset +// NOTE: These instructions are not specified in the SOG. +def : InstRW<[V2Write_9cyc_1L_2V], + (instregex "^GLD(FF)?1S?[BHW]_D_([SU]XTW_)?REAL$", + "^GLD(FF)?1D_([SU]XTW_)?REAL$")>; + +// SVE Store instructions +// ----------------------------------------------------------------------------- + +// Store from predicate reg +def : InstRW<[V2Write_1cyc_1L01], (instrs STR_PXI)>; + +// Store from vector reg +def : InstRW<[V2Write_2cyc_1L01_1V01], (instrs STR_ZXI)>; + +// Contiguous store, scalar + imm +def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^ST1[BHWD]_IMM$", + "^ST1B_[HSD]_IMM$", + "^ST1H_[SD]_IMM$", + "^ST1W_D_IMM$")>; + +// Contiguous store, scalar + scalar +def : InstRW<[V2Write_2cyc_1L01_1S_1V01], (instregex "^ST1H(_[SD])?$")>; +def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^ST1[BWD]$", + "^ST1B_[HSD]$", + "^ST1W_D$")>; + +// Contiguous store two structures from two vectors, scalar + imm +def : InstRW<[V2Write_4cyc_1L01_1V01], (instregex "^ST2[BHWD]_IMM$")>; + +// Contiguous store two structures from two vectors, scalar + scalar +def : InstRW<[V2Write_4cyc_2L01_2S_2V01], (instrs ST2H)>; +def : InstRW<[V2Write_4cyc_2L01_2V01], (instregex "^ST2[BWD]$")>; + +// Contiguous store three structures from three vectors, scalar + imm +def : InstRW<[V2Write_7cyc_9L01_9V01], (instregex "^ST3[BHWD]_IMM$")>; + +// Contiguous store three structures from three vectors, scalar + scalar +def : InstRW<[V2Write_7cyc_9L01_9S_9V01], (instregex "^ST3[BHWD]$")>; + +// Contiguous store four structures from four vectors, scalar + imm +def : InstRW<[V2Write_11cyc_18L01_18V01], (instregex "^ST4[BHWD]_IMM$")>; + +// Contiguous store four structures from four vectors, scalar + scalar +def : InstRW<[V2Write_11cyc_18L01_18S_18V01], (instregex "^ST4[BHWD]$")>; + +// Non temporal store, scalar + imm +def : InstRW<[V2Write_2cyc_1L01_1V], (instregex "^STNT1[BHWD]_ZRI$")>; + +// Non temporal store, scalar + scalar +def : InstRW<[V2Write_2cyc_1L01_1S_1V], (instrs STNT1H_ZRR)>; +def : InstRW<[V2Write_2cyc_1L01_1V], (instregex "^STNT1[BWD]_ZRR$")>; + +// Scatter non temporal store, vector + scalar 32-bit element size +def : InstRW<[V2Write_4cyc_4L01_4V01], (instregex "^STNT1[BHW]_ZZR_S")>; + +// Scatter non temporal store, vector + scalar 64-bit element size +def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^STNT1[BHWD]_ZZR_D")>; + +// Scatter store vector + imm 32-bit element size +def : InstRW<[V2Write_4cyc_4L01_4V01], (instregex "^SST1[BH]_S_IMM$", + "^SST1W_IMM$")>; + +// Scatter store vector + imm 64-bit element size +def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^SST1[BHW]_D_IMM$", + "^SST1D_IMM$")>; + +// Scatter store, 32-bit scaled offset +def : InstRW<[V2Write_4cyc_4L01_4V01], + (instregex "^SST1(H_S|W)_[SU]XTW_SCALED$")>; + +// Scatter store, 32-bit unpacked unscaled offset +def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^SST1[BHW]_D_[SU]XTW$", + "^SST1D_[SU]XTW$")>; + +// Scatter store, 32-bit unpacked scaled offset +def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^SST1[HW]_D_[SU]XTW_SCALED$", + "^SST1D_[SU]XTW_SCALED$")>; + +// Scatter store, 32-bit unscaled offset +def : InstRW<[V2Write_4cyc_4L01_4V01], (instregex "^SST1[BH]_S_[SU]XTW$", + "^SST1W_[SU]XTW$")>; + +// Scatter store, 64-bit scaled offset +def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^SST1[HW]_D_SCALED$", + "^SST1D_SCALED$")>; + +// Scatter store, 64-bit unscaled offset +def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^SST1[BHW]_D$", + "^SST1D$")>; + +// SVE Miscellaneous instructions +// ----------------------------------------------------------------------------- + +// Read first fault register, unpredicated +def : InstRW<[V2Write_2cyc_1M0], (instrs RDFFR_P_REAL)>; + +// Read first fault register, predicated +def : InstRW<[V2Write_3or4cyc_1M0_1M], (instrs RDFFR_PPz_REAL)>; + +// Read first fault register and set flags +def : InstRW<[V2Write_4or5cyc_2M0_2M], (instrs RDFFRS_PPz)>; + +// Set first fault register +// Write to first fault register +def : InstRW<[V2Write_2cyc_1M0], (instrs SETFFR, WRFFR)>; + +// Prefetch +// NOTE: This is not specified in the SOG. +def : InstRW<[V2Write_4cyc_1L], (instregex "^PRF[BHWD]")>; + +// SVE Cryptographic instructions +// ----------------------------------------------------------------------------- + +// Crypto AES ops +def : InstRW<[V2Write_2cyc_1V], (instregex "^AES[DE]_ZZZ_B$", + "^AESI?MC_ZZ_B$")>; + +// Crypto SHA3 ops +def : InstRW<[V2Write_2cyc_1V0], (instregex "^(BCAX|EOR3)_ZZZZ$", + "^RAX1_ZZZ_D$", + "^XAR_ZZZI_[BHSD]$")>; + +// Crypto SM4 ops +def : InstRW<[V2Write_4cyc_1V0], (instregex "^SM4E(KEY)?_ZZZ_S$")>; + +} diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td b/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td --- a/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td +++ b/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td @@ -28,3 +28,44 @@ def NeoverseNoLSL : MCSchedPredicate< CheckAll<[CheckShiftLSL, CheckShiftBy0]>>; + +// Check if the fourth operand of an instruction is WZR or XZR +def NeoverseReg3IsZero : MCSchedPredicate< + CheckAll< + [CheckIsRegOperand<3>, + CheckAny< + [CheckRegOperand<3, WZR>, + CheckRegOperand<3, XZR>]>]>>; + +// Identify EXTR with one register (alias for ROR immediate) +def NeoverseOneRegEXTR : MCSchedPredicate< + CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>, + CheckSameRegOperand<1, 2>]>>; + +// Identify LDR/STR H/Q-form scaled (and potentially extended) FP instructions +def NeoverseHQForm : MCSchedPredicate< + CheckAll<[ + CheckAny<[CheckHForm, CheckQForm]>, + CheckImmOperand<4, 1>]>>; + +// Check if == +def NeoversePdIsPgFn : TIIPredicate< + "isNeoversePdSameAsPg", + MCOpcodeSwitchStatement< + [MCOpcodeSwitchCase<[BRKA_PPmP, BRKB_PPmP], + MCReturnStatement>>], + MCReturnStatement>>>; +def NeoversePdIsPg : MCSchedPredicate; + +// Check if SVE INC/DEC (scalar), ALL, {1, 2, 4} +def NeoverseCheapIncDec : MCSchedPredicate< + CheckAll<[CheckOpcode<[ + INCB_XPiI, INCH_XPiI, + INCW_XPiI, INCD_XPiI, + DECB_XPiI, DECH_XPiI, + DECW_XPiI, DECD_XPiI]>, + CheckImmOperand<2, 31>, + CheckAny<[ + CheckImmOperand<3, 1>, + CheckImmOperand<3, 2>, + CheckImmOperand<3, 4>]>]>>; diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td --- a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td +++ b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td @@ -65,6 +65,12 @@ "AArch64InstrInfo::isFpOrNEON" >; +// Identify whether an instruction is the 16-bit NEON form based on its result. +def CheckHForm : CheckFunctionPredicateWithTII< + "AArch64_MC::isHForm", + "AArch64InstrInfo::isHForm" +>; + // Identify whether an instruction is the 128-bit NEON form based on its result. def CheckQForm : CheckFunctionPredicateWithTII< "AArch64_MC::isQForm", diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h @@ -63,6 +63,7 @@ namespace AArch64_MC { void initLLVMToCVRegMapping(MCRegisterInfo *MRI); +bool isHForm(const MCInst &MI, const MCInstrInfo *MCII); bool isQForm(const MCInst &MI, const MCInstrInfo *MCII); bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII); } diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp @@ -300,6 +300,13 @@ MRI->mapLLVMRegToCVReg(I.Reg, static_cast(I.CVReg)); } +bool AArch64_MC::isHForm(const MCInst &MI, const MCInstrInfo *MCII) { + const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID]; + return llvm::any_of(MI, [&](const MCOperand &Op) { + return Op.isReg() && FPR16.contains(Op.getReg()); + }); +} + bool AArch64_MC::isQForm(const MCInst &MI, const MCInstrInfo *MCII) { const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID]; return llvm::any_of(MI, [&](const MCOperand &Op) { diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s new file mode 100644 --- /dev/null +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s @@ -0,0 +1,3765 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %s | FileCheck %s + +#------------------------------------------------------------------------------ +# Add/sub (immediate) +#------------------------------------------------------------------------------ + +add w2, w3, #4095 +add w30, w29, #1, lsl #12 +add w13, w5, #4095, lsl #12 +add x5, x7, #1638 +add w20, wsp, #801 +add wsp, wsp, #1104 +add wsp, w30, #4084 +add x0, x24, #291 +add x3, x24, #4095, lsl #12 +add x8, sp, #1074 +add sp, x29, #3816 +sub w0, wsp, #4077 +sub w4, w20, #546, lsl #12 +sub sp, sp, #288 +sub wsp, w19, #16 +adds w13, w23, #291, lsl #12 +cmn w2, #4095 +adds w20, wsp, #0 +cmn x3, #1, lsl #12 +cmp sp, #20, lsl #12 +cmp x30, #4095 +subs x4, sp, #3822 +cmn w3, #291, lsl #12 +cmn wsp, #1365 +cmn sp, #1092, lsl #12 +mov sp, x30 +mov wsp, w20 +mov x11, sp +mov w24, wsp + +#------------------------------------------------------------------------------ +# Add-subtract (shifted register) +#------------------------------------------------------------------------------ + +add w3, w5, w7 +add wzr, w3, w5 +add w20, wzr, w4 +add w4, w6, wzr +add w11, w13, w15 +add w9, w3, wzr, lsl #10 +add w17, w29, w20, lsl #31 +add w21, w22, w23, lsr #0 +add w24, w25, w26, lsr #18 +add w27, w28, w29, lsr #31 +add w2, w3, w4, asr #0 +add w5, w6, w7, asr #21 +add w8, w9, w10, asr #31 +add x3, x5, x7 +add xzr, x3, x5 +add x20, xzr, x4 +add x4, x6, xzr +add x11, x13, x15 +add x9, x3, xzr, lsl #10 +add x17, x29, x20, lsl #63 +add x21, x22, x23, lsr #0 +add x24, x25, x26, lsr #18 +add x27, x28, x29, lsr #63 +add x2, x3, x4, asr #0 +add x5, x6, x7, asr #21 +add x8, x9, x10, asr #63 +adds w3, w5, w7 +cmn w3, w5 +adds w20, wzr, w4 +adds w4, w6, wzr +adds w11, w13, w15 +adds w9, w3, wzr, lsl #10 +adds w17, w29, w20, lsl #31 +adds w21, w22, w23, lsr #0 +adds w24, w25, w26, lsr #18 +adds w27, w28, w29, lsr #31 +adds w2, w3, w4, asr #0 +adds w5, w6, w7, asr #21 +adds w8, w9, w10, asr #31 +adds x3, x5, x7 +cmn x3, x5 +adds x20, xzr, x4 +adds x4, x6, xzr +adds x11, x13, x15 +adds x9, x3, xzr, lsl #10 +adds x17, x29, x20, lsl #63 +adds x21, x22, x23, lsr #0 +adds x24, x25, x26, lsr #18 +adds x27, x28, x29, lsr #63 +adds x2, x3, x4, asr #0 +adds x5, x6, x7, asr #21 +adds x8, x9, x10, asr #63 +sub w3, w5, w7 +sub wzr, w3, w5 +sub w4, w6, wzr +sub w11, w13, w15 +sub w9, w3, wzr, lsl #10 +sub w17, w29, w20, lsl #31 +sub w21, w22, w23, lsr #0 +sub w24, w25, w26, lsr #18 +sub w27, w28, w29, lsr #31 +sub w2, w3, w4, asr #0 +sub w5, w6, w7, asr #21 +sub w8, w9, w10, asr #31 +sub x3, x5, x7 +sub xzr, x3, x5 +sub x4, x6, xzr +sub x11, x13, x15 +sub x9, x3, xzr, lsl #10 +sub x17, x29, x20, lsl #63 +sub x21, x22, x23, lsr #0 +sub x24, x25, x26, lsr #18 +sub x27, x28, x29, lsr #63 +sub x2, x3, x4, asr #0 +sub x5, x6, x7, asr #21 +sub x8, x9, x10, asr #63 +subs w3, w5, w7 +cmp w3, w5 +subs w4, w6, wzr +subs w11, w13, w15 +subs w9, w3, wzr, lsl #10 +subs w17, w29, w20, lsl #31 +subs w21, w22, w23, lsr #0 +subs w24, w25, w26, lsr #18 +subs w27, w28, w29, lsr #31 +subs w2, w3, w4, asr #0 +subs w5, w6, w7, asr #21 +subs w8, w9, w10, asr #31 +subs x3, x5, x7 +cmp x3, x5 +subs x4, x6, xzr +subs x11, x13, x15 +subs x9, x3, xzr, lsl #10 +subs x17, x29, x20, lsl #63 +subs x21, x22, x23, lsr #0 +subs x24, x25, x26, lsr #18 +subs x27, x28, x29, lsr #63 +subs x2, x3, x4, asr #0 +subs x5, x6, x7, asr #21 +subs x8, x9, x10, asr #63 +cmn wzr, w4 +cmn w5, wzr +cmn w6, w7 +cmn w8, w9, lsl #15 +cmn w10, w11, lsl #31 +cmn w12, w13, lsr #0 +cmn w14, w15, lsr #21 +cmn w16, w17, lsr #31 +cmn w18, w19, asr #0 +cmn w20, w21, asr #22 +cmn w22, w23, asr #31 +cmn x0, x3 +cmn xzr, x4 +cmn x5, xzr +cmn x6, x7 +cmn x8, x9, lsl #15 +cmn x10, x11, lsl #63 +cmn x12, x13, lsr #0 +cmn x14, x15, lsr #41 +cmn x16, x17, lsr #63 +cmn x18, x19, asr #0 +cmn x20, x21, asr #55 +cmn x22, x23, asr #63 +cmp w0, w3 +cmp wzr, w4 +cmp w5, wzr +cmp w6, w7 +cmp w8, w9, lsl #15 +cmp w10, w11, lsl #31 +cmp w12, w13, lsr #0 +cmp w14, w15, lsr #21 +cmp w18, w19, asr #0 +cmp w20, w21, asr #22 +cmp w22, w23, asr #31 +cmp x0, x3 +cmp xzr, x4 +cmp x5, xzr +cmp x6, x7 +cmp x8, x9, lsl #15 +cmp x10, x11, lsl #63 +cmp x12, x13, lsr #0 +cmp x14, x15, lsr #41 +cmp x16, x17, lsr #63 +cmp x18, x19, asr #0 +cmp x20, x21, asr #55 +cmp x22, x23, asr #63 +cmp wzr, w0 +cmp xzr, x0 + +#------------------------------------------------------------------------------ +# Add-subtract (shifted register) +#------------------------------------------------------------------------------ + +adc w29, w27, w25 +adc wzr, w3, w4 +adc w9, wzr, w10 +adc w20, w0, wzr +adc x29, x27, x25 +adc xzr, x3, x4 +adc x9, xzr, x10 +adc x20, x0, xzr +adcs w29, w27, w25 +adcs wzr, w3, w4 +adcs w9, wzr, w10 +adcs w20, w0, wzr +adcs x29, x27, x25 +adcs xzr, x3, x4 +adcs x9, xzr, x10 +adcs x20, x0, xzr +sbc w29, w27, w25 +sbc wzr, w3, w4 +ngc w9, w10 +sbc w20, w0, wzr +sbc x29, x27, x25 +sbc xzr, x3, x4 +ngc x9, x10 +sbc x20, x0, xzr +sbcs w29, w27, w25 +sbcs wzr, w3, w4 +ngcs w9, w10 +sbcs w20, w0, wzr +sbcs x29, x27, x25 +sbcs xzr, x3, x4 +ngcs x9, x10 +sbcs x20, x0, xzr +ngc w3, w12 +ngc wzr, w9 +ngc w23, wzr +ngc x29, x30 +ngc xzr, x0 +ngc x0, xzr +ngcs w3, w12 +ngcs wzr, w9 +ngcs w23, wzr +ngcs x29, x30 +ngcs xzr, x0 +ngcs x0, xzr + +#------------------------------------------------------------------------------ +# Compare and branch (immediate) +#------------------------------------------------------------------------------ + +sbfx x1, x2, #3, #2 +asr x3, x4, #63 +asr wzr, wzr, #31 +sbfx w12, w9, #0, #1 +ubfiz x4, x5, #52, #11 +ubfx xzr, x4, #0, #1 +ubfiz x4, xzr, #1, #6 +lsr x5, x6, #12 +bfi x4, x5, #52, #11 +bfxil xzr, x4, #0, #1 +bfi x4, xzr, #1, #6 +bfxil x5, x6, #12, #52 +sxtb w1, w2 +sxtb xzr, w3 +sxth w9, w10 +sxth x0, w1 +sxtw x3, w30 +uxtb w1, w2 +uxth w9, w10 +ubfx x3, x30, #0, #32 +asr w3, w2, #0 +asr w9, w10, #31 +asr x20, x21, #63 +asr w1, wzr, #3 +lsr w3, w2, #0 +lsr w9, w10, #31 +lsr x20, x21, #63 +lsr wzr, wzr, #3 +lsr w3, w2, #0 +lsl w9, w10, #31 +lsl x20, x21, #63 +lsl w1, wzr, #3 +sbfx w9, w10, #0, #1 +sbfiz x2, x3, #63, #1 +asr x19, x20, #0 +sbfiz x9, x10, #5, #59 +asr w9, w10, #0 +sbfiz w11, w12, #31, #1 +sbfiz w13, w14, #29, #3 +sbfiz xzr, xzr, #10, #11 +sbfx w9, w10, #0, #1 +asr x2, x3, #63 +asr x19, x20, #0 +asr x9, x10, #5 +asr w9, w10, #0 +asr w11, w12, #31 +asr w13, w14, #29 +sbfx xzr, xzr, #10, #11 +bfxil w9, w10, #0, #1 +bfi x2, x3, #63, #1 +bfxil x19, x20, #0, #64 +bfi x9, x10, #5, #59 +bfxil w9, w10, #0, #32 +bfi w11, w12, #31, #1 +bfi w13, w14, #29, #3 +bfi xzr, xzr, #10, #11 +bfxil w9, w10, #0, #1 +bfxil x2, x3, #63, #1 +bfxil x19, x20, #0, #64 +bfxil x9, x10, #5, #59 +bfxil w9, w10, #0, #32 +bfxil w11, w12, #31, #1 +bfxil w13, w14, #29, #3 +bfxil xzr, xzr, #10, #11 +ubfx w9, w10, #0, #1 +lsl x2, x3, #63 +lsr x19, x20, #0 +lsl x9, x10, #5 +lsr w9, w10, #0 +lsl w11, w12, #31 +lsl w13, w14, #29 +ubfiz xzr, xzr, #10, #11 +ubfx w9, w10, #0, #1 +lsr x2, x3, #63 +lsr x19, x20, #0 +lsr x9, x10, #5 +lsr w9, w10, #0 +lsr w11, w12, #31 +lsr w13, w14, #29 +ubfx xzr, xzr, #10, #11 + +#------------------------------------------------------------------------------ +# Compare and branch (immediate) +#------------------------------------------------------------------------------ + +cbz w5, #4 +cbz x5, #0 +cbnz x2, #-4 +cbnz x26, #1048572 +cbz wzr, #0 +cbnz xzr, #0 + +#------------------------------------------------------------------------------ +# Conditional branch (immediate) +#------------------------------------------------------------------------------ + +b.ne #4 +b.ge #1048572 +b.ge #-4 + +#------------------------------------------------------------------------------ +# Conditional compare (immediate) +#------------------------------------------------------------------------------ + +ccmp w1, #31, #0, eq +ccmp w3, #0, #15, hs +ccmp wzr, #15, #13, hs +ccmp x9, #31, #0, le +ccmp x3, #0, #15, gt +ccmp xzr, #5, #7, ne +ccmn w1, #31, #0, eq +ccmn w3, #0, #15, hs +ccmn wzr, #15, #13, hs +ccmn x9, #31, #0, le +ccmn x3, #0, #15, gt +ccmn xzr, #5, #7, ne + +#------------------------------------------------------------------------------ +# Conditional compare (register) +#------------------------------------------------------------------------------ + +ccmp w1, wzr, #0, eq +ccmp w3, w0, #15, hs +ccmp wzr, w15, #13, hs +ccmp x9, xzr, #0, le +ccmp x3, x0, #15, gt +ccmp xzr, x5, #7, ne +ccmn w1, wzr, #0, eq +ccmn w3, w0, #15, hs +ccmn wzr, w15, #13, hs +ccmn x9, xzr, #0, le +ccmn x3, x0, #15, gt +ccmn xzr, x5, #7, ne + +#------------------------------------------------------------------------------ +# Conditional branch (immediate) +#------------------------------------------------------------------------------ + +csel w1, w0, w19, ne +csel wzr, w5, w9, eq +csel w9, wzr, w30, gt +csel w1, w28, wzr, mi +csel x19, x23, x29, lt +csel xzr, x3, x4, ge +csel x5, xzr, x6, hs +csel x7, x8, xzr, lo +csinc w1, w0, w19, ne +csinc wzr, w5, w9, eq +csinc w9, wzr, w30, gt +csinc w1, w28, wzr, mi +csinc x19, x23, x29, lt +csinc xzr, x3, x4, ge +csinc x5, xzr, x6, hs +csinc x7, x8, xzr, lo +csinv w1, w0, w19, ne +csinv wzr, w5, w9, eq +csinv w9, wzr, w30, gt +csinv w1, w28, wzr, mi +csinv x19, x23, x29, lt +csinv xzr, x3, x4, ge +csinv x5, xzr, x6, hs +csinv x7, x8, xzr, lo +csneg w1, w0, w19, ne +csneg wzr, w5, w9, eq +csneg w9, wzr, w30, gt +csneg w1, w28, wzr, mi +csneg x19, x23, x29, lt +csneg xzr, x3, x4, ge +csneg x5, xzr, x6, hs +csneg x7, x8, xzr, lo +cset w3, eq +cset x9, pl +csetm w20, ne +csetm x30, ge +csinc w2, wzr, wzr, al +csinv x3, xzr, xzr, nv +cinc w3, w5, gt +cinc wzr, w4, le +cset w9, lt +cinc x3, x5, gt +cinc xzr, x4, le +cset x9, lt +csinc w5, w6, w6, nv +csinc x1, x2, x2, al +cinv w3, w5, gt +cinv wzr, w4, le +csetm w9, lt +cinv x3, x5, gt +cinv xzr, x4, le +csetm x9, lt +csinv x1, x0, x0, al +csinv w9, w8, w8, nv +cneg w3, w5, gt +cneg wzr, w4, le +cneg w9, wzr, lt +cneg x3, x5, gt +cneg xzr, x4, le +cneg x9, xzr, lt +csneg x4, x8, x8, al +csinv w9, w8, w8, nv + +#------------------------------------------------------------------------------ +# Data-processing (1 source) +#------------------------------------------------------------------------------ + +rbit w0, w7 +rbit x18, x3 +rev16 w17, w1 +rev16 x5, x2 +rev w18, w0 +rev32 x20, x1 +rev x22, x2 +clz w24, w3 +clz x26, x4 +cls w3, w5 +cls x20, x5 + +#------------------------------------------------------------------------------ +# Data-processing (2 source) +#------------------------------------------------------------------------------ + +udiv w0, w7, w10 +udiv x9, x22, x4 +sdiv w12, w21, w0 +sdiv x13, x2, x1 +lsl w11, w12, w13 +lsl x14, x15, x16 +lsr w17, w18, w19 +lsr x20, x21, x22 +asr w23, w24, w25 +asr x26, x27, x28 +ror w0, w1, w2 +ror x3, x4, x5 +lsl w6, w7, w8 +lsl x9, x10, x11 +lsr w12, w13, w14 +lsr x15, x16, x17 +asr w18, w19, w20 +asr x21, x22, x23 +ror w24, w25, w26 +ror x27, x28, x29 + +#------------------------------------------------------------------------------ +# Data-processing (3 sources) +#------------------------------------------------------------------------------ + +smulh x30, x29, x28 +smulh xzr, x27, x26 +umulh x30, x29, x28 +umulh x23, x30, xzr +madd w1, w3, w7, w4 +madd wzr, w0, w9, w11 +madd w13, wzr, w4, w4 +madd w19, w30, wzr, w29 +mul w4, w5, w6 +madd x1, x3, x7, x4 +madd xzr, x0, x9, x11 +madd x13, xzr, x4, x4 +madd x19, x30, xzr, x29 +mul x4, x5, x6 +msub w1, w3, w7, w4 +msub wzr, w0, w9, w11 +msub w13, wzr, w4, w4 +msub w19, w30, wzr, w29 +mneg w4, w5, w6 +msub x1, x3, x7, x4 +msub xzr, x0, x9, x11 +msub x13, xzr, x4, x4 +msub x19, x30, xzr, x29 +mneg x4, x5, x6 +smaddl x3, w5, w2, x9 +smaddl xzr, w10, w11, x12 +smaddl x13, wzr, w14, x15 +smaddl x16, w17, wzr, x18 +smull x19, w20, w21 +smsubl x3, w5, w2, x9 +smsubl xzr, w10, w11, x12 +smsubl x13, wzr, w14, x15 +smsubl x16, w17, wzr, x18 +smnegl x19, w20, w21 +umaddl x3, w5, w2, x9 +umaddl xzr, w10, w11, x12 +umaddl x13, wzr, w14, x15 +umaddl x16, w17, wzr, x18 +umull x19, w20, w21 +umsubl x3, w5, w2, x9 +umsubl x16, w17, wzr, x18 +umnegl x19, w20, w21 +smulh x30, x29, x28 +smulh x23, x22, xzr +umulh x23, x22, xzr +mul x19, x20, xzr +mneg w21, w22, w23 +smull x11, w13, w17 +umull x11, w13, w17 +smnegl x11, w13, w17 +umnegl x11, w13, w17 + +#------------------------------------------------------------------------------ +# Extract (immediate) +#------------------------------------------------------------------------------ + +extr w3, w5, w7, #0 +extr w11, w13, w17, #31 +extr x3, x5, x7, #15 +extr x11, x13, x17, #63 +ror x19, x23, #24 +ror x29, xzr, #63 +ror w9, w13, #31 + +#------------------------------------------------------------------------------ +# Floating-point compare +#------------------------------------------------------------------------------ + +fcmp s3, s5 +fcmp s31, #0.0 +fcmp s31, #0.0 +fcmpe s29, s30 +fcmpe s15, #0.0 +fcmpe s15, #0.0 +fcmp d4, d12 +fcmp d23, #0.0 +fcmp d23, #0.0 +fcmpe d26, d22 +fcmpe d29, #0.0 +fcmpe d29, #0.0 + +#------------------------------------------------------------------------------ +# Floating-point conditional compare +#------------------------------------------------------------------------------ + +fccmp s1, s31, #0, eq +fccmp s3, s0, #15, hs +fccmp s31, s15, #13, hs +fccmp d9, d31, #0, le +fccmp d3, d0, #15, gt +fccmp d31, d5, #7, ne +fccmpe s1, s31, #0, eq +fccmpe s3, s0, #15, hs +fccmpe s31, s15, #13, hs +fccmpe d9, d31, #0, le +fccmpe d3, d0, #15, gt +fccmpe d31, d5, #7, ne + +#------------------------------------------------------------------------------- +# Floating-point conditional compare +#------------------------------------------------------------------------------- + +fcsel s3, s20, s9, pl +fcsel d9, d10, d11, mi + +#------------------------------------------------------------------------------ +# Floating-point data-processing (1 source) +#------------------------------------------------------------------------------ + +fmov s0, s1 +fabs s2, s3 +fneg s4, s5 +fsqrt s6, s7 +fcvt d8, s9 +fcvt h10, s11 +frintn s12, s13 +frintp s14, s15 +frintm s16, s17 +frintz s18, s19 +frinta s20, s21 +frintx s22, s23 +frinti s24, s25 +fmov d0, d1 +fabs d2, d3 +fneg d4, d5 +fsqrt d6, d7 +fcvt s8, d9 +fcvt h10, d11 +frintn d12, d13 +frintp d14, d15 +frintm d16, d17 +frintz d18, d19 +frinta d20, d21 +frintx d22, d23 +frinti d24, d25 +fcvt s26, h27 +fcvt d28, h29 + +#------------------------------------------------------------------------------ +# Floating-point data-processing (2 sources) +#------------------------------------------------------------------------------ + +fmul s20, s19, s17 +fdiv s1, s2, s3 +fadd s4, s5, s6 +fsub s7, s8, s9 +fmax s10, s11, s12 +fmin s13, s14, s15 +fmaxnm s16, s17, s18 +fminnm s19, s20, s21 +fnmul s22, s23, s2 +fmul d20, d19, d17 +fdiv d1, d2, d3 +fadd d4, d5, d6 +fsub d7, d8, d9 +fmax d10, d11, d12 +fmin d13, d14, d15 +fmaxnm d16, d17, d18 +fminnm d19, d20, d21 +fnmul d22, d23, d24 + +#------------------------------------------------------------------------------ +# Floating-point data-processing (1 source) +#------------------------------------------------------------------------------ + +fmadd s3, s5, s6, s31 +fmadd d3, d13, d0, d23 +fmsub s3, s5, s6, s31 +fmsub d3, d13, d0, d23 +fnmadd s3, s5, s6, s31 +fnmadd d3, d13, d0, d23 +fnmsub s3, s5, s6, s31 +fnmsub d3, d13, d0, d23 + +#------------------------------------------------------------------------------ +# Floating-point <-> fixed-point conversion +#------------------------------------------------------------------------------ + +fcvtzs w3, h5, #1 +fcvtzs wzr, h20, #13 +fcvtzs w19, h0, #32 +fcvtzs x3, h5, #1 +fcvtzs x12, h30, #45 +fcvtzs x19, h0, #64 +fcvtzs w3, s5, #1 +fcvtzs wzr, s20, #13 +fcvtzs w19, s0, #32 +fcvtzs x3, s5, #1 +fcvtzs x12, s30, #45 +fcvtzs x19, s0, #64 +fcvtzs w3, d5, #1 +fcvtzs wzr, d20, #13 +fcvtzs w19, d0, #32 +fcvtzs x3, d5, #1 +fcvtzs x12, d30, #45 +fcvtzs x19, d0, #64 +fcvtzu w3, h5, #1 +fcvtzu wzr, h20, #13 +fcvtzu w19, h0, #32 +fcvtzu x3, h5, #1 +fcvtzu x12, h30, #45 +fcvtzu x19, h0, #64 +fcvtzu w3, s5, #1 +fcvtzu wzr, s20, #13 +fcvtzu w19, s0, #32 +fcvtzu x3, s5, #1 +fcvtzu x12, s30, #45 +fcvtzu x19, s0, #64 +fcvtzu w3, d5, #1 +fcvtzu wzr, d20, #13 +fcvtzu w19, d0, #32 +fcvtzu x3, d5, #1 +fcvtzu x12, d30, #45 +fcvtzu x19, d0, #64 +scvtf h23, w19, #1 +scvtf h31, wzr, #20 +scvtf h14, w0, #32 +scvtf h23, x19, #1 +scvtf h31, xzr, #20 +scvtf h14, x0, #64 +scvtf s23, w19, #1 +scvtf s31, wzr, #20 +scvtf s14, w0, #32 +scvtf s23, x19, #1 +scvtf s31, xzr, #20 +scvtf s14, x0, #64 +scvtf d23, w19, #1 +scvtf d31, wzr, #20 +scvtf d14, w0, #32 +scvtf d23, x19, #1 +scvtf d31, xzr, #20 +scvtf d14, x0, #64 +ucvtf h23, w19, #1 +ucvtf h31, wzr, #20 +ucvtf h14, w0, #32 +ucvtf h23, x19, #1 +ucvtf h31, xzr, #20 +ucvtf h14, x0, #64 +ucvtf s23, w19, #1 +ucvtf s31, wzr, #20 +ucvtf s14, w0, #32 +ucvtf s23, x19, #1 +ucvtf s31, xzr, #20 +ucvtf s14, x0, #64 +ucvtf d23, w19, #1 +ucvtf d31, wzr, #20 +ucvtf d14, w0, #32 +ucvtf d23, x19, #1 +ucvtf d31, xzr, #20 +ucvtf d14, x0, #64 + +#------------------------------------------------------------------------------ +# Floating-point <-> integer conversion +#------------------------------------------------------------------------------ + +fcvtns w3, h31 +fcvtns xzr, h12 +fcvtnu wzr, h12 +fcvtnu x0, h0 +fcvtps wzr, h9 +fcvtps x12, h20 +fcvtpu w30, h23 +fcvtpu x29, h3 +fcvtms w2, h3 +fcvtms x4, h5 +fcvtmu w6, h7 +fcvtmu x8, h9 +fcvtzs w10, h11 +fcvtzs x12, h13 +fcvtzu w14, h15 +fcvtzu x15, h16 +scvtf h17, w18 +scvtf h19, x20 +ucvtf h21, w22 +scvtf h23, x24 +fcvtas w25, h26 +fcvtas x27, h28 +fcvtau w29, h30 +fcvtau xzr, h0 +fcvtns w3, s31 +fcvtns xzr, s12 +fcvtnu wzr, s12 +fcvtnu x0, s0 +fcvtps wzr, s9 +fcvtps x12, s20 +fcvtpu w30, s23 +fcvtpu x29, s3 +fcvtms w2, s3 +fcvtms x4, s5 +fcvtmu w6, s7 +fcvtmu x8, s9 +fcvtzs w10, s11 +fcvtzs x12, s13 +fcvtzu w14, s15 +fcvtzu x15, s16 +scvtf s17, w18 +scvtf s19, x20 +ucvtf s21, w22 +scvtf s23, x24 +fcvtas w25, s26 +fcvtas x27, s28 +fcvtau w29, s30 +fcvtau xzr, s0 +fcvtns w3, d31 +fcvtns xzr, d12 +fcvtnu wzr, d12 +fcvtnu x0, d0 +fcvtps wzr, d9 +fcvtps x12, d20 +fcvtpu w30, d23 +fcvtpu x29, d3 +fcvtms w2, d3 +fcvtms x4, d5 +fcvtmu w6, d7 +fcvtmu x8, d9 +fcvtzs w10, d11 +fcvtzs x12, d13 +fcvtzu w14, d15 +fcvtzu x15, d16 +scvtf d17, w18 +scvtf d19, x20 +ucvtf d21, w22 +ucvtf d23, x24 +fcvtas w25, d26 +fcvtas x27, d28 +fcvtau w29, d30 +fcvtau xzr, d0 +fmov w3, s9 +fmov s9, w3 +fmov x20, d31 +fmov d1, x15 +fmov x3, v12.d[1] +fmov v1.d[1], x19 + +#------------------------------------------------------------------------------ +# Floating-point immediate +#------------------------------------------------------------------------------ + +fmov s2, #0.12500000 +fmov s3, #1.00000000 +fmov d30, #16.00000000 +fmov s4, #1.06250000 +fmov d10, #1.93750000 +fmov s12, #-1.00000000 +fmov d16, #8.50000000 + +#------------------------------------------------------------------------------ +# Load-register (literal) +#------------------------------------------------------------------------------ + +ldr w3, #0 +ldr x29, #4 +ldrsw xzr, #-4 +ldr s0, #8 +ldr d0, #1048572 +ldr q0, #-1048576 +prfm pldl1strm, #0 +prfm #22, #0 + +#------------------------------------------------------------------------------ +# Load/store exclusive +#------------------------------------------------------------------------------ + +stxrb w18, w8, [sp] +stxrh w24, w15, [x16] +stxr w5, w6, [x17] +stxr w1, x10, [x21] +ldxrb w30, [x0] +ldxrh w17, [x4] +ldxr w22, [sp] +ldxr x11, [x29] +ldxr x11, [x29] +ldxr x11, [x29] +stxp w12, w11, w10, [sp] +stxp wzr, x27, x9, [x12] +ldxp w0, wzr, [sp] +ldxp x17, x0, [x18] +ldxp x17, x0, [x18] +stlxrb w12, w22, [x0] +stlxrh w10, w1, [x1] +stlxr w9, w2, [x2] +stlxr w9, x3, [sp] +ldaxrb w8, [x4] +ldaxrh w7, [x5] +ldaxr w6, [sp] +ldaxr x5, [x6] +ldaxr x5, [x6] +ldaxr x5, [x6] +stlxp w4, w5, w6, [sp] +stlxp wzr, x6, x7, [x1] +ldaxp w5, w18, [sp] +ldaxp x6, x19, [x22] +ldaxp x6, x19, [x22] +stlrb w24, [sp] +stlrh w25, [x30] +stlr w26, [x29] +stlr x27, [x28] +stlr x27, [x28] +stlr x27, [x28] +ldarb w23, [sp] +ldarh w22, [x30] +ldar wzr, [x29] +ldar x21, [x28] +ldar x21, [x28] +ldar x21, [x28] + +#------------------------------------------------------------------------------ +# Load/store (unscaled immediate) +#------------------------------------------------------------------------------ + +sturb w9, [sp] +sturh wzr, [x12, #255] +stur w16, [x0, #-256] +stur x28, [x14, #1] +ldurb w1, [x20, #255] +ldurh w20, [x1, #255] +ldur w12, [sp, #255] +ldur xzr, [x12, #255] +ldursb x9, [x7, #-256] +ldursh x17, [x19, #-256] +ldursw x20, [x15, #-256] +prfum pldl2keep, [sp, #-256] +ldursb w19, [x1, #-256] +ldursh w15, [x21, #-256] +stur b0, [sp, #1] +stur h12, [x12, #-1] +stur s15, [x0, #255] +stur d31, [x5, #25] +stur q9, [x5] +ldur b3, [sp] +ldur h5, [x4, #-256] +ldur s7, [x12, #-1] +ldur d11, [x19, #4] +ldur q13, [x1, #2] + +#------------------------------------------------------------------------------ +# Load/store (immediate post-indexed) +#------------------------------------------------------------------------------ + +strb w9, [x2], #255 +strb w10, [x3], #1 +strb w10, [x3], #-256 +strh w9, [x2], #255 +strh w9, [x2], #1 +strh w10, [x3], #-256 +str w19, [sp], #255 +str w20, [x30], #1 +str w21, [x12], #-256 +str xzr, [x9], #255 +str x2, [x3], #1 +str x19, [x12], #-256 +ldrb w9, [x2], #255 +ldrb w10, [x3], #1 +ldrb w10, [x3], #-256 +ldrh w9, [x2], #255 +ldrh w9, [x2], #1 +ldrh w10, [x3], #-256 +ldr w19, [sp], #255 +ldr w20, [x30], #1 +ldr w21, [x12], #-256 +ldr xzr, [x9], #255 +ldr x2, [x3], #1 +ldr x19, [x12], #-256 +ldrsb xzr, [x9], #255 +ldrsb x2, [x3], #1 +ldrsb x19, [x12], #-256 +ldrsh xzr, [x9], #255 +ldrsh x2, [x3], #1 +ldrsh x19, [x12], #-256 +ldrsw xzr, [x9], #255 +ldrsw x2, [x3], #1 +ldrsw x19, [x12], #-256 +ldrsb wzr, [x9], #255 +ldrsb w2, [x3], #1 +ldrsb w19, [x12], #-256 +ldrsh wzr, [x9], #255 +ldrsh w2, [x3], #1 +ldrsh w19, [x12], #-256 +str b0, [x0], #255 +str b3, [x3], #1 +str b5, [sp], #-256 +str h10, [x10], #255 +str h13, [x23], #1 +str h15, [sp], #-256 +str s20, [x20], #255 +str s23, [x23], #1 +str s25, [x0], #-256 +str d20, [x20], #255 +str d23, [x23], #1 +str d25, [x0], #-256 +ldr b0, [x0], #255 +ldr b3, [x3], #1 +ldr b5, [sp], #-256 +ldr h10, [x10], #255 +ldr h13, [x23], #1 +ldr h15, [sp], #-256 +ldr s20, [x20], #255 +ldr s23, [x23], #1 +ldr s25, [x0], #-256 +ldr d20, [x20], #255 +ldr d23, [x23], #1 +ldr d25, [x0], #-256 +ldr q20, [x1], #255 +ldr q23, [x9], #1 +ldr q25, [x20], #-256 +str q10, [x1], #255 +str q22, [sp], #1 +str q21, [x20], #-256 + +#------------------------------------------------------------------------------- +# Load-store register (immediate pre-indexed) +#------------------------------------------------------------------------------- + +ldr x3, [x4, #0]! +strb w9, [x2, #255]! +strb w10, [x3, #1]! +strb w10, [x3, #-256]! +strh w9, [x2, #255]! +strh w9, [x2, #1]! +strh w10, [x3, #-256]! +str w19, [sp, #255]! +str w20, [x30, #1]! +str w21, [x12, #-256]! +str xzr, [x9, #255]! +str x2, [x3, #1]! +str x19, [x12, #-256]! +ldrb w9, [x2, #255]! +ldrb w10, [x3, #1]! +ldrb w10, [x3, #-256]! +ldrh w9, [x2, #255]! +ldrh w9, [x2, #1]! +ldrh w10, [x3, #-256]! +ldr w19, [sp, #255]! +ldr w20, [x30, #1]! +ldr w21, [x12, #-256]! +ldr xzr, [x9, #255]! +ldr x2, [x3, #1]! +ldr x19, [x12, #-256]! +ldrsb xzr, [x9, #255]! +ldrsb x2, [x3, #1]! +ldrsb x19, [x12, #-256]! +ldrsh xzr, [x9, #255]! +ldrsh x2, [x3, #1]! +ldrsh x19, [x12, #-256]! +ldrsw xzr, [x9, #255]! +ldrsw x2, [x3, #1]! +ldrsw x19, [x12, #-256]! +ldrsb wzr, [x9, #255]! +ldrsb w2, [x3, #1]! +ldrsb w19, [x12, #-256]! +ldrsh wzr, [x9, #255]! +ldrsh w2, [x3, #1]! +ldrsh w19, [x12, #-256]! +str b0, [x0, #255]! +str b3, [x3, #1]! +str b5, [sp, #-256]! +str h10, [x10, #255]! +str h13, [x23, #1]! +str h15, [sp, #-256]! +str s20, [x20, #255]! +str s23, [x23, #1]! +str s25, [x0, #-256]! +str d20, [x20, #255]! +str d23, [x23, #1]! +str d25, [x0, #-256]! +ldr b0, [x0, #255]! +ldr b3, [x3, #1]! +ldr b5, [sp, #-256]! +ldr h10, [x10, #255]! +ldr h13, [x23, #1]! +ldr h15, [sp, #-256]! +ldr s20, [x20, #255]! +ldr s23, [x23, #1]! +ldr s25, [x0, #-256]! +ldr d20, [x20, #255]! +ldr d23, [x23, #1]! +ldr d25, [x0, #-256]! +ldr q20, [x1, #255]! +ldr q23, [x9, #1]! +ldr q25, [x20, #-256]! +str q10, [x1, #255]! +str q22, [sp, #1]! +str q21, [x20, #-256]! + +#------------------------------------------------------------------------------ +# Load/store (unprivileged) +#------------------------------------------------------------------------------ + +sttrb w9, [sp] +sttrh wzr, [x12, #255] +sttr w16, [x0, #-256] +sttr x28, [x14, #1] +ldtrb w1, [x20, #255] +ldtrh w20, [x1, #255] +ldtr w12, [sp, #255] +ldtr xzr, [x12, #255] +ldtrsb x9, [x7, #-256] +ldtrsh x17, [x19, #-256] +ldtrsw x20, [x15, #-256] +ldtrsb w19, [x1, #-256] +ldtrsh w15, [x21, #-256] + +#------------------------------------------------------------------------------ +# Load/store (unsigned immediate) +#------------------------------------------------------------------------------ + +ldr x4, [x29] +ldr x30, [x12, #32760] +ldr x20, [sp, #8] +ldr xzr, [sp] +ldr w2, [sp] +ldr w17, [sp, #16380] +ldr w13, [x2, #4] +ldrsw x2, [x5, #4] +ldrsw x23, [sp, #16380] +ldrh w2, [x4] +ldrsh w23, [x6, #8190] +ldrsh wzr, [sp, #2] +ldrsh x29, [x2, #2] +ldrb w26, [x3, #121] +ldrb w12, [x2] +ldrsb w27, [sp, #4095] +ldrsb xzr, [x15] +str x30, [sp] +str w20, [x4, #16380] +strh w17, [sp, #8190] +strb w23, [x3, #4095] +strb wzr, [x2] +ldr b31, [sp, #4095] +ldr h20, [x2, #8190] +ldr s10, [x19, #16380] +ldr d3, [x10, #32760] +str q12, [sp, #65520] + +#------------------------------------------------------------------------------ +# Load/store (register offset) +#------------------------------------------------------------------------------ + +ldr h3, [sp, x5] +ldr h9, [x27, x6] +ldr h10, [x30, x7, lsl #1] +str h11, [x29, x3, sxtx] +str h12, [x28, xzr, sxtx] +str h13, [x27, x5, sxtx #1] +ldr h14, [x26, w6, uxtw] +ldr h15, [x25, w7, uxtw] +ldr h16, [x24, w8, uxtw #1] +ldr h17, [x23, w9, sxtw] +str h18, [x22, w10, sxtw] +ldr h19, [x21, wzr, sxtw #1] +ldrb w3, [sp, x5] +ldrb w9, [x27, x6] +ldrsb w10, [x30, x7] +ldrb w11, [x29, x3, sxtx] +strb w12, [x28, xzr, sxtx] +ldrb w14, [x26, w6, uxtw] +ldrsb w15, [x25, w7, uxtw] +ldrb w17, [x23, w9, sxtw] +ldrsb x18, [x22, w10, sxtw] +ldrsh w3, [sp, x5] +ldrsh w9, [x27, x6] +ldrh w10, [x30, x7, lsl #1] +strh w11, [x29, x3, sxtx] +ldrh w12, [x28, xzr, sxtx] +ldrsh x13, [x27, x5, sxtx #1] +ldrh w14, [x26, w6, uxtw] +ldrh w15, [x25, w7, uxtw] +ldrsh w16, [x24, w8, uxtw #1] +ldrh w17, [x23, w9, sxtw] +ldrh w18, [x22, w10, sxtw] +strh w19, [x21, wzr, sxtw #1] +ldr w3, [sp, x5] +ldr s9, [x27, x6] +ldr w10, [x30, x7, lsl #2] +ldr w11, [x29, x3, sxtx] +str s12, [x28, xzr, sxtx] +str w13, [x27, x5, sxtx #2] +str w14, [x26, w6, uxtw] +ldr w15, [x25, w7, uxtw] +ldr w16, [x24, w8, uxtw #2] +ldrsw x17, [x23, w9, sxtw] +ldr w18, [x22, w10, sxtw] +ldrsw x19, [x21, wzr, sxtw #2] +ldr x3, [sp, x5] +str x9, [x27, x6] +ldr d10, [x30, x7, lsl #3] +str x11, [x29, x3, sxtx] +ldr x12, [x28, xzr, sxtx] +ldr x13, [x27, x5, sxtx #3] +prfm pldl1keep, [x26, w6, uxtw] +ldr x15, [x25, w7, uxtw] +ldr x16, [x24, w8, uxtw #3] +ldr x17, [x23, w9, sxtw] +ldr x18, [x22, w10, sxtw] +str d19, [x21, wzr, sxtw #3] +ldr q3, [sp, x5] +ldr q9, [x27, x6] +ldr q10, [x30, x7, lsl #4] +str q11, [x29, x3, sxtx] +str q12, [x28, xzr, sxtx] +str q13, [x27, x5, sxtx #4] +ldr q14, [x26, w6, uxtw] +ldr q15, [x25, w7, uxtw] +ldr q16, [x24, w8, uxtw #4] +ldr q17, [x23, w9, sxtw] +str q18, [x22, w10, sxtw] +ldr q19, [x21, wzr, sxtw #4] + +#------------------------------------------------------------------------------ +# Load/store register pair (offset) +#------------------------------------------------------------------------------ + +ldp w3, w5, [sp] +stp wzr, w9, [sp, #252] +ldp w2, wzr, [sp, #-256] +ldp w9, w10, [sp, #4] +ldpsw x9, x10, [sp, #4] +ldpsw x9, x10, [x2, #-256] +ldpsw x20, x30, [sp, #252] +ldp x21, x29, [x2, #504] +ldp x22, x23, [x3, #-512] +ldp x24, x25, [x4, #8] +ldp s29, s28, [sp, #252] +stp s27, s26, [sp, #-256] +ldp s1, s2, [x3, #44] +stp d3, d5, [x9, #504] +stp d7, d11, [x10, #-512] +ldp d2, d3, [x30, #-8] +stp q3, q5, [sp] +stp q17, q19, [sp, #1008] +ldp q23, q29, [x1, #-1024] + +#------------------------------------------------------------------------------ +# Load/store register pair (post-indexed) +#------------------------------------------------------------------------------ + +ldp w3, w5, [sp], #0 +stp wzr, w9, [sp], #252 +ldp w2, wzr, [sp], #-256 +ldp w9, w10, [sp], #4 +ldpsw x9, x10, [sp], #4 +ldpsw x9, x10, [x2], #-256 +ldpsw x20, x30, [sp], #252 +ldp x21, x29, [x2], #504 +ldp x22, x23, [x3], #-512 +ldp x24, x25, [x4], #8 +ldp s29, s28, [sp], #252 +stp s27, s26, [sp], #-256 +ldp s1, s2, [x3], #44 +stp d3, d5, [x9], #504 +stp d7, d11, [x10], #-512 +ldp d2, d3, [x30], #-8 +stp q3, q5, [sp], #0 +stp q17, q19, [sp], #1008 +ldp q23, q29, [x1], #-1024 + +#------------------------------------------------------------------------------ +# Load/store register pair (pre-indexed) +#------------------------------------------------------------------------------ + +ldp w3, w5, [sp, #0]! +stp wzr, w9, [sp, #252]! +ldp w2, wzr, [sp, #-256]! +ldp w9, w10, [sp, #4]! +ldpsw x9, x10, [sp, #4]! +ldpsw x9, x10, [x2, #-256]! +ldpsw x20, x30, [sp, #252]! +ldp x21, x29, [x2, #504]! +ldp x22, x23, [x3, #-512]! +ldp x24, x25, [x4, #8]! +ldp s29, s28, [sp, #252]! +stp s27, s26, [sp, #-256]! +ldp s1, s2, [x3, #44]! +stp d3, d5, [x9, #504]! +stp d7, d11, [x10, #-512]! +ldp d2, d3, [x30, #-8]! +stp q3, q5, [sp, #0]! +stp q17, q19, [sp, #1008]! +ldp q23, q29, [x1, #-1024]! + +#------------------------------------------------------------------------------ +# Load/store register pair (offset) +#------------------------------------------------------------------------------ + +ldnp w3, w5, [sp] +stnp wzr, w9, [sp, #252] +ldnp w2, wzr, [sp, #-256] +ldnp w9, w10, [sp, #4] +ldnp x21, x29, [x2, #504] +ldnp x22, x23, [x3, #-512] +ldnp x24, x25, [x4, #8] +ldnp s29, s28, [sp, #252] +stnp s27, s26, [sp, #-256] +ldnp s1, s2, [x3, #44] +stnp d3, d5, [x9, #504] +stnp d7, d11, [x10, #-512] +ldnp d2, d3, [x30, #-8] +stnp q3, q5, [sp] +stnp q17, q19, [sp, #1008] +ldnp q23, q29, [x1, #-1024] + +#------------------------------------------------------------------------------ +# Logical (immediate) +#------------------------------------------------------------------------------ + +mov w3, #983055 +mov x10, #-6148914691236517206 + +#------------------------------------------------------------------------------ +# Logical (shifted register) +#------------------------------------------------------------------------------ + +and w12, w23, w21 +and w16, w15, w1, lsl #1 +and w9, w4, w10, lsl #31 +and w3, w30, w11 +and x3, x5, x7, lsl #63 +and x5, x14, x19, asr #4 +and w3, w17, w19, ror #31 +and w0, w2, wzr, lsr #17 +and w3, w30, w11, asr #2 +and xzr, x4, x26 +and w3, wzr, w20, ror #2 +and x7, x20, xzr, asr #63 +bic x13, x20, x14, lsl #47 +bic w2, w7, w9 +orr w2, w7, w0, asr #31 +orr x8, x9, x10, lsl #12 +orn x3, x5, x7, asr #2 +orn w2, w5, w29 +ands w7, wzr, w9, lsl #1 +ands x3, x5, x20, ror #63 +bics w3, w5, w7 +bics x3, xzr, x3, lsl #1 +tst w3, w7, lsl #31 +tst x2, x20, asr #2 +mov x3, x6 +mov x3, xzr +mov wzr, w2 +mov w3, w5 + +#------------------------------------------------------------------------------ +# Move wide (immediate) +#------------------------------------------------------------------------------ + +movz w2, #0, lsl #16 +mov w2, #-1235 +mov x2, #5299989643264 +mov x2, #0 +movk w3, #0 +movz x4, #0, lsl #16 +movk w5, #0, lsl #16 +movz x6, #0, lsl #32 +movk x7, #0, lsl #32 +movz x8, #0, lsl #48 +movk x9, #0, lsl #48 + +#------------------------------------------------------------------------------ +# PC-relative addressing +#------------------------------------------------------------------------------ + +adr x2, #1600 +adrp x21, #6553600 +adr x0, #262144 + +#------------------------------------------------------------------------------ +# Test and branch (immediate) +#------------------------------------------------------------------------------ + +tbz x12, #62, #0 +tbz x12, #62, #4 +tbz x12, #62, #-32768 +tbnz x12, #60, #32764 + +#------------------------------------------------------------------------------ +# Unconditional branch (immediate) +#------------------------------------------------------------------------------ + +b #4 +b #-4 +b #134217724 + +#------------------------------------------------------------------------------ +# Unconditional branch (register) +#------------------------------------------------------------------------------ + +br x20 +blr xzr +ret x10 +ret +eret +drps + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.17 add w2, w3, #4095 +# CHECK-NEXT: 1 1 0.17 add w30, w29, #1, lsl #12 +# CHECK-NEXT: 1 1 0.17 add w13, w5, #4095, lsl #12 +# CHECK-NEXT: 1 1 0.17 add x5, x7, #1638 +# CHECK-NEXT: 1 1 0.17 add w20, wsp, #801 +# CHECK-NEXT: 1 1 0.17 add wsp, wsp, #1104 +# CHECK-NEXT: 1 1 0.17 add wsp, w30, #4084 +# CHECK-NEXT: 1 1 0.17 add x0, x24, #291 +# CHECK-NEXT: 1 1 0.17 add x3, x24, #4095, lsl #12 +# CHECK-NEXT: 1 1 0.17 add x8, sp, #1074 +# CHECK-NEXT: 1 1 0.17 add sp, x29, #3816 +# CHECK-NEXT: 1 1 0.17 sub w0, wsp, #4077 +# CHECK-NEXT: 1 1 0.17 sub w4, w20, #546, lsl #12 +# CHECK-NEXT: 1 1 0.17 sub sp, sp, #288 +# CHECK-NEXT: 1 1 0.17 sub wsp, w19, #16 +# CHECK-NEXT: 1 1 0.17 adds w13, w23, #291, lsl #12 +# CHECK-NEXT: 1 1 0.17 cmn w2, #4095 +# CHECK-NEXT: 1 1 0.17 adds w20, wsp, #0 +# CHECK-NEXT: 1 1 0.17 cmn x3, #1, lsl #12 +# CHECK-NEXT: 1 1 0.17 cmp sp, #20, lsl #12 +# CHECK-NEXT: 1 1 0.17 cmp x30, #4095 +# CHECK-NEXT: 1 1 0.17 subs x4, sp, #3822 +# CHECK-NEXT: 1 1 0.17 cmn w3, #291, lsl #12 +# CHECK-NEXT: 1 1 0.17 cmn wsp, #1365 +# CHECK-NEXT: 1 1 0.17 cmn sp, #1092, lsl #12 +# CHECK-NEXT: 1 1 0.17 mov sp, x30 +# CHECK-NEXT: 1 1 0.17 mov wsp, w20 +# CHECK-NEXT: 1 1 0.17 mov x11, sp +# CHECK-NEXT: 1 1 0.17 mov w24, wsp +# CHECK-NEXT: 1 1 0.17 add w3, w5, w7 +# CHECK-NEXT: 1 1 0.17 add wzr, w3, w5 +# CHECK-NEXT: 1 1 0.17 add w20, wzr, w4 +# CHECK-NEXT: 1 1 0.17 add w4, w6, wzr +# CHECK-NEXT: 1 1 0.17 add w11, w13, w15 +# CHECK-NEXT: 1 2 0.50 add w9, w3, wzr, lsl #10 +# CHECK-NEXT: 1 2 0.50 add w17, w29, w20, lsl #31 +# CHECK-NEXT: 1 2 0.50 add w21, w22, w23, lsr #0 +# CHECK-NEXT: 1 2 0.50 add w24, w25, w26, lsr #18 +# CHECK-NEXT: 1 2 0.50 add w27, w28, w29, lsr #31 +# CHECK-NEXT: 1 2 0.50 add w2, w3, w4, asr #0 +# CHECK-NEXT: 1 2 0.50 add w5, w6, w7, asr #21 +# CHECK-NEXT: 1 2 0.50 add w8, w9, w10, asr #31 +# CHECK-NEXT: 1 1 0.17 add x3, x5, x7 +# CHECK-NEXT: 1 1 0.17 add xzr, x3, x5 +# CHECK-NEXT: 1 1 0.17 add x20, xzr, x4 +# CHECK-NEXT: 1 1 0.17 add x4, x6, xzr +# CHECK-NEXT: 1 1 0.17 add x11, x13, x15 +# CHECK-NEXT: 1 2 0.50 add x9, x3, xzr, lsl #10 +# CHECK-NEXT: 1 2 0.50 add x17, x29, x20, lsl #63 +# CHECK-NEXT: 1 2 0.50 add x21, x22, x23, lsr #0 +# CHECK-NEXT: 1 2 0.50 add x24, x25, x26, lsr #18 +# CHECK-NEXT: 1 2 0.50 add x27, x28, x29, lsr #63 +# CHECK-NEXT: 1 2 0.50 add x2, x3, x4, asr #0 +# CHECK-NEXT: 1 2 0.50 add x5, x6, x7, asr #21 +# CHECK-NEXT: 1 2 0.50 add x8, x9, x10, asr #63 +# CHECK-NEXT: 1 1 0.25 adds w3, w5, w7 +# CHECK-NEXT: 1 1 0.25 cmn w3, w5 +# CHECK-NEXT: 1 1 0.25 adds w20, wzr, w4 +# CHECK-NEXT: 1 1 0.25 adds w4, w6, wzr +# CHECK-NEXT: 1 1 0.25 adds w11, w13, w15 +# CHECK-NEXT: 1 2 0.50 adds w9, w3, wzr, lsl #10 +# CHECK-NEXT: 1 2 0.50 adds w17, w29, w20, lsl #31 +# CHECK-NEXT: 1 2 0.50 adds w21, w22, w23, lsr #0 +# CHECK-NEXT: 1 2 0.50 adds w24, w25, w26, lsr #18 +# CHECK-NEXT: 1 2 0.50 adds w27, w28, w29, lsr #31 +# CHECK-NEXT: 1 2 0.50 adds w2, w3, w4, asr #0 +# CHECK-NEXT: 1 2 0.50 adds w5, w6, w7, asr #21 +# CHECK-NEXT: 1 2 0.50 adds w8, w9, w10, asr #31 +# CHECK-NEXT: 1 1 0.25 adds x3, x5, x7 +# CHECK-NEXT: 1 1 0.25 cmn x3, x5 +# CHECK-NEXT: 1 1 0.25 adds x20, xzr, x4 +# CHECK-NEXT: 1 1 0.25 adds x4, x6, xzr +# CHECK-NEXT: 1 1 0.25 adds x11, x13, x15 +# CHECK-NEXT: 1 2 0.50 adds x9, x3, xzr, lsl #10 +# CHECK-NEXT: 1 2 0.50 adds x17, x29, x20, lsl #63 +# CHECK-NEXT: 1 2 0.50 adds x21, x22, x23, lsr #0 +# CHECK-NEXT: 1 2 0.50 adds x24, x25, x26, lsr #18 +# CHECK-NEXT: 1 2 0.50 adds x27, x28, x29, lsr #63 +# CHECK-NEXT: 1 2 0.50 adds x2, x3, x4, asr #0 +# CHECK-NEXT: 1 2 0.50 adds x5, x6, x7, asr #21 +# CHECK-NEXT: 1 2 0.50 adds x8, x9, x10, asr #63 +# CHECK-NEXT: 1 1 0.17 sub w3, w5, w7 +# CHECK-NEXT: 1 1 0.17 sub wzr, w3, w5 +# CHECK-NEXT: 1 1 0.17 sub w4, w6, wzr +# CHECK-NEXT: 1 1 0.17 sub w11, w13, w15 +# CHECK-NEXT: 1 2 0.50 sub w9, w3, wzr, lsl #10 +# CHECK-NEXT: 1 2 0.50 sub w17, w29, w20, lsl #31 +# CHECK-NEXT: 1 2 0.50 sub w21, w22, w23, lsr #0 +# CHECK-NEXT: 1 2 0.50 sub w24, w25, w26, lsr #18 +# CHECK-NEXT: 1 2 0.50 sub w27, w28, w29, lsr #31 +# CHECK-NEXT: 1 2 0.50 sub w2, w3, w4, asr #0 +# CHECK-NEXT: 1 2 0.50 sub w5, w6, w7, asr #21 +# CHECK-NEXT: 1 2 0.50 sub w8, w9, w10, asr #31 +# CHECK-NEXT: 1 1 0.17 sub x3, x5, x7 +# CHECK-NEXT: 1 1 0.17 sub xzr, x3, x5 +# CHECK-NEXT: 1 1 0.17 sub x4, x6, xzr +# CHECK-NEXT: 1 1 0.17 sub x11, x13, x15 +# CHECK-NEXT: 1 2 0.50 sub x9, x3, xzr, lsl #10 +# CHECK-NEXT: 1 2 0.50 sub x17, x29, x20, lsl #63 +# CHECK-NEXT: 1 2 0.50 sub x21, x22, x23, lsr #0 +# CHECK-NEXT: 1 2 0.50 sub x24, x25, x26, lsr #18 +# CHECK-NEXT: 1 2 0.50 sub x27, x28, x29, lsr #63 +# CHECK-NEXT: 1 2 0.50 sub x2, x3, x4, asr #0 +# CHECK-NEXT: 1 2 0.50 sub x5, x6, x7, asr #21 +# CHECK-NEXT: 1 2 0.50 sub x8, x9, x10, asr #63 +# CHECK-NEXT: 1 1 0.25 subs w3, w5, w7 +# CHECK-NEXT: 1 1 0.25 cmp w3, w5 +# CHECK-NEXT: 1 1 0.25 subs w4, w6, wzr +# CHECK-NEXT: 1 1 0.25 subs w11, w13, w15 +# CHECK-NEXT: 1 2 0.50 subs w9, w3, wzr, lsl #10 +# CHECK-NEXT: 1 2 0.50 subs w17, w29, w20, lsl #31 +# CHECK-NEXT: 1 2 0.50 subs w21, w22, w23, lsr #0 +# CHECK-NEXT: 1 2 0.50 subs w24, w25, w26, lsr #18 +# CHECK-NEXT: 1 2 0.50 subs w27, w28, w29, lsr #31 +# CHECK-NEXT: 1 2 0.50 subs w2, w3, w4, asr #0 +# CHECK-NEXT: 1 2 0.50 subs w5, w6, w7, asr #21 +# CHECK-NEXT: 1 2 0.50 subs w8, w9, w10, asr #31 +# CHECK-NEXT: 1 1 0.25 subs x3, x5, x7 +# CHECK-NEXT: 1 1 0.25 cmp x3, x5 +# CHECK-NEXT: 1 1 0.25 subs x4, x6, xzr +# CHECK-NEXT: 1 1 0.25 subs x11, x13, x15 +# CHECK-NEXT: 1 2 0.50 subs x9, x3, xzr, lsl #10 +# CHECK-NEXT: 1 2 0.50 subs x17, x29, x20, lsl #63 +# CHECK-NEXT: 1 2 0.50 subs x21, x22, x23, lsr #0 +# CHECK-NEXT: 1 2 0.50 subs x24, x25, x26, lsr #18 +# CHECK-NEXT: 1 2 0.50 subs x27, x28, x29, lsr #63 +# CHECK-NEXT: 1 2 0.50 subs x2, x3, x4, asr #0 +# CHECK-NEXT: 1 2 0.50 subs x5, x6, x7, asr #21 +# CHECK-NEXT: 1 2 0.50 subs x8, x9, x10, asr #63 +# CHECK-NEXT: 1 1 0.25 cmn wzr, w4 +# CHECK-NEXT: 1 1 0.25 cmn w5, wzr +# CHECK-NEXT: 1 1 0.25 cmn w6, w7 +# CHECK-NEXT: 1 2 0.50 cmn w8, w9, lsl #15 +# CHECK-NEXT: 1 2 0.50 cmn w10, w11, lsl #31 +# CHECK-NEXT: 1 2 0.50 cmn w12, w13, lsr #0 +# CHECK-NEXT: 1 2 0.50 cmn w14, w15, lsr #21 +# CHECK-NEXT: 1 2 0.50 cmn w16, w17, lsr #31 +# CHECK-NEXT: 1 2 0.50 cmn w18, w19, asr #0 +# CHECK-NEXT: 1 2 0.50 cmn w20, w21, asr #22 +# CHECK-NEXT: 1 2 0.50 cmn w22, w23, asr #31 +# CHECK-NEXT: 1 1 0.25 cmn x0, x3 +# CHECK-NEXT: 1 1 0.25 cmn xzr, x4 +# CHECK-NEXT: 1 1 0.25 cmn x5, xzr +# CHECK-NEXT: 1 1 0.25 cmn x6, x7 +# CHECK-NEXT: 1 2 0.50 cmn x8, x9, lsl #15 +# CHECK-NEXT: 1 2 0.50 cmn x10, x11, lsl #63 +# CHECK-NEXT: 1 2 0.50 cmn x12, x13, lsr #0 +# CHECK-NEXT: 1 2 0.50 cmn x14, x15, lsr #41 +# CHECK-NEXT: 1 2 0.50 cmn x16, x17, lsr #63 +# CHECK-NEXT: 1 2 0.50 cmn x18, x19, asr #0 +# CHECK-NEXT: 1 2 0.50 cmn x20, x21, asr #55 +# CHECK-NEXT: 1 2 0.50 cmn x22, x23, asr #63 +# CHECK-NEXT: 1 1 0.25 cmp w0, w3 +# CHECK-NEXT: 1 1 0.25 cmp wzr, w4 +# CHECK-NEXT: 1 1 0.25 cmp w5, wzr +# CHECK-NEXT: 1 1 0.25 cmp w6, w7 +# CHECK-NEXT: 1 2 0.50 cmp w8, w9, lsl #15 +# CHECK-NEXT: 1 2 0.50 cmp w10, w11, lsl #31 +# CHECK-NEXT: 1 2 0.50 cmp w12, w13, lsr #0 +# CHECK-NEXT: 1 2 0.50 cmp w14, w15, lsr #21 +# CHECK-NEXT: 1 2 0.50 cmp w18, w19, asr #0 +# CHECK-NEXT: 1 2 0.50 cmp w20, w21, asr #22 +# CHECK-NEXT: 1 2 0.50 cmp w22, w23, asr #31 +# CHECK-NEXT: 1 1 0.25 cmp x0, x3 +# CHECK-NEXT: 1 1 0.25 cmp xzr, x4 +# CHECK-NEXT: 1 1 0.25 cmp x5, xzr +# CHECK-NEXT: 1 1 0.25 cmp x6, x7 +# CHECK-NEXT: 1 2 0.50 cmp x8, x9, lsl #15 +# CHECK-NEXT: 1 2 0.50 cmp x10, x11, lsl #63 +# CHECK-NEXT: 1 2 0.50 cmp x12, x13, lsr #0 +# CHECK-NEXT: 1 2 0.50 cmp x14, x15, lsr #41 +# CHECK-NEXT: 1 2 0.50 cmp x16, x17, lsr #63 +# CHECK-NEXT: 1 2 0.50 cmp x18, x19, asr #0 +# CHECK-NEXT: 1 2 0.50 cmp x20, x21, asr #55 +# CHECK-NEXT: 1 2 0.50 cmp x22, x23, asr #63 +# CHECK-NEXT: 1 1 0.25 cmp wzr, w0 +# CHECK-NEXT: 1 1 0.25 cmp xzr, x0 +# CHECK-NEXT: 1 1 0.17 adc w29, w27, w25 +# CHECK-NEXT: 1 1 0.17 adc wzr, w3, w4 +# CHECK-NEXT: 1 1 0.17 adc w9, wzr, w10 +# CHECK-NEXT: 1 1 0.17 adc w20, w0, wzr +# CHECK-NEXT: 1 1 0.17 adc x29, x27, x25 +# CHECK-NEXT: 1 1 0.17 adc xzr, x3, x4 +# CHECK-NEXT: 1 1 0.17 adc x9, xzr, x10 +# CHECK-NEXT: 1 1 0.17 adc x20, x0, xzr +# CHECK-NEXT: 1 1 0.25 adcs w29, w27, w25 +# CHECK-NEXT: 1 1 0.25 adcs wzr, w3, w4 +# CHECK-NEXT: 1 1 0.25 adcs w9, wzr, w10 +# CHECK-NEXT: 1 1 0.25 adcs w20, w0, wzr +# CHECK-NEXT: 1 1 0.25 adcs x29, x27, x25 +# CHECK-NEXT: 1 1 0.25 adcs xzr, x3, x4 +# CHECK-NEXT: 1 1 0.25 adcs x9, xzr, x10 +# CHECK-NEXT: 1 1 0.25 adcs x20, x0, xzr +# CHECK-NEXT: 1 1 0.17 sbc w29, w27, w25 +# CHECK-NEXT: 1 1 0.17 sbc wzr, w3, w4 +# CHECK-NEXT: 1 1 0.17 ngc w9, w10 +# CHECK-NEXT: 1 1 0.17 sbc w20, w0, wzr +# CHECK-NEXT: 1 1 0.17 sbc x29, x27, x25 +# CHECK-NEXT: 1 1 0.17 sbc xzr, x3, x4 +# CHECK-NEXT: 1 1 0.17 ngc x9, x10 +# CHECK-NEXT: 1 1 0.17 sbc x20, x0, xzr +# CHECK-NEXT: 1 1 0.25 sbcs w29, w27, w25 +# CHECK-NEXT: 1 1 0.25 sbcs wzr, w3, w4 +# CHECK-NEXT: 1 1 0.25 ngcs w9, w10 +# CHECK-NEXT: 1 1 0.25 sbcs w20, w0, wzr +# CHECK-NEXT: 1 1 0.25 sbcs x29, x27, x25 +# CHECK-NEXT: 1 1 0.25 sbcs xzr, x3, x4 +# CHECK-NEXT: 1 1 0.25 ngcs x9, x10 +# CHECK-NEXT: 1 1 0.25 sbcs x20, x0, xzr +# CHECK-NEXT: 1 1 0.17 ngc w3, w12 +# CHECK-NEXT: 1 1 0.17 ngc wzr, w9 +# CHECK-NEXT: 1 1 0.17 ngc w23, wzr +# CHECK-NEXT: 1 1 0.17 ngc x29, x30 +# CHECK-NEXT: 1 1 0.17 ngc xzr, x0 +# CHECK-NEXT: 1 1 0.17 ngc x0, xzr +# CHECK-NEXT: 1 1 0.25 ngcs w3, w12 +# CHECK-NEXT: 1 1 0.25 ngcs wzr, w9 +# CHECK-NEXT: 1 1 0.25 ngcs w23, wzr +# CHECK-NEXT: 1 1 0.25 ngcs x29, x30 +# CHECK-NEXT: 1 1 0.25 ngcs xzr, x0 +# CHECK-NEXT: 1 1 0.25 ngcs x0, xzr +# CHECK-NEXT: 1 1 0.17 sbfx x1, x2, #3, #2 +# CHECK-NEXT: 1 1 0.17 asr x3, x4, #63 +# CHECK-NEXT: 1 1 0.17 asr wzr, wzr, #31 +# CHECK-NEXT: 1 1 0.17 sbfx w12, w9, #0, #1 +# CHECK-NEXT: 1 1 0.17 ubfiz x4, x5, #52, #11 +# CHECK-NEXT: 1 1 0.17 ubfx xzr, x4, #0, #1 +# CHECK-NEXT: 1 1 0.17 ubfiz x4, xzr, #1, #6 +# CHECK-NEXT: 1 1 0.17 lsr x5, x6, #12 +# CHECK-NEXT: 1 2 0.50 bfi x4, x5, #52, #11 +# CHECK-NEXT: 1 2 0.50 bfxil xzr, x4, #0, #1 +# CHECK-NEXT: 1 2 0.50 bfc x4, #1, #6 +# CHECK-NEXT: 1 2 0.50 bfxil x5, x6, #12, #52 +# CHECK-NEXT: 1 1 0.17 sxtb w1, w2 +# CHECK-NEXT: 1 1 0.17 sxtb xzr, w3 +# CHECK-NEXT: 1 1 0.17 sxth w9, w10 +# CHECK-NEXT: 1 1 0.17 sxth x0, w1 +# CHECK-NEXT: 1 1 0.17 sxtw x3, w30 +# CHECK-NEXT: 1 1 0.17 uxtb w1, w2 +# CHECK-NEXT: 1 1 0.17 uxth w9, w10 +# CHECK-NEXT: 1 1 0.17 ubfx x3, x30, #0, #32 +# CHECK-NEXT: 1 1 0.17 asr w3, w2, #0 +# CHECK-NEXT: 1 1 0.17 asr w9, w10, #31 +# CHECK-NEXT: 1 1 0.17 asr x20, x21, #63 +# CHECK-NEXT: 1 1 0.17 asr w1, wzr, #3 +# CHECK-NEXT: 1 1 0.17 lsr w3, w2, #0 +# CHECK-NEXT: 1 1 0.17 lsr w9, w10, #31 +# CHECK-NEXT: 1 1 0.17 lsr x20, x21, #63 +# CHECK-NEXT: 1 1 0.17 lsr wzr, wzr, #3 +# CHECK-NEXT: 1 1 0.17 lsr w3, w2, #0 +# CHECK-NEXT: 1 1 0.17 lsl w9, w10, #31 +# CHECK-NEXT: 1 1 0.17 lsl x20, x21, #63 +# CHECK-NEXT: 1 1 0.17 lsl w1, wzr, #3 +# CHECK-NEXT: 1 1 0.17 sbfx w9, w10, #0, #1 +# CHECK-NEXT: 1 1 0.17 sbfiz x2, x3, #63, #1 +# CHECK-NEXT: 1 1 0.17 asr x19, x20, #0 +# CHECK-NEXT: 1 1 0.17 sbfiz x9, x10, #5, #59 +# CHECK-NEXT: 1 1 0.17 asr w9, w10, #0 +# CHECK-NEXT: 1 1 0.17 sbfiz w11, w12, #31, #1 +# CHECK-NEXT: 1 1 0.17 sbfiz w13, w14, #29, #3 +# CHECK-NEXT: 1 1 0.17 sbfiz xzr, xzr, #10, #11 +# CHECK-NEXT: 1 1 0.17 sbfx w9, w10, #0, #1 +# CHECK-NEXT: 1 1 0.17 asr x2, x3, #63 +# CHECK-NEXT: 1 1 0.17 asr x19, x20, #0 +# CHECK-NEXT: 1 1 0.17 asr x9, x10, #5 +# CHECK-NEXT: 1 1 0.17 asr w9, w10, #0 +# CHECK-NEXT: 1 1 0.17 asr w11, w12, #31 +# CHECK-NEXT: 1 1 0.17 asr w13, w14, #29 +# CHECK-NEXT: 1 1 0.17 sbfx xzr, xzr, #10, #11 +# CHECK-NEXT: 1 2 0.50 bfxil w9, w10, #0, #1 +# CHECK-NEXT: 1 2 0.50 bfi x2, x3, #63, #1 +# CHECK-NEXT: 1 2 0.50 bfxil x19, x20, #0, #64 +# CHECK-NEXT: 1 2 0.50 bfi x9, x10, #5, #59 +# CHECK-NEXT: 1 2 0.50 bfxil w9, w10, #0, #32 +# CHECK-NEXT: 1 2 0.50 bfi w11, w12, #31, #1 +# CHECK-NEXT: 1 2 0.50 bfi w13, w14, #29, #3 +# CHECK-NEXT: 1 2 0.50 bfc xzr, #10, #11 +# CHECK-NEXT: 1 2 0.50 bfxil w9, w10, #0, #1 +# CHECK-NEXT: 1 2 0.50 bfxil x2, x3, #63, #1 +# CHECK-NEXT: 1 2 0.50 bfxil x19, x20, #0, #64 +# CHECK-NEXT: 1 2 0.50 bfxil x9, x10, #5, #59 +# CHECK-NEXT: 1 2 0.50 bfxil w9, w10, #0, #32 +# CHECK-NEXT: 1 2 0.50 bfxil w11, w12, #31, #1 +# CHECK-NEXT: 1 2 0.50 bfxil w13, w14, #29, #3 +# CHECK-NEXT: 1 2 0.50 bfxil xzr, xzr, #10, #11 +# CHECK-NEXT: 1 1 0.17 ubfx w9, w10, #0, #1 +# CHECK-NEXT: 1 1 0.17 lsl x2, x3, #63 +# CHECK-NEXT: 1 1 0.17 lsr x19, x20, #0 +# CHECK-NEXT: 1 1 0.17 lsl x9, x10, #5 +# CHECK-NEXT: 1 1 0.17 lsr w9, w10, #0 +# CHECK-NEXT: 1 1 0.17 lsl w11, w12, #31 +# CHECK-NEXT: 1 1 0.17 lsl w13, w14, #29 +# CHECK-NEXT: 1 1 0.17 ubfiz xzr, xzr, #10, #11 +# CHECK-NEXT: 1 1 0.17 ubfx w9, w10, #0, #1 +# CHECK-NEXT: 1 1 0.17 lsr x2, x3, #63 +# CHECK-NEXT: 1 1 0.17 lsr x19, x20, #0 +# CHECK-NEXT: 1 1 0.17 lsr x9, x10, #5 +# CHECK-NEXT: 1 1 0.17 lsr w9, w10, #0 +# CHECK-NEXT: 1 1 0.17 lsr w11, w12, #31 +# CHECK-NEXT: 1 1 0.17 lsr w13, w14, #29 +# CHECK-NEXT: 1 1 0.17 ubfx xzr, xzr, #10, #11 +# CHECK-NEXT: 1 1 0.50 cbz w5, #4 +# CHECK-NEXT: 1 1 0.50 cbz x5, #0 +# CHECK-NEXT: 1 1 0.50 cbnz x2, #-4 +# CHECK-NEXT: 1 1 0.50 cbnz x26, #1048572 +# CHECK-NEXT: 1 1 0.50 cbz wzr, #0 +# CHECK-NEXT: 1 1 0.50 cbnz xzr, #0 +# CHECK-NEXT: 1 1 0.50 b.ne #4 +# CHECK-NEXT: 1 1 0.50 b.ge #1048572 +# CHECK-NEXT: 1 1 0.50 b.ge #-4 +# CHECK-NEXT: 1 1 0.17 ccmp w1, #31, #0, eq +# CHECK-NEXT: 1 1 0.17 ccmp w3, #0, #15, hs +# CHECK-NEXT: 1 1 0.17 ccmp wzr, #15, #13, hs +# CHECK-NEXT: 1 1 0.17 ccmp x9, #31, #0, le +# CHECK-NEXT: 1 1 0.17 ccmp x3, #0, #15, gt +# CHECK-NEXT: 1 1 0.17 ccmp xzr, #5, #7, ne +# CHECK-NEXT: 1 1 0.17 ccmn w1, #31, #0, eq +# CHECK-NEXT: 1 1 0.17 ccmn w3, #0, #15, hs +# CHECK-NEXT: 1 1 0.17 ccmn wzr, #15, #13, hs +# CHECK-NEXT: 1 1 0.17 ccmn x9, #31, #0, le +# CHECK-NEXT: 1 1 0.17 ccmn x3, #0, #15, gt +# CHECK-NEXT: 1 1 0.17 ccmn xzr, #5, #7, ne +# CHECK-NEXT: 1 1 0.17 ccmp w1, wzr, #0, eq +# CHECK-NEXT: 1 1 0.17 ccmp w3, w0, #15, hs +# CHECK-NEXT: 1 1 0.17 ccmp wzr, w15, #13, hs +# CHECK-NEXT: 1 1 0.17 ccmp x9, xzr, #0, le +# CHECK-NEXT: 1 1 0.17 ccmp x3, x0, #15, gt +# CHECK-NEXT: 1 1 0.17 ccmp xzr, x5, #7, ne +# CHECK-NEXT: 1 1 0.17 ccmn w1, wzr, #0, eq +# CHECK-NEXT: 1 1 0.17 ccmn w3, w0, #15, hs +# CHECK-NEXT: 1 1 0.17 ccmn wzr, w15, #13, hs +# CHECK-NEXT: 1 1 0.17 ccmn x9, xzr, #0, le +# CHECK-NEXT: 1 1 0.17 ccmn x3, x0, #15, gt +# CHECK-NEXT: 1 1 0.17 ccmn xzr, x5, #7, ne +# CHECK-NEXT: 1 1 0.17 csel w1, w0, w19, ne +# CHECK-NEXT: 1 1 0.17 csel wzr, w5, w9, eq +# CHECK-NEXT: 1 1 0.17 csel w9, wzr, w30, gt +# CHECK-NEXT: 1 1 0.17 csel w1, w28, wzr, mi +# CHECK-NEXT: 1 1 0.17 csel x19, x23, x29, lt +# CHECK-NEXT: 1 1 0.17 csel xzr, x3, x4, ge +# CHECK-NEXT: 1 1 0.17 csel x5, xzr, x6, hs +# CHECK-NEXT: 1 1 0.17 csel x7, x8, xzr, lo +# CHECK-NEXT: 1 1 0.17 csinc w1, w0, w19, ne +# CHECK-NEXT: 1 1 0.17 csinc wzr, w5, w9, eq +# CHECK-NEXT: 1 1 0.17 csinc w9, wzr, w30, gt +# CHECK-NEXT: 1 1 0.17 csinc w1, w28, wzr, mi +# CHECK-NEXT: 1 1 0.17 csinc x19, x23, x29, lt +# CHECK-NEXT: 1 1 0.17 csinc xzr, x3, x4, ge +# CHECK-NEXT: 1 1 0.17 csinc x5, xzr, x6, hs +# CHECK-NEXT: 1 1 0.17 csinc x7, x8, xzr, lo +# CHECK-NEXT: 1 1 0.17 csinv w1, w0, w19, ne +# CHECK-NEXT: 1 1 0.17 csinv wzr, w5, w9, eq +# CHECK-NEXT: 1 1 0.17 csinv w9, wzr, w30, gt +# CHECK-NEXT: 1 1 0.17 csinv w1, w28, wzr, mi +# CHECK-NEXT: 1 1 0.17 csinv x19, x23, x29, lt +# CHECK-NEXT: 1 1 0.17 csinv xzr, x3, x4, ge +# CHECK-NEXT: 1 1 0.17 csinv x5, xzr, x6, hs +# CHECK-NEXT: 1 1 0.17 csinv x7, x8, xzr, lo +# CHECK-NEXT: 1 1 0.17 csneg w1, w0, w19, ne +# CHECK-NEXT: 1 1 0.17 csneg wzr, w5, w9, eq +# CHECK-NEXT: 1 1 0.17 csneg w9, wzr, w30, gt +# CHECK-NEXT: 1 1 0.17 csneg w1, w28, wzr, mi +# CHECK-NEXT: 1 1 0.17 csneg x19, x23, x29, lt +# CHECK-NEXT: 1 1 0.17 csneg xzr, x3, x4, ge +# CHECK-NEXT: 1 1 0.17 csneg x5, xzr, x6, hs +# CHECK-NEXT: 1 1 0.17 csneg x7, x8, xzr, lo +# CHECK-NEXT: 1 1 0.17 cset w3, eq +# CHECK-NEXT: 1 1 0.17 cset x9, pl +# CHECK-NEXT: 1 1 0.17 csetm w20, ne +# CHECK-NEXT: 1 1 0.17 csetm x30, ge +# CHECK-NEXT: 1 1 0.17 csinc w2, wzr, wzr, al +# CHECK-NEXT: 1 1 0.17 csinv x3, xzr, xzr, nv +# CHECK-NEXT: 1 1 0.17 cinc w3, w5, gt +# CHECK-NEXT: 1 1 0.17 cinc wzr, w4, le +# CHECK-NEXT: 1 1 0.17 cset w9, lt +# CHECK-NEXT: 1 1 0.17 cinc x3, x5, gt +# CHECK-NEXT: 1 1 0.17 cinc xzr, x4, le +# CHECK-NEXT: 1 1 0.17 cset x9, lt +# CHECK-NEXT: 1 1 0.17 csinc w5, w6, w6, nv +# CHECK-NEXT: 1 1 0.17 csinc x1, x2, x2, al +# CHECK-NEXT: 1 1 0.17 cinv w3, w5, gt +# CHECK-NEXT: 1 1 0.17 cinv wzr, w4, le +# CHECK-NEXT: 1 1 0.17 csetm w9, lt +# CHECK-NEXT: 1 1 0.17 cinv x3, x5, gt +# CHECK-NEXT: 1 1 0.17 cinv xzr, x4, le +# CHECK-NEXT: 1 1 0.17 csetm x9, lt +# CHECK-NEXT: 1 1 0.17 csinv x1, x0, x0, al +# CHECK-NEXT: 1 1 0.17 csinv w9, w8, w8, nv +# CHECK-NEXT: 1 1 0.17 cneg w3, w5, gt +# CHECK-NEXT: 1 1 0.17 cneg wzr, w4, le +# CHECK-NEXT: 1 1 0.17 cneg w9, wzr, lt +# CHECK-NEXT: 1 1 0.17 cneg x3, x5, gt +# CHECK-NEXT: 1 1 0.17 cneg xzr, x4, le +# CHECK-NEXT: 1 1 0.17 cneg x9, xzr, lt +# CHECK-NEXT: 1 1 0.17 csneg x4, x8, x8, al +# CHECK-NEXT: 1 1 0.17 csinv w9, w8, w8, nv +# CHECK-NEXT: 1 1 0.17 rbit w0, w7 +# CHECK-NEXT: 1 1 0.17 rbit x18, x3 +# CHECK-NEXT: 1 1 0.17 rev16 w17, w1 +# CHECK-NEXT: 1 1 0.17 rev16 x5, x2 +# CHECK-NEXT: 1 1 0.17 rev w18, w0 +# CHECK-NEXT: 1 1 0.17 rev32 x20, x1 +# CHECK-NEXT: 1 1 0.17 rev x22, x2 +# CHECK-NEXT: 1 1 0.17 clz w24, w3 +# CHECK-NEXT: 1 1 0.17 clz x26, x4 +# CHECK-NEXT: 1 1 0.17 cls w3, w5 +# CHECK-NEXT: 1 1 0.17 cls x20, x5 +# CHECK-NEXT: 1 12 12.00 udiv w0, w7, w10 +# CHECK-NEXT: 1 20 20.00 udiv x9, x22, x4 +# CHECK-NEXT: 1 12 12.00 sdiv w12, w21, w0 +# CHECK-NEXT: 1 20 20.00 sdiv x13, x2, x1 +# CHECK-NEXT: 1 1 0.17 lsl w11, w12, w13 +# CHECK-NEXT: 1 1 0.17 lsl x14, x15, x16 +# CHECK-NEXT: 1 1 0.17 lsr w17, w18, w19 +# CHECK-NEXT: 1 1 0.17 lsr x20, x21, x22 +# CHECK-NEXT: 1 1 0.17 asr w23, w24, w25 +# CHECK-NEXT: 1 1 0.17 asr x26, x27, x28 +# CHECK-NEXT: 1 1 0.17 ror w0, w1, w2 +# CHECK-NEXT: 1 1 0.17 ror x3, x4, x5 +# CHECK-NEXT: 1 1 0.17 lsl w6, w7, w8 +# CHECK-NEXT: 1 1 0.17 lsl x9, x10, x11 +# CHECK-NEXT: 1 1 0.17 lsr w12, w13, w14 +# CHECK-NEXT: 1 1 0.17 lsr x15, x16, x17 +# CHECK-NEXT: 1 1 0.17 asr w18, w19, w20 +# CHECK-NEXT: 1 1 0.17 asr x21, x22, x23 +# CHECK-NEXT: 1 1 0.17 ror w24, w25, w26 +# CHECK-NEXT: 1 1 0.17 ror x27, x28, x29 +# CHECK-NEXT: 1 3 0.50 smulh x30, x29, x28 +# CHECK-NEXT: 1 3 0.50 smulh xzr, x27, x26 +# CHECK-NEXT: 1 3 0.50 umulh x30, x29, x28 +# CHECK-NEXT: 1 3 0.50 umulh x23, x30, xzr +# CHECK-NEXT: 1 2 1.00 madd w1, w3, w7, w4 +# CHECK-NEXT: 1 2 1.00 madd wzr, w0, w9, w11 +# CHECK-NEXT: 1 2 1.00 madd w13, wzr, w4, w4 +# CHECK-NEXT: 1 2 1.00 madd w19, w30, wzr, w29 +# CHECK-NEXT: 1 2 0.50 mul w4, w5, w6 +# CHECK-NEXT: 1 2 1.00 madd x1, x3, x7, x4 +# CHECK-NEXT: 1 2 1.00 madd xzr, x0, x9, x11 +# CHECK-NEXT: 1 2 1.00 madd x13, xzr, x4, x4 +# CHECK-NEXT: 1 2 1.00 madd x19, x30, xzr, x29 +# CHECK-NEXT: 1 2 0.50 mul x4, x5, x6 +# CHECK-NEXT: 1 2 1.00 msub w1, w3, w7, w4 +# CHECK-NEXT: 1 2 1.00 msub wzr, w0, w9, w11 +# CHECK-NEXT: 1 2 1.00 msub w13, wzr, w4, w4 +# CHECK-NEXT: 1 2 1.00 msub w19, w30, wzr, w29 +# CHECK-NEXT: 1 2 0.50 mneg w4, w5, w6 +# CHECK-NEXT: 1 2 1.00 msub x1, x3, x7, x4 +# CHECK-NEXT: 1 2 1.00 msub xzr, x0, x9, x11 +# CHECK-NEXT: 1 2 1.00 msub x13, xzr, x4, x4 +# CHECK-NEXT: 1 2 1.00 msub x19, x30, xzr, x29 +# CHECK-NEXT: 1 2 0.50 mneg x4, x5, x6 +# CHECK-NEXT: 1 2 1.00 smaddl x3, w5, w2, x9 +# CHECK-NEXT: 1 2 1.00 smaddl xzr, w10, w11, x12 +# CHECK-NEXT: 1 2 1.00 smaddl x13, wzr, w14, x15 +# CHECK-NEXT: 1 2 1.00 smaddl x16, w17, wzr, x18 +# CHECK-NEXT: 1 2 0.50 smull x19, w20, w21 +# CHECK-NEXT: 1 2 1.00 smsubl x3, w5, w2, x9 +# CHECK-NEXT: 1 2 1.00 smsubl xzr, w10, w11, x12 +# CHECK-NEXT: 1 2 1.00 smsubl x13, wzr, w14, x15 +# CHECK-NEXT: 1 2 1.00 smsubl x16, w17, wzr, x18 +# CHECK-NEXT: 1 2 0.50 smnegl x19, w20, w21 +# CHECK-NEXT: 1 2 1.00 umaddl x3, w5, w2, x9 +# CHECK-NEXT: 1 2 1.00 umaddl xzr, w10, w11, x12 +# CHECK-NEXT: 1 2 1.00 umaddl x13, wzr, w14, x15 +# CHECK-NEXT: 1 2 1.00 umaddl x16, w17, wzr, x18 +# CHECK-NEXT: 1 2 0.50 umull x19, w20, w21 +# CHECK-NEXT: 1 2 1.00 umsubl x3, w5, w2, x9 +# CHECK-NEXT: 1 2 1.00 umsubl x16, w17, wzr, x18 +# CHECK-NEXT: 1 2 0.50 umnegl x19, w20, w21 +# CHECK-NEXT: 1 3 0.50 smulh x30, x29, x28 +# CHECK-NEXT: 1 3 0.50 smulh x23, x22, xzr +# CHECK-NEXT: 1 3 0.50 umulh x23, x22, xzr +# CHECK-NEXT: 1 2 0.50 mul x19, x20, xzr +# CHECK-NEXT: 1 2 0.50 mneg w21, w22, w23 +# CHECK-NEXT: 1 2 0.50 smull x11, w13, w17 +# CHECK-NEXT: 1 2 0.50 umull x11, w13, w17 +# CHECK-NEXT: 1 2 0.50 smnegl x11, w13, w17 +# CHECK-NEXT: 1 2 0.50 umnegl x11, w13, w17 +# CHECK-NEXT: 2 3 0.50 extr w3, w5, w7, #0 +# CHECK-NEXT: 2 3 0.50 extr w11, w13, w17, #31 +# CHECK-NEXT: 2 3 0.50 extr x3, x5, x7, #15 +# CHECK-NEXT: 2 3 0.50 extr x11, x13, x17, #63 +# CHECK-NEXT: 1 1 0.17 ror x19, x23, #24 +# CHECK-NEXT: 1 1 0.17 ror x29, xzr, #63 +# CHECK-NEXT: 1 1 0.17 ror w9, w13, #31 +# CHECK-NEXT: 1 2 1.00 fcmp s3, s5 +# CHECK-NEXT: 1 2 1.00 fcmp s31, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmp s31, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmpe s29, s30 +# CHECK-NEXT: 1 2 1.00 fcmpe s15, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmpe s15, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmp d4, d12 +# CHECK-NEXT: 1 2 1.00 fcmp d23, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmp d23, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmpe d26, d22 +# CHECK-NEXT: 1 2 1.00 fcmpe d29, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmpe d29, #0.0 +# CHECK-NEXT: 1 2 1.00 fccmp s1, s31, #0, eq +# CHECK-NEXT: 1 2 1.00 fccmp s3, s0, #15, hs +# CHECK-NEXT: 1 2 1.00 fccmp s31, s15, #13, hs +# CHECK-NEXT: 1 2 1.00 fccmp d9, d31, #0, le +# CHECK-NEXT: 1 2 1.00 fccmp d3, d0, #15, gt +# CHECK-NEXT: 1 2 1.00 fccmp d31, d5, #7, ne +# CHECK-NEXT: 1 2 1.00 fccmpe s1, s31, #0, eq +# CHECK-NEXT: 1 2 1.00 fccmpe s3, s0, #15, hs +# CHECK-NEXT: 1 2 1.00 fccmpe s31, s15, #13, hs +# CHECK-NEXT: 1 2 1.00 fccmpe d9, d31, #0, le +# CHECK-NEXT: 1 2 1.00 fccmpe d3, d0, #15, gt +# CHECK-NEXT: 1 2 1.00 fccmpe d31, d5, #7, ne +# CHECK-NEXT: 1 2 0.25 fcsel s3, s20, s9, pl +# CHECK-NEXT: 1 2 0.25 fcsel d9, d10, d11, mi +# CHECK-NEXT: 1 2 0.25 fmov s0, s1 +# CHECK-NEXT: 1 2 0.25 fabs s2, s3 +# CHECK-NEXT: 1 2 0.25 fneg s4, s5 +# CHECK-NEXT: 1 9 1.00 fsqrt s6, s7 +# CHECK-NEXT: 1 3 0.50 fcvt d8, s9 +# CHECK-NEXT: 1 3 0.50 fcvt h10, s11 +# CHECK-NEXT: 1 3 0.50 frintn s12, s13 +# CHECK-NEXT: 1 3 0.50 frintp s14, s15 +# CHECK-NEXT: 1 3 0.50 frintm s16, s17 +# CHECK-NEXT: 1 3 0.50 frintz s18, s19 +# CHECK-NEXT: 1 3 0.50 frinta s20, s21 +# CHECK-NEXT: 1 3 0.50 frintx s22, s23 +# CHECK-NEXT: 1 3 0.50 frinti s24, s25 +# CHECK-NEXT: 1 2 0.25 fmov d0, d1 +# CHECK-NEXT: 1 2 0.25 fabs d2, d3 +# CHECK-NEXT: 1 2 0.25 fneg d4, d5 +# CHECK-NEXT: 1 16 4.00 fsqrt d6, d7 +# CHECK-NEXT: 1 3 0.50 fcvt s8, d9 +# CHECK-NEXT: 1 3 0.50 fcvt h10, d11 +# CHECK-NEXT: 1 3 0.50 frintn d12, d13 +# CHECK-NEXT: 1 3 0.50 frintp d14, d15 +# CHECK-NEXT: 1 3 0.50 frintm d16, d17 +# CHECK-NEXT: 1 3 0.50 frintz d18, d19 +# CHECK-NEXT: 1 3 0.50 frinta d20, d21 +# CHECK-NEXT: 1 3 0.50 frintx d22, d23 +# CHECK-NEXT: 1 3 0.50 frinti d24, d25 +# CHECK-NEXT: 1 3 0.50 fcvt s26, h27 +# CHECK-NEXT: 1 3 0.50 fcvt d28, h29 +# CHECK-NEXT: 1 3 0.25 fmul s20, s19, s17 +# CHECK-NEXT: 1 10 1.00 fdiv s1, s2, s3 +# CHECK-NEXT: 1 2 0.25 fadd s4, s5, s6 +# CHECK-NEXT: 1 2 0.25 fsub s7, s8, s9 +# CHECK-NEXT: 1 2 0.25 fmax s10, s11, s12 +# CHECK-NEXT: 1 2 0.25 fmin s13, s14, s15 +# CHECK-NEXT: 1 2 0.25 fmaxnm s16, s17, s18 +# CHECK-NEXT: 1 2 0.25 fminnm s19, s20, s21 +# CHECK-NEXT: 1 3 0.25 fnmul s22, s23, s2 +# CHECK-NEXT: 1 3 0.25 fmul d20, d19, d17 +# CHECK-NEXT: 1 15 4.00 fdiv d1, d2, d3 +# CHECK-NEXT: 1 2 0.25 fadd d4, d5, d6 +# CHECK-NEXT: 1 2 0.25 fsub d7, d8, d9 +# CHECK-NEXT: 1 2 0.25 fmax d10, d11, d12 +# CHECK-NEXT: 1 2 0.25 fmin d13, d14, d15 +# CHECK-NEXT: 1 2 0.25 fmaxnm d16, d17, d18 +# CHECK-NEXT: 1 2 0.25 fminnm d19, d20, d21 +# CHECK-NEXT: 1 3 0.25 fnmul d22, d23, d24 +# CHECK-NEXT: 1 4 0.25 fmadd s3, s5, s6, s31 +# CHECK-NEXT: 1 4 0.25 fmadd d3, d13, d0, d23 +# CHECK-NEXT: 1 4 0.25 fmsub s3, s5, s6, s31 +# CHECK-NEXT: 1 4 0.25 fmsub d3, d13, d0, d23 +# CHECK-NEXT: 1 4 0.25 fnmadd s3, s5, s6, s31 +# CHECK-NEXT: 1 4 0.25 fnmadd d3, d13, d0, d23 +# CHECK-NEXT: 1 4 0.25 fnmsub s3, s5, s6, s31 +# CHECK-NEXT: 1 4 0.25 fnmsub d3, d13, d0, d23 +# CHECK-NEXT: 1 3 1.00 fcvtzs w3, h5, #1 +# CHECK-NEXT: 1 3 1.00 fcvtzs wzr, h20, #13 +# CHECK-NEXT: 1 3 1.00 fcvtzs w19, h0, #32 +# CHECK-NEXT: 1 3 1.00 fcvtzs x3, h5, #1 +# CHECK-NEXT: 1 3 1.00 fcvtzs x12, h30, #45 +# CHECK-NEXT: 1 3 1.00 fcvtzs x19, h0, #64 +# CHECK-NEXT: 1 3 1.00 fcvtzs w3, s5, #1 +# CHECK-NEXT: 1 3 1.00 fcvtzs wzr, s20, #13 +# CHECK-NEXT: 1 3 1.00 fcvtzs w19, s0, #32 +# CHECK-NEXT: 1 3 1.00 fcvtzs x3, s5, #1 +# CHECK-NEXT: 1 3 1.00 fcvtzs x12, s30, #45 +# CHECK-NEXT: 1 3 1.00 fcvtzs x19, s0, #64 +# CHECK-NEXT: 1 3 1.00 fcvtzs w3, d5, #1 +# CHECK-NEXT: 1 3 1.00 fcvtzs wzr, d20, #13 +# CHECK-NEXT: 1 3 1.00 fcvtzs w19, d0, #32 +# CHECK-NEXT: 1 3 1.00 fcvtzs x3, d5, #1 +# CHECK-NEXT: 1 3 1.00 fcvtzs x12, d30, #45 +# CHECK-NEXT: 1 3 1.00 fcvtzs x19, d0, #64 +# CHECK-NEXT: 1 3 1.00 fcvtzu w3, h5, #1 +# CHECK-NEXT: 1 3 1.00 fcvtzu wzr, h20, #13 +# CHECK-NEXT: 1 3 1.00 fcvtzu w19, h0, #32 +# CHECK-NEXT: 1 3 1.00 fcvtzu x3, h5, #1 +# CHECK-NEXT: 1 3 1.00 fcvtzu x12, h30, #45 +# CHECK-NEXT: 1 3 1.00 fcvtzu x19, h0, #64 +# CHECK-NEXT: 1 3 1.00 fcvtzu w3, s5, #1 +# CHECK-NEXT: 1 3 1.00 fcvtzu wzr, s20, #13 +# CHECK-NEXT: 1 3 1.00 fcvtzu w19, s0, #32 +# CHECK-NEXT: 1 3 1.00 fcvtzu x3, s5, #1 +# CHECK-NEXT: 1 3 1.00 fcvtzu x12, s30, #45 +# CHECK-NEXT: 1 3 1.00 fcvtzu x19, s0, #64 +# CHECK-NEXT: 1 3 1.00 fcvtzu w3, d5, #1 +# CHECK-NEXT: 1 3 1.00 fcvtzu wzr, d20, #13 +# CHECK-NEXT: 1 3 1.00 fcvtzu w19, d0, #32 +# CHECK-NEXT: 1 3 1.00 fcvtzu x3, d5, #1 +# CHECK-NEXT: 1 3 1.00 fcvtzu x12, d30, #45 +# CHECK-NEXT: 1 3 1.00 fcvtzu x19, d0, #64 +# CHECK-NEXT: 1 3 1.00 scvtf h23, w19, #1 +# CHECK-NEXT: 1 3 1.00 scvtf h31, wzr, #20 +# CHECK-NEXT: 1 3 1.00 scvtf h14, w0, #32 +# CHECK-NEXT: 1 3 1.00 scvtf h23, x19, #1 +# CHECK-NEXT: 1 3 1.00 scvtf h31, xzr, #20 +# CHECK-NEXT: 1 3 1.00 scvtf h14, x0, #64 +# CHECK-NEXT: 1 3 1.00 scvtf s23, w19, #1 +# CHECK-NEXT: 1 3 1.00 scvtf s31, wzr, #20 +# CHECK-NEXT: 1 3 1.00 scvtf s14, w0, #32 +# CHECK-NEXT: 1 3 1.00 scvtf s23, x19, #1 +# CHECK-NEXT: 1 3 1.00 scvtf s31, xzr, #20 +# CHECK-NEXT: 1 3 1.00 scvtf s14, x0, #64 +# CHECK-NEXT: 1 3 1.00 scvtf d23, w19, #1 +# CHECK-NEXT: 1 3 1.00 scvtf d31, wzr, #20 +# CHECK-NEXT: 1 3 1.00 scvtf d14, w0, #32 +# CHECK-NEXT: 1 3 1.00 scvtf d23, x19, #1 +# CHECK-NEXT: 1 3 1.00 scvtf d31, xzr, #20 +# CHECK-NEXT: 1 3 1.00 scvtf d14, x0, #64 +# CHECK-NEXT: 1 3 1.00 ucvtf h23, w19, #1 +# CHECK-NEXT: 1 3 1.00 ucvtf h31, wzr, #20 +# CHECK-NEXT: 1 3 1.00 ucvtf h14, w0, #32 +# CHECK-NEXT: 1 3 1.00 ucvtf h23, x19, #1 +# CHECK-NEXT: 1 3 1.00 ucvtf h31, xzr, #20 +# CHECK-NEXT: 1 3 1.00 ucvtf h14, x0, #64 +# CHECK-NEXT: 1 3 1.00 ucvtf s23, w19, #1 +# CHECK-NEXT: 1 3 1.00 ucvtf s31, wzr, #20 +# CHECK-NEXT: 1 3 1.00 ucvtf s14, w0, #32 +# CHECK-NEXT: 1 3 1.00 ucvtf s23, x19, #1 +# CHECK-NEXT: 1 3 1.00 ucvtf s31, xzr, #20 +# CHECK-NEXT: 1 3 1.00 ucvtf s14, x0, #64 +# CHECK-NEXT: 1 3 1.00 ucvtf d23, w19, #1 +# CHECK-NEXT: 1 3 1.00 ucvtf d31, wzr, #20 +# CHECK-NEXT: 1 3 1.00 ucvtf d14, w0, #32 +# CHECK-NEXT: 1 3 1.00 ucvtf d23, x19, #1 +# CHECK-NEXT: 1 3 1.00 ucvtf d31, xzr, #20 +# CHECK-NEXT: 1 3 1.00 ucvtf d14, x0, #64 +# CHECK-NEXT: 1 3 1.00 fcvtns w3, h31 +# CHECK-NEXT: 1 3 1.00 fcvtns xzr, h12 +# CHECK-NEXT: 1 3 1.00 fcvtnu wzr, h12 +# CHECK-NEXT: 1 3 1.00 fcvtnu x0, h0 +# CHECK-NEXT: 1 3 1.00 fcvtps wzr, h9 +# CHECK-NEXT: 1 3 1.00 fcvtps x12, h20 +# CHECK-NEXT: 1 3 1.00 fcvtpu w30, h23 +# CHECK-NEXT: 1 3 1.00 fcvtpu x29, h3 +# CHECK-NEXT: 1 3 1.00 fcvtms w2, h3 +# CHECK-NEXT: 1 3 1.00 fcvtms x4, h5 +# CHECK-NEXT: 1 3 1.00 fcvtmu w6, h7 +# CHECK-NEXT: 1 3 1.00 fcvtmu x8, h9 +# CHECK-NEXT: 1 3 1.00 fcvtzs w10, h11 +# CHECK-NEXT: 1 3 1.00 fcvtzs x12, h13 +# CHECK-NEXT: 1 3 1.00 fcvtzu w14, h15 +# CHECK-NEXT: 1 3 1.00 fcvtzu x15, h16 +# CHECK-NEXT: 1 3 1.00 scvtf h17, w18 +# CHECK-NEXT: 1 3 1.00 scvtf h19, x20 +# CHECK-NEXT: 1 3 1.00 ucvtf h21, w22 +# CHECK-NEXT: 1 3 1.00 scvtf h23, x24 +# CHECK-NEXT: 1 3 1.00 fcvtas w25, h26 +# CHECK-NEXT: 1 3 1.00 fcvtas x27, h28 +# CHECK-NEXT: 1 3 1.00 fcvtau w29, h30 +# CHECK-NEXT: 1 3 1.00 fcvtau xzr, h0 +# CHECK-NEXT: 1 3 1.00 fcvtns w3, s31 +# CHECK-NEXT: 1 3 1.00 fcvtns xzr, s12 +# CHECK-NEXT: 1 3 1.00 fcvtnu wzr, s12 +# CHECK-NEXT: 1 3 1.00 fcvtnu x0, s0 +# CHECK-NEXT: 1 3 1.00 fcvtps wzr, s9 +# CHECK-NEXT: 1 3 1.00 fcvtps x12, s20 +# CHECK-NEXT: 1 3 1.00 fcvtpu w30, s23 +# CHECK-NEXT: 1 3 1.00 fcvtpu x29, s3 +# CHECK-NEXT: 1 3 1.00 fcvtms w2, s3 +# CHECK-NEXT: 1 3 1.00 fcvtms x4, s5 +# CHECK-NEXT: 1 3 1.00 fcvtmu w6, s7 +# CHECK-NEXT: 1 3 1.00 fcvtmu x8, s9 +# CHECK-NEXT: 1 3 1.00 fcvtzs w10, s11 +# CHECK-NEXT: 1 3 1.00 fcvtzs x12, s13 +# CHECK-NEXT: 1 3 1.00 fcvtzu w14, s15 +# CHECK-NEXT: 1 3 1.00 fcvtzu x15, s16 +# CHECK-NEXT: 1 3 1.00 scvtf s17, w18 +# CHECK-NEXT: 1 3 1.00 scvtf s19, x20 +# CHECK-NEXT: 1 3 1.00 ucvtf s21, w22 +# CHECK-NEXT: 1 3 1.00 scvtf s23, x24 +# CHECK-NEXT: 1 3 1.00 fcvtas w25, s26 +# CHECK-NEXT: 1 3 1.00 fcvtas x27, s28 +# CHECK-NEXT: 1 3 1.00 fcvtau w29, s30 +# CHECK-NEXT: 1 3 1.00 fcvtau xzr, s0 +# CHECK-NEXT: 1 3 1.00 fcvtns w3, d31 +# CHECK-NEXT: 1 3 1.00 fcvtns xzr, d12 +# CHECK-NEXT: 1 3 1.00 fcvtnu wzr, d12 +# CHECK-NEXT: 1 3 1.00 fcvtnu x0, d0 +# CHECK-NEXT: 1 3 1.00 fcvtps wzr, d9 +# CHECK-NEXT: 1 3 1.00 fcvtps x12, d20 +# CHECK-NEXT: 1 3 1.00 fcvtpu w30, d23 +# CHECK-NEXT: 1 3 1.00 fcvtpu x29, d3 +# CHECK-NEXT: 1 3 1.00 fcvtms w2, d3 +# CHECK-NEXT: 1 3 1.00 fcvtms x4, d5 +# CHECK-NEXT: 1 3 1.00 fcvtmu w6, d7 +# CHECK-NEXT: 1 3 1.00 fcvtmu x8, d9 +# CHECK-NEXT: 1 3 1.00 fcvtzs w10, d11 +# CHECK-NEXT: 1 3 1.00 fcvtzs x12, d13 +# CHECK-NEXT: 1 3 1.00 fcvtzu w14, d15 +# CHECK-NEXT: 1 3 1.00 fcvtzu x15, d16 +# CHECK-NEXT: 1 3 1.00 scvtf d17, w18 +# CHECK-NEXT: 1 3 1.00 scvtf d19, x20 +# CHECK-NEXT: 1 3 1.00 ucvtf d21, w22 +# CHECK-NEXT: 1 3 1.00 ucvtf d23, x24 +# CHECK-NEXT: 1 3 1.00 fcvtas w25, d26 +# CHECK-NEXT: 1 3 1.00 fcvtas x27, d28 +# CHECK-NEXT: 1 3 1.00 fcvtau w29, d30 +# CHECK-NEXT: 1 3 1.00 fcvtau xzr, d0 +# CHECK-NEXT: 2 2 1.00 fmov w3, s9 +# CHECK-NEXT: 1 3 1.00 fmov s9, w3 +# CHECK-NEXT: 2 2 1.00 fmov x20, d31 +# CHECK-NEXT: 1 3 1.00 fmov d1, x15 +# CHECK-NEXT: 2 2 1.00 fmov x3, v12.d[1] +# CHECK-NEXT: 2 5 1.00 fmov v1.d[1], x19 +# CHECK-NEXT: 1 2 0.25 fmov s2, #0.12500000 +# CHECK-NEXT: 1 2 0.25 fmov s3, #1.00000000 +# CHECK-NEXT: 1 2 0.25 fmov d30, #16.00000000 +# CHECK-NEXT: 1 2 0.25 fmov s4, #1.06250000 +# CHECK-NEXT: 1 2 0.25 fmov d10, #1.93750000 +# CHECK-NEXT: 1 2 0.25 fmov s12, #-1.00000000 +# CHECK-NEXT: 1 2 0.25 fmov d16, #8.50000000 +# CHECK-NEXT: 2 5 0.33 * ldr w3, #0 +# CHECK-NEXT: 2 5 0.33 * ldr x29, #4 +# CHECK-NEXT: 2 5 0.33 * ldrsw xzr, #-4 +# CHECK-NEXT: 2 7 0.33 * ldr s0, #8 +# CHECK-NEXT: 2 7 0.33 * ldr d0, #1048572 +# CHECK-NEXT: 2 7 0.33 * ldr q0, #-1048576 +# CHECK-NEXT: 2 5 0.33 U prfm pldl1strm, #0 +# CHECK-NEXT: 2 5 0.33 U prfm #22, #0 +# CHECK-NEXT: 3 5 0.67 * * U stxrb w18, w8, [sp] +# CHECK-NEXT: 3 5 0.67 * * U stxrh w24, w15, [x16] +# CHECK-NEXT: 3 5 0.67 * * U stxr w5, w6, [x17] +# CHECK-NEXT: 3 5 0.67 * * U stxr w1, x10, [x21] +# CHECK-NEXT: 1 4 0.33 * * U ldxrb w30, [x0] +# CHECK-NEXT: 1 4 0.33 * * U ldxrh w17, [x4] +# CHECK-NEXT: 1 4 0.33 * * U ldxr w22, [sp] +# CHECK-NEXT: 1 4 0.33 * * U ldxr x11, [x29] +# CHECK-NEXT: 1 4 0.33 * * U ldxr x11, [x29] +# CHECK-NEXT: 1 4 0.33 * * U ldxr x11, [x29] +# CHECK-NEXT: 3 5 0.67 * * U stxp w12, w11, w10, [sp] +# CHECK-NEXT: 3 5 0.67 * * U stxp wzr, x27, x9, [x12] +# CHECK-NEXT: 2 4 0.33 * * U ldxp w0, wzr, [sp] +# CHECK-NEXT: 2 4 0.33 * * U ldxp x17, x0, [x18] +# CHECK-NEXT: 2 4 0.33 * * U ldxp x17, x0, [x18] +# CHECK-NEXT: 3 5 0.67 * * U stlxrb w12, w22, [x0] +# CHECK-NEXT: 3 5 0.67 * * U stlxrh w10, w1, [x1] +# CHECK-NEXT: 3 5 0.67 * * U stlxr w9, w2, [x2] +# CHECK-NEXT: 3 5 0.67 * * U stlxr w9, x3, [sp] +# CHECK-NEXT: 1 4 0.33 * * U ldaxrb w8, [x4] +# CHECK-NEXT: 1 4 0.33 * * U ldaxrh w7, [x5] +# CHECK-NEXT: 1 4 0.33 * * U ldaxr w6, [sp] +# CHECK-NEXT: 1 4 0.33 * * U ldaxr x5, [x6] +# CHECK-NEXT: 1 4 0.33 * * U ldaxr x5, [x6] +# CHECK-NEXT: 1 4 0.33 * * U ldaxr x5, [x6] +# CHECK-NEXT: 3 5 0.67 * * U stlxp w4, w5, w6, [sp] +# CHECK-NEXT: 3 5 0.67 * * U stlxp wzr, x6, x7, [x1] +# CHECK-NEXT: 2 4 0.33 * * U ldaxp w5, w18, [sp] +# CHECK-NEXT: 2 4 0.33 * * U ldaxp x6, x19, [x22] +# CHECK-NEXT: 2 4 0.33 * * U ldaxp x6, x19, [x22] +# CHECK-NEXT: 2 1 0.50 * U stlrb w24, [sp] +# CHECK-NEXT: 2 1 0.50 * U stlrh w25, [x30] +# CHECK-NEXT: 2 1 0.50 * U stlr w26, [x29] +# CHECK-NEXT: 2 1 0.50 * U stlr x27, [x28] +# CHECK-NEXT: 2 1 0.50 * U stlr x27, [x28] +# CHECK-NEXT: 2 1 0.50 * U stlr x27, [x28] +# CHECK-NEXT: 1 4 0.33 * U ldarb w23, [sp] +# CHECK-NEXT: 1 4 0.33 * U ldarh w22, [x30] +# CHECK-NEXT: 1 4 0.33 * U ldar wzr, [x29] +# CHECK-NEXT: 1 4 0.33 * U ldar x21, [x28] +# CHECK-NEXT: 1 4 0.33 * U ldar x21, [x28] +# CHECK-NEXT: 1 4 0.33 * U ldar x21, [x28] +# CHECK-NEXT: 2 1 0.50 * sturb w9, [sp] +# CHECK-NEXT: 2 1 0.50 * sturh wzr, [x12, #255] +# CHECK-NEXT: 2 1 0.50 * stur w16, [x0, #-256] +# CHECK-NEXT: 2 1 0.50 * stur x28, [x14, #1] +# CHECK-NEXT: 1 4 0.33 * ldurb w1, [x20, #255] +# CHECK-NEXT: 1 4 0.33 * ldurh w20, [x1, #255] +# CHECK-NEXT: 1 4 0.33 * ldur w12, [sp, #255] +# CHECK-NEXT: 1 4 0.33 * ldur xzr, [x12, #255] +# CHECK-NEXT: 1 4 0.33 * ldursb x9, [x7, #-256] +# CHECK-NEXT: 1 4 0.33 * ldursh x17, [x19, #-256] +# CHECK-NEXT: 1 4 0.33 * ldursw x20, [x15, #-256] +# CHECK-NEXT: 1 4 0.33 U prfum pldl2keep, [sp, #-256] +# CHECK-NEXT: 1 4 0.33 * ldursb w19, [x1, #-256] +# CHECK-NEXT: 1 4 0.33 * ldursh w15, [x21, #-256] +# CHECK-NEXT: 2 2 0.50 * stur b0, [sp, #1] +# CHECK-NEXT: 2 2 0.50 * stur h12, [x12, #-1] +# CHECK-NEXT: 2 2 0.50 * stur s15, [x0, #255] +# CHECK-NEXT: 2 2 0.50 * stur d31, [x5, #25] +# CHECK-NEXT: 2 2 0.50 * stur q9, [x5] +# CHECK-NEXT: 1 6 0.33 * ldur b3, [sp] +# CHECK-NEXT: 1 6 0.33 * ldur h5, [x4, #-256] +# CHECK-NEXT: 1 6 0.33 * ldur s7, [x12, #-1] +# CHECK-NEXT: 1 6 0.33 * ldur d11, [x19, #4] +# CHECK-NEXT: 1 6 0.33 * ldur q13, [x1, #2] +# CHECK-NEXT: 3 1 0.50 * strb w9, [x2], #255 +# CHECK-NEXT: 3 1 0.50 * strb w10, [x3], #1 +# CHECK-NEXT: 3 1 0.50 * strb w10, [x3], #-256 +# CHECK-NEXT: 3 1 0.50 * strh w9, [x2], #255 +# CHECK-NEXT: 3 1 0.50 * strh w9, [x2], #1 +# CHECK-NEXT: 3 1 0.50 * strh w10, [x3], #-256 +# CHECK-NEXT: 3 1 0.50 * str w19, [sp], #255 +# CHECK-NEXT: 3 1 0.50 * str w20, [x30], #1 +# CHECK-NEXT: 3 1 0.50 * str w21, [x12], #-256 +# CHECK-NEXT: 3 1 0.50 * str xzr, [x9], #255 +# CHECK-NEXT: 3 1 0.50 * str x2, [x3], #1 +# CHECK-NEXT: 3 1 0.50 * str x19, [x12], #-256 +# CHECK-NEXT: 2 4 0.33 * ldrb w9, [x2], #255 +# CHECK-NEXT: 2 4 0.33 * ldrb w10, [x3], #1 +# CHECK-NEXT: 2 4 0.33 * ldrb w10, [x3], #-256 +# CHECK-NEXT: 2 4 0.33 * ldrh w9, [x2], #255 +# CHECK-NEXT: 2 4 0.33 * ldrh w9, [x2], #1 +# CHECK-NEXT: 2 4 0.33 * ldrh w10, [x3], #-256 +# CHECK-NEXT: 2 4 0.33 * ldr w19, [sp], #255 +# CHECK-NEXT: 2 4 0.33 * ldr w20, [x30], #1 +# CHECK-NEXT: 2 4 0.33 * ldr w21, [x12], #-256 +# CHECK-NEXT: 2 4 0.33 * ldr xzr, [x9], #255 +# CHECK-NEXT: 2 4 0.33 * ldr x2, [x3], #1 +# CHECK-NEXT: 2 4 0.33 * ldr x19, [x12], #-256 +# CHECK-NEXT: 2 4 0.33 * ldrsb xzr, [x9], #255 +# CHECK-NEXT: 2 4 0.33 * ldrsb x2, [x3], #1 +# CHECK-NEXT: 2 4 0.33 * ldrsb x19, [x12], #-256 +# CHECK-NEXT: 2 4 0.33 * ldrsh xzr, [x9], #255 +# CHECK-NEXT: 2 4 0.33 * ldrsh x2, [x3], #1 +# CHECK-NEXT: 2 4 0.33 * ldrsh x19, [x12], #-256 +# CHECK-NEXT: 2 4 0.33 * ldrsw xzr, [x9], #255 +# CHECK-NEXT: 2 4 0.33 * ldrsw x2, [x3], #1 +# CHECK-NEXT: 2 4 0.33 * ldrsw x19, [x12], #-256 +# CHECK-NEXT: 2 4 0.33 * ldrsb wzr, [x9], #255 +# CHECK-NEXT: 2 4 0.33 * ldrsb w2, [x3], #1 +# CHECK-NEXT: 2 4 0.33 * ldrsb w19, [x12], #-256 +# CHECK-NEXT: 2 4 0.33 * ldrsh wzr, [x9], #255 +# CHECK-NEXT: 2 4 0.33 * ldrsh w2, [x3], #1 +# CHECK-NEXT: 2 4 0.33 * ldrsh w19, [x12], #-256 +# CHECK-NEXT: 4 2 0.50 * str b0, [x0], #255 +# CHECK-NEXT: 4 2 0.50 * str b3, [x3], #1 +# CHECK-NEXT: 4 2 0.50 * str b5, [sp], #-256 +# CHECK-NEXT: 4 2 0.50 * str h10, [x10], #255 +# CHECK-NEXT: 4 2 0.50 * str h13, [x23], #1 +# CHECK-NEXT: 4 2 0.50 * str h15, [sp], #-256 +# CHECK-NEXT: 4 2 0.50 * str s20, [x20], #255 +# CHECK-NEXT: 4 2 0.50 * str s23, [x23], #1 +# CHECK-NEXT: 4 2 0.50 * str s25, [x0], #-256 +# CHECK-NEXT: 4 2 0.50 * str d20, [x20], #255 +# CHECK-NEXT: 4 2 0.50 * str d23, [x23], #1 +# CHECK-NEXT: 4 2 0.50 * str d25, [x0], #-256 +# CHECK-NEXT: 3 6 0.33 * ldr b0, [x0], #255 +# CHECK-NEXT: 3 6 0.33 * ldr b3, [x3], #1 +# CHECK-NEXT: 3 6 0.33 * ldr b5, [sp], #-256 +# CHECK-NEXT: 3 6 0.33 * ldr h10, [x10], #255 +# CHECK-NEXT: 3 6 0.33 * ldr h13, [x23], #1 +# CHECK-NEXT: 3 6 0.33 * ldr h15, [sp], #-256 +# CHECK-NEXT: 3 6 0.33 * ldr s20, [x20], #255 +# CHECK-NEXT: 3 6 0.33 * ldr s23, [x23], #1 +# CHECK-NEXT: 3 6 0.33 * ldr s25, [x0], #-256 +# CHECK-NEXT: 3 6 0.33 * ldr d20, [x20], #255 +# CHECK-NEXT: 3 6 0.33 * ldr d23, [x23], #1 +# CHECK-NEXT: 3 6 0.33 * ldr d25, [x0], #-256 +# CHECK-NEXT: 3 6 0.33 * ldr q20, [x1], #255 +# CHECK-NEXT: 3 6 0.33 * ldr q23, [x9], #1 +# CHECK-NEXT: 3 6 0.33 * ldr q25, [x20], #-256 +# CHECK-NEXT: 4 2 0.50 * str q10, [x1], #255 +# CHECK-NEXT: 4 2 0.50 * str q22, [sp], #1 +# CHECK-NEXT: 4 2 0.50 * str q21, [x20], #-256 +# CHECK-NEXT: 2 4 0.33 * ldr x3, [x4, #0]! +# CHECK-NEXT: 3 1 0.50 * strb w9, [x2, #255]! +# CHECK-NEXT: 3 1 0.50 * strb w10, [x3, #1]! +# CHECK-NEXT: 3 1 0.50 * strb w10, [x3, #-256]! +# CHECK-NEXT: 3 1 0.50 * strh w9, [x2, #255]! +# CHECK-NEXT: 3 1 0.50 * strh w9, [x2, #1]! +# CHECK-NEXT: 3 1 0.50 * strh w10, [x3, #-256]! +# CHECK-NEXT: 3 1 0.50 * str w19, [sp, #255]! +# CHECK-NEXT: 3 1 0.50 * str w20, [x30, #1]! +# CHECK-NEXT: 3 1 0.50 * str w21, [x12, #-256]! +# CHECK-NEXT: 3 1 0.50 * str xzr, [x9, #255]! +# CHECK-NEXT: 3 1 0.50 * str x2, [x3, #1]! +# CHECK-NEXT: 3 1 0.50 * str x19, [x12, #-256]! +# CHECK-NEXT: 2 4 0.33 * ldrb w9, [x2, #255]! +# CHECK-NEXT: 2 4 0.33 * ldrb w10, [x3, #1]! +# CHECK-NEXT: 2 4 0.33 * ldrb w10, [x3, #-256]! +# CHECK-NEXT: 2 4 0.33 * ldrh w9, [x2, #255]! +# CHECK-NEXT: 2 4 0.33 * ldrh w9, [x2, #1]! +# CHECK-NEXT: 2 4 0.33 * ldrh w10, [x3, #-256]! +# CHECK-NEXT: 2 4 0.33 * ldr w19, [sp, #255]! +# CHECK-NEXT: 2 4 0.33 * ldr w20, [x30, #1]! +# CHECK-NEXT: 2 4 0.33 * ldr w21, [x12, #-256]! +# CHECK-NEXT: 2 4 0.33 * ldr xzr, [x9, #255]! +# CHECK-NEXT: 2 4 0.33 * ldr x2, [x3, #1]! +# CHECK-NEXT: 2 4 0.33 * ldr x19, [x12, #-256]! +# CHECK-NEXT: 2 4 0.33 * ldrsb xzr, [x9, #255]! +# CHECK-NEXT: 2 4 0.33 * ldrsb x2, [x3, #1]! +# CHECK-NEXT: 2 4 0.33 * ldrsb x19, [x12, #-256]! +# CHECK-NEXT: 2 4 0.33 * ldrsh xzr, [x9, #255]! +# CHECK-NEXT: 2 4 0.33 * ldrsh x2, [x3, #1]! +# CHECK-NEXT: 2 4 0.33 * ldrsh x19, [x12, #-256]! +# CHECK-NEXT: 2 4 0.33 * ldrsw xzr, [x9, #255]! +# CHECK-NEXT: 2 4 0.33 * ldrsw x2, [x3, #1]! +# CHECK-NEXT: 2 4 0.33 * ldrsw x19, [x12, #-256]! +# CHECK-NEXT: 2 4 0.33 * ldrsb wzr, [x9, #255]! +# CHECK-NEXT: 2 4 0.33 * ldrsb w2, [x3, #1]! +# CHECK-NEXT: 2 4 0.33 * ldrsb w19, [x12, #-256]! +# CHECK-NEXT: 2 4 0.33 * ldrsh wzr, [x9, #255]! +# CHECK-NEXT: 2 4 0.33 * ldrsh w2, [x3, #1]! +# CHECK-NEXT: 2 4 0.33 * ldrsh w19, [x12, #-256]! +# CHECK-NEXT: 4 2 0.50 * str b0, [x0, #255]! +# CHECK-NEXT: 4 2 0.50 * str b3, [x3, #1]! +# CHECK-NEXT: 4 2 0.50 * str b5, [sp, #-256]! +# CHECK-NEXT: 4 2 0.50 * str h10, [x10, #255]! +# CHECK-NEXT: 4 2 0.50 * str h13, [x23, #1]! +# CHECK-NEXT: 4 2 0.50 * str h15, [sp, #-256]! +# CHECK-NEXT: 4 2 0.50 * str s20, [x20, #255]! +# CHECK-NEXT: 4 2 0.50 * str s23, [x23, #1]! +# CHECK-NEXT: 4 2 0.50 * str s25, [x0, #-256]! +# CHECK-NEXT: 4 2 0.50 * str d20, [x20, #255]! +# CHECK-NEXT: 4 2 0.50 * str d23, [x23, #1]! +# CHECK-NEXT: 4 2 0.50 * str d25, [x0, #-256]! +# CHECK-NEXT: 3 6 0.33 * ldr b0, [x0, #255]! +# CHECK-NEXT: 3 6 0.33 * ldr b3, [x3, #1]! +# CHECK-NEXT: 3 6 0.33 * ldr b5, [sp, #-256]! +# CHECK-NEXT: 3 6 0.33 * ldr h10, [x10, #255]! +# CHECK-NEXT: 3 6 0.33 * ldr h13, [x23, #1]! +# CHECK-NEXT: 3 6 0.33 * ldr h15, [sp, #-256]! +# CHECK-NEXT: 3 6 0.33 * ldr s20, [x20, #255]! +# CHECK-NEXT: 3 6 0.33 * ldr s23, [x23, #1]! +# CHECK-NEXT: 3 6 0.33 * ldr s25, [x0, #-256]! +# CHECK-NEXT: 3 6 0.33 * ldr d20, [x20, #255]! +# CHECK-NEXT: 3 6 0.33 * ldr d23, [x23, #1]! +# CHECK-NEXT: 3 6 0.33 * ldr d25, [x0, #-256]! +# CHECK-NEXT: 3 6 0.33 * ldr q20, [x1, #255]! +# CHECK-NEXT: 3 6 0.33 * ldr q23, [x9, #1]! +# CHECK-NEXT: 3 6 0.33 * ldr q25, [x20, #-256]! +# CHECK-NEXT: 4 2 0.50 * str q10, [x1, #255]! +# CHECK-NEXT: 4 2 0.50 * str q22, [sp, #1]! +# CHECK-NEXT: 4 2 0.50 * str q21, [x20, #-256]! +# CHECK-NEXT: 2 1 0.50 * sttrb w9, [sp] +# CHECK-NEXT: 2 1 0.50 * sttrh wzr, [x12, #255] +# CHECK-NEXT: 2 1 0.50 * sttr w16, [x0, #-256] +# CHECK-NEXT: 2 1 0.50 * sttr x28, [x14, #1] +# CHECK-NEXT: 1 4 0.33 * ldtrb w1, [x20, #255] +# CHECK-NEXT: 1 4 0.33 * ldtrh w20, [x1, #255] +# CHECK-NEXT: 1 4 0.33 * ldtr w12, [sp, #255] +# CHECK-NEXT: 1 4 0.33 * ldtr xzr, [x12, #255] +# CHECK-NEXT: 1 4 0.33 * ldtrsb x9, [x7, #-256] +# CHECK-NEXT: 1 4 0.33 * ldtrsh x17, [x19, #-256] +# CHECK-NEXT: 1 4 0.33 * ldtrsw x20, [x15, #-256] +# CHECK-NEXT: 1 4 0.33 * ldtrsb w19, [x1, #-256] +# CHECK-NEXT: 1 4 0.33 * ldtrsh w15, [x21, #-256] +# CHECK-NEXT: 1 4 0.33 * ldr x4, [x29] +# CHECK-NEXT: 1 4 0.33 * ldr x30, [x12, #32760] +# CHECK-NEXT: 1 4 0.33 * ldr x20, [sp, #8] +# CHECK-NEXT: 1 4 0.33 * ldr xzr, [sp] +# CHECK-NEXT: 1 4 0.33 * ldr w2, [sp] +# CHECK-NEXT: 1 4 0.33 * ldr w17, [sp, #16380] +# CHECK-NEXT: 1 4 0.33 * ldr w13, [x2, #4] +# CHECK-NEXT: 1 4 0.33 * ldrsw x2, [x5, #4] +# CHECK-NEXT: 1 4 0.33 * ldrsw x23, [sp, #16380] +# CHECK-NEXT: 1 4 0.33 * ldrh w2, [x4] +# CHECK-NEXT: 1 4 0.33 * ldrsh w23, [x6, #8190] +# CHECK-NEXT: 1 4 0.33 * ldrsh wzr, [sp, #2] +# CHECK-NEXT: 1 4 0.33 * ldrsh x29, [x2, #2] +# CHECK-NEXT: 1 4 0.33 * ldrb w26, [x3, #121] +# CHECK-NEXT: 1 4 0.33 * ldrb w12, [x2] +# CHECK-NEXT: 1 4 0.33 * ldrsb w27, [sp, #4095] +# CHECK-NEXT: 1 4 0.33 * ldrsb xzr, [x15] +# CHECK-NEXT: 2 1 0.50 * str x30, [sp] +# CHECK-NEXT: 2 1 0.50 * str w20, [x4, #16380] +# CHECK-NEXT: 2 1 0.50 * strh w17, [sp, #8190] +# CHECK-NEXT: 2 1 0.50 * strb w23, [x3, #4095] +# CHECK-NEXT: 2 1 0.50 * strb wzr, [x2] +# CHECK-NEXT: 1 6 0.33 * ldr b31, [sp, #4095] +# CHECK-NEXT: 1 6 0.33 * ldr h20, [x2, #8190] +# CHECK-NEXT: 1 6 0.33 * ldr s10, [x19, #16380] +# CHECK-NEXT: 1 6 0.33 * ldr d3, [x10, #32760] +# CHECK-NEXT: 2 2 0.50 * str q12, [sp, #65520] +# CHECK-NEXT: 1 6 0.33 * ldr h3, [sp, x5] +# CHECK-NEXT: 1 6 0.33 * ldr h9, [x27, x6] +# CHECK-NEXT: 2 7 0.33 * ldr h10, [x30, x7, lsl #1] +# CHECK-NEXT: 2 2 0.50 * str h11, [x29, x3, sxtx] +# CHECK-NEXT: 2 2 0.50 * str h12, [x28, xzr, sxtx] +# CHECK-NEXT: 3 2 0.50 * str h13, [x27, x5, sxtx #1] +# CHECK-NEXT: 1 6 0.33 * ldr h14, [x26, w6, uxtw] +# CHECK-NEXT: 1 6 0.33 * ldr h15, [x25, w7, uxtw] +# CHECK-NEXT: 2 7 0.33 * ldr h16, [x24, w8, uxtw #1] +# CHECK-NEXT: 1 6 0.33 * ldr h17, [x23, w9, sxtw] +# CHECK-NEXT: 2 2 0.50 * str h18, [x22, w10, sxtw] +# CHECK-NEXT: 2 7 0.33 * ldr h19, [x21, wzr, sxtw #1] +# CHECK-NEXT: 1 4 0.33 * ldrb w3, [sp, x5] +# CHECK-NEXT: 1 4 0.33 * ldrb w9, [x27, x6] +# CHECK-NEXT: 1 4 0.33 * ldrsb w10, [x30, x7] +# CHECK-NEXT: 1 4 0.33 * ldrb w11, [x29, x3, sxtx] +# CHECK-NEXT: 2 1 0.50 * strb w12, [x28, xzr, sxtx] +# CHECK-NEXT: 1 4 0.33 * ldrb w14, [x26, w6, uxtw] +# CHECK-NEXT: 1 4 0.33 * ldrsb w15, [x25, w7, uxtw] +# CHECK-NEXT: 1 4 0.33 * ldrb w17, [x23, w9, sxtw] +# CHECK-NEXT: 1 4 0.33 * ldrsb x18, [x22, w10, sxtw] +# CHECK-NEXT: 1 4 0.33 * ldrsh w3, [sp, x5] +# CHECK-NEXT: 1 4 0.33 * ldrsh w9, [x27, x6] +# CHECK-NEXT: 1 4 0.33 * ldrh w10, [x30, x7, lsl #1] +# CHECK-NEXT: 2 1 0.50 * strh w11, [x29, x3, sxtx] +# CHECK-NEXT: 1 4 0.33 * ldrh w12, [x28, xzr, sxtx] +# CHECK-NEXT: 1 4 0.33 * ldrsh x13, [x27, x5, sxtx #1] +# CHECK-NEXT: 1 4 0.33 * ldrh w14, [x26, w6, uxtw] +# CHECK-NEXT: 1 4 0.33 * ldrh w15, [x25, w7, uxtw] +# CHECK-NEXT: 1 4 0.33 * ldrsh w16, [x24, w8, uxtw #1] +# CHECK-NEXT: 1 4 0.33 * ldrh w17, [x23, w9, sxtw] +# CHECK-NEXT: 1 4 0.33 * ldrh w18, [x22, w10, sxtw] +# CHECK-NEXT: 2 1 0.50 * strh w19, [x21, wzr, sxtw #1] +# CHECK-NEXT: 1 4 0.33 * ldr w3, [sp, x5] +# CHECK-NEXT: 1 6 0.33 * ldr s9, [x27, x6] +# CHECK-NEXT: 1 4 0.33 * ldr w10, [x30, x7, lsl #2] +# CHECK-NEXT: 1 4 0.33 * ldr w11, [x29, x3, sxtx] +# CHECK-NEXT: 2 2 0.50 * str s12, [x28, xzr, sxtx] +# CHECK-NEXT: 2 1 0.50 * str w13, [x27, x5, sxtx #2] +# CHECK-NEXT: 2 1 0.50 * str w14, [x26, w6, uxtw] +# CHECK-NEXT: 1 4 0.33 * ldr w15, [x25, w7, uxtw] +# CHECK-NEXT: 1 4 0.33 * ldr w16, [x24, w8, uxtw #2] +# CHECK-NEXT: 1 4 0.33 * ldrsw x17, [x23, w9, sxtw] +# CHECK-NEXT: 1 4 0.33 * ldr w18, [x22, w10, sxtw] +# CHECK-NEXT: 1 4 0.33 * ldrsw x19, [x21, wzr, sxtw #2] +# CHECK-NEXT: 1 4 0.33 * ldr x3, [sp, x5] +# CHECK-NEXT: 2 1 0.50 * str x9, [x27, x6] +# CHECK-NEXT: 1 6 0.33 * ldr d10, [x30, x7, lsl #3] +# CHECK-NEXT: 2 1 0.50 * str x11, [x29, x3, sxtx] +# CHECK-NEXT: 1 4 0.33 * ldr x12, [x28, xzr, sxtx] +# CHECK-NEXT: 1 4 0.33 * ldr x13, [x27, x5, sxtx #3] +# CHECK-NEXT: 1 4 0.33 U prfm pldl1keep, [x26, w6, uxtw] +# CHECK-NEXT: 1 4 0.33 * ldr x15, [x25, w7, uxtw] +# CHECK-NEXT: 1 4 0.33 * ldr x16, [x24, w8, uxtw #3] +# CHECK-NEXT: 1 4 0.33 * ldr x17, [x23, w9, sxtw] +# CHECK-NEXT: 1 4 0.33 * ldr x18, [x22, w10, sxtw] +# CHECK-NEXT: 2 2 0.50 * str d19, [x21, wzr, sxtw #3] +# CHECK-NEXT: 1 6 0.33 * ldr q3, [sp, x5] +# CHECK-NEXT: 1 6 0.33 * ldr q9, [x27, x6] +# CHECK-NEXT: 2 7 0.33 * ldr q10, [x30, x7, lsl #4] +# CHECK-NEXT: 2 2 0.50 * str q11, [x29, x3, sxtx] +# CHECK-NEXT: 2 2 0.50 * str q12, [x28, xzr, sxtx] +# CHECK-NEXT: 3 2 0.50 * str q13, [x27, x5, sxtx #4] +# CHECK-NEXT: 1 6 0.33 * ldr q14, [x26, w6, uxtw] +# CHECK-NEXT: 1 6 0.33 * ldr q15, [x25, w7, uxtw] +# CHECK-NEXT: 2 7 0.33 * ldr q16, [x24, w8, uxtw #4] +# CHECK-NEXT: 1 6 0.33 * ldr q17, [x23, w9, sxtw] +# CHECK-NEXT: 2 2 0.50 * str q18, [x22, w10, sxtw] +# CHECK-NEXT: 2 7 0.33 * ldr q19, [x21, wzr, sxtw #4] +# CHECK-NEXT: 2 4 0.33 * ldp w3, w5, [sp] +# CHECK-NEXT: 2 1 0.50 * stp wzr, w9, [sp, #252] +# CHECK-NEXT: 2 4 0.33 * ldp w2, wzr, [sp, #-256] +# CHECK-NEXT: 2 4 0.33 * ldp w9, w10, [sp, #4] +# CHECK-NEXT: 5 5 1.00 * ldpsw x9, x10, [sp, #4] +# CHECK-NEXT: 5 5 1.00 * ldpsw x9, x10, [x2, #-256] +# CHECK-NEXT: 5 5 1.00 * ldpsw x20, x30, [sp, #252] +# CHECK-NEXT: 2 4 0.33 * ldp x21, x29, [x2, #504] +# CHECK-NEXT: 2 4 0.33 * ldp x22, x23, [x3, #-512] +# CHECK-NEXT: 2 4 0.33 * ldp x24, x25, [x4, #8] +# CHECK-NEXT: 2 6 0.33 * ldp s29, s28, [sp, #252] +# CHECK-NEXT: 2 2 0.50 * stp s27, s26, [sp, #-256] +# CHECK-NEXT: 2 6 0.33 * ldp s1, s2, [x3, #44] +# CHECK-NEXT: 2 2 0.50 * stp d3, d5, [x9, #504] +# CHECK-NEXT: 2 2 0.50 * stp d7, d11, [x10, #-512] +# CHECK-NEXT: 2 6 0.33 * ldp d2, d3, [x30, #-8] +# CHECK-NEXT: 3 2 1.00 * stp q3, q5, [sp] +# CHECK-NEXT: 3 2 1.00 * stp q17, q19, [sp, #1008] +# CHECK-NEXT: 3 6 0.67 * ldp q23, q29, [x1, #-1024] +# CHECK-NEXT: 3 4 0.33 * ldp w3, w5, [sp], #0 +# CHECK-NEXT: 3 1 0.50 * stp wzr, w9, [sp], #252 +# CHECK-NEXT: 3 4 0.33 * ldp w2, wzr, [sp], #-256 +# CHECK-NEXT: 3 4 0.33 * ldp w9, w10, [sp], #4 +# CHECK-NEXT: 6 5 1.00 * ldpsw x9, x10, [sp], #4 +# CHECK-NEXT: 6 5 1.00 * ldpsw x9, x10, [x2], #-256 +# CHECK-NEXT: 6 5 1.00 * ldpsw x20, x30, [sp], #252 +# CHECK-NEXT: 3 4 0.33 * ldp x21, x29, [x2], #504 +# CHECK-NEXT: 3 4 0.33 * ldp x22, x23, [x3], #-512 +# CHECK-NEXT: 3 4 0.33 * ldp x24, x25, [x4], #8 +# CHECK-NEXT: 4 6 0.33 * ldp s29, s28, [sp], #252 +# CHECK-NEXT: 4 2 0.50 * stp s27, s26, [sp], #-256 +# CHECK-NEXT: 4 6 0.33 * ldp s1, s2, [x3], #44 +# CHECK-NEXT: 4 2 0.50 * stp d3, d5, [x9], #504 +# CHECK-NEXT: 4 2 0.50 * stp d7, d11, [x10], #-512 +# CHECK-NEXT: 4 6 0.33 * ldp d2, d3, [x30], #-8 +# CHECK-NEXT: 4 2 1.00 * stp q3, q5, [sp], #0 +# CHECK-NEXT: 4 2 1.00 * stp q17, q19, [sp], #1008 +# CHECK-NEXT: 6 6 0.67 * ldp q23, q29, [x1], #-1024 +# CHECK-NEXT: 3 4 0.33 * ldp w3, w5, [sp, #0]! +# CHECK-NEXT: 3 1 0.50 * stp wzr, w9, [sp, #252]! +# CHECK-NEXT: 3 4 0.33 * ldp w2, wzr, [sp, #-256]! +# CHECK-NEXT: 3 4 0.33 * ldp w9, w10, [sp, #4]! +# CHECK-NEXT: 6 5 1.00 * ldpsw x9, x10, [sp, #4]! +# CHECK-NEXT: 6 5 1.00 * ldpsw x9, x10, [x2, #-256]! +# CHECK-NEXT: 6 5 1.00 * ldpsw x20, x30, [sp, #252]! +# CHECK-NEXT: 3 4 0.33 * ldp x21, x29, [x2, #504]! +# CHECK-NEXT: 3 4 0.33 * ldp x22, x23, [x3, #-512]! +# CHECK-NEXT: 3 4 0.33 * ldp x24, x25, [x4, #8]! +# CHECK-NEXT: 4 6 0.33 * ldp s29, s28, [sp, #252]! +# CHECK-NEXT: 4 2 0.50 * stp s27, s26, [sp, #-256]! +# CHECK-NEXT: 4 6 0.33 * ldp s1, s2, [x3, #44]! +# CHECK-NEXT: 4 2 0.50 * stp d3, d5, [x9, #504]! +# CHECK-NEXT: 4 2 0.50 * stp d7, d11, [x10, #-512]! +# CHECK-NEXT: 4 6 0.33 * ldp d2, d3, [x30, #-8]! +# CHECK-NEXT: 5 2 1.00 * stp q3, q5, [sp, #0]! +# CHECK-NEXT: 5 2 1.00 * stp q17, q19, [sp, #1008]! +# CHECK-NEXT: 6 6 0.67 * ldp q23, q29, [x1, #-1024]! +# CHECK-NEXT: 2 4 0.33 * ldnp w3, w5, [sp] +# CHECK-NEXT: 2 1 0.50 * stnp wzr, w9, [sp, #252] +# CHECK-NEXT: 2 4 0.33 * ldnp w2, wzr, [sp, #-256] +# CHECK-NEXT: 2 4 0.33 * ldnp w9, w10, [sp, #4] +# CHECK-NEXT: 2 4 0.33 * ldnp x21, x29, [x2, #504] +# CHECK-NEXT: 2 4 0.33 * ldnp x22, x23, [x3, #-512] +# CHECK-NEXT: 2 4 0.33 * ldnp x24, x25, [x4, #8] +# CHECK-NEXT: 2 6 0.33 * ldnp s29, s28, [sp, #252] +# CHECK-NEXT: 2 2 0.50 * stnp s27, s26, [sp, #-256] +# CHECK-NEXT: 2 6 0.33 * ldnp s1, s2, [x3, #44] +# CHECK-NEXT: 2 2 0.50 * stnp d3, d5, [x9, #504] +# CHECK-NEXT: 2 2 0.50 * stnp d7, d11, [x10, #-512] +# CHECK-NEXT: 2 6 0.33 * ldnp d2, d3, [x30, #-8] +# CHECK-NEXT: 3 2 1.00 * stnp q3, q5, [sp] +# CHECK-NEXT: 3 2 1.00 * stnp q17, q19, [sp, #1008] +# CHECK-NEXT: 3 6 0.67 * ldnp q23, q29, [x1, #-1024] +# CHECK-NEXT: 1 1 0.17 mov w3, #983055 +# CHECK-NEXT: 1 1 0.17 mov x10, #-6148914691236517206 +# CHECK-NEXT: 1 1 0.17 and w12, w23, w21 +# CHECK-NEXT: 1 1 0.17 and w16, w15, w1, lsl #1 +# CHECK-NEXT: 1 1 0.17 and w9, w4, w10, lsl #31 +# CHECK-NEXT: 1 1 0.17 and w3, w30, w11 +# CHECK-NEXT: 1 1 0.17 and x3, x5, x7, lsl #63 +# CHECK-NEXT: 1 1 0.17 and x5, x14, x19, asr #4 +# CHECK-NEXT: 1 1 0.17 and w3, w17, w19, ror #31 +# CHECK-NEXT: 1 1 0.17 and w0, w2, wzr, lsr #17 +# CHECK-NEXT: 1 1 0.17 and w3, w30, w11, asr #2 +# CHECK-NEXT: 1 1 0.17 and xzr, x4, x26 +# CHECK-NEXT: 1 1 0.17 and w3, wzr, w20, ror #2 +# CHECK-NEXT: 1 1 0.17 and x7, x20, xzr, asr #63 +# CHECK-NEXT: 1 1 0.17 bic x13, x20, x14, lsl #47 +# CHECK-NEXT: 1 1 0.17 bic w2, w7, w9 +# CHECK-NEXT: 1 1 0.17 orr w2, w7, w0, asr #31 +# CHECK-NEXT: 1 1 0.17 orr x8, x9, x10, lsl #12 +# CHECK-NEXT: 1 1 0.17 orn x3, x5, x7, asr #2 +# CHECK-NEXT: 1 1 0.17 orn w2, w5, w29 +# CHECK-NEXT: 1 2 0.50 ands w7, wzr, w9, lsl #1 +# CHECK-NEXT: 1 2 0.50 ands x3, x5, x20, ror #63 +# CHECK-NEXT: 1 1 0.25 bics w3, w5, w7 +# CHECK-NEXT: 1 2 0.50 bics x3, xzr, x3, lsl #1 +# CHECK-NEXT: 1 2 0.50 tst w3, w7, lsl #31 +# CHECK-NEXT: 1 2 0.50 tst x2, x20, asr #2 +# CHECK-NEXT: 1 1 0.17 mov x3, x6 +# CHECK-NEXT: 1 1 0.17 mov x3, xzr +# CHECK-NEXT: 1 1 0.17 mov wzr, w2 +# CHECK-NEXT: 1 1 0.17 mov w3, w5 +# CHECK-NEXT: 1 1 0.17 movz w2, #0, lsl #16 +# CHECK-NEXT: 1 1 0.17 mov w2, #-1235 +# CHECK-NEXT: 1 1 0.17 mov x2, #5299989643264 +# CHECK-NEXT: 1 1 0.17 mov x2, #0 +# CHECK-NEXT: 1 1 0.17 movk w3, #0 +# CHECK-NEXT: 1 1 0.17 movz x4, #0, lsl #16 +# CHECK-NEXT: 1 1 0.17 movk w5, #0, lsl #16 +# CHECK-NEXT: 1 1 0.17 movz x6, #0, lsl #32 +# CHECK-NEXT: 1 1 0.17 movk x7, #0, lsl #32 +# CHECK-NEXT: 1 1 0.17 movz x8, #0, lsl #48 +# CHECK-NEXT: 1 1 0.17 movk x9, #0, lsl #48 +# CHECK-NEXT: 1 1 0.25 adr x2, #1600 +# CHECK-NEXT: 1 1 0.25 adrp x21, #6553600 +# CHECK-NEXT: 1 1 0.25 adr x0, #262144 +# CHECK-NEXT: 1 1 0.50 tbz x12, #62, #0 +# CHECK-NEXT: 1 1 0.50 tbz x12, #62, #4 +# CHECK-NEXT: 1 1 0.50 tbz x12, #62, #-32768 +# CHECK-NEXT: 1 1 0.50 tbnz x12, #60, #32764 +# CHECK-NEXT: 1 1 0.50 b #4 +# CHECK-NEXT: 1 1 0.50 b #-4 +# CHECK-NEXT: 1 1 0.50 b #134217724 +# CHECK-NEXT: 1 1 0.50 br x20 +# CHECK-NEXT: 2 1 0.50 blr xzr +# CHECK-NEXT: 1 1 0.50 U ret x10 +# CHECK-NEXT: 1 1 0.50 U ret +# CHECK-NEXT: 1 1 0.50 U eret +# CHECK-NEXT: 1 1 0.50 U drps + +# CHECK: Resources: +# CHECK-NEXT: [0.0] - V2UnitB +# CHECK-NEXT: [0.1] - V2UnitB +# CHECK-NEXT: [1.0] - V2UnitD +# CHECK-NEXT: [1.1] - V2UnitD +# CHECK-NEXT: [2] - V2UnitL2 +# CHECK-NEXT: [3.0] - V2UnitL01 +# CHECK-NEXT: [3.1] - V2UnitL01 +# CHECK-NEXT: [4] - V2UnitM0 +# CHECK-NEXT: [5] - V2UnitM1 +# CHECK-NEXT: [6] - V2UnitS0 +# CHECK-NEXT: [7] - V2UnitS1 +# CHECK-NEXT: [8] - V2UnitS2 +# CHECK-NEXT: [9] - V2UnitS3 +# CHECK-NEXT: [10] - V2UnitV0 +# CHECK-NEXT: [11] - V2UnitV1 +# CHECK-NEXT: [12] - V2UnitV2 +# CHECK-NEXT: [13] - V2UnitV3 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] +# CHECK-NEXT: 11.00 11.00 33.00 33.00 99.00 165.00 165.00 327.42 182.42 110.42 110.42 92.67 92.67 190.00 146.00 30.00 10.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add w2, w3, #4095 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add w30, w29, #1, lsl #12 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add w13, w5, #4095, lsl #12 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add x5, x7, #1638 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add w20, wsp, #801 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add wsp, wsp, #1104 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add wsp, w30, #4084 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add x0, x24, #291 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add x3, x24, #4095, lsl #12 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add x8, sp, #1074 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add sp, x29, #3816 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sub w0, wsp, #4077 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sub w4, w20, #546, lsl #12 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sub sp, sp, #288 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sub wsp, w19, #16 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - adds w13, w23, #291, lsl #12 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cmn w2, #4095 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - adds w20, wsp, #0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cmn x3, #1, lsl #12 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cmp sp, #20, lsl #12 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cmp x30, #4095 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - subs x4, sp, #3822 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cmn w3, #291, lsl #12 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cmn wsp, #1365 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cmn sp, #1092, lsl #12 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - mov sp, x30 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - mov wsp, w20 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - mov x11, sp +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - mov w24, wsp +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add w3, w5, w7 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add wzr, w3, w5 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add w20, wzr, w4 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add w4, w6, wzr +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add w11, w13, w15 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - add w9, w3, wzr, lsl #10 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - add w17, w29, w20, lsl #31 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - add w21, w22, w23, lsr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - add w24, w25, w26, lsr #18 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - add w27, w28, w29, lsr #31 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - add w2, w3, w4, asr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - add w5, w6, w7, asr #21 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - add w8, w9, w10, asr #31 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add x3, x5, x7 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add xzr, x3, x5 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add x20, xzr, x4 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add x4, x6, xzr +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - add x11, x13, x15 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - add x9, x3, xzr, lsl #10 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - add x17, x29, x20, lsl #63 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - add x21, x22, x23, lsr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - add x24, x25, x26, lsr #18 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - add x27, x28, x29, lsr #63 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - add x2, x3, x4, asr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - add x5, x6, x7, asr #21 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - add x8, x9, x10, asr #63 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adds w3, w5, w7 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmn w3, w5 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adds w20, wzr, w4 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adds w4, w6, wzr +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adds w11, w13, w15 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - adds w9, w3, wzr, lsl #10 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - adds w17, w29, w20, lsl #31 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - adds w21, w22, w23, lsr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - adds w24, w25, w26, lsr #18 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - adds w27, w28, w29, lsr #31 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - adds w2, w3, w4, asr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - adds w5, w6, w7, asr #21 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - adds w8, w9, w10, asr #31 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adds x3, x5, x7 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmn x3, x5 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adds x20, xzr, x4 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adds x4, x6, xzr +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adds x11, x13, x15 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - adds x9, x3, xzr, lsl #10 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - adds x17, x29, x20, lsl #63 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - adds x21, x22, x23, lsr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - adds x24, x25, x26, lsr #18 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - adds x27, x28, x29, lsr #63 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - adds x2, x3, x4, asr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - adds x5, x6, x7, asr #21 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - adds x8, x9, x10, asr #63 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sub w3, w5, w7 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sub wzr, w3, w5 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sub w4, w6, wzr +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sub w11, w13, w15 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - sub w9, w3, wzr, lsl #10 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - sub w17, w29, w20, lsl #31 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - sub w21, w22, w23, lsr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - sub w24, w25, w26, lsr #18 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - sub w27, w28, w29, lsr #31 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - sub w2, w3, w4, asr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - sub w5, w6, w7, asr #21 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - sub w8, w9, w10, asr #31 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sub x3, x5, x7 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sub xzr, x3, x5 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sub x4, x6, xzr +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sub x11, x13, x15 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - sub x9, x3, xzr, lsl #10 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - sub x17, x29, x20, lsl #63 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - sub x21, x22, x23, lsr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - sub x24, x25, x26, lsr #18 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - sub x27, x28, x29, lsr #63 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - sub x2, x3, x4, asr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - sub x5, x6, x7, asr #21 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - sub x8, x9, x10, asr #63 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - subs w3, w5, w7 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmp w3, w5 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - subs w4, w6, wzr +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - subs w11, w13, w15 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - subs w9, w3, wzr, lsl #10 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - subs w17, w29, w20, lsl #31 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - subs w21, w22, w23, lsr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - subs w24, w25, w26, lsr #18 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - subs w27, w28, w29, lsr #31 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - subs w2, w3, w4, asr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - subs w5, w6, w7, asr #21 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - subs w8, w9, w10, asr #31 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - subs x3, x5, x7 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmp x3, x5 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - subs x4, x6, xzr +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - subs x11, x13, x15 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - subs x9, x3, xzr, lsl #10 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - subs x17, x29, x20, lsl #63 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - subs x21, x22, x23, lsr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - subs x24, x25, x26, lsr #18 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - subs x27, x28, x29, lsr #63 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - subs x2, x3, x4, asr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - subs x5, x6, x7, asr #21 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - subs x8, x9, x10, asr #63 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmn wzr, w4 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmn w5, wzr +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmn w6, w7 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmn w8, w9, lsl #15 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmn w10, w11, lsl #31 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmn w12, w13, lsr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmn w14, w15, lsr #21 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmn w16, w17, lsr #31 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmn w18, w19, asr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmn w20, w21, asr #22 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmn w22, w23, asr #31 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmn x0, x3 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmn xzr, x4 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmn x5, xzr +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmn x6, x7 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmn x8, x9, lsl #15 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmn x10, x11, lsl #63 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmn x12, x13, lsr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmn x14, x15, lsr #41 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmn x16, x17, lsr #63 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmn x18, x19, asr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmn x20, x21, asr #55 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmn x22, x23, asr #63 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmp w0, w3 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmp wzr, w4 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmp w5, wzr +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmp w6, w7 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmp w8, w9, lsl #15 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmp w10, w11, lsl #31 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmp w12, w13, lsr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmp w14, w15, lsr #21 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmp w18, w19, asr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmp w20, w21, asr #22 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmp w22, w23, asr #31 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmp x0, x3 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmp xzr, x4 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmp x5, xzr +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmp x6, x7 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmp x8, x9, lsl #15 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmp x10, x11, lsl #63 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmp x12, x13, lsr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmp x14, x15, lsr #41 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmp x16, x17, lsr #63 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmp x18, x19, asr #0 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmp x20, x21, asr #55 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - cmp x22, x23, asr #63 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmp wzr, w0 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - cmp xzr, x0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - adc w29, w27, w25 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - adc wzr, w3, w4 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - adc w9, wzr, w10 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - adc w20, w0, wzr +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - adc x29, x27, x25 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - adc xzr, x3, x4 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - adc x9, xzr, x10 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - adc x20, x0, xzr +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adcs w29, w27, w25 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adcs wzr, w3, w4 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adcs w9, wzr, w10 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adcs w20, w0, wzr +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adcs x29, x27, x25 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adcs xzr, x3, x4 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adcs x9, xzr, x10 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adcs x20, x0, xzr +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sbc w29, w27, w25 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sbc wzr, w3, w4 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ngc w9, w10 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sbc w20, w0, wzr +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sbc x29, x27, x25 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sbc xzr, x3, x4 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ngc x9, x10 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sbc x20, x0, xzr +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - sbcs w29, w27, w25 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - sbcs wzr, w3, w4 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - ngcs w9, w10 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - sbcs w20, w0, wzr +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - sbcs x29, x27, x25 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - sbcs xzr, x3, x4 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - ngcs x9, x10 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - sbcs x20, x0, xzr +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ngc w3, w12 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ngc wzr, w9 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ngc w23, wzr +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ngc x29, x30 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ngc xzr, x0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ngc x0, xzr +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - ngcs w3, w12 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - ngcs wzr, w9 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - ngcs w23, wzr +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - ngcs x29, x30 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - ngcs xzr, x0 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - ngcs x0, xzr +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sbfx x1, x2, #3, #2 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr x3, x4, #63 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr wzr, wzr, #31 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sbfx w12, w9, #0, #1 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ubfiz x4, x5, #52, #11 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ubfx xzr, x4, #0, #1 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ubfiz x4, xzr, #1, #6 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr x5, x6, #12 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfi x4, x5, #52, #11 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfxil xzr, x4, #0, #1 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfc x4, #1, #6 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfxil x5, x6, #12, #52 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sxtb w1, w2 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sxtb xzr, w3 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sxth w9, w10 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sxth x0, w1 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sxtw x3, w30 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - uxtb w1, w2 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - uxth w9, w10 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ubfx x3, x30, #0, #32 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr w3, w2, #0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr w9, w10, #31 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr x20, x21, #63 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr w1, wzr, #3 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr w3, w2, #0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr w9, w10, #31 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr x20, x21, #63 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr wzr, wzr, #3 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr w3, w2, #0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsl w9, w10, #31 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsl x20, x21, #63 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsl w1, wzr, #3 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sbfx w9, w10, #0, #1 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sbfiz x2, x3, #63, #1 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr x19, x20, #0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sbfiz x9, x10, #5, #59 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr w9, w10, #0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sbfiz w11, w12, #31, #1 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sbfiz w13, w14, #29, #3 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sbfiz xzr, xzr, #10, #11 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sbfx w9, w10, #0, #1 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr x2, x3, #63 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr x19, x20, #0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr x9, x10, #5 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr w9, w10, #0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr w11, w12, #31 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr w13, w14, #29 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - sbfx xzr, xzr, #10, #11 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfxil w9, w10, #0, #1 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfi x2, x3, #63, #1 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfxil x19, x20, #0, #64 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfi x9, x10, #5, #59 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfxil w9, w10, #0, #32 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfi w11, w12, #31, #1 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfi w13, w14, #29, #3 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfc xzr, #10, #11 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfxil w9, w10, #0, #1 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfxil x2, x3, #63, #1 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfxil x19, x20, #0, #64 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfxil x9, x10, #5, #59 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfxil w9, w10, #0, #32 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfxil w11, w12, #31, #1 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfxil w13, w14, #29, #3 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bfxil xzr, xzr, #10, #11 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ubfx w9, w10, #0, #1 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsl x2, x3, #63 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr x19, x20, #0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsl x9, x10, #5 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr w9, w10, #0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsl w11, w12, #31 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsl w13, w14, #29 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ubfiz xzr, xzr, #10, #11 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ubfx w9, w10, #0, #1 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr x2, x3, #63 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr x19, x20, #0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr x9, x10, #5 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr w9, w10, #0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr w11, w12, #31 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr w13, w14, #29 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ubfx xzr, xzr, #10, #11 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - cbz w5, #4 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - cbz x5, #0 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - cbnz x2, #-4 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - cbnz x26, #1048572 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - cbz wzr, #0 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - cbnz xzr, #0 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - b.ne #4 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - b.ge #1048572 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - b.ge #-4 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmp w1, #31, #0, eq +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmp w3, #0, #15, hs +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmp wzr, #15, #13, hs +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmp x9, #31, #0, le +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmp x3, #0, #15, gt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmp xzr, #5, #7, ne +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmn w1, #31, #0, eq +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmn w3, #0, #15, hs +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmn wzr, #15, #13, hs +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmn x9, #31, #0, le +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmn x3, #0, #15, gt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmn xzr, #5, #7, ne +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmp w1, wzr, #0, eq +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmp w3, w0, #15, hs +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmp wzr, w15, #13, hs +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmp x9, xzr, #0, le +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmp x3, x0, #15, gt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmp xzr, x5, #7, ne +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmn w1, wzr, #0, eq +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmn w3, w0, #15, hs +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmn wzr, w15, #13, hs +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmn x9, xzr, #0, le +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmn x3, x0, #15, gt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ccmn xzr, x5, #7, ne +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csel w1, w0, w19, ne +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csel wzr, w5, w9, eq +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csel w9, wzr, w30, gt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csel w1, w28, wzr, mi +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csel x19, x23, x29, lt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csel xzr, x3, x4, ge +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csel x5, xzr, x6, hs +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csel x7, x8, xzr, lo +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinc w1, w0, w19, ne +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinc wzr, w5, w9, eq +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinc w9, wzr, w30, gt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinc w1, w28, wzr, mi +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinc x19, x23, x29, lt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinc xzr, x3, x4, ge +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinc x5, xzr, x6, hs +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinc x7, x8, xzr, lo +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinv w1, w0, w19, ne +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinv wzr, w5, w9, eq +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinv w9, wzr, w30, gt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinv w1, w28, wzr, mi +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinv x19, x23, x29, lt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinv xzr, x3, x4, ge +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinv x5, xzr, x6, hs +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinv x7, x8, xzr, lo +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csneg w1, w0, w19, ne +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csneg wzr, w5, w9, eq +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csneg w9, wzr, w30, gt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csneg w1, w28, wzr, mi +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csneg x19, x23, x29, lt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csneg xzr, x3, x4, ge +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csneg x5, xzr, x6, hs +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csneg x7, x8, xzr, lo +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cset w3, eq +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cset x9, pl +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csetm w20, ne +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csetm x30, ge +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinc w2, wzr, wzr, al +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinv x3, xzr, xzr, nv +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cinc w3, w5, gt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cinc wzr, w4, le +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cset w9, lt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cinc x3, x5, gt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cinc xzr, x4, le +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cset x9, lt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinc w5, w6, w6, nv +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinc x1, x2, x2, al +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cinv w3, w5, gt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cinv wzr, w4, le +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csetm w9, lt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cinv x3, x5, gt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cinv xzr, x4, le +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csetm x9, lt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinv x1, x0, x0, al +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinv w9, w8, w8, nv +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cneg w3, w5, gt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cneg wzr, w4, le +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cneg w9, wzr, lt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cneg x3, x5, gt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cneg xzr, x4, le +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cneg x9, xzr, lt +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csneg x4, x8, x8, al +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - csinv w9, w8, w8, nv +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - rbit w0, w7 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - rbit x18, x3 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - rev16 w17, w1 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - rev16 x5, x2 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - rev w18, w0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - rev32 x20, x1 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - rev x22, x2 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - clz w24, w3 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - clz x26, x4 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cls w3, w5 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - cls x20, x5 +# CHECK-NEXT: - - - - - - - 12.00 - - - - - - - - - udiv w0, w7, w10 +# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - udiv x9, x22, x4 +# CHECK-NEXT: - - - - - - - 12.00 - - - - - - - - - sdiv w12, w21, w0 +# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - sdiv x13, x2, x1 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsl w11, w12, w13 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsl x14, x15, x16 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr w17, w18, w19 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr x20, x21, x22 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr w23, w24, w25 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr x26, x27, x28 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ror w0, w1, w2 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ror x3, x4, x5 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsl w6, w7, w8 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsl x9, x10, x11 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr w12, w13, w14 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - lsr x15, x16, x17 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr w18, w19, w20 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - asr x21, x22, x23 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ror w24, w25, w26 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ror x27, x28, x29 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - smulh x30, x29, x28 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - smulh xzr, x27, x26 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - umulh x30, x29, x28 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - umulh x23, x30, xzr +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - madd w1, w3, w7, w4 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - madd wzr, w0, w9, w11 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - madd w13, wzr, w4, w4 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - madd w19, w30, wzr, w29 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - mul w4, w5, w6 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - madd x1, x3, x7, x4 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - madd xzr, x0, x9, x11 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - madd x13, xzr, x4, x4 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - madd x19, x30, xzr, x29 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - mul x4, x5, x6 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - msub w1, w3, w7, w4 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - msub wzr, w0, w9, w11 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - msub w13, wzr, w4, w4 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - msub w19, w30, wzr, w29 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - mneg w4, w5, w6 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - msub x1, x3, x7, x4 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - msub xzr, x0, x9, x11 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - msub x13, xzr, x4, x4 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - msub x19, x30, xzr, x29 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - mneg x4, x5, x6 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - smaddl x3, w5, w2, x9 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - smaddl xzr, w10, w11, x12 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - smaddl x13, wzr, w14, x15 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - smaddl x16, w17, wzr, x18 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - smull x19, w20, w21 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - smsubl x3, w5, w2, x9 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - smsubl xzr, w10, w11, x12 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - smsubl x13, wzr, w14, x15 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - smsubl x16, w17, wzr, x18 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - smnegl x19, w20, w21 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - umaddl x3, w5, w2, x9 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - umaddl xzr, w10, w11, x12 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - umaddl x13, wzr, w14, x15 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - umaddl x16, w17, wzr, x18 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - umull x19, w20, w21 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - umsubl x3, w5, w2, x9 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - umsubl x16, w17, wzr, x18 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - umnegl x19, w20, w21 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - smulh x30, x29, x28 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - smulh x23, x22, xzr +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - umulh x23, x22, xzr +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - mul x19, x20, xzr +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - mneg w21, w22, w23 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - smull x11, w13, w17 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - umull x11, w13, w17 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - smnegl x11, w13, w17 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - umnegl x11, w13, w17 +# CHECK-NEXT: - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 - - - - extr w3, w5, w7, #0 +# CHECK-NEXT: - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 - - - - extr w11, w13, w17, #31 +# CHECK-NEXT: - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 - - - - extr x3, x5, x7, #15 +# CHECK-NEXT: - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 - - - - extr x11, x13, x17, #63 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ror x19, x23, #24 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ror x29, xzr, #63 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ror w9, w13, #31 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fcmp s3, s5 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fcmp s31, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fcmp s31, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fcmpe s29, s30 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fcmpe s15, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fcmpe s15, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fcmp d4, d12 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fcmp d23, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fcmp d23, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fcmpe d26, d22 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fcmpe d29, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fcmpe d29, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fccmp s1, s31, #0, eq +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fccmp s3, s0, #15, hs +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fccmp s31, s15, #13, hs +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fccmp d9, d31, #0, le +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fccmp d3, d0, #15, gt +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fccmp d31, d5, #7, ne +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fccmpe s1, s31, #0, eq +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fccmpe s3, s0, #15, hs +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fccmpe s31, s15, #13, hs +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fccmpe d9, d31, #0, le +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fccmpe d3, d0, #15, gt +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - fccmpe d31, d5, #7, ne +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcsel s3, s20, s9, pl +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcsel d9, d10, d11, mi +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmov s0, s1 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fabs s2, s3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fneg s4, s5 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fsqrt s6, s7 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvt d8, s9 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvt h10, s11 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintn s12, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintp s14, s15 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintm s16, s17 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintz s18, s19 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frinta s20, s21 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintx s22, s23 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frinti s24, s25 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmov d0, d1 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fabs d2, d3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fneg d4, d5 +# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - 4.00 - fsqrt d6, d7 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvt s8, d9 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvt h10, d11 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintn d12, d13 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintp d14, d15 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintm d16, d17 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintz d18, d19 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frinta d20, d21 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintx d22, d23 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frinti d24, d25 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvt s26, h27 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvt d28, h29 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmul s20, s19, s17 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fdiv s1, s2, s3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fadd s4, s5, s6 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fsub s7, s8, s9 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmax s10, s11, s12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmin s13, s14, s15 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmaxnm s16, s17, s18 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fminnm s19, s20, s21 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fnmul s22, s23, s2 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmul d20, d19, d17 +# CHECK-NEXT: - - - - - - - - - - - - - 4.00 - 4.00 - fdiv d1, d2, d3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fadd d4, d5, d6 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fsub d7, d8, d9 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmax d10, d11, d12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmin d13, d14, d15 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmaxnm d16, d17, d18 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fminnm d19, d20, d21 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fnmul d22, d23, d24 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmadd s3, s5, s6, s31 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmadd d3, d13, d0, d23 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmsub s3, s5, s6, s31 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmsub d3, d13, d0, d23 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fnmadd s3, s5, s6, s31 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fnmadd d3, d13, d0, d23 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fnmsub s3, s5, s6, s31 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fnmsub d3, d13, d0, d23 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs w3, h5, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs wzr, h20, #13 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs w19, h0, #32 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs x3, h5, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs x12, h30, #45 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs x19, h0, #64 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs w3, s5, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs wzr, s20, #13 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs w19, s0, #32 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs x3, s5, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs x12, s30, #45 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs x19, s0, #64 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs w3, d5, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs wzr, d20, #13 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs w19, d0, #32 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs x3, d5, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs x12, d30, #45 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs x19, d0, #64 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu w3, h5, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu wzr, h20, #13 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu w19, h0, #32 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu x3, h5, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu x12, h30, #45 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu x19, h0, #64 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu w3, s5, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu wzr, s20, #13 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu w19, s0, #32 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu x3, s5, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu x12, s30, #45 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu x19, s0, #64 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu w3, d5, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu wzr, d20, #13 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu w19, d0, #32 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu x3, d5, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu x12, d30, #45 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu x19, d0, #64 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf h23, w19, #1 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf h31, wzr, #20 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf h14, w0, #32 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf h23, x19, #1 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf h31, xzr, #20 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf h14, x0, #64 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf s23, w19, #1 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf s31, wzr, #20 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf s14, w0, #32 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf s23, x19, #1 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf s31, xzr, #20 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf s14, x0, #64 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf d23, w19, #1 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf d31, wzr, #20 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf d14, w0, #32 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf d23, x19, #1 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf d31, xzr, #20 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf d14, x0, #64 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf h23, w19, #1 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf h31, wzr, #20 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf h14, w0, #32 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf h23, x19, #1 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf h31, xzr, #20 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf h14, x0, #64 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf s23, w19, #1 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf s31, wzr, #20 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf s14, w0, #32 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf s23, x19, #1 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf s31, xzr, #20 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf s14, x0, #64 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf d23, w19, #1 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf d31, wzr, #20 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf d14, w0, #32 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf d23, x19, #1 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf d31, xzr, #20 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf d14, x0, #64 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtns w3, h31 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtns xzr, h12 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtnu wzr, h12 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtnu x0, h0 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtps wzr, h9 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtps x12, h20 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtpu w30, h23 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtpu x29, h3 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtms w2, h3 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtms x4, h5 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtmu w6, h7 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtmu x8, h9 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs w10, h11 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs x12, h13 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu w14, h15 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu x15, h16 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf h17, w18 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf h19, x20 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf h21, w22 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf h23, x24 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtas w25, h26 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtas x27, h28 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtau w29, h30 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtau xzr, h0 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtns w3, s31 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtns xzr, s12 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtnu wzr, s12 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtnu x0, s0 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtps wzr, s9 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtps x12, s20 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtpu w30, s23 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtpu x29, s3 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtms w2, s3 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtms x4, s5 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtmu w6, s7 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtmu x8, s9 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs w10, s11 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs x12, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu w14, s15 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu x15, s16 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf s17, w18 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf s19, x20 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf s21, w22 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf s23, x24 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtas w25, s26 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtas x27, s28 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtau w29, s30 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtau xzr, s0 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtns w3, d31 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtns xzr, d12 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtnu wzr, d12 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtnu x0, d0 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtps wzr, d9 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtps x12, d20 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtpu w30, d23 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtpu x29, d3 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtms w2, d3 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtms x4, d5 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtmu w6, d7 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtmu x8, d9 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs w10, d11 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzs x12, d13 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu w14, d15 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtzu x15, d16 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf d17, w18 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - scvtf d19, x20 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf d21, w22 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ucvtf d23, x24 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtas w25, d26 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtas x27, d28 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtau w29, d30 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fcvtau xzr, d0 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fmov w3, s9 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - fmov s9, w3 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fmov x20, d31 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - fmov d1, x15 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - fmov x3, v12.d[1] +# CHECK-NEXT: - - - - - - - 1.00 - - - - - 0.25 0.25 0.25 0.25 fmov v1.d[1], x19 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmov s2, #0.12500000 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmov s3, #1.00000000 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmov d30, #16.00000000 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmov s4, #1.06250000 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmov d10, #1.93750000 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmov s12, #-1.00000000 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmov d16, #8.50000000 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - ldr w3, #0 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - ldr x29, #4 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - ldrsw xzr, #-4 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - ldr s0, #8 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - ldr d0, #1048572 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - ldr q0, #-1048576 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - prfm pldl1strm, #0 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - - prfm #22, #0 +# CHECK-NEXT: - - 0.50 0.50 0.33 0.83 0.83 - - - - - - - - - - stxrb w18, w8, [sp] +# CHECK-NEXT: - - 0.50 0.50 0.33 0.83 0.83 - - - - - - - - - - stxrh w24, w15, [x16] +# CHECK-NEXT: - - 0.50 0.50 0.33 0.83 0.83 - - - - - - - - - - stxr w5, w6, [x17] +# CHECK-NEXT: - - 0.50 0.50 0.33 0.83 0.83 - - - - - - - - - - stxr w1, x10, [x21] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldxrb w30, [x0] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldxrh w17, [x4] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldxr w22, [sp] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldxr x11, [x29] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldxr x11, [x29] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldxr x11, [x29] +# CHECK-NEXT: - - 0.50 0.50 0.33 0.83 0.83 - - - - - - - - - - stxp w12, w11, w10, [sp] +# CHECK-NEXT: - - 0.50 0.50 0.33 0.83 0.83 - - - - - - - - - - stxp wzr, x27, x9, [x12] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldxp w0, wzr, [sp] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldxp x17, x0, [x18] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldxp x17, x0, [x18] +# CHECK-NEXT: - - 0.50 0.50 0.33 0.83 0.83 - - - - - - - - - - stlxrb w12, w22, [x0] +# CHECK-NEXT: - - 0.50 0.50 0.33 0.83 0.83 - - - - - - - - - - stlxrh w10, w1, [x1] +# CHECK-NEXT: - - 0.50 0.50 0.33 0.83 0.83 - - - - - - - - - - stlxr w9, w2, [x2] +# CHECK-NEXT: - - 0.50 0.50 0.33 0.83 0.83 - - - - - - - - - - stlxr w9, x3, [sp] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldaxrb w8, [x4] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldaxrh w7, [x5] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldaxr w6, [sp] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldaxr x5, [x6] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldaxr x5, [x6] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldaxr x5, [x6] +# CHECK-NEXT: - - 0.50 0.50 0.33 0.83 0.83 - - - - - - - - - - stlxp w4, w5, w6, [sp] +# CHECK-NEXT: - - 0.50 0.50 0.33 0.83 0.83 - - - - - - - - - - stlxp wzr, x6, x7, [x1] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldaxp w5, w18, [sp] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldaxp x6, x19, [x22] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldaxp x6, x19, [x22] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - stlrb w24, [sp] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - stlrh w25, [x30] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - stlr w26, [x29] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - stlr x27, [x28] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - stlr x27, [x28] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - stlr x27, [x28] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldarb w23, [sp] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldarh w22, [x30] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldar wzr, [x29] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldar x21, [x28] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldar x21, [x28] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldar x21, [x28] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - sturb w9, [sp] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - sturh wzr, [x12, #255] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - stur w16, [x0, #-256] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - stur x28, [x14, #1] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldurb w1, [x20, #255] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldurh w20, [x1, #255] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldur w12, [sp, #255] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldur xzr, [x12, #255] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldursb x9, [x7, #-256] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldursh x17, [x19, #-256] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldursw x20, [x15, #-256] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - prfum pldl2keep, [sp, #-256] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldursb w19, [x1, #-256] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldursh w15, [x21, #-256] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - stur b0, [sp, #1] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - stur h12, [x12, #-1] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - stur s15, [x0, #255] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - stur d31, [x5, #25] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - stur q9, [x5] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldur b3, [sp] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldur h5, [x4, #-256] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldur s7, [x12, #-1] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldur d11, [x19, #4] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldur q13, [x1, #2] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - strb w9, [x2], #255 +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - strb w10, [x3], #1 +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - strb w10, [x3], #-256 +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - strh w9, [x2], #255 +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - strh w9, [x2], #1 +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - strh w10, [x3], #-256 +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - str w19, [sp], #255 +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - str w20, [x30], #1 +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - str w21, [x12], #-256 +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - str xzr, [x9], #255 +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - str x2, [x3], #1 +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - str x19, [x12], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrb w9, [x2], #255 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrb w10, [x3], #1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrb w10, [x3], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrh w9, [x2], #255 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrh w9, [x2], #1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrh w10, [x3], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr w19, [sp], #255 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr w20, [x30], #1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr w21, [x12], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr xzr, [x9], #255 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr x2, [x3], #1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr x19, [x12], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsb xzr, [x9], #255 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsb x2, [x3], #1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsb x19, [x12], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsh xzr, [x9], #255 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsh x2, [x3], #1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsh x19, [x12], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsw xzr, [x9], #255 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsw x2, [x3], #1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsw x19, [x12], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsb wzr, [x9], #255 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsb w2, [x3], #1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsb w19, [x12], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsh wzr, [x9], #255 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsh w2, [x3], #1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsh w19, [x12], #-256 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str b0, [x0], #255 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str b3, [x3], #1 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str b5, [sp], #-256 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str h10, [x10], #255 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str h13, [x23], #1 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str h15, [sp], #-256 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str s20, [x20], #255 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str s23, [x23], #1 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str s25, [x0], #-256 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str d20, [x20], #255 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str d23, [x23], #1 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str d25, [x0], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr b0, [x0], #255 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr b3, [x3], #1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr b5, [sp], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr h10, [x10], #255 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr h13, [x23], #1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr h15, [sp], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr s20, [x20], #255 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr s23, [x23], #1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr s25, [x0], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr d20, [x20], #255 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr d23, [x23], #1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr d25, [x0], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr q20, [x1], #255 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr q23, [x9], #1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr q25, [x20], #-256 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str q10, [x1], #255 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str q22, [sp], #1 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str q21, [x20], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr x3, [x4, #0]! +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - strb w9, [x2, #255]! +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - strb w10, [x3, #1]! +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - strb w10, [x3, #-256]! +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - strh w9, [x2, #255]! +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - strh w9, [x2, #1]! +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - strh w10, [x3, #-256]! +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - str w19, [sp, #255]! +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - str w20, [x30, #1]! +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - str w21, [x12, #-256]! +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - str xzr, [x9, #255]! +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - str x2, [x3, #1]! +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - str x19, [x12, #-256]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrb w9, [x2, #255]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrb w10, [x3, #1]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrb w10, [x3, #-256]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrh w9, [x2, #255]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrh w9, [x2, #1]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrh w10, [x3, #-256]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr w19, [sp, #255]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr w20, [x30, #1]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr w21, [x12, #-256]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr xzr, [x9, #255]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr x2, [x3, #1]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr x19, [x12, #-256]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsb xzr, [x9, #255]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsb x2, [x3, #1]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsb x19, [x12, #-256]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsh xzr, [x9, #255]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsh x2, [x3, #1]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsh x19, [x12, #-256]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsw xzr, [x9, #255]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsw x2, [x3, #1]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsw x19, [x12, #-256]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsb wzr, [x9, #255]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsb w2, [x3, #1]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsb w19, [x12, #-256]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsh wzr, [x9, #255]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsh w2, [x3, #1]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldrsh w19, [x12, #-256]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str b0, [x0, #255]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str b3, [x3, #1]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str b5, [sp, #-256]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str h10, [x10, #255]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str h13, [x23, #1]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str h15, [sp, #-256]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str s20, [x20, #255]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str s23, [x23, #1]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str s25, [x0, #-256]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str d20, [x20, #255]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str d23, [x23, #1]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str d25, [x0, #-256]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr b0, [x0, #255]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr b3, [x3, #1]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr b5, [sp, #-256]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr h10, [x10, #255]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr h13, [x23, #1]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr h15, [sp, #-256]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr s20, [x20, #255]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr s23, [x23, #1]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr s25, [x0, #-256]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr d20, [x20, #255]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr d23, [x23, #1]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr d25, [x0, #-256]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr q20, [x1, #255]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr q23, [x9, #1]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldr q25, [x20, #-256]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str q10, [x1, #255]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str q22, [sp, #1]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - str q21, [x20, #-256]! +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - sttrb w9, [sp] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - sttrh wzr, [x12, #255] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - sttr w16, [x0, #-256] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - sttr x28, [x14, #1] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldtrb w1, [x20, #255] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldtrh w20, [x1, #255] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldtr w12, [sp, #255] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldtr xzr, [x12, #255] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldtrsb x9, [x7, #-256] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldtrsh x17, [x19, #-256] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldtrsw x20, [x15, #-256] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldtrsb w19, [x1, #-256] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldtrsh w15, [x21, #-256] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr x4, [x29] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr x30, [x12, #32760] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr x20, [sp, #8] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr xzr, [sp] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr w2, [sp] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr w17, [sp, #16380] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr w13, [x2, #4] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrsw x2, [x5, #4] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrsw x23, [sp, #16380] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrh w2, [x4] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrsh w23, [x6, #8190] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrsh wzr, [sp, #2] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrsh x29, [x2, #2] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrb w26, [x3, #121] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrb w12, [x2] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrsb w27, [sp, #4095] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrsb xzr, [x15] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - str x30, [sp] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - str w20, [x4, #16380] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - strh w17, [sp, #8190] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - strb w23, [x3, #4095] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - strb wzr, [x2] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr b31, [sp, #4095] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr h20, [x2, #8190] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr s10, [x19, #16380] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr d3, [x10, #32760] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - str q12, [sp, #65520] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr h3, [sp, x5] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr h9, [x27, x6] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr h10, [x30, x7, lsl #1] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - str h11, [x29, x3, sxtx] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - str h12, [x28, xzr, sxtx] +# CHECK-NEXT: - - - - - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 - - str h13, [x27, x5, sxtx #1] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr h14, [x26, w6, uxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr h15, [x25, w7, uxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr h16, [x24, w8, uxtw #1] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr h17, [x23, w9, sxtw] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - str h18, [x22, w10, sxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr h19, [x21, wzr, sxtw #1] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrb w3, [sp, x5] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrb w9, [x27, x6] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrsb w10, [x30, x7] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrb w11, [x29, x3, sxtx] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - strb w12, [x28, xzr, sxtx] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrb w14, [x26, w6, uxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrsb w15, [x25, w7, uxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrb w17, [x23, w9, sxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrsb x18, [x22, w10, sxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrsh w3, [sp, x5] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrsh w9, [x27, x6] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrh w10, [x30, x7, lsl #1] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - strh w11, [x29, x3, sxtx] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrh w12, [x28, xzr, sxtx] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrsh x13, [x27, x5, sxtx #1] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrh w14, [x26, w6, uxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrh w15, [x25, w7, uxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrsh w16, [x24, w8, uxtw #1] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrh w17, [x23, w9, sxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrh w18, [x22, w10, sxtw] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - strh w19, [x21, wzr, sxtw #1] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr w3, [sp, x5] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr s9, [x27, x6] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr w10, [x30, x7, lsl #2] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr w11, [x29, x3, sxtx] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - str s12, [x28, xzr, sxtx] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - str w13, [x27, x5, sxtx #2] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - str w14, [x26, w6, uxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr w15, [x25, w7, uxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr w16, [x24, w8, uxtw #2] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrsw x17, [x23, w9, sxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr w18, [x22, w10, sxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldrsw x19, [x21, wzr, sxtw #2] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr x3, [sp, x5] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - str x9, [x27, x6] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr d10, [x30, x7, lsl #3] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - str x11, [x29, x3, sxtx] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr x12, [x28, xzr, sxtx] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr x13, [x27, x5, sxtx #3] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - prfm pldl1keep, [x26, w6, uxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr x15, [x25, w7, uxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr x16, [x24, w8, uxtw #3] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr x17, [x23, w9, sxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr x18, [x22, w10, sxtw] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - str d19, [x21, wzr, sxtw #3] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr q3, [sp, x5] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr q9, [x27, x6] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr q10, [x30, x7, lsl #4] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - str q11, [x29, x3, sxtx] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - str q12, [x28, xzr, sxtx] +# CHECK-NEXT: - - - - - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 - - str q13, [x27, x5, sxtx #4] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr q14, [x26, w6, uxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr q15, [x25, w7, uxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr q16, [x24, w8, uxtw #4] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldr q17, [x23, w9, sxtw] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - str q18, [x22, w10, sxtw] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldr q19, [x21, wzr, sxtw #4] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldp w3, w5, [sp] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - stp wzr, w9, [sp, #252] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldp w2, wzr, [sp, #-256] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldp w9, w10, [sp, #4] +# CHECK-NEXT: - - - - 1.00 1.00 1.00 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldpsw x9, x10, [sp, #4] +# CHECK-NEXT: - - - - 1.00 1.00 1.00 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldpsw x9, x10, [x2, #-256] +# CHECK-NEXT: - - - - 1.00 1.00 1.00 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldpsw x20, x30, [sp, #252] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldp x21, x29, [x2, #504] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldp x22, x23, [x3, #-512] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldp x24, x25, [x4, #8] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldp s29, s28, [sp, #252] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - stp s27, s26, [sp, #-256] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldp s1, s2, [x3, #44] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - stp d3, d5, [x9, #504] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - stp d7, d11, [x10, #-512] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldp d2, d3, [x30, #-8] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 1.00 1.00 - - stp q3, q5, [sp] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 1.00 1.00 - - stp q17, q19, [sp, #1008] +# CHECK-NEXT: - - - - 0.67 0.67 0.67 - - - - - - - - - - ldp q23, q29, [x1, #-1024] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldp w3, w5, [sp], #0 +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - stp wzr, w9, [sp], #252 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldp w2, wzr, [sp], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldp w9, w10, [sp], #4 +# CHECK-NEXT: - - - - 1.00 1.00 1.00 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldpsw x9, x10, [sp], #4 +# CHECK-NEXT: - - - - 1.00 1.00 1.00 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldpsw x9, x10, [x2], #-256 +# CHECK-NEXT: - - - - 1.00 1.00 1.00 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldpsw x20, x30, [sp], #252 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldp x21, x29, [x2], #504 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldp x22, x23, [x3], #-512 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldp x24, x25, [x4], #8 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldp s29, s28, [sp], #252 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - stp s27, s26, [sp], #-256 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldp s1, s2, [x3], #44 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - stp d3, d5, [x9], #504 +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - stp d7, d11, [x10], #-512 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldp d2, d3, [x30], #-8 +# CHECK-NEXT: - - - - - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 1.00 1.00 - - stp q3, q5, [sp], #0 +# CHECK-NEXT: - - - - - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 1.00 1.00 - - stp q17, q19, [sp], #1008 +# CHECK-NEXT: - - - - 0.67 0.67 0.67 0.50 0.50 0.50 0.50 0.50 0.50 - - - - ldp q23, q29, [x1], #-1024 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldp w3, w5, [sp, #0]! +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 - - - - stp wzr, w9, [sp, #252]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldp w2, wzr, [sp, #-256]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldp w9, w10, [sp, #4]! +# CHECK-NEXT: - - - - 1.00 1.00 1.00 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldpsw x9, x10, [sp, #4]! +# CHECK-NEXT: - - - - 1.00 1.00 1.00 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldpsw x9, x10, [x2, #-256]! +# CHECK-NEXT: - - - - 1.00 1.00 1.00 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldpsw x20, x30, [sp, #252]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldp x21, x29, [x2, #504]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldp x22, x23, [x3, #-512]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ldp x24, x25, [x4, #8]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldp s29, s28, [sp, #252]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - stp s27, s26, [sp, #-256]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldp s1, s2, [x3, #44]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - stp d3, d5, [x9, #504]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - stp d7, d11, [x10, #-512]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 - - - - ldp d2, d3, [x30, #-8]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 1.00 1.00 - - stp q3, q5, [sp, #0]! +# CHECK-NEXT: - - - - - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 1.00 1.00 - - stp q17, q19, [sp, #1008]! +# CHECK-NEXT: - - - - 0.67 0.67 0.67 0.50 0.50 0.50 0.50 0.50 0.50 - - - - ldp q23, q29, [x1, #-1024]! +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldnp w3, w5, [sp] +# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - - - - - - stnp wzr, w9, [sp, #252] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldnp w2, wzr, [sp, #-256] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldnp w9, w10, [sp, #4] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldnp x21, x29, [x2, #504] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldnp x22, x23, [x3, #-512] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldnp x24, x25, [x4, #8] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldnp s29, s28, [sp, #252] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - stnp s27, s26, [sp, #-256] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldnp s1, s2, [x3, #44] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - stnp d3, d5, [x9, #504] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - stnp d7, d11, [x10, #-512] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ldnp d2, d3, [x30, #-8] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 1.00 1.00 - - stnp q3, q5, [sp] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 1.00 1.00 - - stnp q17, q19, [sp, #1008] +# CHECK-NEXT: - - - - 0.67 0.67 0.67 - - - - - - - - - - ldnp q23, q29, [x1, #-1024] +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - mov w3, #983055 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - mov x10, #-6148914691236517206 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - and w12, w23, w21 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - and w16, w15, w1, lsl #1 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - and w9, w4, w10, lsl #31 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - and w3, w30, w11 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - and x3, x5, x7, lsl #63 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - and x5, x14, x19, asr #4 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - and w3, w17, w19, ror #31 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - and w0, w2, wzr, lsr #17 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - and w3, w30, w11, asr #2 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - and xzr, x4, x26 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - and w3, wzr, w20, ror #2 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - and x7, x20, xzr, asr #63 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - bic x13, x20, x14, lsl #47 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - bic w2, w7, w9 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - orr w2, w7, w0, asr #31 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - orr x8, x9, x10, lsl #12 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - orn x3, x5, x7, asr #2 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - orn w2, w5, w29 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - ands w7, wzr, w9, lsl #1 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - ands x3, x5, x20, ror #63 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - bics w3, w5, w7 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - bics x3, xzr, x3, lsl #1 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - tst w3, w7, lsl #31 +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - tst x2, x20, asr #2 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - mov x3, x6 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - mov x3, xzr +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - mov wzr, w2 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - mov w3, w5 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - movz w2, #0, lsl #16 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - mov w2, #-1235 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - mov x2, #5299989643264 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - mov x2, #0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - movk w3, #0 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - movz x4, #0, lsl #16 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - movk w5, #0, lsl #16 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - movz x6, #0, lsl #32 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - movk x7, #0, lsl #32 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - movz x8, #0, lsl #48 +# CHECK-NEXT: - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - movk x9, #0, lsl #48 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adr x2, #1600 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adrp x21, #6553600 +# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - adr x0, #262144 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - tbz x12, #62, #0 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - tbz x12, #62, #4 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - tbz x12, #62, #-32768 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - tbnz x12, #60, #32764 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - b #4 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - b #-4 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - b #134217724 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - br x20 +# CHECK-NEXT: 0.50 0.50 - - - - - - - 0.50 0.50 - - - - - - blr xzr +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - ret x10 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - ret +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - eret +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - drps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-forwarding.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-forwarding.s new file mode 100644 --- /dev/null +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-forwarding.s @@ -0,0 +1,1961 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 --instruction-info=0 --resource-pressure=0 --timeline --timeline-max-iterations=2 < %s | FileCheck %s + +# LLVM-MCA-BEGIN madd +mul x0, x0, x0 +madd x0, x1, x2, x0 +madd x0, x1, x2, x0 +madd x0, x0, x0, x0 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN smaddl +mul x0, x0, x0 +smaddl x0, w1, w2, x0 +smaddl x0, w1, w2, x0 +smaddl x0, w0, w0, x0 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN fmadd +fadd d0, d0, d0 +fmadd d0, d1, d2, d0 +fmul d0, d0, d0 +fmadd d0, d1, d2, d0 +fmadd d0, d1, d2, d0 +fmadd d0, d0, d1, d2 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN saba +mul v0.4s, v0.4s, v0.4s +saba v0.4s, v1.4s, v2.4s +saba v0.4s, v1.4s, v2.4s +saba v0.4s, v0.4s, v1.4s +# LLVM-MCA-END + +# LLVM-MCA-BEGIN sdot +mul v0.4s, v0.4s, v0.4s +sdot v0.4s, v1.16b, v2.16b +sdot v0.4s, v1.16b, v2.16b +sdot v0.4s, v0.16b, v1.16b +# LLVM-MCA-END + +# LLVM-MCA-BEGIN smmla +mul v0.4s, v0.4s, v0.4s +smmla v0.4s, v1.16b, v2.16b +smmla v0.4s, v1.16b, v2.16b +smmla v0.4s, v0.16b, v1.16b +# LLVM-MCA-END + +# LLVM-MCA-BEGIN mla +mul v0.4s, v0.4s, v0.4s +mla v0.4s, v1.4s, v2.4s +mla v0.4s, v1.4s, v2.4s +mla v0.4s, v0.4s, v1.4s +# LLVM-MCA-END + +# LLVM-MCA-BEGIN sqrdmlah +mul v0.4s, v0.4s, v0.4s +sqrdmlah v0.4s, v1.4s, v2.4s +sqrdmlah v0.4s, v1.4s, v2.4s +sqrdmlah v0.4s, v0.4s, v1.4s +# LLVM-MCA-END + +# LLVM-MCA-BEGIN smlal2 +mul v0.4s, v0.4s, v0.4s +smlal2 v0.4s, v1.8h, v2.8h +smlal2 v0.4s, v1.8h, v2.8h +smlal2 v0.4s, v0.8h, v1.8h +# LLVM-MCA-END + +# LLVM-MCA-BEGIN sadalp +mul v0.4s, v0.4s, v0.4s +sadalp v0.2d, v1.4s +sadalp v0.2d, v1.4s +sadalp v0.2d, v0.4s +# LLVM-MCA-END + +# LLVM-MCA-BEGIN ssra +mul v0.4s, v0.4s, v0.4s +ssra v0.2d, v1.2d, #1 +ssra v0.2d, v1.2d, #1 +ssra v0.2d, v0.2d, #1 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN fcmla +fmul v0.4s, v0.4s, v0.4s +fcmla v0.2d, v1.2d, v2.2d, #90 +fcmla v0.2d, v1.2d, v2.2d, #90 +fcmla v0.2d, v0.2d, v1.2d, #90 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN fmla +fmul v0.2d, v0.2d, v0.2d +fmla v0.2d, v1.2d, v2.2d +fadd v0.2d, v0.2d, v0.2d +fmla v0.2d, v1.2d, v2.2d +fmla v0.2d, v1.2d, v2.2d +fmla v0.2d, v0.2d, v1.2d +# LLVM-MCA-END + +# LLVM-MCA-BEGIN fmlal +fmul v0.2d, v0.2d, v0.2d +fmlal v0.4s, v1.4h, v2.4h +fadd v0.2d, v0.2d, v0.2d +fmlal v0.4s, v1.4h, v2.4h +fmlal v0.4s, v1.4h, v2.4h +fmlal v0.4s, v0.4h, v1.4h +# LLVM-MCA-END + +# LLVM-MCA-BEGIN bfdot +fmul v0.2d, v0.2d, v0.2d +bfdot v0.4s, v1.8h, v2.8h +bfdot v0.4s, v1.8h, v2.8h +bfdot v0.4s, v0.8h, v1.8h +# LLVM-MCA-END + +# LLVM-MCA-BEGIN bfmmla +fmul v0.2d, v0.2d, v0.2d +bfmmla v0.4s, v1.8h, v2.8h +bfmmla v0.4s, v1.8h, v2.8h +bfmmla v0.4s, v0.8h, v1.8h +# LLVM-MCA-END + +# LLVM-MCA-BEGIN bfmlalb +fmul v0.2d, v0.2d, v0.2d +bfmlalb v0.4s, v1.8h, v2.8h +bfmlalb v0.4s, v1.8h, v2.8h +bfmlalb v0.4s, v0.8h, v1.8h +# LLVM-MCA-END + +# LLVM-MCA-BEGIN crc32b +mul w0, w0, w0 +crc32b w0, w0, w1 +crc32b w0, w0, w1 +crc32b w0, w0, w0 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z saba +mul z0.d, z0.d, z0.d +saba z0.d, z1.d, z2.d +saba z0.d, z1.d, z2.d +saba z0.d, z0.d, z1.d +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z sadalp +mul z0.d, z0.d, z0.d +sadalp z0.d, p0/m, z1.s +sadalp z0.d, p0/m, z1.s +sadalp z0.d, p0/m, z0.s +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z ssra +mul z0.d, z0.d, z0.d +ssra z0.d, z1.d, #1 +ssra z0.d, z1.d, #1 +ssra z0.d, z0.d, #1 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z cdot.s +mul z0.d, z0.d, z0.d +cdot z0.s, z1.b, z2.b, #90 +cdot z0.s, z1.b, z2.b, #90 +cdot z0.s, z0.b, z1.b, #90 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z cdot.d +mul z0.d, z0.d, z0.d +cdot z0.d, z1.h, z2.h, #90 +cdot z0.d, z1.h, z2.h, #90 +cdot z0.d, z0.h, z1.h, #90 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z cmla.b +mul z0.d, z0.d, z0.d +cmla z0.b, z1.b, z2.b, #90 +cmla z0.b, z1.b, z2.b, #90 +cmla z0.b, z0.b, z1.b, #90 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z cmla.d +mul z0.d, z0.d, z0.d +cmla z0.d, z1.d, z2.d, #90 +cmla z0.d, z1.d, z2.d, #90 +cmla z0.d, z0.d, z1.d, #90 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z sdot.s +mul z0.d, z0.d, z0.d +sdot z0.s, z1.b, z2.b +sdot z0.s, z1.b, z2.b +sdot z0.s, z0.b, z1.b +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z sudot +mul z0.d, z0.d, z0.d +sdot z0.s, z1.b, z2.b[1] +sdot z0.s, z1.b, z2.b[1] +sdot z0.s, z0.b, z1.b[1] +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z sdot.d +mul z0.d, z0.d, z0.d +sdot z0.d, z1.h, z2.h +sdot z0.d, z1.h, z2.h +sdot z0.d, z0.h, z1.h +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z smmla +mul z0.s, z0.s, z0.s +smmla z0.s, z1.b, z2.b +smmla z0.s, z1.b, z2.b +smmla z0.s, z0.b, z1.b +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z mla.b +mul z0.d, z0.d, z0.d +mla z0.b, p0/m, z1.b, z2.b +mla z0.b, p0/m, z1.b, z2.b +mla z0.b, p0/m, z0.b, z1.b +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z mla.d +mul z0.d, z0.d, z0.d +mla z0.d, p0/m, z1.d, z2.d +mla z0.d, p0/m, z1.d, z2.d +mla z0.d, p0/m, z0.d, z1.d +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z smlalb +mul z0.d, z0.d, z0.d +smlalb z0.d, z1.s, z2.s +smlalb z0.d, z1.s, z2.s +smlalb z0.d, z0.s, z1.s +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z sqdmlalb +mul z0.d, z0.d, z0.d +sqdmlalb z0.d, z1.s, z2.s +sqdmlalb z0.d, z1.s, z2.s +sqdmlalb z0.d, z0.s, z1.s +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z sqrdmlah.b +mul z0.d, z0.d, z0.d +sqrdmlah z0.b, z1.b, z2.b +sqrdmlah z0.b, z1.b, z2.b +sqrdmlah z0.b, z0.b, z1.b +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z sqrdmlah.d +mul z0.d, z0.d, z0.d +sqrdmlah z0.d, z1.d, z2.d +sqrdmlah z0.d, z1.d, z2.d +sqrdmlah z0.d, z0.d, z1.d +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z fcmla ZPmZZ +fmul z0.d, z0.d, z0.d +fcmla z0.d, p0/m, z1.d, z2.d, 90 +fcmla z0.d, p0/m, z1.d, z2.d, 90 +fcmla z0.d, p0/m, z0.d, z1.d, 90 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z fcmla ZZZI +fmul z0.d, z0.d, z0.d +fcmla z0.s, z1.s, z2.s[1], 90 +fcmla z0.s, z1.s, z2.s[1], 90 +fcmla z0.s, z0.s, z1.s[1], 90 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z fmla ZPmZZ +fmul z0.d, z0.d, z0.d +fmla z0.d, p0/m, z1.d, z2.d +fmla z0.d, p0/m, z1.d, z2.d +fmla z0.d, p0/m, z0.d, z1.d +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z fmla ZZZI +fmul z0.d, z0.d, z0.d +fmla z0.d, z1.d, z2.d[1] +fmla z0.d, z1.d, z2.d[1] +fmla z0.d, z0.d, z1.d[1] +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z fmlalb ZZZ +fmul z0.d, z0.d, z0.d +fmlalb z0.s, z1.h, z2.h +fmlalb z0.s, z1.h, z2.h +fmlalb z0.s, z0.h, z1.h +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z bfdot +fmul z0.d, z0.d, z0.d +bfdot z0.s, z1.h, z2.h +bfdot z0.s, z1.h, z2.h +bfdot z0.s, z0.h, z1.h +# LLVM-MCA-END + +# LLVM-MCA-BEGIN Z bfmmla +fmul z0.d, z0.d, z0.d +bfmmla z0.s, z1.h, z2.h +bfmmla z0.s, z1.h, z2.h +bfmmla z0.s, z0.h, z1.h +# LLVM-MCA-END + +# LLVM-MCA-BEGIN bfmlalb +fmul z0.d, z0.d, z0.d +bfmlalb z0.s, z1.h, z2.h +bfmlalb z0.s, z1.h, z2.h +bfmlalb z0.s, z0.h, z1.h +# LLVM-MCA-END + +# CHECK: [0] Code Region - madd + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 703 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.57 +# CHECK-NEXT: IPC: 0.57 +# CHECK-NEXT: Block RThroughput: 3.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeER. . .. mul x0, x0, x0 +# CHECK-NEXT: [0,1] D==eeER . .. madd x0, x1, x2, x0 +# CHECK-NEXT: [0,2] D===eeER . .. madd x0, x1, x2, x0 +# CHECK-NEXT: [0,3] D=====eeER. .. madd x0, x0, x0, x0 +# CHECK-NEXT: [1,0] D=======eeER .. mul x0, x0, x0 +# CHECK-NEXT: [1,1] D=========eeER .. madd x0, x1, x2, x0 +# CHECK-NEXT: [1,2] D==========eeER.. madd x0, x1, x2, x0 +# CHECK-NEXT: [1,3] D============eeER madd x0, x0, x0, x0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 4.5 0.5 0.0 mul x0, x0, x0 +# CHECK-NEXT: 1. 2 6.5 0.0 0.0 madd x0, x1, x2, x0 +# CHECK-NEXT: 2. 2 7.5 0.0 0.0 madd x0, x1, x2, x0 +# CHECK-NEXT: 3. 2 9.5 0.0 0.0 madd x0, x0, x0, x0 +# CHECK-NEXT: 2 7.0 0.1 0.0 + +# CHECK: [1] Code Region - smaddl + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 703 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.57 +# CHECK-NEXT: IPC: 0.57 +# CHECK-NEXT: Block RThroughput: 3.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeER. . .. mul x0, x0, x0 +# CHECK-NEXT: [0,1] D==eeER . .. smaddl x0, w1, w2, x0 +# CHECK-NEXT: [0,2] D===eeER . .. smaddl x0, w1, w2, x0 +# CHECK-NEXT: [0,3] D=====eeER. .. smaddl x0, w0, w0, x0 +# CHECK-NEXT: [1,0] D=======eeER .. mul x0, x0, x0 +# CHECK-NEXT: [1,1] D=========eeER .. smaddl x0, w1, w2, x0 +# CHECK-NEXT: [1,2] D==========eeER.. smaddl x0, w1, w2, x0 +# CHECK-NEXT: [1,3] D============eeER smaddl x0, w0, w0, x0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 4.5 0.5 0.0 mul x0, x0, x0 +# CHECK-NEXT: 1. 2 6.5 0.0 0.0 smaddl x0, w1, w2, x0 +# CHECK-NEXT: 2. 2 7.5 0.0 0.0 smaddl x0, w1, w2, x0 +# CHECK-NEXT: 3. 2 9.5 0.0 0.0 smaddl x0, w0, w0, x0 +# CHECK-NEXT: 2 7.0 0.1 0.0 + +# CHECK: [2] Code Region - fmadd + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 600 +# CHECK-NEXT: Total Cycles: 1703 +# CHECK-NEXT: Total uOps: 600 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.35 +# CHECK-NEXT: IPC: 0.35 +# CHECK-NEXT: Block RThroughput: 1.5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0123456 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeER. . . . . . .. fadd d0, d0, d0 +# CHECK-NEXT: [0,1] D==eeeeER . . . . . .. fmadd d0, d1, d2, d0 +# CHECK-NEXT: [0,2] D======eeeER . . . . .. fmul d0, d0, d0 +# CHECK-NEXT: [0,3] D=======eeeeER . . . . .. fmadd d0, d1, d2, d0 +# CHECK-NEXT: [0,4] D=========eeeeER . . . .. fmadd d0, d1, d2, d0 +# CHECK-NEXT: [0,5] D=============eeeeER. . . .. fmadd d0, d0, d1, d2 +# CHECK-NEXT: [1,0] D=================eeER . . .. fadd d0, d0, d0 +# CHECK-NEXT: [1,1] D===================eeeeER . .. fmadd d0, d1, d2, d0 +# CHECK-NEXT: [1,2] D=======================eeeER . .. fmul d0, d0, d0 +# CHECK-NEXT: [1,3] D========================eeeeER .. fmadd d0, d1, d2, d0 +# CHECK-NEXT: [1,4] D==========================eeeeER .. fmadd d0, d1, d2, d0 +# CHECK-NEXT: [1,5] D==============================eeeeER fmadd d0, d0, d1, d2 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 9.5 0.5 0.0 fadd d0, d0, d0 +# CHECK-NEXT: 1. 2 11.5 0.0 0.0 fmadd d0, d1, d2, d0 +# CHECK-NEXT: 2. 2 15.5 0.0 0.0 fmul d0, d0, d0 +# CHECK-NEXT: 3. 2 16.5 0.0 0.0 fmadd d0, d1, d2, d0 +# CHECK-NEXT: 4. 2 18.5 0.0 0.0 fmadd d0, d1, d2, d0 +# CHECK-NEXT: 5. 2 22.5 0.0 0.0 fmadd d0, d0, d1, d2 +# CHECK-NEXT: 2 15.7 0.1 0.0 + +# CHECK: [3] Code Region - saba + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1303 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.31 +# CHECK-NEXT: IPC: 0.31 +# CHECK-NEXT: Block RThroughput: 1.5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 012345678 + +# CHECK: [0,0] DeeeeER . . . . . mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [0,1] D====eeeeER . . . . saba v0.4s, v1.4s, v2.4s +# CHECK-NEXT: [0,2] D=====eeeeER . . . . saba v0.4s, v1.4s, v2.4s +# CHECK-NEXT: [0,3] D=========eeeeER . . . saba v0.4s, v0.4s, v1.4s +# CHECK-NEXT: [1,0] D=============eeeeER. . . mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [1,1] D=================eeeeER . . saba v0.4s, v1.4s, v2.4s +# CHECK-NEXT: [1,2] D==================eeeeER. . saba v0.4s, v1.4s, v2.4s +# CHECK-NEXT: [1,3] D======================eeeeER saba v0.4s, v0.4s, v1.4s + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 7.5 0.5 0.0 mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1. 2 11.5 0.0 0.0 saba v0.4s, v1.4s, v2.4s +# CHECK-NEXT: 2. 2 12.5 0.0 0.0 saba v0.4s, v1.4s, v2.4s +# CHECK-NEXT: 3. 2 16.5 0.0 0.0 saba v0.4s, v0.4s, v1.4s +# CHECK-NEXT: 2 12.0 0.1 0.0 + +# CHECK: [4] Code Region - sdot + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1103 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.36 +# CHECK-NEXT: IPC: 0.36 +# CHECK-NEXT: Block RThroughput: 0.8 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 01234 + +# CHECK: [0,0] DeeeeER . . . . mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [0,1] D====eeeER. . . . sdot v0.4s, v1.16b, v2.16b +# CHECK-NEXT: [0,2] D=====eeeER . . . sdot v0.4s, v1.16b, v2.16b +# CHECK-NEXT: [0,3] D========eeeER . . . sdot v0.4s, v0.16b, v1.16b +# CHECK-NEXT: [1,0] D===========eeeeER . . mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [1,1] D===============eeeER . sdot v0.4s, v1.16b, v2.16b +# CHECK-NEXT: [1,2] D================eeeER . sdot v0.4s, v1.16b, v2.16b +# CHECK-NEXT: [1,3] D===================eeeER sdot v0.4s, v0.16b, v1.16b + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 6.5 0.5 0.0 mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1. 2 10.5 0.0 0.0 sdot v0.4s, v1.16b, v2.16b +# CHECK-NEXT: 2. 2 11.5 0.0 0.0 sdot v0.4s, v1.16b, v2.16b +# CHECK-NEXT: 3. 2 14.5 0.0 0.0 sdot v0.4s, v0.16b, v1.16b +# CHECK-NEXT: 2 10.8 0.1 0.0 + +# CHECK: [5] Code Region - smmla + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1103 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.36 +# CHECK-NEXT: IPC: 0.36 +# CHECK-NEXT: Block RThroughput: 0.8 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 01234 + +# CHECK: [0,0] DeeeeER . . . . mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [0,1] D====eeeER. . . . smmla v0.4s, v1.16b, v2.16b +# CHECK-NEXT: [0,2] D=====eeeER . . . smmla v0.4s, v1.16b, v2.16b +# CHECK-NEXT: [0,3] D========eeeER . . . smmla v0.4s, v0.16b, v1.16b +# CHECK-NEXT: [1,0] D===========eeeeER . . mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [1,1] D===============eeeER . smmla v0.4s, v1.16b, v2.16b +# CHECK-NEXT: [1,2] D================eeeER . smmla v0.4s, v1.16b, v2.16b +# CHECK-NEXT: [1,3] D===================eeeER smmla v0.4s, v0.16b, v1.16b + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 6.5 0.5 0.0 mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1. 2 10.5 0.0 0.0 smmla v0.4s, v1.16b, v2.16b +# CHECK-NEXT: 2. 2 11.5 0.0 0.0 smmla v0.4s, v1.16b, v2.16b +# CHECK-NEXT: 3. 2 14.5 0.0 0.0 smmla v0.4s, v0.16b, v1.16b +# CHECK-NEXT: 2 10.8 0.1 0.0 + +# CHECK: [6] Code Region - mla + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1303 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.31 +# CHECK-NEXT: IPC: 0.31 +# CHECK-NEXT: Block RThroughput: 2.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 012345678 + +# CHECK: [0,0] DeeeeER . . . . . mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [0,1] D====eeeeER . . . . mla v0.4s, v1.4s, v2.4s +# CHECK-NEXT: [0,2] D=====eeeeER . . . . mla v0.4s, v1.4s, v2.4s +# CHECK-NEXT: [0,3] D=========eeeeER . . . mla v0.4s, v0.4s, v1.4s +# CHECK-NEXT: [1,0] D=============eeeeER. . . mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [1,1] D=================eeeeER . . mla v0.4s, v1.4s, v2.4s +# CHECK-NEXT: [1,2] D==================eeeeER. . mla v0.4s, v1.4s, v2.4s +# CHECK-NEXT: [1,3] D======================eeeeER mla v0.4s, v0.4s, v1.4s + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 7.5 0.5 0.0 mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1. 2 11.5 0.0 0.0 mla v0.4s, v1.4s, v2.4s +# CHECK-NEXT: 2. 2 12.5 0.0 0.0 mla v0.4s, v1.4s, v2.4s +# CHECK-NEXT: 3. 2 16.5 0.0 0.0 mla v0.4s, v0.4s, v1.4s +# CHECK-NEXT: 2 12.0 0.1 0.0 + +# CHECK: [7] Code Region - sqrdmlah + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1403 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.29 +# CHECK-NEXT: IPC: 0.29 +# CHECK-NEXT: Block RThroughput: 3.5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeER . . . . . mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [0,1] D====eeeeER . . . . sqrdmlah v0.4s, v1.4s, v2.4s +# CHECK-NEXT: [0,2] D======eeeeER . . . . sqrdmlah v0.4s, v1.4s, v2.4s +# CHECK-NEXT: [0,3] D==========eeeeER . . . sqrdmlah v0.4s, v0.4s, v1.4s +# CHECK-NEXT: [1,0] D==============eeeeER . . mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [1,1] D==================eeeeER. . sqrdmlah v0.4s, v1.4s, v2.4s +# CHECK-NEXT: [1,2] D====================eeeeER . sqrdmlah v0.4s, v1.4s, v2.4s +# CHECK-NEXT: [1,3] D========================eeeeER sqrdmlah v0.4s, v0.4s, v1.4s + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 8.0 0.5 0.0 mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1. 2 12.0 0.0 0.0 sqrdmlah v0.4s, v1.4s, v2.4s +# CHECK-NEXT: 2. 2 14.0 0.0 0.0 sqrdmlah v0.4s, v1.4s, v2.4s +# CHECK-NEXT: 3. 2 18.0 0.0 0.0 sqrdmlah v0.4s, v0.4s, v1.4s +# CHECK-NEXT: 2 13.0 0.1 0.0 + +# CHECK: [8] Code Region - smlal2 + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1303 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.31 +# CHECK-NEXT: IPC: 0.31 +# CHECK-NEXT: Block RThroughput: 2.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 012345678 + +# CHECK: [0,0] DeeeeER . . . . . mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [0,1] D====eeeeER . . . . smlal2 v0.4s, v1.8h, v2.8h +# CHECK-NEXT: [0,2] D=====eeeeER . . . . smlal2 v0.4s, v1.8h, v2.8h +# CHECK-NEXT: [0,3] D=========eeeeER . . . smlal2 v0.4s, v0.8h, v1.8h +# CHECK-NEXT: [1,0] D=============eeeeER. . . mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [1,1] D=================eeeeER . . smlal2 v0.4s, v1.8h, v2.8h +# CHECK-NEXT: [1,2] D==================eeeeER. . smlal2 v0.4s, v1.8h, v2.8h +# CHECK-NEXT: [1,3] D======================eeeeER smlal2 v0.4s, v0.8h, v1.8h + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 7.5 0.5 0.0 mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1. 2 11.5 0.0 0.0 smlal2 v0.4s, v1.8h, v2.8h +# CHECK-NEXT: 2. 2 12.5 0.0 0.0 smlal2 v0.4s, v1.8h, v2.8h +# CHECK-NEXT: 3. 2 16.5 0.0 0.0 smlal2 v0.4s, v0.8h, v1.8h +# CHECK-NEXT: 2 12.0 0.1 0.0 + +# CHECK: [9] Code Region - sadalp + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1303 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.31 +# CHECK-NEXT: IPC: 0.31 +# CHECK-NEXT: Block RThroughput: 1.5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 012345678 + +# CHECK: [0,0] DeeeeER . . . . . mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [0,1] D====eeeeER . . . . sadalp v0.2d, v1.4s +# CHECK-NEXT: [0,2] D=====eeeeER . . . . sadalp v0.2d, v1.4s +# CHECK-NEXT: [0,3] D=========eeeeER . . . sadalp v0.2d, v0.4s +# CHECK-NEXT: [1,0] D=============eeeeER. . . mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [1,1] D=================eeeeER . . sadalp v0.2d, v1.4s +# CHECK-NEXT: [1,2] D==================eeeeER. . sadalp v0.2d, v1.4s +# CHECK-NEXT: [1,3] D======================eeeeER sadalp v0.2d, v0.4s + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 7.5 0.5 0.0 mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1. 2 11.5 0.0 0.0 sadalp v0.2d, v1.4s +# CHECK-NEXT: 2. 2 12.5 0.0 0.0 sadalp v0.2d, v1.4s +# CHECK-NEXT: 3. 2 16.5 0.0 0.0 sadalp v0.2d, v0.4s +# CHECK-NEXT: 2 12.0 0.1 0.0 + +# CHECK: [10] Code Region - ssra + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1303 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.31 +# CHECK-NEXT: IPC: 0.31 +# CHECK-NEXT: Block RThroughput: 1.5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 012345678 + +# CHECK: [0,0] DeeeeER . . . . . mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [0,1] D====eeeeER . . . . ssra v0.2d, v1.2d, #1 +# CHECK-NEXT: [0,2] D=====eeeeER . . . . ssra v0.2d, v1.2d, #1 +# CHECK-NEXT: [0,3] D=========eeeeER . . . ssra v0.2d, v0.2d, #1 +# CHECK-NEXT: [1,0] D=============eeeeER. . . mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [1,1] D=================eeeeER . . ssra v0.2d, v1.2d, #1 +# CHECK-NEXT: [1,2] D==================eeeeER. . ssra v0.2d, v1.2d, #1 +# CHECK-NEXT: [1,3] D======================eeeeER ssra v0.2d, v0.2d, #1 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 7.5 0.5 0.0 mul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1. 2 11.5 0.0 0.0 ssra v0.2d, v1.2d, #1 +# CHECK-NEXT: 2. 2 12.5 0.0 0.0 ssra v0.2d, v1.2d, #1 +# CHECK-NEXT: 3. 2 16.5 0.0 0.0 ssra v0.2d, v0.2d, #1 +# CHECK-NEXT: 2 12.0 0.1 0.0 + +# CHECK: [11] Code Region - fcmla + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1303 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.31 +# CHECK-NEXT: IPC: 0.31 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 012345678 + +# CHECK: [0,0] DeeeER . . . . . fmul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [0,1] D===eeeeER. . . . . fcmla v0.2d, v1.2d, v2.2d, #90 +# CHECK-NEXT: [0,2] D=====eeeeER . . . . fcmla v0.2d, v1.2d, v2.2d, #90 +# CHECK-NEXT: [0,3] D=========eeeeER . . . fcmla v0.2d, v0.2d, v1.2d, #90 +# CHECK-NEXT: [1,0] D=============eeeER . . . fmul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: [1,1] D================eeeeER . . fcmla v0.2d, v1.2d, v2.2d, #90 +# CHECK-NEXT: [1,2] D==================eeeeER. . fcmla v0.2d, v1.2d, v2.2d, #90 +# CHECK-NEXT: [1,3] D======================eeeeER fcmla v0.2d, v0.2d, v1.2d, #90 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 7.5 0.5 0.0 fmul v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1. 2 10.5 0.0 0.0 fcmla v0.2d, v1.2d, v2.2d, #90 +# CHECK-NEXT: 2. 2 12.5 0.0 0.0 fcmla v0.2d, v1.2d, v2.2d, #90 +# CHECK-NEXT: 3. 2 16.5 0.0 0.0 fcmla v0.2d, v0.2d, v1.2d, #90 +# CHECK-NEXT: 2 11.8 0.1 0.0 + +# CHECK: [12] Code Region - fmla + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 600 +# CHECK-NEXT: Total Cycles: 1703 +# CHECK-NEXT: Total uOps: 600 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.35 +# CHECK-NEXT: IPC: 0.35 +# CHECK-NEXT: Block RThroughput: 1.5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0123456 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeER . . . . . .. fmul v0.2d, v0.2d, v0.2d +# CHECK-NEXT: [0,1] D=eeeeER . . . . . .. fmla v0.2d, v1.2d, v2.2d +# CHECK-NEXT: [0,2] D=====eeER. . . . . .. fadd v0.2d, v0.2d, v0.2d +# CHECK-NEXT: [0,3] D=======eeeeER . . . . .. fmla v0.2d, v1.2d, v2.2d +# CHECK-NEXT: [0,4] D=========eeeeER . . . .. fmla v0.2d, v1.2d, v2.2d +# CHECK-NEXT: [0,5] D=============eeeeER. . . .. fmla v0.2d, v0.2d, v1.2d +# CHECK-NEXT: [1,0] D=================eeeER . . .. fmul v0.2d, v0.2d, v0.2d +# CHECK-NEXT: [1,1] D==================eeeeER. . .. fmla v0.2d, v1.2d, v2.2d +# CHECK-NEXT: [1,2] D======================eeER . .. fadd v0.2d, v0.2d, v0.2d +# CHECK-NEXT: [1,3] D========================eeeeER .. fmla v0.2d, v1.2d, v2.2d +# CHECK-NEXT: [1,4] D==========================eeeeER .. fmla v0.2d, v1.2d, v2.2d +# CHECK-NEXT: [1,5] D==============================eeeeER fmla v0.2d, v0.2d, v1.2d + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 9.5 0.5 0.0 fmul v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1. 2 10.5 0.0 0.0 fmla v0.2d, v1.2d, v2.2d +# CHECK-NEXT: 2. 2 14.5 0.0 0.0 fadd v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 3. 2 16.5 0.0 0.0 fmla v0.2d, v1.2d, v2.2d +# CHECK-NEXT: 4. 2 18.5 0.0 0.0 fmla v0.2d, v1.2d, v2.2d +# CHECK-NEXT: 5. 2 22.5 0.0 0.0 fmla v0.2d, v0.2d, v1.2d +# CHECK-NEXT: 2 15.3 0.1 0.0 + +# CHECK: [13] Code Region - fmlal + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 600 +# CHECK-NEXT: Total Cycles: 1903 +# CHECK-NEXT: Total uOps: 600 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.32 +# CHECK-NEXT: IPC: 0.32 +# CHECK-NEXT: Block RThroughput: 1.5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 0 + +# CHECK: [0,0] DeeeER . . . . . . . fmul v0.2d, v0.2d, v0.2d +# CHECK-NEXT: [0,1] D===eeeeER. . . . . . . fmlal v0.4s, v1.4h, v2.4h +# CHECK-NEXT: [0,2] D=======eeER . . . . . . fadd v0.2d, v0.2d, v0.2d +# CHECK-NEXT: [0,3] D=========eeeeER . . . . . fmlal v0.4s, v1.4h, v2.4h +# CHECK-NEXT: [0,4] D===========eeeeER . . . . . fmlal v0.4s, v1.4h, v2.4h +# CHECK-NEXT: [0,5] D===============eeeeER . . . . fmlal v0.4s, v0.4h, v1.4h +# CHECK-NEXT: [1,0] D===================eeeER. . . . fmul v0.2d, v0.2d, v0.2d +# CHECK-NEXT: [1,1] D======================eeeeER . . . fmlal v0.4s, v1.4h, v2.4h +# CHECK-NEXT: [1,2] D==========================eeER . . fadd v0.2d, v0.2d, v0.2d +# CHECK-NEXT: [1,3] D============================eeeeER. . fmlal v0.4s, v1.4h, v2.4h +# CHECK-NEXT: [1,4] D==============================eeeeER . fmlal v0.4s, v1.4h, v2.4h +# CHECK-NEXT: [1,5] D==================================eeeeER fmlal v0.4s, v0.4h, v1.4h + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 10.5 0.5 0.0 fmul v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1. 2 13.5 0.0 0.0 fmlal v0.4s, v1.4h, v2.4h +# CHECK-NEXT: 2. 2 17.5 0.0 0.0 fadd v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 3. 2 19.5 0.0 0.0 fmlal v0.4s, v1.4h, v2.4h +# CHECK-NEXT: 4. 2 21.5 0.0 0.0 fmlal v0.4s, v1.4h, v2.4h +# CHECK-NEXT: 5. 2 25.5 0.0 0.0 fmlal v0.4s, v0.4h, v1.4h +# CHECK-NEXT: 2 18.0 0.1 0.0 + +# CHECK: [14] Code Region - bfdot + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1603 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.25 +# CHECK-NEXT: IPC: 0.25 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 01234 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeER . . . . . . fmul v0.2d, v0.2d, v0.2d +# CHECK-NEXT: [0,1] D===eeeeeER . . . . . bfdot v0.4s, v1.8h, v2.8h +# CHECK-NEXT: [0,2] D======eeeeeER . . . . . bfdot v0.4s, v1.8h, v2.8h +# CHECK-NEXT: [0,3] D===========eeeeeER . . . . bfdot v0.4s, v0.8h, v1.8h +# CHECK-NEXT: [1,0] D================eeeER . . . fmul v0.2d, v0.2d, v0.2d +# CHECK-NEXT: [1,1] D===================eeeeeER . . bfdot v0.4s, v1.8h, v2.8h +# CHECK-NEXT: [1,2] D======================eeeeeER. . bfdot v0.4s, v1.8h, v2.8h +# CHECK-NEXT: [1,3] D===========================eeeeeER bfdot v0.4s, v0.8h, v1.8h + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 9.0 0.5 0.0 fmul v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1. 2 12.0 0.0 0.0 bfdot v0.4s, v1.8h, v2.8h +# CHECK-NEXT: 2. 2 15.0 0.0 0.0 bfdot v0.4s, v1.8h, v2.8h +# CHECK-NEXT: 3. 2 20.0 0.0 0.0 bfdot v0.4s, v0.8h, v1.8h +# CHECK-NEXT: 2 14.0 0.1 0.0 + +# CHECK: [15] Code Region - bfmmla + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1903 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.21 +# CHECK-NEXT: IPC: 0.21 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 0 + +# CHECK: [0,0] DeeeER . . . . . . . fmul v0.2d, v0.2d, v0.2d +# CHECK-NEXT: [0,1] D===eeeeeeER . . . . . . bfmmla v0.4s, v1.8h, v2.8h +# CHECK-NEXT: [0,2] D=======eeeeeeER . . . . . bfmmla v0.4s, v1.8h, v2.8h +# CHECK-NEXT: [0,3] D=============eeeeeeER . . . . bfmmla v0.4s, v0.8h, v1.8h +# CHECK-NEXT: [1,0] D===================eeeER. . . . fmul v0.2d, v0.2d, v0.2d +# CHECK-NEXT: [1,1] D======================eeeeeeER . . bfmmla v0.4s, v1.8h, v2.8h +# CHECK-NEXT: [1,2] D==========================eeeeeeER. . bfmmla v0.4s, v1.8h, v2.8h +# CHECK-NEXT: [1,3] D================================eeeeeeER bfmmla v0.4s, v0.8h, v1.8h + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 10.5 0.5 0.0 fmul v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1. 2 13.5 0.0 0.0 bfmmla v0.4s, v1.8h, v2.8h +# CHECK-NEXT: 2. 2 17.5 0.0 0.0 bfmmla v0.4s, v1.8h, v2.8h +# CHECK-NEXT: 3. 2 23.5 0.0 0.0 bfmmla v0.4s, v0.8h, v1.8h +# CHECK-NEXT: 2 16.3 0.1 0.0 + +# CHECK: [16] Code Region - bfmlalb + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1503 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.27 +# CHECK-NEXT: IPC: 0.27 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 012 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeER . . . . . . fmul v0.2d, v0.2d, v0.2d +# CHECK-NEXT: [0,1] D===eeeeeER . . . . . bfmlalb v0.4s, v1.8h, v2.8h +# CHECK-NEXT: [0,2] D=====eeeeeER . . . . . bfmlalb v0.4s, v1.8h, v2.8h +# CHECK-NEXT: [0,3] D==========eeeeeER . . . . bfmlalb v0.4s, v0.8h, v1.8h +# CHECK-NEXT: [1,0] D===============eeeER . . . fmul v0.2d, v0.2d, v0.2d +# CHECK-NEXT: [1,1] D==================eeeeeER . . bfmlalb v0.4s, v1.8h, v2.8h +# CHECK-NEXT: [1,2] D====================eeeeeER . . bfmlalb v0.4s, v1.8h, v2.8h +# CHECK-NEXT: [1,3] D=========================eeeeeER bfmlalb v0.4s, v0.8h, v1.8h + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 8.5 0.5 0.0 fmul v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1. 2 11.5 0.0 0.0 bfmlalb v0.4s, v1.8h, v2.8h +# CHECK-NEXT: 2. 2 13.5 0.0 0.0 bfmlalb v0.4s, v1.8h, v2.8h +# CHECK-NEXT: 3. 2 18.5 0.0 0.0 bfmlalb v0.4s, v0.8h, v1.8h +# CHECK-NEXT: 2 13.0 0.1 0.0 + +# CHECK: [17] Code Region - crc32b + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 703 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.57 +# CHECK-NEXT: IPC: 0.57 +# CHECK-NEXT: Block RThroughput: 3.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeER. . .. mul w0, w0, w0 +# CHECK-NEXT: [0,1] D==eeER . .. crc32b w0, w0, w1 +# CHECK-NEXT: [0,2] D===eeER . .. crc32b w0, w0, w1 +# CHECK-NEXT: [0,3] D=====eeER. .. crc32b w0, w0, w0 +# CHECK-NEXT: [1,0] D=======eeER .. mul w0, w0, w0 +# CHECK-NEXT: [1,1] D=========eeER .. crc32b w0, w0, w1 +# CHECK-NEXT: [1,2] D==========eeER.. crc32b w0, w0, w1 +# CHECK-NEXT: [1,3] D============eeER crc32b w0, w0, w0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 4.5 0.5 0.0 mul w0, w0, w0 +# CHECK-NEXT: 1. 2 6.5 0.0 0.0 crc32b w0, w0, w1 +# CHECK-NEXT: 2. 2 7.5 0.0 0.0 crc32b w0, w0, w1 +# CHECK-NEXT: 3. 2 9.5 0.0 0.0 crc32b w0, w0, w0 +# CHECK-NEXT: 2 7.0 0.1 0.0 + +# CHECK: [18] Code Region - Z saba + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1403 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.36 +# CHECK-NEXT: IPC: 0.29 +# CHECK-NEXT: Block RThroughput: 1.5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeER . . . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D=====eeeeER . . . . saba z0.d, z1.d, z2.d +# CHECK-NEXT: [0,2] D======eeeeER . . . . saba z0.d, z1.d, z2.d +# CHECK-NEXT: [0,3] D==========eeeeER . . . saba z0.d, z0.d, z1.d +# CHECK-NEXT: [1,0] D==============eeeeeER . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D===================eeeeER . saba z0.d, z1.d, z2.d +# CHECK-NEXT: [1,2] D====================eeeeER . saba z0.d, z1.d, z2.d +# CHECK-NEXT: [1,3] D========================eeeeER saba z0.d, z0.d, z1.d + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 8.0 0.5 0.0 mul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 13.0 0.0 0.0 saba z0.d, z1.d, z2.d +# CHECK-NEXT: 2. 2 14.0 0.0 0.0 saba z0.d, z1.d, z2.d +# CHECK-NEXT: 3. 2 18.0 0.0 0.0 saba z0.d, z0.d, z1.d +# CHECK-NEXT: 2 13.3 0.1 0.0 + +# CHECK: [19] Code Region - Z sadalp + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1403 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.36 +# CHECK-NEXT: IPC: 0.29 +# CHECK-NEXT: Block RThroughput: 1.5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeER . . . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D=====eeeeER . . . . sadalp z0.d, p0/m, z1.s +# CHECK-NEXT: [0,2] D======eeeeER . . . . sadalp z0.d, p0/m, z1.s +# CHECK-NEXT: [0,3] D==========eeeeER . . . sadalp z0.d, p0/m, z0.s +# CHECK-NEXT: [1,0] D==============eeeeeER . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D===================eeeeER . sadalp z0.d, p0/m, z1.s +# CHECK-NEXT: [1,2] D====================eeeeER . sadalp z0.d, p0/m, z1.s +# CHECK-NEXT: [1,3] D========================eeeeER sadalp z0.d, p0/m, z0.s + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 8.0 0.5 0.0 mul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 13.0 0.0 0.0 sadalp z0.d, p0/m, z1.s +# CHECK-NEXT: 2. 2 14.0 0.0 0.0 sadalp z0.d, p0/m, z1.s +# CHECK-NEXT: 3. 2 18.0 0.0 0.0 sadalp z0.d, p0/m, z0.s +# CHECK-NEXT: 2 13.3 0.1 0.0 + +# CHECK: [20] Code Region - Z ssra + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1403 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.36 +# CHECK-NEXT: IPC: 0.29 +# CHECK-NEXT: Block RThroughput: 1.5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeER . . . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D=====eeeeER . . . . ssra z0.d, z1.d, #1 +# CHECK-NEXT: [0,2] D======eeeeER . . . . ssra z0.d, z1.d, #1 +# CHECK-NEXT: [0,3] D==========eeeeER . . . ssra z0.d, z0.d, #1 +# CHECK-NEXT: [1,0] D==============eeeeeER . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D===================eeeeER . ssra z0.d, z1.d, #1 +# CHECK-NEXT: [1,2] D====================eeeeER . ssra z0.d, z1.d, #1 +# CHECK-NEXT: [1,3] D========================eeeeER ssra z0.d, z0.d, #1 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 8.0 0.5 0.0 mul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 13.0 0.0 0.0 ssra z0.d, z1.d, #1 +# CHECK-NEXT: 2. 2 14.0 0.0 0.0 ssra z0.d, z1.d, #1 +# CHECK-NEXT: 3. 2 18.0 0.0 0.0 ssra z0.d, z0.d, #1 +# CHECK-NEXT: 2 13.3 0.1 0.0 + +# CHECK: [21] Code Region - Z cdot.s + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1203 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.42 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 0123456 + +# CHECK: [0,0] DeeeeeER . . . .. mul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D=====eeeER . . .. cdot z0.s, z1.b, z2.b, #90 +# CHECK-NEXT: [0,2] D======eeeER . . .. cdot z0.s, z1.b, z2.b, #90 +# CHECK-NEXT: [0,3] D=========eeeER. . .. cdot z0.s, z0.b, z1.b, #90 +# CHECK-NEXT: [1,0] D============eeeeeER. .. mul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D=================eeeER .. cdot z0.s, z1.b, z2.b, #90 +# CHECK-NEXT: [1,2] D==================eeeER .. cdot z0.s, z1.b, z2.b, #90 +# CHECK-NEXT: [1,3] D=====================eeeER cdot z0.s, z0.b, z1.b, #90 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 7.0 0.5 0.0 mul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 12.0 0.0 0.0 cdot z0.s, z1.b, z2.b, #90 +# CHECK-NEXT: 2. 2 13.0 0.0 0.0 cdot z0.s, z1.b, z2.b, #90 +# CHECK-NEXT: 3. 2 16.0 0.0 0.0 cdot z0.s, z0.b, z1.b, #90 +# CHECK-NEXT: 2 12.0 0.1 0.0 + +# CHECK: [22] Code Region - Z cdot.d + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1403 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.36 +# CHECK-NEXT: IPC: 0.29 +# CHECK-NEXT: Block RThroughput: 2.5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeER . . . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D=====eeeeER . . . . cdot z0.d, z1.h, z2.h, #90 +# CHECK-NEXT: [0,2] D======eeeeER . . . . cdot z0.d, z1.h, z2.h, #90 +# CHECK-NEXT: [0,3] D==========eeeeER . . . cdot z0.d, z0.h, z1.h, #90 +# CHECK-NEXT: [1,0] D==============eeeeeER . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D===================eeeeER . cdot z0.d, z1.h, z2.h, #90 +# CHECK-NEXT: [1,2] D====================eeeeER . cdot z0.d, z1.h, z2.h, #90 +# CHECK-NEXT: [1,3] D========================eeeeER cdot z0.d, z0.h, z1.h, #90 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 8.0 0.5 0.0 mul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 13.0 0.0 0.0 cdot z0.d, z1.h, z2.h, #90 +# CHECK-NEXT: 2. 2 14.0 0.0 0.0 cdot z0.d, z1.h, z2.h, #90 +# CHECK-NEXT: 3. 2 18.0 0.0 0.0 cdot z0.d, z0.h, z1.h, #90 +# CHECK-NEXT: 2 13.3 0.1 0.0 + +# CHECK: [23] Code Region - Z cmla.b + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1403 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.36 +# CHECK-NEXT: IPC: 0.29 +# CHECK-NEXT: Block RThroughput: 2.5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeER . . . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D=====eeeeER . . . . cmla z0.b, z1.b, z2.b, #90 +# CHECK-NEXT: [0,2] D======eeeeER . . . . cmla z0.b, z1.b, z2.b, #90 +# CHECK-NEXT: [0,3] D==========eeeeER . . . cmla z0.b, z0.b, z1.b, #90 +# CHECK-NEXT: [1,0] D==============eeeeeER . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D===================eeeeER . cmla z0.b, z1.b, z2.b, #90 +# CHECK-NEXT: [1,2] D====================eeeeER . cmla z0.b, z1.b, z2.b, #90 +# CHECK-NEXT: [1,3] D========================eeeeER cmla z0.b, z0.b, z1.b, #90 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 8.0 0.5 0.0 mul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 13.0 0.0 0.0 cmla z0.b, z1.b, z2.b, #90 +# CHECK-NEXT: 2. 2 14.0 0.0 0.0 cmla z0.b, z1.b, z2.b, #90 +# CHECK-NEXT: 3. 2 18.0 0.0 0.0 cmla z0.b, z0.b, z1.b, #90 +# CHECK-NEXT: 2 13.3 0.1 0.0 + +# CHECK: [24] Code Region - Z cmla.d + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1803 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.28 +# CHECK-NEXT: IPC: 0.22 +# CHECK-NEXT: Block RThroughput: 4.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 012345678 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeER . . . . . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D=====eeeeeER . . . . . . cmla z0.d, z1.d, z2.d, #90 +# CHECK-NEXT: [0,2] D========eeeeeER . . . . . cmla z0.d, z1.d, z2.d, #90 +# CHECK-NEXT: [0,3] D=============eeeeeER . . . . cmla z0.d, z0.d, z1.d, #90 +# CHECK-NEXT: [1,0] D==================eeeeeER . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D=======================eeeeeER . . cmla z0.d, z1.d, z2.d, #90 +# CHECK-NEXT: [1,2] D==========================eeeeeER . . cmla z0.d, z1.d, z2.d, #90 +# CHECK-NEXT: [1,3] D===============================eeeeeER cmla z0.d, z0.d, z1.d, #90 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 10.0 0.5 0.0 mul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 15.0 0.0 0.0 cmla z0.d, z1.d, z2.d, #90 +# CHECK-NEXT: 2. 2 18.0 0.0 0.0 cmla z0.d, z1.d, z2.d, #90 +# CHECK-NEXT: 3. 2 23.0 0.0 0.0 cmla z0.d, z0.d, z1.d, #90 +# CHECK-NEXT: 2 16.5 0.1 0.0 + +# CHECK: [25] Code Region - Z sdot.s + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1203 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.42 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 0123456 + +# CHECK: [0,0] DeeeeeER . . . .. mul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D=====eeeER . . .. sdot z0.s, z1.b, z2.b +# CHECK-NEXT: [0,2] D======eeeER . . .. sdot z0.s, z1.b, z2.b +# CHECK-NEXT: [0,3] D=========eeeER. . .. sdot z0.s, z0.b, z1.b +# CHECK-NEXT: [1,0] D============eeeeeER. .. mul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D=================eeeER .. sdot z0.s, z1.b, z2.b +# CHECK-NEXT: [1,2] D==================eeeER .. sdot z0.s, z1.b, z2.b +# CHECK-NEXT: [1,3] D=====================eeeER sdot z0.s, z0.b, z1.b + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 7.0 0.5 0.0 mul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 12.0 0.0 0.0 sdot z0.s, z1.b, z2.b +# CHECK-NEXT: 2. 2 13.0 0.0 0.0 sdot z0.s, z1.b, z2.b +# CHECK-NEXT: 3. 2 16.0 0.0 0.0 sdot z0.s, z0.b, z1.b +# CHECK-NEXT: 2 12.0 0.1 0.0 + +# CHECK: [26] Code Region - Z sudot + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1203 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.42 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 0123456 + +# CHECK: [0,0] DeeeeeER . . . .. mul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D=====eeeER . . .. sdot z0.s, z1.b, z2.b[1] +# CHECK-NEXT: [0,2] D======eeeER . . .. sdot z0.s, z1.b, z2.b[1] +# CHECK-NEXT: [0,3] D=========eeeER. . .. sdot z0.s, z0.b, z1.b[1] +# CHECK-NEXT: [1,0] D============eeeeeER. .. mul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D=================eeeER .. sdot z0.s, z1.b, z2.b[1] +# CHECK-NEXT: [1,2] D==================eeeER .. sdot z0.s, z1.b, z2.b[1] +# CHECK-NEXT: [1,3] D=====================eeeER sdot z0.s, z0.b, z1.b[1] + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 7.0 0.5 0.0 mul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 12.0 0.0 0.0 sdot z0.s, z1.b, z2.b[1] +# CHECK-NEXT: 2. 2 13.0 0.0 0.0 sdot z0.s, z1.b, z2.b[1] +# CHECK-NEXT: 3. 2 16.0 0.0 0.0 sdot z0.s, z0.b, z1.b[1] +# CHECK-NEXT: 2 12.0 0.1 0.0 + +# CHECK: [27] Code Region - Z sdot.d + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1403 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.36 +# CHECK-NEXT: IPC: 0.29 +# CHECK-NEXT: Block RThroughput: 2.5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeER . . . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D=====eeeeER . . . . sdot z0.d, z1.h, z2.h +# CHECK-NEXT: [0,2] D======eeeeER . . . . sdot z0.d, z1.h, z2.h +# CHECK-NEXT: [0,3] D==========eeeeER . . . sdot z0.d, z0.h, z1.h +# CHECK-NEXT: [1,0] D==============eeeeeER . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D===================eeeeER . sdot z0.d, z1.h, z2.h +# CHECK-NEXT: [1,2] D====================eeeeER . sdot z0.d, z1.h, z2.h +# CHECK-NEXT: [1,3] D========================eeeeER sdot z0.d, z0.h, z1.h + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 8.0 0.5 0.0 mul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 13.0 0.0 0.0 sdot z0.d, z1.h, z2.h +# CHECK-NEXT: 2. 2 14.0 0.0 0.0 sdot z0.d, z1.h, z2.h +# CHECK-NEXT: 3. 2 18.0 0.0 0.0 sdot z0.d, z0.h, z1.h +# CHECK-NEXT: 2 13.3 0.1 0.0 + +# CHECK: [28] Code Region - Z smmla + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1103 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.36 +# CHECK-NEXT: IPC: 0.36 +# CHECK-NEXT: Block RThroughput: 0.8 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 01234 + +# CHECK: [0,0] DeeeeER . . . . mul z0.s, z0.s, z0.s +# CHECK-NEXT: [0,1] D====eeeER. . . . smmla z0.s, z1.b, z2.b +# CHECK-NEXT: [0,2] D=====eeeER . . . smmla z0.s, z1.b, z2.b +# CHECK-NEXT: [0,3] D========eeeER . . . smmla z0.s, z0.b, z1.b +# CHECK-NEXT: [1,0] D===========eeeeER . . mul z0.s, z0.s, z0.s +# CHECK-NEXT: [1,1] D===============eeeER . smmla z0.s, z1.b, z2.b +# CHECK-NEXT: [1,2] D================eeeER . smmla z0.s, z1.b, z2.b +# CHECK-NEXT: [1,3] D===================eeeER smmla z0.s, z0.b, z1.b + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 6.5 0.5 0.0 mul z0.s, z0.s, z0.s +# CHECK-NEXT: 1. 2 10.5 0.0 0.0 smmla z0.s, z1.b, z2.b +# CHECK-NEXT: 2. 2 11.5 0.0 0.0 smmla z0.s, z1.b, z2.b +# CHECK-NEXT: 3. 2 14.5 0.0 0.0 smmla z0.s, z0.b, z1.b +# CHECK-NEXT: 2 10.8 0.1 0.0 + +# CHECK: [29] Code Region - Z mla.b + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1403 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.36 +# CHECK-NEXT: IPC: 0.29 +# CHECK-NEXT: Block RThroughput: 4.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeER . . . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D=====eeeeER . . . . mla z0.b, p0/m, z1.b, z2.b +# CHECK-NEXT: [0,2] D======eeeeER . . . . mla z0.b, p0/m, z1.b, z2.b +# CHECK-NEXT: [0,3] D==========eeeeER . . . mla z0.b, p0/m, z0.b, z1.b +# CHECK-NEXT: [1,0] D==============eeeeeER . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D===================eeeeER . mla z0.b, p0/m, z1.b, z2.b +# CHECK-NEXT: [1,2] D====================eeeeER . mla z0.b, p0/m, z1.b, z2.b +# CHECK-NEXT: [1,3] D========================eeeeER mla z0.b, p0/m, z0.b, z1.b + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 8.0 0.5 0.0 mul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 13.0 0.0 0.0 mla z0.b, p0/m, z1.b, z2.b +# CHECK-NEXT: 2. 2 14.0 0.0 0.0 mla z0.b, p0/m, z1.b, z2.b +# CHECK-NEXT: 3. 2 18.0 0.0 0.0 mla z0.b, p0/m, z0.b, z1.b +# CHECK-NEXT: 2 13.3 0.1 0.0 + +# CHECK: [30] Code Region - Z mla.d + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1803 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.28 +# CHECK-NEXT: IPC: 0.22 +# CHECK-NEXT: Block RThroughput: 4.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 012345678 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeER . . . . . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D=====eeeeeER . . . . . . mla z0.d, p0/m, z1.d, z2.d +# CHECK-NEXT: [0,2] D========eeeeeER . . . . . mla z0.d, p0/m, z1.d, z2.d +# CHECK-NEXT: [0,3] D=============eeeeeER . . . . mla z0.d, p0/m, z0.d, z1.d +# CHECK-NEXT: [1,0] D==================eeeeeER . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D=======================eeeeeER . . mla z0.d, p0/m, z1.d, z2.d +# CHECK-NEXT: [1,2] D==========================eeeeeER . . mla z0.d, p0/m, z1.d, z2.d +# CHECK-NEXT: [1,3] D===============================eeeeeER mla z0.d, p0/m, z0.d, z1.d + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 10.0 0.5 0.0 mul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 15.0 0.0 0.0 mla z0.d, p0/m, z1.d, z2.d +# CHECK-NEXT: 2. 2 18.0 0.0 0.0 mla z0.d, p0/m, z1.d, z2.d +# CHECK-NEXT: 3. 2 23.0 0.0 0.0 mla z0.d, p0/m, z0.d, z1.d +# CHECK-NEXT: 2 16.5 0.1 0.0 + +# CHECK: [31] Code Region - Z smlalb + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1403 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.36 +# CHECK-NEXT: IPC: 0.29 +# CHECK-NEXT: Block RThroughput: 2.5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeER . . . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D=====eeeeER . . . . smlalb z0.d, z1.s, z2.s +# CHECK-NEXT: [0,2] D======eeeeER . . . . smlalb z0.d, z1.s, z2.s +# CHECK-NEXT: [0,3] D==========eeeeER . . . smlalb z0.d, z0.s, z1.s +# CHECK-NEXT: [1,0] D==============eeeeeER . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D===================eeeeER . smlalb z0.d, z1.s, z2.s +# CHECK-NEXT: [1,2] D====================eeeeER . smlalb z0.d, z1.s, z2.s +# CHECK-NEXT: [1,3] D========================eeeeER smlalb z0.d, z0.s, z1.s + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 8.0 0.5 0.0 mul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 13.0 0.0 0.0 smlalb z0.d, z1.s, z2.s +# CHECK-NEXT: 2. 2 14.0 0.0 0.0 smlalb z0.d, z1.s, z2.s +# CHECK-NEXT: 3. 2 18.0 0.0 0.0 smlalb z0.d, z0.s, z1.s +# CHECK-NEXT: 2 13.3 0.1 0.0 + +# CHECK: [32] Code Region - Z sqdmlalb + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1503 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.33 +# CHECK-NEXT: IPC: 0.27 +# CHECK-NEXT: Block RThroughput: 2.5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 012 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeER . . . . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D=====eeeeER . . . . . sqdmlalb z0.d, z1.s, z2.s +# CHECK-NEXT: [0,2] D=======eeeeER . . . . . sqdmlalb z0.d, z1.s, z2.s +# CHECK-NEXT: [0,3] D===========eeeeER . . . . sqdmlalb z0.d, z0.s, z1.s +# CHECK-NEXT: [1,0] D===============eeeeeER . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D====================eeeeER . . sqdmlalb z0.d, z1.s, z2.s +# CHECK-NEXT: [1,2] D======================eeeeER . . sqdmlalb z0.d, z1.s, z2.s +# CHECK-NEXT: [1,3] D==========================eeeeER sqdmlalb z0.d, z0.s, z1.s + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 8.5 0.5 0.0 mul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 13.5 0.0 0.0 sqdmlalb z0.d, z1.s, z2.s +# CHECK-NEXT: 2. 2 15.5 0.0 0.0 sqdmlalb z0.d, z1.s, z2.s +# CHECK-NEXT: 3. 2 19.5 0.0 0.0 sqdmlalb z0.d, z0.s, z1.s +# CHECK-NEXT: 2 14.3 0.1 0.0 + +# CHECK: [33] Code Region - Z sqrdmlah.b + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1503 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.33 +# CHECK-NEXT: IPC: 0.27 +# CHECK-NEXT: Block RThroughput: 2.5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 012 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeER . . . . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D=====eeeeER . . . . . sqrdmlah z0.b, z1.b, z2.b +# CHECK-NEXT: [0,2] D=======eeeeER . . . . . sqrdmlah z0.b, z1.b, z2.b +# CHECK-NEXT: [0,3] D===========eeeeER . . . . sqrdmlah z0.b, z0.b, z1.b +# CHECK-NEXT: [1,0] D===============eeeeeER . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D====================eeeeER . . sqrdmlah z0.b, z1.b, z2.b +# CHECK-NEXT: [1,2] D======================eeeeER . . sqrdmlah z0.b, z1.b, z2.b +# CHECK-NEXT: [1,3] D==========================eeeeER sqrdmlah z0.b, z0.b, z1.b + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 8.5 0.5 0.0 mul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 13.5 0.0 0.0 sqrdmlah z0.b, z1.b, z2.b +# CHECK-NEXT: 2. 2 15.5 0.0 0.0 sqrdmlah z0.b, z1.b, z2.b +# CHECK-NEXT: 3. 2 19.5 0.0 0.0 sqrdmlah z0.b, z0.b, z1.b +# CHECK-NEXT: 2 14.3 0.1 0.0 + +# CHECK: [34] Code Region - Z sqrdmlah.d + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1803 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.28 +# CHECK-NEXT: IPC: 0.22 +# CHECK-NEXT: Block RThroughput: 4.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 012345678 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeER . . . . . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D=====eeeeeER . . . . . . sqrdmlah z0.d, z1.d, z2.d +# CHECK-NEXT: [0,2] D========eeeeeER . . . . . sqrdmlah z0.d, z1.d, z2.d +# CHECK-NEXT: [0,3] D=============eeeeeER . . . . sqrdmlah z0.d, z0.d, z1.d +# CHECK-NEXT: [1,0] D==================eeeeeER . . . mul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D=======================eeeeeER . . sqrdmlah z0.d, z1.d, z2.d +# CHECK-NEXT: [1,2] D==========================eeeeeER . . sqrdmlah z0.d, z1.d, z2.d +# CHECK-NEXT: [1,3] D===============================eeeeeER sqrdmlah z0.d, z0.d, z1.d + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 10.0 0.5 0.0 mul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 15.0 0.0 0.0 sqrdmlah z0.d, z1.d, z2.d +# CHECK-NEXT: 2. 2 18.0 0.0 0.0 sqrdmlah z0.d, z1.d, z2.d +# CHECK-NEXT: 3. 2 23.0 0.0 0.0 sqrdmlah z0.d, z0.d, z1.d +# CHECK-NEXT: 2 16.5 0.1 0.0 + +# CHECK: [35] Code Region - Z fcmla ZPmZZ + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1503 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.27 +# CHECK-NEXT: IPC: 0.27 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 012 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeER . . . . . . fmul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D===eeeeeER . . . . . fcmla z0.d, p0/m, z1.d, z2.d, #90 +# CHECK-NEXT: [0,2] D=====eeeeeER . . . . . fcmla z0.d, p0/m, z1.d, z2.d, #90 +# CHECK-NEXT: [0,3] D==========eeeeeER . . . . fcmla z0.d, p0/m, z0.d, z1.d, #90 +# CHECK-NEXT: [1,0] D===============eeeER . . . fmul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D==================eeeeeER . . fcmla z0.d, p0/m, z1.d, z2.d, #90 +# CHECK-NEXT: [1,2] D====================eeeeeER . . fcmla z0.d, p0/m, z1.d, z2.d, #90 +# CHECK-NEXT: [1,3] D=========================eeeeeER fcmla z0.d, p0/m, z0.d, z1.d, #90 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 8.5 0.5 0.0 fmul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 11.5 0.0 0.0 fcmla z0.d, p0/m, z1.d, z2.d, #90 +# CHECK-NEXT: 2. 2 13.5 0.0 0.0 fcmla z0.d, p0/m, z1.d, z2.d, #90 +# CHECK-NEXT: 3. 2 18.5 0.0 0.0 fcmla z0.d, p0/m, z0.d, z1.d, #90 +# CHECK-NEXT: 2 13.0 0.1 0.0 + +# CHECK: [36] Code Region - Z fcmla ZZZI + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1503 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.27 +# CHECK-NEXT: IPC: 0.27 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 012 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeER . . . . . . fmul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D===eeeeeER . . . . . fcmla z0.s, z1.s, z2.s[1], #90 +# CHECK-NEXT: [0,2] D=====eeeeeER . . . . . fcmla z0.s, z1.s, z2.s[1], #90 +# CHECK-NEXT: [0,3] D==========eeeeeER . . . . fcmla z0.s, z0.s, z1.s[1], #90 +# CHECK-NEXT: [1,0] D===============eeeER . . . fmul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D==================eeeeeER . . fcmla z0.s, z1.s, z2.s[1], #90 +# CHECK-NEXT: [1,2] D====================eeeeeER . . fcmla z0.s, z1.s, z2.s[1], #90 +# CHECK-NEXT: [1,3] D=========================eeeeeER fcmla z0.s, z0.s, z1.s[1], #90 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 8.5 0.5 0.0 fmul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 11.5 0.0 0.0 fcmla z0.s, z1.s, z2.s[1], #90 +# CHECK-NEXT: 2. 2 13.5 0.0 0.0 fcmla z0.s, z1.s, z2.s[1], #90 +# CHECK-NEXT: 3. 2 18.5 0.0 0.0 fcmla z0.s, z0.s, z1.s[1], #90 +# CHECK-NEXT: 2 13.0 0.1 0.0 + +# CHECK: [37] Code Region - Z fmla ZPmZZ + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1303 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.31 +# CHECK-NEXT: IPC: 0.31 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 012345678 + +# CHECK: [0,0] DeeeER . . . . . fmul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D===eeeeER. . . . . fmla z0.d, p0/m, z1.d, z2.d +# CHECK-NEXT: [0,2] D=====eeeeER . . . . fmla z0.d, p0/m, z1.d, z2.d +# CHECK-NEXT: [0,3] D=========eeeeER . . . fmla z0.d, p0/m, z0.d, z1.d +# CHECK-NEXT: [1,0] D=============eeeER . . . fmul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D================eeeeER . . fmla z0.d, p0/m, z1.d, z2.d +# CHECK-NEXT: [1,2] D==================eeeeER. . fmla z0.d, p0/m, z1.d, z2.d +# CHECK-NEXT: [1,3] D======================eeeeER fmla z0.d, p0/m, z0.d, z1.d + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 7.5 0.5 0.0 fmul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 10.5 0.0 0.0 fmla z0.d, p0/m, z1.d, z2.d +# CHECK-NEXT: 2. 2 12.5 0.0 0.0 fmla z0.d, p0/m, z1.d, z2.d +# CHECK-NEXT: 3. 2 16.5 0.0 0.0 fmla z0.d, p0/m, z0.d, z1.d +# CHECK-NEXT: 2 11.8 0.1 0.0 + +# CHECK: [38] Code Region - Z fmla ZZZI + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1303 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.31 +# CHECK-NEXT: IPC: 0.31 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 012345678 + +# CHECK: [0,0] DeeeER . . . . . fmul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D===eeeeER. . . . . fmla z0.d, z1.d, z2.d[1] +# CHECK-NEXT: [0,2] D=====eeeeER . . . . fmla z0.d, z1.d, z2.d[1] +# CHECK-NEXT: [0,3] D=========eeeeER . . . fmla z0.d, z0.d, z1.d[1] +# CHECK-NEXT: [1,0] D=============eeeER . . . fmul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D================eeeeER . . fmla z0.d, z1.d, z2.d[1] +# CHECK-NEXT: [1,2] D==================eeeeER. . fmla z0.d, z1.d, z2.d[1] +# CHECK-NEXT: [1,3] D======================eeeeER fmla z0.d, z0.d, z1.d[1] + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 7.5 0.5 0.0 fmul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 10.5 0.0 0.0 fmla z0.d, z1.d, z2.d[1] +# CHECK-NEXT: 2. 2 12.5 0.0 0.0 fmla z0.d, z1.d, z2.d[1] +# CHECK-NEXT: 3. 2 16.5 0.0 0.0 fmla z0.d, z0.d, z1.d[1] +# CHECK-NEXT: 2 11.8 0.1 0.0 + +# CHECK: [39] Code Region - Z fmlalb ZZZ + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1303 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.31 +# CHECK-NEXT: IPC: 0.31 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 012345678 + +# CHECK: [0,0] DeeeER . . . . . fmul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D===eeeeER. . . . . fmlalb z0.s, z1.h, z2.h +# CHECK-NEXT: [0,2] D=====eeeeER . . . . fmlalb z0.s, z1.h, z2.h +# CHECK-NEXT: [0,3] D=========eeeeER . . . fmlalb z0.s, z0.h, z1.h +# CHECK-NEXT: [1,0] D=============eeeER . . . fmul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D================eeeeER . . fmlalb z0.s, z1.h, z2.h +# CHECK-NEXT: [1,2] D==================eeeeER. . fmlalb z0.s, z1.h, z2.h +# CHECK-NEXT: [1,3] D======================eeeeER fmlalb z0.s, z0.h, z1.h + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 7.5 0.5 0.0 fmul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 10.5 0.0 0.0 fmlalb z0.s, z1.h, z2.h +# CHECK-NEXT: 2. 2 12.5 0.0 0.0 fmlalb z0.s, z1.h, z2.h +# CHECK-NEXT: 3. 2 16.5 0.0 0.0 fmlalb z0.s, z0.h, z1.h +# CHECK-NEXT: 2 11.8 0.1 0.0 + +# CHECK: [40] Code Region - Z bfdot + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1603 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.25 +# CHECK-NEXT: IPC: 0.25 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 01234 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeER . . . . . . fmul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D===eeeeeER . . . . . bfdot z0.s, z1.h, z2.h +# CHECK-NEXT: [0,2] D======eeeeeER . . . . . bfdot z0.s, z1.h, z2.h +# CHECK-NEXT: [0,3] D===========eeeeeER . . . . bfdot z0.s, z0.h, z1.h +# CHECK-NEXT: [1,0] D================eeeER . . . fmul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D===================eeeeeER . . bfdot z0.s, z1.h, z2.h +# CHECK-NEXT: [1,2] D======================eeeeeER. . bfdot z0.s, z1.h, z2.h +# CHECK-NEXT: [1,3] D===========================eeeeeER bfdot z0.s, z0.h, z1.h + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 9.0 0.5 0.0 fmul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 12.0 0.0 0.0 bfdot z0.s, z1.h, z2.h +# CHECK-NEXT: 2. 2 15.0 0.0 0.0 bfdot z0.s, z1.h, z2.h +# CHECK-NEXT: 3. 2 20.0 0.0 0.0 bfdot z0.s, z0.h, z1.h +# CHECK-NEXT: 2 14.0 0.1 0.0 + +# CHECK: [41] Code Region - Z bfmmla + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1903 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.21 +# CHECK-NEXT: IPC: 0.21 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 0 + +# CHECK: [0,0] DeeeER . . . . . . . fmul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D===eeeeeeER . . . . . . bfmmla z0.s, z1.h, z2.h +# CHECK-NEXT: [0,2] D=======eeeeeeER . . . . . bfmmla z0.s, z1.h, z2.h +# CHECK-NEXT: [0,3] D=============eeeeeeER . . . . bfmmla z0.s, z0.h, z1.h +# CHECK-NEXT: [1,0] D===================eeeER. . . . fmul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D======================eeeeeeER . . bfmmla z0.s, z1.h, z2.h +# CHECK-NEXT: [1,2] D==========================eeeeeeER. . bfmmla z0.s, z1.h, z2.h +# CHECK-NEXT: [1,3] D================================eeeeeeER bfmmla z0.s, z0.h, z1.h + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 10.5 0.5 0.0 fmul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 13.5 0.0 0.0 bfmmla z0.s, z1.h, z2.h +# CHECK-NEXT: 2. 2 17.5 0.0 0.0 bfmmla z0.s, z1.h, z2.h +# CHECK-NEXT: 3. 2 23.5 0.0 0.0 bfmmla z0.s, z0.h, z1.h +# CHECK-NEXT: 2 16.3 0.1 0.0 + +# CHECK: [42] Code Region - bfmlalb + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 1503 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 16 +# CHECK-NEXT: uOps Per Cycle: 0.27 +# CHECK-NEXT: IPC: 0.27 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 012 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeER . . . . . . fmul z0.d, z0.d, z0.d +# CHECK-NEXT: [0,1] D===eeeeeER . . . . . bfmlalb z0.s, z1.h, z2.h +# CHECK-NEXT: [0,2] D=====eeeeeER . . . . . bfmlalb z0.s, z1.h, z2.h +# CHECK-NEXT: [0,3] D==========eeeeeER . . . . bfmlalb z0.s, z0.h, z1.h +# CHECK-NEXT: [1,0] D===============eeeER . . . fmul z0.d, z0.d, z0.d +# CHECK-NEXT: [1,1] D==================eeeeeER . . bfmlalb z0.s, z1.h, z2.h +# CHECK-NEXT: [1,2] D====================eeeeeER . . bfmlalb z0.s, z1.h, z2.h +# CHECK-NEXT: [1,3] D=========================eeeeeER bfmlalb z0.s, z0.h, z1.h + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 8.5 0.5 0.0 fmul z0.d, z0.d, z0.d +# CHECK-NEXT: 1. 2 11.5 0.0 0.0 bfmlalb z0.s, z1.h, z2.h +# CHECK-NEXT: 2. 2 13.5 0.0 0.0 bfmlalb z0.s, z1.h, z2.h +# CHECK-NEXT: 3. 2 18.5 0.0 0.0 bfmlalb z0.s, z0.h, z1.h +# CHECK-NEXT: 2 13.0 0.1 0.0 diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s new file mode 100644 --- /dev/null +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s @@ -0,0 +1,3723 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -mattr=+aes,+sha3,+sm4 -instruction-tables < %s | FileCheck %s + +abs d29, d24 +abs v0.16b, v0.16b +abs v0.2d, v0.2d +abs v0.2s, v0.2s +abs v0.4h, v0.4h +abs v0.4s, v0.4s +abs v0.8b, v0.8b +abs v0.8h, v0.8h +add d17, d31, d29 +add v0.8b, v0.8b, v0.8b +addhn v0.2s, v0.2d, v0.2d +addhn v0.4h, v0.4s, v0.4s +addhn v0.8b, v0.8h, v0.8h +addhn2 v0.16b, v0.8h, v0.8h +addhn2 v0.4s, v0.2d, v0.2d +addhn2 v0.8h, v0.4s, v0.4s +addp v0.2d, v0.2d, v0.2d +addp v0.8b, v0.8b, v0.8b +addv s0, v0.4s +addv h0, v0.4h +addv h0, v0.8h +addv b0, v0.8b +addv b0, v0.16b +aesd v0.16b, v0.16b +aese v0.16b, v0.16b +aesimc v0.16b, v0.16b +aesmc v0.16b, v0.16b +and v0.8b, v0.8b, v0.8b +bfcvt h0, s0 +bfcvtn v0.4h, v0.4s +bfcvtn2 v0.8h, v0.4s +bfdot v0.2s, v0.4h, v0.4h +bfdot v0.4s, v0.8h, v0.8h +bfmlalb v0.4s, v0.8h, v0.8h +bfmlalb v0.4s, v0.8h, v0.h[3] +bfmlalt v0.4s, v0.8h, v0.8h +bfmlalt v0.4s, v0.8h, v0.h[3] +bfmmla v0.4s, v0.8h, v0.8h +bic v0.4h, #15, lsl #8 +bic v0.8b, v0.8b, v0.8b +bif v0.16b, v0.16b, v0.16b +bit v0.16b, v0.16b, v0.16b +bsl v0.8b, v0.8b, v0.8b +cls v0.16b, v0.16b +cls v0.2s, v0.2s +cls v0.4h, v0.4h +cls v0.4s, v0.4s +cls v0.8b, v0.8b +cls v0.8h, v0.8h +clz v0.16b, v0.16b +clz v0.2s, v0.2s +clz v0.4h, v0.4h +clz v0.4s, v0.4s +clz v0.8b, v0.8b +clz v0.8h, v0.8h +cmeq d20, d21, 0 +cmeq d20, d21, d22 +cmeq v0.16b, v0.16b, 0 +cmeq v0.16b, v0.16b, v0.16b +cmge d20, d21, 0 +cmge d20, d21, d22 +cmge v0.4h, v0.4h, v0.4h +cmge v0.8b, v0.8b, 0 +cmgt d20, d21, 0 +cmgt d20, d21, d22 +cmgt v0.2s, v0.2s, 0 +cmgt v0.4s, v0.4s, v0.4s +cmhi d20, d21, d22 +cmhi v0.8h, v0.8h, v0.8h +cmhs d20, d21, d22 +cmhs v0.8b, v0.8b, v0.8b +cmle d20, d21, 0 +cmle v0.2d, v0.2d, 0 +cmlt d20, d21, 0 +cmlt v0.8h, v0.8h, 0 +cmtst d20, d21, d22 +cmtst v0.2s, v0.2s, v0.2s +cnt v0.16b, v0.16b +cnt v0.8b, v0.8b +dup v0.16b,w28 +dup v0.2d,x28 +dup v0.2s,w28 +dup v0.4h,w28 +dup v0.4s,w28 +dup v0.8b,w28 +dup v0.8h,w28 +dup b0, v0.b[1] +dup d0, v0.d[1] +dup h0, v0.h[1] +dup s0, v0.s[1] +dup v0.16b, v0.b[1] +dup v0.2d, v0.d[1] +dup v0.2s, v0.s[1] +dup v0.4h, v0.h[1] +dup v0.4s, v0.s[1] +dup v0.8b, v0.b[1] +dup v0.8h, v0.h[1] +eor v0.16b, v0.16b, v0.16b +ext v0.16b, v0.16b, v0.16b, #3 +ext v0.8b, v0.8b, v0.8b, #3 +fabd d29, d24, d20 +fabd s29, s24, s20 +fabd v0.4s, v0.4s, v0.4s +fabs v0.2d, v0.2d +fabs v0.2s, v0.2s +fabs v0.4h, v0.4h +fabs v0.4s, v0.4s +fabs v0.8h, v0.8h +facge d20, d21, d22 +facge s10, s11, s12 +facge v0.4s, v0.4s, v0.4s +facgt d20, d21, d22 +facgt s10, s11, s12 +facgt v0.2d, v0.2d, v0.2d +fadd v0.4s, v0.4s, v0.4s +faddp v0.2s, v0.2s, v0.2s +faddp v0.4s, v0.4s, v0.4s +fcadd v0.2s, v0.2s, v0.2s, 90 +fcadd v0.4s, v0.4s, v0.4s, 270 +fcmeq d20, d21, #0.0 +fcmeq d20, d21, d22 +fcmeq s10, s11, #0.0 +fcmeq s10, s11, s12 +fcmeq v0.2s, v0.2s, #0.0 +fcmeq v0.2s, v0.2s, v0.2s +fcmge d20, d21, #0.0 +fcmge d20, d21, d22 +fcmge s10, s11, #0.0 +fcmge s10, s11, s12 +fcmge v0.2d, v0.2d, #0.0 +fcmge v0.4s, v0.4s, v0.4s +fcmgt d20, d21, #0.0 +fcmgt d20, d21, d22 +fcmgt s10, s11, #0.0 +fcmgt s10, s11, s12 +fcmgt v0.4s, v0.4s, #0.0 +fcmgt v0.4s, v0.4s, v0.4s +fcmla v0.2s, v0.2s, v0.2s, #90 +fcmla v0.4s, v0.4s, v0.s[1], #0 +fcmle d20, d21, #0.0 +fcmle s10, s11, #0.0 +fcmle v0.2d, v0.2d, #0.0 +fcmlt d20, d21, #0.0 +fcmlt s10, s11, #0.0 +fcmlt v0.4s, v0.4s, #0.0 +fcvtas d21, d14 +fcvtas s12, s13 +fcvtas h12, h13 +fcvtas v0.2d, v0.2d +fcvtas v0.2s, v0.2s +fcvtas v0.4h, v0.4h +fcvtas v0.4s, v0.4s +fcvtas v0.8h, v0.8h +fcvtau d21, d14 +fcvtau s12, s13 +fcvtau h12, h13 +fcvtau v0.2d, v0.2d +fcvtau v0.2s, v0.2s +fcvtau v0.4h, v0.4h +fcvtau v0.4s, v0.4s +fcvtau v0.8h, v0.8h +fcvtl v0.2d, v0.2s +fcvtl v0.4s, v0.4h +fcvtl2 v0.2d, v0.4s +fcvtl2 v0.4s, v0.8h +fcvtms d21, d14 +fcvtms s22, s13 +fcvtms h22, h13 +fcvtms v0.2d, v0.2d +fcvtms v0.2s, v0.2s +fcvtms v0.4h, v0.4h +fcvtms v0.4s, v0.4s +fcvtms v0.8h, v0.8h +fcvtmu d21, d14 +fcvtmu s12, s13 +fcvtmu h12, h13 +fcvtmu v0.2d, v0.2d +fcvtmu v0.2s, v0.2s +fcvtmu v0.4h, v0.4h +fcvtmu v0.4s, v0.4s +fcvtmu v0.8h, v0.8h +fcvtn v0.2s, v0.2d +fcvtn v0.4h, v0.4s +fcvtn2 v0.4s, v0.2d +fcvtn2 v0.8h, v0.4s +fcvtns d21, d14 +fcvtns s22, s13 +fcvtns h22, h13 +fcvtns v0.2d, v0.2d +fcvtns v0.2s, v0.2s +fcvtns v0.4h, v0.4h +fcvtns v0.4s, v0.4s +fcvtns v0.8h, v0.8h +fcvtnu d21, d14 +fcvtnu s12, s13 +fcvtnu h12, h13 +fcvtnu v0.2d, v0.2d +fcvtnu v0.2s, v0.2s +fcvtnu v0.4h, v0.4h +fcvtnu v0.4s, v0.4s +fcvtnu v0.8h, v0.8h +fcvtps d21, d14 +fcvtps s22, s13 +fcvtps h22, h13 +fcvtps v0.2d, v0.2d +fcvtps v0.2s, v0.2s +fcvtps v0.4h, v0.4h +fcvtps v0.4s, v0.4s +fcvtps v0.8h, v0.8h +fcvtpu d21, d14 +fcvtpu s12, s13 +fcvtpu h12, h13 +fcvtpu v0.2d, v0.2d +fcvtpu v0.2s, v0.2s +fcvtpu v0.4h, v0.4h +fcvtpu v0.4s, v0.4s +fcvtpu v0.8h, v0.8h +fcvtxn s22, d13 +fcvtxn v0.2s, v0.2d +fcvtxn2 v0.4s, v0.2d +fcvtzs d21, d12, #1 +fcvtzs d21, d14 +fcvtzs s12, s13 +fcvtzs s21, s12, #1 +fcvtzs h21, h14 +fcvtzs h21, h12, #1 +fcvtzs v0.2d, v0.2d +fcvtzs v0.2d, v0.2d, #3 +fcvtzs v0.2s, v0.2s +fcvtzs v0.2s, v0.2s, #3 +fcvtzs v0.4h, v0.4h +fcvtzs v0.4s, v0.4s +fcvtzs v0.4s, v0.4s, #3 +fcvtzs v0.8h, v0.8h +fcvtzu d21, d12, #1 +fcvtzu d21, d14 +fcvtzu s12, s13 +fcvtzu s21, s12, #1 +fcvtzu h12, h13 +fcvtzu h21, h12, #1 +fcvtzu v0.2d, v0.2d +fcvtzu v0.2d, v0.2d, #3 +fcvtzu v0.2s, v0.2s +fcvtzu v0.2s, v0.2s, #3 +fcvtzu v0.4h, v0.4h +fcvtzu v0.4s, v0.4s +fcvtzu v0.4s, v0.4s, #3 +fcvtzu v0.8h, v0.8h +fdiv v0.2d, v0.2d, v0.2d +fdiv v0.2s, v0.2s, v0.2s +fdiv v0.4h, v0.4h, v0.4h +fdiv v0.4s, v0.4s, v0.4s +fdiv v0.8h, v0.8h, v0.8h +fmax v0.2d, v0.2d, v0.2d +fmax v0.2s, v0.2s, v0.2s +fmax v0.4s, v0.4s, v0.4s +fmaxnm v0.2d, v0.2d, v0.2d +fmaxnm v0.2s, v0.2s, v0.2s +fmaxnm v0.4s, v0.4s, v0.4s +fmaxnmp v0.2d, v0.2d, v0.2d +fmaxnmp v0.2s, v0.2s, v0.2s +fmaxnmp v0.4s, v0.4s, v0.4s +fmaxp v0.2d, v0.2d, v0.2d +fmaxp v0.2s, v0.2s, v0.2s +fmaxp v0.4s, v0.4s, v0.4s +fmaxv h0, v0.4h +fmaxv h0, v0.8h +fmaxv s0, v0.4s +fmin v0.2d, v0.2d, v0.2d +fmin v0.2s, v0.2s, v0.2s +fmin v0.4s, v0.4s, v0.4s +fminnm v0.2d, v0.2d, v0.2d +fminnm v0.2s, v0.2s, v0.2s +fminnm v0.4s, v0.4s, v0.4s +fminnmp v0.2d, v0.2d, v0.2d +fminnmp v0.2s, v0.2s, v0.2s +fminnmp v0.4s, v0.4s, v0.4s +fminp v0.2d, v0.2d, v0.2d +fminp v0.2s, v0.2s, v0.2s +fminp v0.4s, v0.4s, v0.4s +fmla d0, d1, v0.d[1] +fmla s0, s1, v0.s[3] +fmla v0.2s, v0.2s, v0.2s +fmlal v0.2s, v0.2h, v0.h[1] +fmlal v0.4s, v0.4h, v0.h[3] +fmlal v0.2s, v0.2h, v0.2h +fmlal v0.4s, v0.4h, v0.4h +fmlal2 v0.2s, v0.2h, v0.h[1] +fmlal2 v0.4s, v0.4h, v0.h[3] +fmlal2 v0.2s, v0.2h, v0.2h +fmlal2 v0.4s, v0.4h, v0.4h +fmls d0, d4, v0.d[1] +fmls s3, s5, v0.s[3] +fmls v0.2s, v0.2s, v0.2s +fmlsl v0.2s, v0.2h, v0.h[1] +fmlsl v0.4s, v0.4h, v0.h[3] +fmlsl v0.2s, v0.2h, v0.2h +fmlsl v0.4s, v0.4h, v0.4h +fmlsl2 v0.2s, v0.2h, v0.h[1] +fmlsl2 v0.4s, v0.4h, v0.h[3] +fmlsl2 v0.2s, v0.2h, v0.2h +fmlsl2 v0.4s, v0.4h, v0.4h +fmov v0.2d, #-1.25 +fmov v0.2s, #13.0 +fmov v0.4s, #1.0 +fmul d0, d1, v0.d[1] +fmul s0, s1, v0.s[3] +fmul v0.2s, v0.2s, v0.2s +fmulx d0, d4, v0.d[1] +fmulx d23, d11, d1 +fmulx s20, s22, s15 +fmulx s3, s5, v0.s[3] +fmulx v0.2d, v0.2d, v0.2d +fmulx v0.2s, v0.2s, v0.2s +fmulx v0.4s, v0.4s, v0.4s +fneg v0.2d, v0.2d +fneg v0.2s, v0.2s +fneg v0.4h, v0.4h +fneg v0.4s, v0.4s +fneg v0.8h, v0.8h +frecpe d13, d13 +frecpe s19, s14 +frecpe v0.2d, v0.2d +frecpe v0.2s, v0.2s +frecpe v0.4h, v0.4h +frecpe v0.4s, v0.4s +frecpe v0.8h, v0.8h +frecps v0.4s, v0.4s, v0.4s +frecps d22, d30, d21 +frecps s21, s16, s13 +frecpx d16, d19 +frecpx s18, s10 +frint32x v0.2d, v0.2d +frint32x v0.2s, v0.2s +frint32x v0.4s, v0.4s +frint32z v0.2d, v0.2d +frint32z v0.2s, v0.2s +frint32z v0.4s, v0.4s +frint64x v0.2d, v0.2d +frint64x v0.2s, v0.2s +frint64x v0.4s, v0.4s +frint64z v0.2d, v0.2d +frint64z v0.2s, v0.2s +frint64z v0.4s, v0.4s +frinta v0.2d, v0.2d +frinta v0.2s, v0.2s +frinta v0.4h, v0.4h +frinta v0.4s, v0.4s +frinta v0.8h, v0.8h +frinti v0.2d, v0.2d +frinti v0.2s, v0.2s +frinti v0.4h, v0.4h +frinti v0.4s, v0.4s +frinti v0.8h, v0.8h +frintm v0.2d, v0.2d +frintm v0.2s, v0.2s +frintm v0.4h, v0.4h +frintm v0.4s, v0.4s +frintm v0.8h, v0.8h +frintn v0.2d, v0.2d +frintn v0.2s, v0.2s +frintn v0.4h, v0.4h +frintn v0.4s, v0.4s +frintn v0.8h, v0.8h +frintp v0.2d, v0.2d +frintp v0.2s, v0.2s +frintp v0.4h, v0.4h +frintp v0.4s, v0.4s +frintp v0.8h, v0.8h +frintx v0.2d, v0.2d +frintx v0.2s, v0.2s +frintx v0.4h, v0.4h +frintx v0.4s, v0.4s +frintx v0.8h, v0.8h +frintz v0.2d, v0.2d +frintz v0.2s, v0.2s +frintz v0.4h, v0.4h +frintz v0.4s, v0.4s +frintz v0.8h, v0.8h +frsqrte d21, d12 +frsqrte s22, s13 +frsqrte v0.2d, v0.2d +frsqrte v0.2s, v0.2s +frsqrte v0.4h, v0.4h +frsqrte v0.4s, v0.4s +frsqrte v0.8h, v0.8h +frsqrts d8, d22, d18 +frsqrts s21, s5, s12 +frsqrts v0.2d, v0.2d, v0.2d +fsqrt v0.2d, v0.2d +fsqrt v0.2s, v0.2s +fsqrt v0.4h, v0.4h +fsqrt v0.4s, v0.4s +fsqrt v0.8h, v0.8h +fsub v0.2s, v0.2s, v0.2s +ld1 { v0.16b }, [x0] +ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48 +ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] +ld1 { v0.4s, v1.4s }, [sp], #32 +ld1 { v0.4s, v1.4s, v2.4s }, [sp] +ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 +ld1 { v0.8h }, [x15], x2 +ld1 { v0.8h, v1.8h }, [x15] +ld1 { v0.b }[9], [x0] +ld1 { v0.b }[9], [x0], #1 +ld1r { v0.16b }, [x0] +ld1r { v0.16b }, [x0], #1 +ld1r { v0.8h }, [x15] +ld1r { v0.8h }, [x15], #2 +ld2 { v0.16b, v1.16b }, [x0], x1 +ld2 { v0.8b, v1.8b }, [x0] +ld2 { v0.h, v1.h }[7], [x15] +ld2 { v0.h, v1.h }[7], [x15], #4 +ld2r { v0.2d, v1.2d }, [x0] +ld2r { v0.2d, v1.2d }, [x0], #16 +ld2r { v0.4s, v1.4s }, [sp] +ld2r { v0.4s, v1.4s }, [sp], #8 +ld3 { v0.4h, v1.4h, v2.4h }, [x15] +ld3 { v0.8h, v1.8h, v2.8h }, [x15], x2 +ld3 { v0.s, v1.s, v2.s }[3], [sp] +ld3 { v0.s, v1.s, v2.s }[3], [sp], x3 +ld3r { v0.4h, v1.4h, v2.4h }, [x15] +ld3r { v0.4h, v1.4h, v2.4h }, [x15], #6 +ld3r { v0.8b, v1.8b, v2.8b }, [x0] +ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3 +ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp] +ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64 +ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] +ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 +ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0 +ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp] +ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp], x7 +ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp] +ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x30 +mla v0.8b, v0.8b, v0.8b +mls v0.4h, v0.4h, v0.4h +mov b0, v0.b[15] +mov d6, v0.d[1] +mov h2, v0.h[5] +mov s17, v0.s[2] +mov v2.b[0], v0.b[0] +mov v2.h[1], v0.h[1] +mov v2.s[2], v0.s[2] +mov v2.d[1], v0.d[1] +mov v0.b[0], w8 +mov v0.h[1], w8 +mov v0.s[2], w8 +mov v0.d[1], x8 +mov v0.16b, v0.16b +mov v0.8b, v0.8b +movi d15, #0xff00ff00ff00ff +movi v0.16b, #31 +movi v0.2d, #0xff0000ff0000ffff +movi v0.2s, #8, msl #8 +movi v0.4s, #255, lsl #24 +movi v0.8b, #255 +mul v0.8b, v0.8b, v0.8b +mvni v0.2s, 0 +mvni v0.4s, #16, msl #16 +neg d29, d24 +neg v0.16b, v0.16b +neg v0.2d, v0.2d +neg v0.2s, v0.2s +neg v0.4h, v0.4h +neg v0.4s, v0.4s +neg v0.8b, v0.8b +neg v0.8h, v0.8h +not v0.16b, v0.16b +not v0.8b, v0.8b +orn v0.16b, v0.16b, v0.16b +orr v0.16b, v0.16b, v0.16b +orr v0.8h, #31 +pmul v0.16b, v0.16b, v0.16b +pmul v0.8b, v0.8b, v0.8b +pmull v0.8h, v0.8b, v0.8b +pmull2 v0.8h, v0.16b, v0.16b +raddhn v0.2s, v0.2d, v0.2d +raddhn v0.4h, v0.4s, v0.4s +raddhn v0.8b, v0.8h, v0.8h +raddhn2 v0.16b, v0.8h, v0.8h +raddhn2 v0.4s, v0.2d, v0.2d +raddhn2 v0.8h, v0.4s, v0.4s +rbit v0.16b, v0.16b +rbit v0.8b, v0.8b +rev16 v21.8b, v1.8b +rev16 v30.16b, v31.16b +rev32 v0.4h, v9.4h +rev32 v21.8b, v1.8b +rev32 v30.16b, v31.16b +rev32 v4.8h, v7.8h +rev64 v0.16b, v31.16b +rev64 v1.8b, v9.8b +rev64 v13.4h, v21.4h +rev64 v2.8h, v4.8h +rev64 v4.2s, v0.2s +rev64 v6.4s, v8.4s +rshrn v0.2s, v0.2d, #3 +rshrn v0.4h, v0.4s, #3 +rshrn v0.8b, v0.8h, #3 +rshrn2 v0.16b, v0.8h, #3 +rshrn2 v0.4s, v0.2d, #3 +rshrn2 v0.8h, v0.4s, #3 +rsubhn v0.2s, v0.2d, v0.2d +rsubhn v0.4h, v0.4s, v0.4s +rsubhn v0.8b, v0.8h, v0.8h +rsubhn2 v0.16b, v0.8h, v0.8h +rsubhn2 v0.4s, v0.2d, v0.2d +rsubhn2 v0.8h, v0.4s, v0.4s +saba v0.16b, v0.16b, v0.16b +sabal v0.2d, v0.2s, v0.2s +sabal v0.4s, v0.4h, v0.4h +sabal v0.8h, v0.8b, v0.8b +sabal2 v0.2d, v0.4s, v0.4s +sabal2 v0.4s, v0.8h, v0.8h +sabal2 v0.8h, v0.16b, v0.16b +sabd v0.4h, v0.4h, v0.4h +sabdl v0.2d, v0.2s, v0.2s +sabdl v0.4s, v0.4h, v0.4h +sabdl v0.8h, v0.8b, v0.8b +sabdl2 v0.2d, v0.4s, v0.4s +sabdl2 v0.4s, v0.8h, v0.8h +sabdl2 v0.8h, v0.16b, v0.16b +sadalp v0.1d, v0.2s +sadalp v0.2d, v0.4s +sadalp v0.2s, v0.4h +sadalp v0.4h, v0.8b +sadalp v0.4s, v0.8h +sadalp v0.8h, v0.16b +saddl v0.2d, v0.2s, v0.2s +saddl v0.4s, v0.4h, v0.4h +saddl v0.8h, v0.8b, v0.8b +saddl2 v0.2d, v0.4s, v0.4s +saddl2 v0.4s, v0.8h, v0.8h +saddl2 v0.8h, v0.16b, v0.16b +saddlp v0.1d, v0.2s +saddlp v0.2d, v0.4s +saddlp v0.2s, v0.4h +saddlp v0.4h, v0.8b +saddlp v0.4s, v0.8h +saddlp v0.8h, v0.16b +saddlv d0, v0.4s +saddlv s0, v0.4h +saddlv s0, v0.8h +saddlv h0, v0.8b +saddlv h0, v0.16b +saddw v0.2d, v0.2d, v0.2s +saddw v0.4s, v0.4s, v0.4h +saddw v0.8h, v0.8h, v0.8b +saddw2 v0.2d, v0.2d, v0.4s +saddw2 v0.4s, v0.4s, v0.8h +saddw2 v0.8h, v0.8h, v0.16b +scvtf d21, d12 +scvtf d21, d12, #64 +scvtf s22, s13 +scvtf s22, s13, #32 +scvtf v0.2d, v0.2d +scvtf v0.2d, v0.2d, #3 +scvtf v0.2s, v0.2s +scvtf v0.2s, v0.2s, #3 +scvtf v0.4h, v0.4h +scvtf v0.4s, v0.4s +scvtf v0.4s, v0.4s, #3 +scvtf v0.8h, v0.8h +sdot v0.2s, v0.8b, v0.4b[2] +sdot v0.2s, v0.8b, v0.8b +sdot v0.4s, v0.16b, v0.16b +sdot v0.4s, v0.16b, v0.4b[2] +shadd v0.8b, v0.8b, v0.8b +shl d7, d10, #12 +shl v0.16b, v0.16b, #3 +shl v0.2d, v0.2d, #3 +shl v0.4h, v0.4h, #3 +shl v0.4s, v0.4s, #3 +shll v0.2d, v0.2s, #32 +shll v0.4s, v0.4h, #16 +shll v0.8h, v0.8b, #8 +shll v0.2d, v0.2s, #32 +shll v0.4s, v0.4h, #16 +shll v0.8h, v0.8b, #8 +shll2 v0.2d, v0.4s, #32 +shll2 v0.4s, v0.8h, #16 +shll2 v0.8h, v0.16b, #8 +shll2 v0.2d, v0.4s, #32 +shll2 v0.4s, v0.8h, #16 +shll2 v0.8h, v0.16b, #8 +shrn v0.2s, v0.2d, #3 +shrn v0.4h, v0.4s, #3 +shrn v0.8b, v0.8h, #3 +shrn2 v0.16b, v0.8h, #3 +shrn2 v0.4s, v0.2d, #3 +shrn2 v0.8h, v0.4s, #3 +shsub v0.2s, v0.2s, v0.2s +shsub v0.4h, v0.4h, v0.4h +sli d10, d14, #12 +sli v0.16b, v0.16b, #3 +sli v0.2d, v0.2d, #3 +sli v0.2s, v0.2s, #3 +sli v0.4h, v0.4h, #3 +sli v0.4s, v0.4s, #3 +sli v0.8b, v0.8b, #3 +sli v0.8h, v0.8h, #3 +smax v0.2s, v0.2s, v0.2s +smax v0.4h, v0.4h, v0.4h +smax v0.8b, v0.8b, v0.8b +smaxp v0.2s, v0.2s, v0.2s +smaxp v0.4h, v0.4h, v0.4h +smaxp v0.8b, v0.8b, v0.8b +smaxv b0, v0.8b +smaxv b0, v0.16b +smaxv h0, v0.4h +smaxv h0, v0.8h +smaxv s0, v0.4s +smin v0.16b, v0.16b, v0.16b +smin v0.4s, v0.4s, v0.4s +smin v0.8h, v0.8h, v0.8h +sminp v0.16b, v0.16b, v0.16b +sminp v0.4s, v0.4s, v0.4s +sminp v0.8h, v0.8h, v0.8h +sminv b0, v0.8b +sminv b0, v0.16b +sminv h0, v0.4h +sminv h0, v0.8h +sminv s0, v0.4s +smlal v0.2d, v0.2s, v0.2s +smlal v0.4s, v0.4h, v0.4h +smlal v0.8h, v0.8b, v0.8b +smlal2 v0.2d, v0.4s, v0.4s +smlal2 v0.4s, v0.8h, v0.8h +smlal2 v0.8h, v0.16b, v0.16b +smlsl v0.2d, v0.2s, v0.2s +smlsl v0.4s, v0.4h, v0.4h +smlsl v0.8h, v0.8b, v0.8b +smlsl2 v0.2d, v0.4s, v0.4s +smlsl2 v0.4s, v0.8h, v0.8h +smlsl2 v0.8h, v0.16b, v0.16b +smmla v0.4s, v0.16b, v0.16b +smull v0.2d, v0.2s, v0.2s +smull v0.4s, v0.4h, v0.4h +smull v0.8h, v0.8b, v0.8b +smull2 v0.2d, v0.4s, v0.4s +smull2 v0.4s, v0.8h, v0.8h +smull2 v0.8h, v0.16b, v0.16b +sqabs b19, b14 +sqabs d18, d12 +sqabs h21, h15 +sqabs s20, s12 +sqabs v0.16b, v0.16b +sqabs v0.2d, v0.2d +sqabs v0.2s, v0.2s +sqabs v0.4h, v0.4h +sqabs v0.4s, v0.4s +sqabs v0.8b, v0.8b +sqabs v0.8h, v0.8h +sqadd b20, b11, b15 +sqadd v0.16b, v0.16b, v0.16b +sqadd v0.2s, v0.2s, v0.2s +sqdmlal d19, s24, s12 +sqdmlal d8, s9, v0.s[1] +sqdmlal s0, h0, v0.h[3] +sqdmlal s17, h27, h12 +sqdmlal v0.2d, v0.2s, v0.2s +sqdmlal v0.4s, v0.4h, v0.4h +sqdmlal2 v0.2d, v0.4s, v0.4s +sqdmlal2 v0.4s, v0.8h, v0.8h +sqdmlsl d12, s23, s13 +sqdmlsl d8, s9, v0.s[1] +sqdmlsl s0, h0, v0.h[3] +sqdmlsl s14, h12, h25 +sqdmlsl v0.2d, v0.2s, v0.2s +sqdmlsl v0.4s, v0.4h, v0.4h +sqdmlsl2 v0.2d, v0.4s, v0.4s +sqdmlsl2 v0.4s, v0.8h, v0.8h +sqdmulh h10, h11, h12 +sqdmulh h7, h15, v0.h[3] +sqdmulh s15, s14, v0.s[1] +sqdmulh s20, s21, s2 +sqdmulh v0.2s, v0.2s, v0.2s +sqdmulh v0.4s, v0.4s, v0.4s +sqdmull d1, s1, v0.s[1] +sqdmull d15, s22, s12 +sqdmull s1, h1, v0.h[3] +sqdmull s12, h22, h12 +sqdmull v0.2d, v0.2s, v0.2s +sqdmull v0.4s, v0.4h, v0.4h +sqdmull2 v0.2d, v0.4s, v0.4s +sqdmull2 v0.4s, v0.8h, v0.8h +sqneg b19, b14 +sqneg d18, d12 +sqneg h21, h15 +sqneg s20, s12 +sqneg v0.16b, v0.16b +sqneg v0.2d, v0.2d +sqneg v0.2s, v0.2s +sqneg v0.4h, v0.4h +sqneg v0.4s, v0.4s +sqneg v0.8b, v0.8b +sqneg v0.8h, v0.8h +sqrdmlah h0, h1, v2.h[3] +sqrdmlah v0.4h, v1.4h, v2.h[3] +sqrdmlah v0.8h, v1.8h, v2.h[3] +sqrdmlah s0, s1, v2.s[1] +sqrdmlah v0.2s, v1.2s, v2.s[1] +sqrdmlah v0.4s, v1.4s, v2.s[1] +sqrdmlah h0, h1, h2 +sqrdmlah v0.4h, v1.4h, v2.4h +sqrdmlah v0.8h, v1.8h, v2.8h +sqrdmlah s0, s1, s2 +sqrdmlah v0.2s, v1.2s, v2.2s +sqrdmlah v0.4s, v1.4s, v2.4s +sqrdmlsh h0, h1, v2.h[3] +sqrdmlsh v0.4h, v1.4h, v2.h[3] +sqrdmlsh v0.8h, v1.8h, v2.h[3] +sqrdmlsh s0, s1, v2.s[1] +sqrdmlsh v0.2s, v1.2s, v2.s[1] +sqrdmlsh v0.4s, v1.4s, v2.s[1] +sqrdmlsh h0, h1, h2 +sqrdmlsh v0.4h, v1.4h, v2.4h +sqrdmlsh v0.8h, v1.8h, v2.8h +sqrdmlsh s0, s1, s2 +sqrdmlsh v0.2s, v1.2s, v2.2s +sqrdmlsh v0.4s, v1.4s, v2.4s +sqrdmulh h10, h11, h12 +sqrdmulh h7, h15, v0.h[3] +sqrdmulh s15, s14, v0.s[1] +sqrdmulh s20, s21, s2 +sqrdmulh v0.4h, v0.4h, v0.4h +sqrdmulh v0.8h, v0.8h, v0.8h +sqrshl d31, d31, d31 +sqrshl h3, h4, h15 +sqrshl v0.2s, v0.2s, v0.2s +sqrshl v0.4h, v0.4h, v0.4h +sqrshl v0.8b, v0.8b, v0.8b +sqrshrn b10, h13, #2 +sqrshrn h15, s10, #6 +sqrshrn s15, d12, #9 +sqrshrn v0.2s, v0.2d, #3 +sqrshrn v0.4h, v0.4s, #3 +sqrshrn v0.8b, v0.8h, #3 +sqrshrn2 v0.16b, v0.8h, #3 +sqrshrn2 v0.4s, v0.2d, #3 +sqrshrn2 v0.8h, v0.4s, #3 +sqrshrun b17, h10, #6 +sqrshrun h10, s13, #15 +sqrshrun s22, d16, #31 +sqrshrun v0.2s, v0.2d, #3 +sqrshrun v0.4h, v0.4s, #3 +sqrshrun v0.8b, v0.8h, #3 +sqrshrun2 v0.16b, v0.8h, #3 +sqrshrun2 v0.4s, v0.2d, #3 +sqrshrun2 v0.8h, v0.4s, #3 +sqshl b11, b19, #7 +sqshl d15, d16, #51 +sqshl d31, d31, d31 +sqshl h13, h18, #11 +sqshl h3, h4, h15 +sqshl s14, s17, #22 +sqshl v0.16b, v0.16b, #3 +sqshl v0.2d, v0.2d, #3 +sqshl v0.2s, v0.2s, #3 +sqshl v0.2s, v0.2s, v0.2s +sqshl v0.4h, v0.4h, #3 +sqshl v0.4h, v0.4h, v0.4h +sqshl v0.4s, v0.4s, #3 +sqshl v0.8b, v0.8b, #3 +sqshl v0.8b, v0.8b, v0.8b +sqshl v0.8h, v0.8h, #3 +sqshlu b15, b18, #6 +sqshlu d11, d13, #32 +sqshlu h19, h17, #6 +sqshlu s16, s14, #25 +sqshlu v0.16b, v0.16b, #3 +sqshlu v0.2d, v0.2d, #3 +sqshlu v0.2s, v0.2s, #3 +sqshlu v0.4h, v0.4h, #3 +sqshlu v0.4s, v0.4s, #3 +sqshlu v0.8b, v0.8b, #3 +sqshlu v0.8h, v0.8h, #3 +sqshrn b10, h15, #5 +sqshrn h17, s10, #4 +sqshrn s18, d10, #31 +sqshrn v0.2s, v0.2d, #3 +sqshrn v0.4h, v0.4s, #3 +sqshrn v0.8b, v0.8h, #3 +sqshrn2 v0.16b, v0.8h, #3 +sqshrn2 v0.4s, v0.2d, #3 +sqshrn2 v0.8h, v0.4s, #3 +sqshrun b15, h10, #7 +sqshrun h20, s14, #3 +sqshrun s10, d15, #15 +sqshrun v0.2s, v0.2d, #3 +sqshrun v0.4h, v0.4s, #3 +sqshrun v0.8b, v0.8h, #3 +sqshrun2 v0.16b, v0.8h, #3 +sqshrun2 v0.4s, v0.2d, #3 +sqshrun2 v0.8h, v0.4s, #3 +sqsub s20, s10, s7 +sqsub v0.2d, v0.2d, v0.2d +sqsub v0.4s, v0.4s, v0.4s +sqsub v0.8b, v0.8b, v0.8b +sqxtn b18, h18 +sqxtn h20, s17 +sqxtn s19, d14 +sqxtn v0.2s, v0.2d +sqxtn v0.4h, v0.4s +sqxtn v0.8b, v0.8h +sqxtn2 v0.16b, v0.8h +sqxtn2 v0.4s, v0.2d +sqxtn2 v0.8h, v0.4s +sqxtun b19, h14 +sqxtun h21, s15 +sqxtun s20, d12 +sqxtun v0.2s, v0.2d +sqxtun v0.4h, v0.4s +sqxtun v0.8b, v0.8h +sqxtun2 v0.16b, v0.8h +sqxtun2 v0.4s, v0.2d +sqxtun2 v0.8h, v0.4s +srhadd v0.2s, v0.2s, v0.2s +srhadd v0.4h, v0.4h, v0.4h +srhadd v0.8b, v0.8b, v0.8b +sri d10, d12, #14 +sri v0.16b, v0.16b, #3 +sri v0.2d, v0.2d, #3 +sri v0.2s, v0.2s, #3 +sri v0.4h, v0.4h, #3 +sri v0.4s, v0.4s, #3 +sri v0.8b, v0.8b, #3 +sri v0.8h, v0.8h, #3 +srshl d16, d16, d16 +srshl v0.2s, v0.2s, v0.2s +srshl v0.4h, v0.4h, v0.4h +srshl v0.8b, v0.8b, v0.8b +srshr d19, d18, #7 +srshr v0.16b, v0.16b, #3 +srshr v0.2d, v0.2d, #3 +srshr v0.2s, v0.2s, #3 +srshr v0.4h, v0.4h, #3 +srshr v0.4s, v0.4s, #3 +srshr v0.8b, v0.8b, #3 +srshr v0.8h, v0.8h, #3 +srsra d15, d11, #19 +srsra v0.16b, v0.16b, #3 +srsra v0.2d, v0.2d, #3 +srsra v0.2s, v0.2s, #3 +srsra v0.4h, v0.4h, #3 +srsra v0.4s, v0.4s, #3 +srsra v0.8b, v0.8b, #3 +srsra v0.8h, v0.8h, #3 +sshl d31, d31, d31 +sshl v0.2d, v0.2d, v0.2d +sshl v0.2s, v0.2s, v0.2s +sshl v0.4h, v0.4h, v0.4h +sshl v0.8b, v0.8b, v0.8b +sshll v0.2d, v0.2s, #3 +sshll2 v0.4s, v0.8h, #3 +sshr d15, d16, #12 +sshr v0.16b, v0.16b, #3 +sshr v0.2d, v0.2d, #3 +sshr v0.2s, v0.2s, #3 +sshr v0.4h, v0.4h, #3 +sshr v0.4s, v0.4s, #3 +sshr v0.8b, v0.8b, #3 +sshr v0.8h, v0.8h, #3 +ssra d18, d12, #21 +ssra v0.16b, v0.16b, #3 +ssra v0.2d, v0.2d, #3 +ssra v0.2s, v0.2s, #3 +ssra v0.4h, v0.4h, #3 +ssra v0.4s, v0.4s, #3 +ssra v0.8b, v0.8b, #3 +ssra v0.8h, v0.8h, #3 +ssubl v0.2d, v0.2s, v0.2s +ssubl v0.4s, v0.4h, v0.4h +ssubl v0.8h, v0.8b, v0.8b +ssubl2 v0.2d, v0.4s, v0.4s +ssubl2 v0.4s, v0.8h, v0.8h +ssubl2 v0.8h, v0.16b, v0.16b +ssubw v0.2d, v0.2d, v0.2s +ssubw v0.4s, v0.4s, v0.4h +ssubw v0.8h, v0.8h, v0.8b +ssubw2 v0.2d, v0.2d, v0.4s +ssubw2 v0.4s, v0.4s, v0.8h +ssubw2 v0.8h, v0.8h, v0.16b +st1 { v0.16b }, [x0] +st1 { v0.2d, v1.2d, v2.2d }, [x0], #48 +st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] +st1 { v0.4s, v1.4s }, [sp], #32 +st1 { v0.4s, v1.4s, v2.4s }, [sp] +st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 +st1 { v0.8h }, [x15], x2 +st1 { v0.8h, v1.8h }, [x15] +st1 { v0.d }[1], [x0] +st1 { v0.d }[1], [x0], #8 +st2 { v0.16b, v1.16b }, [x0], x1 +st2 { v0.8b, v1.8b }, [x0] +st2 { v0.s, v1.s }[3], [sp] +st2 { v0.s, v1.s }[3], [sp], #8 +st3 { v0.4h, v1.4h, v2.4h }, [x15] +st3 { v0.8h, v1.8h, v2.8h }, [x15], x2 +st3 { v0.h, v1.h, v2.h }[7], [x15] +st3 { v0.h, v1.h, v2.h }[7], [x15], #6 +st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp] +st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64 +st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] +st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], x5 +sub d15, d5, d16 +sub v0.2d, v0.2d, v0.2d +sudot v0.2s, v0.8b, v0.4b[2] +sudot v0.4s, v0.16b, v0.4b[2] +suqadd b19, b14 +suqadd d18, d22 +suqadd h20, h15 +suqadd s21, s12 +suqadd v0.16b, v0.16b +suqadd v0.2d, v0.2d +suqadd v0.2s, v0.2s +suqadd v0.4h, v0.4h +suqadd v0.4s, v0.4s +suqadd v0.8b, v0.8b +suqadd v0.8h, v0.8h +tbl v0.16b, { v0.16b }, v0.16b +tbl v0.16b, { v0.16b, v1.16b }, v0.16b +tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b +tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b +tbl v0.8b, { v0.16b }, v0.8b +tbl v0.8b, { v0.16b, v1.16b }, v0.8b +tbl v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b +tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b +tbx v0.16b, { v0.16b }, v0.16b +tbx v0.16b, { v0.16b, v1.16b }, v0.16b +tbx v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b +tbx v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b +tbx v0.8b, { v0.16b }, v0.8b +tbx v0.8b, { v0.16b, v1.16b }, v0.8b +tbx v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b +tbx v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b +trn1 v0.16b, v0.16b, v0.16b +trn1 v0.2d, v0.2d, v0.2d +trn1 v0.2s, v0.2s, v0.2s +trn1 v0.4h, v0.4h, v0.4h +trn1 v0.4s, v0.4s, v0.4s +trn1 v0.8b, v0.8b, v0.8b +trn1 v0.8h, v0.8h, v0.8h +trn2 v0.16b, v0.16b, v0.16b +trn2 v0.2d, v0.2d, v0.2d +trn2 v0.2s, v0.2s, v0.2s +trn2 v0.4h, v0.4h, v0.4h +trn2 v0.4s, v0.4s, v0.4s +trn2 v0.8b, v0.8b, v0.8b +trn2 v0.8h, v0.8h, v0.8h +uaba v0.8b, v0.8b, v0.8b +uabal v0.2d, v0.2s, v0.2s +uabal v0.4s, v0.4h, v0.4h +uabal v0.8h, v0.8b, v0.8b +uabal2 v0.2d, v0.4s, v0.4s +uabal2 v0.4s, v0.8h, v0.8h +uabal2 v0.8h, v0.16b, v0.16b +uabd v0.4h, v0.4h, v0.4h +uabdl v0.2d, v0.2s, v0.2s +uabdl v0.4s, v0.4h, v0.4h +uabdl v0.8h, v0.8b, v0.8b +uabdl2 v0.2d, v0.4s, v0.4s +uabdl2 v0.4s, v0.8h, v0.8h +uabdl2 v0.8h, v0.16b, v0.16b +uadalp v0.1d, v0.2s +uadalp v0.2d, v0.4s +uadalp v0.2s, v0.4h +uadalp v0.4h, v0.8b +uadalp v0.4s, v0.8h +uadalp v0.8h, v0.16b +uaddl v0.2d, v0.2s, v0.2s +uaddl v0.4s, v0.4h, v0.4h +uaddl v0.8h, v0.8b, v0.8b +uaddl2 v0.2d, v0.4s, v0.4s +uaddl2 v0.4s, v0.8h, v0.8h +uaddl2 v0.8h, v0.16b, v0.16b +uaddlp v0.1d, v0.2s +uaddlp v0.2d, v0.4s +uaddlp v0.2s, v0.4h +uaddlp v0.4h, v0.8b +uaddlp v0.4s, v0.8h +uaddlp v0.8h, v0.16b +uaddlv d0, v0.4s +uaddlv s0, v0.4h +uaddlv s0, v0.8h +uaddlv h0, v0.8b +uaddlv h0, v0.16b +uaddw v0.2d, v0.2d, v0.2s +uaddw v0.4s, v0.4s, v0.4h +uaddw v0.8h, v0.8h, v0.8b +uaddw2 v0.2d, v0.2d, v0.4s +uaddw2 v0.4s, v0.4s, v0.8h +uaddw2 v0.8h, v0.8h, v0.16b +ucvtf d21, d14 +ucvtf d21, d14, #64 +ucvtf s22, s13 +ucvtf s22, s13, #32 +ucvtf v0.2d, v0.2d +ucvtf v0.2d, v0.2d, #3 +ucvtf v0.2s, v0.2s +ucvtf v0.2s, v0.2s, #3 +ucvtf v0.4h, v0.4h +ucvtf v0.4s, v0.4s +ucvtf v0.4s, v0.4s, #3 +ucvtf v0.8h, v0.8h +udot v0.2s, v0.8b, v0.4b[2] +udot v0.2s, v0.8b, v0.8b +udot v0.4s, v0.16b, v0.16b +udot v0.4s, v0.16b, v0.4b[2] +uhadd v0.16b, v0.16b, v0.16b +uhadd v0.8h, v0.8h, v0.8h +uhsub v0.4s, v0.4s, v0.4s +umax v0.16b, v0.16b, v0.16b +umax v0.4s, v0.4s, v0.4s +umax v0.8h, v0.8h, v0.8h +umaxp v0.16b, v0.16b, v0.16b +umaxp v0.4s, v0.4s, v0.4s +umaxp v0.8h, v0.8h, v0.8h +umaxv b0, v0.8b +umaxv b0, v0.16b +umaxv h0, v0.4h +umaxv h0, v0.8h +umaxv s0, v0.4s +umin v0.2s, v0.2s, v0.2s +umin v0.4h, v0.4h, v0.4h +umin v0.8b, v0.8b, v0.8b +uminp v0.2s, v0.2s, v0.2s +uminp v0.4h, v0.4h, v0.4h +uminp v0.8b, v0.8b, v0.8b +uminv b0, v0.8b +uminv b0, v0.16b +uminv h0, v0.4h +uminv h0, v0.8h +uminv s0, v0.4s +umlal v0.2d, v0.2s, v0.2s +umlal v0.4s, v0.4h, v0.4h +umlal v0.8h, v0.8b, v0.8b +umlal2 v0.2d, v0.4s, v0.4s +umlal2 v0.4s, v0.8h, v0.8h +umlal2 v0.8h, v0.16b, v0.16b +umlsl v0.2d, v0.2s, v0.2s +umlsl v0.4s, v0.4h, v0.4h +umlsl v0.8h, v0.8b, v0.8b +umlsl2 v0.2d, v0.4s, v0.4s +umlsl2 v0.4s, v0.8h, v0.8h +umlsl2 v0.8h, v0.16b, v0.16b +ummla v0.4s, v0.16b, v0.16b +umov w0, v0.b[1] +umov w0, v0.h[1] +umov w0, v0.s[1] +umov x0, v0.d[1] +umull v0.2d, v0.2s, v0.2s +umull v0.4s, v0.4h, v0.4h +umull v0.8h, v0.8b, v0.8b +umull2 v0.2d, v0.4s, v0.4s +umull2 v0.4s, v0.8h, v0.8h +umull2 v0.8h, v0.16b, v0.16b +uqadd h0, h1, h5 +uqadd v0.8h, v0.8h, v0.8h +uqrshl b11, b20, b30 +uqrshl s23, s20, s16 +uqrshl v0.16b, v0.16b, v0.16b +uqrshl v0.4s, v0.4s, v0.4s +uqrshl v0.4s, v0.4s, v0.4s +uqrshl v0.8h, v0.8h, v0.8h +uqrshrn b10, h12, #5 +uqrshrn h12, s10, #14 +uqrshrn s10, d10, #25 +uqrshrn v0.2s, v0.2d, #3 +uqrshrn v0.4h, v0.4s, #3 +uqrshrn v0.8b, v0.8h, #3 +uqrshrn2 v0.16b, v0.8h, #3 +uqrshrn2 v0.4s, v0.2d, #3 +uqrshrn2 v0.8h, v0.4s, #3 +uqshl b11, b20, b30 +uqshl b18, b15, #6 +uqshl d15, d12, #19 +uqshl h11, h18, #7 +uqshl s14, s19, #18 +uqshl s23, s20, s16 +uqshl v0.16b, v0.16b, #3 +uqshl v0.16b, v0.16b, v0.16b +uqshl v0.2d, v0.2d, #3 +uqshl v0.2d, v0.2d, v0.2d +uqshl v0.2s, v0.2s, #3 +uqshl v0.4h, v0.4h, #3 +uqshl v0.4s, v0.4s, #3 +uqshl v0.4s, v0.4s, v0.4s +uqshl v0.8b, v0.8b, #3 +uqshl v0.8h, v0.8h, #3 +uqshl v0.8h, v0.8h, v0.8h +uqshrn b12, h10, #7 +uqshrn h10, s14, #5 +uqshrn s10, d12, #13 +uqshrn v0.2s, v0.2d, #3 +uqshrn v0.4h, v0.4s, #3 +uqshrn v0.8b, v0.8h, #3 +uqshrn2 v0.16b, v0.8h, #3 +uqshrn2 v0.4s, v0.2d, #3 +uqshrn2 v0.8h, v0.4s, #3 +uqsub d16, d16, d16 +uqsub v0.4h, v0.4h, v0.4h +uqxtn b18, h18 +uqxtn h20, s17 +uqxtn s19, d14 +uqxtn v0.2s, v0.2d +uqxtn v0.4h, v0.4s +uqxtn v0.8b, v0.8h +uqxtn2 v0.16b, v0.8h +uqxtn2 v0.4s, v0.2d +uqxtn2 v0.8h, v0.4s +urecpe v0.2s, v0.2s +urecpe v0.4s, v0.4s +urhadd v0.16b, v0.16b, v0.16b +urhadd v0.4s, v0.4s, v0.4s +urhadd v0.8h, v0.8h, v0.8h +urshl d8, d7, d4 +urshl v0.16b, v0.16b, v0.16b +urshl v0.2d, v0.2d, v0.2d +urshl v0.4s, v0.4s, v0.4s +urshl v0.8h, v0.8h, v0.8h +urshr d20, d23, #31 +urshr v0.16b, v0.16b, #3 +urshr v0.2d, v0.2d, #3 +urshr v0.2s, v0.2s, #3 +urshr v0.4h, v0.4h, #3 +urshr v0.4s, v0.4s, #3 +urshr v0.8b, v0.8b, #3 +urshr v0.8h, v0.8h, #3 +ursqrte v0.2s, v0.2s +ursqrte v0.4s, v0.4s +ursra d18, d10, #13 +ursra v0.16b, v0.16b, #3 +ursra v0.2d, v0.2d, #3 +ursra v0.2s, v0.2s, #3 +ursra v0.4h, v0.4h, #3 +ursra v0.4s, v0.4s, #3 +ursra v0.8b, v0.8b, #3 +ursra v0.8h, v0.8h, #3 +usdot v0.2s, v0.8b, v0.4b[2] +usdot v0.2s, v0.8b, v0.8b +usdot v0.4s, v0.16b, v0.16b +usdot v0.4s, v0.16b, v0.4b[2] +ushl d0, d0, d0 +ushl v0.16b, v0.16b, v0.16b +ushl v0.4s, v0.4s, v0.4s +ushl v0.8h, v0.8h, v0.8h +ushll v0.4s, v0.4h, #3 +ushll2 v0.8h, v0.16b, #3 +ushr d10, d17, #18 +ushr v0.16b, v0.16b, #3 +ushr v0.2d, v0.2d, #3 +ushr v0.2s, v0.2s, #3 +ushr v0.4h, v0.4h, #3 +ushr v0.4s, v0.4s, #3 +ushr v0.8b, v0.8b, #3 +ushr v0.8h, v0.8h, #3 +usmmla v0.4s, v0.16b, v0.16b +smov w0, v0.b[1] +smov w0, v0.h[1] +smov x0, v0.b[1] +smov x0, v0.h[1] +smov x0, v0.s[1] +usqadd b19, b14 +usqadd d18, d22 +usqadd h20, h15 +usqadd s21, s12 +usqadd v0.16b, v0.16b +usqadd v0.2d, v0.2d +usqadd v0.2s, v0.2s +usqadd v0.4h, v0.4h +usqadd v0.4s, v0.4s +usqadd v0.8b, v0.8b +usqadd v0.8h, v0.8h +usra d20, d13, #61 +usra v0.16b, v0.16b, #3 +usra v0.2d, v0.2d, #3 +usra v0.2s, v0.2s, #3 +usra v0.4h, v0.4h, #3 +usra v0.4s, v0.4s, #3 +usra v0.8b, v0.8b, #3 +usra v0.8h, v0.8h, #3 +usubl v0.2d, v0.2s, v0.2s +usubl v0.4s, v0.4h, v0.4h +usubl v0.8h, v0.8b, v0.8b +usubl2 v0.2d, v0.4s, v0.4s +usubl2 v0.4s, v0.8h, v0.8h +usubl2 v0.8h, v0.16b, v0.16b +usubw v0.2d, v0.2d, v0.2s +usubw v0.4s, v0.4s, v0.4h +usubw v0.8h, v0.8h, v0.8b +usubw2 v0.2d, v0.2d, v0.4s +usubw2 v0.4s, v0.4s, v0.8h +usubw2 v0.8h, v0.8h, v0.16b +uzp1 v0.16b, v0.16b, v0.16b +uzp1 v0.2d, v0.2d, v0.2d +uzp1 v0.2s, v0.2s, v0.2s +uzp1 v0.4h, v0.4h, v0.4h +uzp1 v0.4s, v0.4s, v0.4s +uzp1 v0.8b, v0.8b, v0.8b +uzp1 v0.8h, v0.8h, v0.8h +uzp2 v0.16b, v0.16b, v0.16b +uzp2 v0.2d, v0.2d, v0.2d +uzp2 v0.2s, v0.2s, v0.2s +uzp2 v0.4h, v0.4h, v0.4h +uzp2 v0.4s, v0.4s, v0.4s +uzp2 v0.8b, v0.8b, v0.8b +uzp2 v0.8h, v0.8h, v0.8h +xtn v0.2s, v0.2d +xtn v0.4h, v0.4s +xtn v0.8b, v0.8h +xtn2 v0.16b, v0.8h +xtn2 v0.4s, v0.2d +xtn2 v0.8h, v0.4s +zip1 v0.16b, v0.16b, v0.16b +zip1 v0.2d, v0.2d, v0.2d +zip1 v0.2s, v0.2s, v0.2s +zip1 v0.4h, v0.4h, v0.4h +zip1 v0.4s, v0.4s, v0.4s +zip1 v0.8b, v0.8b, v0.8b +zip1 v0.8h, v0.8h, v0.8h +zip2 v0.16b, v0.16b, v0.16b +zip2 v0.2d, v0.2d, v0.2d +zip2 v0.2s, v0.2s, v0.2s +zip2 v0.4h, v0.4h, v0.4h +zip2 v0.4s, v0.4s, v0.4s +zip2 v0.8b, v0.8b, v0.8b +zip2 v0.8h, v0.8h, v0.8h + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 2 0.25 abs d29, d24 +# CHECK-NEXT: 1 2 0.25 abs v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 abs v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 abs v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 abs v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 abs v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 abs v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 abs v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 add d17, d31, d29 +# CHECK-NEXT: 1 2 0.25 add v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 addhn v0.2s, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 addhn v0.4h, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 addhn v0.8b, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 addhn2 v0.16b, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 addhn2 v0.4s, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 addhn2 v0.8h, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 addp v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 addp v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.50 addv s0, v0.4s +# CHECK-NEXT: 1 2 0.50 addv h0, v0.4h +# CHECK-NEXT: 2 4 0.50 addv h0, v0.8h +# CHECK-NEXT: 2 4 0.50 addv b0, v0.8b +# CHECK-NEXT: 2 4 1.00 addv b0, v0.16b +# CHECK-NEXT: 1 2 0.25 aesd v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 aese v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 aesimc v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 aesmc v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 and v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 3 0.50 bfcvt h0, s0 +# CHECK-NEXT: 2 4 1.00 bfcvtn v0.4h, v0.4s +# CHECK-NEXT: 2 4 1.00 bfcvtn2 v0.8h, v0.4s +# CHECK-NEXT: 1 5 0.25 bfdot v0.2s, v0.4h, v0.4h +# CHECK-NEXT: 1 5 0.25 bfdot v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 5 0.25 bfmlalb v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 5 0.25 bfmlalb v0.4s, v0.8h, v0.h[3] +# CHECK-NEXT: 1 5 0.25 bfmlalt v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 5 0.25 bfmlalt v0.4s, v0.8h, v0.h[3] +# CHECK-NEXT: 1 6 0.25 bfmmla v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 bic v0.4h, #15, lsl #8 +# CHECK-NEXT: 1 2 0.25 bic v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 bif v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 bit v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 bsl v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 cls v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 cls v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 cls v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 cls v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 cls v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 cls v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 clz v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 clz v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 clz v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 clz v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 clz v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 clz v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 cmeq d20, d21, #0 +# CHECK-NEXT: 1 2 0.25 cmeq d20, d21, d22 +# CHECK-NEXT: 1 2 0.25 cmeq v0.16b, v0.16b, #0 +# CHECK-NEXT: 1 2 0.25 cmeq v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 cmge d20, d21, #0 +# CHECK-NEXT: 1 2 0.25 cmge d20, d21, d22 +# CHECK-NEXT: 1 2 0.25 cmge v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 cmge v0.8b, v0.8b, #0 +# CHECK-NEXT: 1 2 0.25 cmgt d20, d21, #0 +# CHECK-NEXT: 1 2 0.25 cmgt d20, d21, d22 +# CHECK-NEXT: 1 2 0.25 cmgt v0.2s, v0.2s, #0 +# CHECK-NEXT: 1 2 0.25 cmgt v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 cmhi d20, d21, d22 +# CHECK-NEXT: 1 2 0.25 cmhi v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 cmhs d20, d21, d22 +# CHECK-NEXT: 1 2 0.25 cmhs v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 cmle d20, d21, #0 +# CHECK-NEXT: 1 2 0.25 cmle v0.2d, v0.2d, #0 +# CHECK-NEXT: 1 2 0.25 cmlt d20, d21, #0 +# CHECK-NEXT: 1 2 0.25 cmlt v0.8h, v0.8h, #0 +# CHECK-NEXT: 1 2 0.25 cmtst d20, d21, d22 +# CHECK-NEXT: 1 2 0.25 cmtst v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 cnt v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 cnt v0.8b, v0.8b +# CHECK-NEXT: 1 3 1.00 dup v0.16b, w28 +# CHECK-NEXT: 1 3 1.00 dup v0.2d, x28 +# CHECK-NEXT: 1 3 1.00 dup v0.2s, w28 +# CHECK-NEXT: 1 3 1.00 dup v0.4h, w28 +# CHECK-NEXT: 1 3 1.00 dup v0.4s, w28 +# CHECK-NEXT: 1 3 1.00 dup v0.8b, w28 +# CHECK-NEXT: 1 3 1.00 dup v0.8h, w28 +# CHECK-NEXT: 1 2 0.25 mov b0, v0.b[1] +# CHECK-NEXT: 1 2 0.25 mov d0, v0.d[1] +# CHECK-NEXT: 1 2 0.25 mov h0, v0.h[1] +# CHECK-NEXT: 1 2 0.25 mov s0, v0.s[1] +# CHECK-NEXT: 1 2 0.25 dup v0.16b, v0.b[1] +# CHECK-NEXT: 1 2 0.25 dup v0.2d, v0.d[1] +# CHECK-NEXT: 1 2 0.25 dup v0.2s, v0.s[1] +# CHECK-NEXT: 1 2 0.25 dup v0.4h, v0.h[1] +# CHECK-NEXT: 1 2 0.25 dup v0.4s, v0.s[1] +# CHECK-NEXT: 1 2 0.25 dup v0.8b, v0.b[1] +# CHECK-NEXT: 1 2 0.25 dup v0.8h, v0.h[1] +# CHECK-NEXT: 1 2 0.25 eor v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 ext v0.16b, v0.16b, v0.16b, #3 +# CHECK-NEXT: 1 2 0.25 ext v0.8b, v0.8b, v0.8b, #3 +# CHECK-NEXT: 1 2 0.25 fabd d29, d24, d20 +# CHECK-NEXT: 1 2 0.25 fabd s29, s24, s20 +# CHECK-NEXT: 1 2 0.25 fabd v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 fabs v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 fabs v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 fabs v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 fabs v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 fabs v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 facge d20, d21, d22 +# CHECK-NEXT: 1 2 0.25 facge s10, s11, s12 +# CHECK-NEXT: 1 2 0.25 facge v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 facgt d20, d21, d22 +# CHECK-NEXT: 1 2 0.25 facgt s10, s11, s12 +# CHECK-NEXT: 1 2 0.25 facgt v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 fadd v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 faddp v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 faddp v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 fcadd v0.2s, v0.2s, v0.2s, #90 +# CHECK-NEXT: 1 2 0.25 fcadd v0.4s, v0.4s, v0.4s, #270 +# CHECK-NEXT: 1 2 0.25 fcmeq d20, d21, #0.0 +# CHECK-NEXT: 1 2 0.25 fcmeq d20, d21, d22 +# CHECK-NEXT: 1 2 0.25 fcmeq s10, s11, #0.0 +# CHECK-NEXT: 1 2 0.25 fcmeq s10, s11, s12 +# CHECK-NEXT: 1 2 0.25 fcmeq v0.2s, v0.2s, #0.0 +# CHECK-NEXT: 1 2 0.25 fcmeq v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 fcmge d20, d21, #0.0 +# CHECK-NEXT: 1 2 0.25 fcmge d20, d21, d22 +# CHECK-NEXT: 1 2 0.25 fcmge s10, s11, #0.0 +# CHECK-NEXT: 1 2 0.25 fcmge s10, s11, s12 +# CHECK-NEXT: 1 2 0.25 fcmge v0.2d, v0.2d, #0.0 +# CHECK-NEXT: 1 2 0.25 fcmge v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 fcmgt d20, d21, #0.0 +# CHECK-NEXT: 1 2 0.25 fcmgt d20, d21, d22 +# CHECK-NEXT: 1 2 0.25 fcmgt s10, s11, #0.0 +# CHECK-NEXT: 1 2 0.25 fcmgt s10, s11, s12 +# CHECK-NEXT: 1 2 0.25 fcmgt v0.4s, v0.4s, #0.0 +# CHECK-NEXT: 1 2 0.25 fcmgt v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.25 fcmla v0.2s, v0.2s, v0.2s, #90 +# CHECK-NEXT: 1 4 0.25 fcmla v0.4s, v0.4s, v0.s[1], #0 +# CHECK-NEXT: 1 2 0.25 fcmle d20, d21, #0.0 +# CHECK-NEXT: 1 2 0.25 fcmle s10, s11, #0.0 +# CHECK-NEXT: 1 2 0.25 fcmle v0.2d, v0.2d, #0.0 +# CHECK-NEXT: 1 2 0.25 fcmlt d20, d21, #0.0 +# CHECK-NEXT: 1 2 0.25 fcmlt s10, s11, #0.0 +# CHECK-NEXT: 1 2 0.25 fcmlt v0.4s, v0.4s, #0.0 +# CHECK-NEXT: 1 3 0.50 fcvtas d21, d14 +# CHECK-NEXT: 2 4 1.00 fcvtas s12, s13 +# CHECK-NEXT: 4 6 2.00 fcvtas h12, h13 +# CHECK-NEXT: 1 3 0.50 fcvtas v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 fcvtas v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 fcvtas v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 fcvtas v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 fcvtas v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 fcvtau d21, d14 +# CHECK-NEXT: 2 4 1.00 fcvtau s12, s13 +# CHECK-NEXT: 4 6 2.00 fcvtau h12, h13 +# CHECK-NEXT: 1 3 0.50 fcvtau v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 fcvtau v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 fcvtau v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 fcvtau v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 fcvtau v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 fcvtl v0.2d, v0.2s +# CHECK-NEXT: 2 4 1.00 fcvtl v0.4s, v0.4h +# CHECK-NEXT: 1 3 0.50 fcvtl2 v0.2d, v0.4s +# CHECK-NEXT: 2 4 1.00 fcvtl2 v0.4s, v0.8h +# CHECK-NEXT: 1 3 0.50 fcvtms d21, d14 +# CHECK-NEXT: 2 4 1.00 fcvtms s22, s13 +# CHECK-NEXT: 4 6 2.00 fcvtms h22, h13 +# CHECK-NEXT: 1 3 0.50 fcvtms v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 fcvtms v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 fcvtms v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 fcvtms v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 fcvtms v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 fcvtmu d21, d14 +# CHECK-NEXT: 2 4 1.00 fcvtmu s12, s13 +# CHECK-NEXT: 4 6 2.00 fcvtmu h12, h13 +# CHECK-NEXT: 1 3 0.50 fcvtmu v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 fcvtmu v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 fcvtmu v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 fcvtmu v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 fcvtmu v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 fcvtn v0.2s, v0.2d +# CHECK-NEXT: 2 4 1.00 fcvtn v0.4h, v0.4s +# CHECK-NEXT: 1 3 0.50 fcvtn2 v0.4s, v0.2d +# CHECK-NEXT: 2 4 1.00 fcvtn2 v0.8h, v0.4s +# CHECK-NEXT: 1 3 0.50 fcvtns d21, d14 +# CHECK-NEXT: 2 4 1.00 fcvtns s22, s13 +# CHECK-NEXT: 4 6 2.00 fcvtns h22, h13 +# CHECK-NEXT: 1 3 0.50 fcvtns v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 fcvtns v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 fcvtns v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 fcvtns v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 fcvtns v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 fcvtnu d21, d14 +# CHECK-NEXT: 2 4 1.00 fcvtnu s12, s13 +# CHECK-NEXT: 4 6 2.00 fcvtnu h12, h13 +# CHECK-NEXT: 1 3 0.50 fcvtnu v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 fcvtnu v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 fcvtnu v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 fcvtnu v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 fcvtnu v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 fcvtps d21, d14 +# CHECK-NEXT: 2 4 1.00 fcvtps s22, s13 +# CHECK-NEXT: 4 6 2.00 fcvtps h22, h13 +# CHECK-NEXT: 1 3 0.50 fcvtps v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 fcvtps v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 fcvtps v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 fcvtps v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 fcvtps v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 fcvtpu d21, d14 +# CHECK-NEXT: 2 4 1.00 fcvtpu s12, s13 +# CHECK-NEXT: 4 6 2.00 fcvtpu h12, h13 +# CHECK-NEXT: 1 3 0.50 fcvtpu v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 fcvtpu v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 fcvtpu v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 fcvtpu v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 fcvtpu v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 fcvtxn s22, d13 +# CHECK-NEXT: 1 3 0.50 fcvtxn v0.2s, v0.2d +# CHECK-NEXT: 1 3 0.50 fcvtxn2 v0.4s, v0.2d +# CHECK-NEXT: 1 3 0.50 fcvtzs d21, d12, #1 +# CHECK-NEXT: 1 3 0.50 fcvtzs d21, d14 +# CHECK-NEXT: 2 4 1.00 fcvtzs s12, s13 +# CHECK-NEXT: 2 4 1.00 fcvtzs s21, s12, #1 +# CHECK-NEXT: 4 6 2.00 fcvtzs h21, h14 +# CHECK-NEXT: 4 6 2.00 fcvtzs h21, h12, #1 +# CHECK-NEXT: 1 3 0.50 fcvtzs v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 fcvtzs v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 3 0.50 fcvtzs v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 fcvtzs v0.2s, v0.2s, #3 +# CHECK-NEXT: 2 4 1.00 fcvtzs v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 fcvtzs v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 fcvtzs v0.4s, v0.4s, #3 +# CHECK-NEXT: 4 6 2.00 fcvtzs v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 fcvtzu d21, d12, #1 +# CHECK-NEXT: 1 3 0.50 fcvtzu d21, d14 +# CHECK-NEXT: 2 4 1.00 fcvtzu s12, s13 +# CHECK-NEXT: 2 4 1.00 fcvtzu s21, s12, #1 +# CHECK-NEXT: 4 6 2.00 fcvtzu h12, h13 +# CHECK-NEXT: 4 6 2.00 fcvtzu h21, h12, #1 +# CHECK-NEXT: 1 3 0.50 fcvtzu v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 fcvtzu v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 3 0.50 fcvtzu v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 fcvtzu v0.2s, v0.2s, #3 +# CHECK-NEXT: 2 4 1.00 fcvtzu v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 fcvtzu v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 fcvtzu v0.4s, v0.4s, #3 +# CHECK-NEXT: 4 6 2.00 fcvtzu v0.8h, v0.8h +# CHECK-NEXT: 1 15 7.00 fdiv v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 10 2.50 fdiv v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 7 3.50 fdiv v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 10 5.00 fdiv v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 13 6.50 fdiv v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 fmax v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 fmax v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 fmax v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 fmaxnm v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 fmaxnm v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 fmaxnm v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 fmaxnmp v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 fmaxnmp v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 fmaxnmp v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 fmaxp v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 fmaxp v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 fmaxp v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 2 4 0.50 fmaxv h0, v0.4h +# CHECK-NEXT: 3 6 0.75 fmaxv h0, v0.8h +# CHECK-NEXT: 2 4 0.50 fmaxv s0, v0.4s +# CHECK-NEXT: 1 2 0.25 fmin v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 fmin v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 fmin v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 fminnm v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 fminnm v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 fminnm v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 fminnmp v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 fminnmp v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 fminnmp v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 fminp v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 fminp v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 fminp v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.25 fmla d0, d1, v0.d[1] +# CHECK-NEXT: 1 4 0.25 fmla s0, s1, v0.s[3] +# CHECK-NEXT: 1 4 0.25 fmla v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 4 0.25 fmlal v0.2s, v0.2h, v0.h[1] +# CHECK-NEXT: 1 4 0.25 fmlal v0.4s, v0.4h, v0.h[3] +# CHECK-NEXT: 1 4 0.25 fmlal v0.2s, v0.2h, v0.2h +# CHECK-NEXT: 1 4 0.25 fmlal v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 4 0.25 fmlal2 v0.2s, v0.2h, v0.h[1] +# CHECK-NEXT: 1 4 0.25 fmlal2 v0.4s, v0.4h, v0.h[3] +# CHECK-NEXT: 1 4 0.25 fmlal2 v0.2s, v0.2h, v0.2h +# CHECK-NEXT: 1 4 0.25 fmlal2 v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 4 0.25 fmls d0, d4, v0.d[1] +# CHECK-NEXT: 1 4 0.25 fmls s3, s5, v0.s[3] +# CHECK-NEXT: 1 4 0.25 fmls v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 4 0.25 fmlsl v0.2s, v0.2h, v0.h[1] +# CHECK-NEXT: 1 4 0.25 fmlsl v0.4s, v0.4h, v0.h[3] +# CHECK-NEXT: 1 4 0.25 fmlsl v0.2s, v0.2h, v0.2h +# CHECK-NEXT: 1 4 0.25 fmlsl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 4 0.25 fmlsl2 v0.2s, v0.2h, v0.h[1] +# CHECK-NEXT: 1 4 0.25 fmlsl2 v0.4s, v0.4h, v0.h[3] +# CHECK-NEXT: 1 4 0.25 fmlsl2 v0.2s, v0.2h, v0.2h +# CHECK-NEXT: 1 4 0.25 fmlsl2 v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 fmov v0.2d, #-1.25000000 +# CHECK-NEXT: 1 2 0.25 fmov v0.2s, #13.00000000 +# CHECK-NEXT: 1 2 0.25 fmov v0.4s, #1.00000000 +# CHECK-NEXT: 1 3 0.25 fmul d0, d1, v0.d[1] +# CHECK-NEXT: 1 3 0.25 fmul s0, s1, v0.s[3] +# CHECK-NEXT: 1 3 0.25 fmul v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 3 0.25 fmulx d0, d4, v0.d[1] +# CHECK-NEXT: 1 2 0.25 fmulx d23, d11, d1 +# CHECK-NEXT: 1 2 0.25 fmulx s20, s22, s15 +# CHECK-NEXT: 1 3 0.25 fmulx s3, s5, v0.s[3] +# CHECK-NEXT: 1 3 0.25 fmulx v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.25 fmulx v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 3 0.25 fmulx v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 fneg v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 fneg v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 fneg v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 fneg v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 fneg v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 frecpe d13, d13 +# CHECK-NEXT: 1 3 0.50 frecpe s19, s14 +# CHECK-NEXT: 1 2 0.25 frecpe v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 frecpe v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 frecpe v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 frecpe v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 frecpe v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.25 frecps v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.25 frecps d22, d30, d21 +# CHECK-NEXT: 1 4 0.25 frecps s21, s16, s13 +# CHECK-NEXT: 1 3 0.50 frecpx d16, d19 +# CHECK-NEXT: 1 3 0.50 frecpx s18, s10 +# CHECK-NEXT: 1 3 0.50 frint32x v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 frint32x v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 frint32x v0.4s, v0.4s +# CHECK-NEXT: 1 3 0.50 frint32z v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 frint32z v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 frint32z v0.4s, v0.4s +# CHECK-NEXT: 1 3 0.50 frint64x v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 frint64x v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 frint64x v0.4s, v0.4s +# CHECK-NEXT: 1 3 0.50 frint64z v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 frint64z v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 frint64z v0.4s, v0.4s +# CHECK-NEXT: 1 3 0.50 frinta v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 frinta v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 frinta v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 frinta v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 frinta v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 frinti v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 frinti v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 frinti v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 frinti v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 frinti v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 frintm v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 frintm v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 frintm v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 frintm v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 frintm v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 frintn v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 frintn v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 frintn v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 frintn v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 frintn v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 frintp v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 frintp v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 frintp v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 frintp v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 frintp v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 frintx v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 frintx v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 frintx v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 frintx v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 frintx v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 frintz v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 frintz v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 frintz v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 frintz v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 frintz v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 frsqrte d21, d12 +# CHECK-NEXT: 1 3 0.50 frsqrte s22, s13 +# CHECK-NEXT: 1 2 0.25 frsqrte v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.50 frsqrte v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 frsqrte v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 frsqrte v0.4s, v0.4s +# CHECK-NEXT: 4 6 2.00 frsqrte v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.25 frsqrts d8, d22, d18 +# CHECK-NEXT: 1 4 0.25 frsqrts s21, s5, s12 +# CHECK-NEXT: 1 4 0.25 frsqrts v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 16 7.50 fsqrt v0.2d, v0.2d +# CHECK-NEXT: 1 10 2.50 fsqrt v0.2s, v0.2s +# CHECK-NEXT: 1 7 3.50 fsqrt v0.4h, v0.4h +# CHECK-NEXT: 1 10 4.50 fsqrt v0.4s, v0.4s +# CHECK-NEXT: 1 13 6.50 fsqrt v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 fsub v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 6 0.33 * ld1 { v0.16b }, [x0] +# CHECK-NEXT: 4 6 1.00 * ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48 +# CHECK-NEXT: 4 7 1.33 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] +# CHECK-NEXT: 3 6 0.67 * ld1 { v0.4s, v1.4s }, [sp], #32 +# CHECK-NEXT: 3 6 1.00 * ld1 { v0.4s, v1.4s, v2.4s }, [sp] +# CHECK-NEXT: 5 7 1.33 * ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 +# CHECK-NEXT: 2 6 0.33 * ld1 { v0.8h }, [x15], x2 +# CHECK-NEXT: 2 6 0.67 * ld1 { v0.8h, v1.8h }, [x15] +# CHECK-NEXT: 2 8 0.33 * ld1 { v0.b }[9], [x0] +# CHECK-NEXT: 3 8 0.33 * ld1 { v0.b }[9], [x0], #1 +# CHECK-NEXT: 2 8 0.33 * ld1r { v0.16b }, [x0] +# CHECK-NEXT: 3 8 0.33 * ld1r { v0.16b }, [x0], #1 +# CHECK-NEXT: 2 8 0.33 * ld1r { v0.8h }, [x15] +# CHECK-NEXT: 3 8 0.33 * ld1r { v0.8h }, [x15], #2 +# CHECK-NEXT: 5 8 0.67 * ld2 { v0.16b, v1.16b }, [x0], x1 +# CHECK-NEXT: 3 8 0.50 * ld2 { v0.8b, v1.8b }, [x0] +# CHECK-NEXT: 3 8 0.50 * ld2 { v0.h, v1.h }[7], [x15] +# CHECK-NEXT: 4 8 0.50 * ld2 { v0.h, v1.h }[7], [x15], #4 +# CHECK-NEXT: 3 8 0.50 * ld2r { v0.2d, v1.2d }, [x0] +# CHECK-NEXT: 4 8 0.50 * ld2r { v0.2d, v1.2d }, [x0], #16 +# CHECK-NEXT: 3 8 0.50 * ld2r { v0.4s, v1.4s }, [sp] +# CHECK-NEXT: 4 8 0.50 * ld2r { v0.4s, v1.4s }, [sp], #8 +# CHECK-NEXT: 5 8 0.75 * ld3 { v0.4h, v1.4h, v2.4h }, [x15] +# CHECK-NEXT: 7 8 1.00 * ld3 { v0.8h, v1.8h, v2.8h }, [x15], x2 +# CHECK-NEXT: 5 8 0.75 * ld3 { v0.s, v1.s, v2.s }[3], [sp] +# CHECK-NEXT: 6 8 0.75 * ld3 { v0.s, v1.s, v2.s }[3], [sp], x3 +# CHECK-NEXT: 5 8 0.75 * ld3r { v0.4h, v1.4h, v2.4h }, [x15] +# CHECK-NEXT: 6 8 0.75 * ld3r { v0.4h, v1.4h, v2.4h }, [x15], #6 +# CHECK-NEXT: 5 8 0.75 * ld3r { v0.8b, v1.8b, v2.8b }, [x0] +# CHECK-NEXT: 6 8 0.75 * ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3 +# CHECK-NEXT: 7 8 1.00 * ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp] +# CHECK-NEXT: 11 9 2.00 * ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64 +# CHECK-NEXT: 7 8 1.00 * ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] +# CHECK-NEXT: 8 8 1.00 * ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 +# CHECK-NEXT: 8 8 1.00 * ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0 +# CHECK-NEXT: 7 8 1.00 * ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp] +# CHECK-NEXT: 8 8 1.00 * ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp], x7 +# CHECK-NEXT: 7 8 1.00 * ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp] +# CHECK-NEXT: 8 8 1.00 * ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x30 +# CHECK-NEXT: 1 4 0.50 mla v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 4 0.50 mls v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 mov b0, v0.b[15] +# CHECK-NEXT: 1 2 0.25 mov d6, v0.d[1] +# CHECK-NEXT: 1 2 0.25 mov h2, v0.h[5] +# CHECK-NEXT: 1 2 0.25 mov s17, v0.s[2] +# CHECK-NEXT: 1 2 0.25 mov v2.b[0], v0.b[0] +# CHECK-NEXT: 1 2 0.25 mov v2.h[1], v0.h[1] +# CHECK-NEXT: 1 2 0.25 mov v2.s[2], v0.s[2] +# CHECK-NEXT: 1 2 0.25 mov v2.d[1], v0.d[1] +# CHECK-NEXT: 2 5 1.00 mov v0.b[0], w8 +# CHECK-NEXT: 2 5 1.00 mov v0.h[1], w8 +# CHECK-NEXT: 2 5 1.00 mov v0.s[2], w8 +# CHECK-NEXT: 2 5 1.00 mov v0.d[1], x8 +# CHECK-NEXT: 1 2 0.25 mov v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 mov v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 movi d15, #0xff00ff00ff00ff +# CHECK-NEXT: 1 2 0.25 movi v0.16b, #31 +# CHECK-NEXT: 1 2 0.25 movi v0.2d, #0xff0000ff0000ffff +# CHECK-NEXT: 1 2 0.25 movi v0.2s, #8, msl #8 +# CHECK-NEXT: 1 2 0.25 movi v0.4s, #255, lsl #24 +# CHECK-NEXT: 1 2 0.25 movi v0.8b, #255 +# CHECK-NEXT: 1 4 0.50 mul v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 mvni v0.2s, #0 +# CHECK-NEXT: 1 2 0.25 mvni v0.4s, #16, msl #16 +# CHECK-NEXT: 1 2 0.25 neg d29, d24 +# CHECK-NEXT: 1 2 0.25 neg v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 neg v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 neg v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 neg v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 neg v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 neg v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 neg v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 mvn v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 mvn v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 orn v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 mov v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 orr v0.8h, #31 +# CHECK-NEXT: 1 3 0.50 pmul v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 3 0.50 pmul v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 3 0.50 pmull v0.8h, v0.8b, v0.8b +# CHECK-NEXT: 1 3 0.50 pmull2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 raddhn v0.2s, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 raddhn v0.4h, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 raddhn v0.8b, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 raddhn2 v0.16b, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 raddhn2 v0.4s, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 raddhn2 v0.8h, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 rbit v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 rbit v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 rev16 v21.8b, v1.8b +# CHECK-NEXT: 1 2 0.25 rev16 v30.16b, v31.16b +# CHECK-NEXT: 1 2 0.25 rev32 v0.4h, v9.4h +# CHECK-NEXT: 1 2 0.25 rev32 v21.8b, v1.8b +# CHECK-NEXT: 1 2 0.25 rev32 v30.16b, v31.16b +# CHECK-NEXT: 1 2 0.25 rev32 v4.8h, v7.8h +# CHECK-NEXT: 1 2 0.25 rev64 v0.16b, v31.16b +# CHECK-NEXT: 1 2 0.25 rev64 v1.8b, v9.8b +# CHECK-NEXT: 1 2 0.25 rev64 v13.4h, v21.4h +# CHECK-NEXT: 1 2 0.25 rev64 v2.8h, v4.8h +# CHECK-NEXT: 1 2 0.25 rev64 v4.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 rev64 v6.4s, v8.4s +# CHECK-NEXT: 1 4 0.50 rshrn v0.2s, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 rshrn v0.4h, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 rshrn v0.8b, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 rshrn2 v0.16b, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 rshrn2 v0.4s, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 rshrn2 v0.8h, v0.4s, #3 +# CHECK-NEXT: 1 2 0.25 rsubhn v0.2s, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 rsubhn v0.4h, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 rsubhn v0.8b, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 rsubhn2 v0.16b, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 rsubhn2 v0.4s, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 rsubhn2 v0.8h, v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.50 saba v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 4 0.50 sabal v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 4 0.50 sabal v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 4 0.50 sabal v0.8h, v0.8b, v0.8b +# CHECK-NEXT: 1 4 0.50 sabal2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.50 sabal2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.50 sabal2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 sabd v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 sabdl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 sabdl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 sabdl v0.8h, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 sabdl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 sabdl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 sabdl2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: 1 4 0.50 sadalp v0.1d, v0.2s +# CHECK-NEXT: 1 4 0.50 sadalp v0.2d, v0.4s +# CHECK-NEXT: 1 4 0.50 sadalp v0.2s, v0.4h +# CHECK-NEXT: 1 4 0.50 sadalp v0.4h, v0.8b +# CHECK-NEXT: 1 4 0.50 sadalp v0.4s, v0.8h +# CHECK-NEXT: 1 4 0.50 sadalp v0.8h, v0.16b +# CHECK-NEXT: 1 2 0.25 saddl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 saddl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 saddl v0.8h, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 saddl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 saddl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 saddl2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 saddlp v0.1d, v0.2s +# CHECK-NEXT: 1 2 0.25 saddlp v0.2d, v0.4s +# CHECK-NEXT: 1 2 0.25 saddlp v0.2s, v0.4h +# CHECK-NEXT: 1 2 0.25 saddlp v0.4h, v0.8b +# CHECK-NEXT: 1 2 0.25 saddlp v0.4s, v0.8h +# CHECK-NEXT: 1 2 0.25 saddlp v0.8h, v0.16b +# CHECK-NEXT: 1 2 0.50 saddlv d0, v0.4s +# CHECK-NEXT: 1 2 0.50 saddlv s0, v0.4h +# CHECK-NEXT: 2 4 0.50 saddlv s0, v0.8h +# CHECK-NEXT: 2 4 0.50 saddlv h0, v0.8b +# CHECK-NEXT: 2 4 1.00 saddlv h0, v0.16b +# CHECK-NEXT: 1 2 0.25 saddw v0.2d, v0.2d, v0.2s +# CHECK-NEXT: 1 2 0.25 saddw v0.4s, v0.4s, v0.4h +# CHECK-NEXT: 1 2 0.25 saddw v0.8h, v0.8h, v0.8b +# CHECK-NEXT: 1 2 0.25 saddw2 v0.2d, v0.2d, v0.4s +# CHECK-NEXT: 1 2 0.25 saddw2 v0.4s, v0.4s, v0.8h +# CHECK-NEXT: 1 2 0.25 saddw2 v0.8h, v0.8h, v0.16b +# CHECK-NEXT: 1 3 0.50 scvtf d21, d12 +# CHECK-NEXT: 1 3 0.50 scvtf d21, d12, #64 +# CHECK-NEXT: 2 4 1.00 scvtf s22, s13 +# CHECK-NEXT: 2 4 1.00 scvtf s22, s13, #32 +# CHECK-NEXT: 1 3 0.50 scvtf v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 scvtf v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 3 0.50 scvtf v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 scvtf v0.2s, v0.2s, #3 +# CHECK-NEXT: 2 4 1.00 scvtf v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 scvtf v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 scvtf v0.4s, v0.4s, #3 +# CHECK-NEXT: 4 6 2.00 scvtf v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.25 sdot v0.2s, v0.8b, v0.4b[2] +# CHECK-NEXT: 1 3 0.25 sdot v0.2s, v0.8b, v0.8b +# CHECK-NEXT: 1 3 0.25 sdot v0.4s, v0.16b, v0.16b +# CHECK-NEXT: 1 3 0.25 sdot v0.4s, v0.16b, v0.4b[2] +# CHECK-NEXT: 1 2 0.25 shadd v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.50 shl d7, d10, #12 +# CHECK-NEXT: 1 2 0.50 shl v0.16b, v0.16b, #3 +# CHECK-NEXT: 1 2 0.50 shl v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 2 0.50 shl v0.4h, v0.4h, #3 +# CHECK-NEXT: 1 2 0.50 shl v0.4s, v0.4s, #3 +# CHECK-NEXT: 1 2 0.50 shll v0.2d, v0.2s, #32 +# CHECK-NEXT: 1 2 0.50 shll v0.4s, v0.4h, #16 +# CHECK-NEXT: 1 2 0.50 shll v0.8h, v0.8b, #8 +# CHECK-NEXT: 1 2 0.50 shll v0.2d, v0.2s, #32 +# CHECK-NEXT: 1 2 0.50 shll v0.4s, v0.4h, #16 +# CHECK-NEXT: 1 2 0.50 shll v0.8h, v0.8b, #8 +# CHECK-NEXT: 1 2 0.50 shll2 v0.2d, v0.4s, #32 +# CHECK-NEXT: 1 2 0.50 shll2 v0.4s, v0.8h, #16 +# CHECK-NEXT: 1 2 0.50 shll2 v0.8h, v0.16b, #8 +# CHECK-NEXT: 1 2 0.50 shll2 v0.2d, v0.4s, #32 +# CHECK-NEXT: 1 2 0.50 shll2 v0.4s, v0.8h, #16 +# CHECK-NEXT: 1 2 0.50 shll2 v0.8h, v0.16b, #8 +# CHECK-NEXT: 1 2 0.50 shrn v0.2s, v0.2d, #3 +# CHECK-NEXT: 1 2 0.50 shrn v0.4h, v0.4s, #3 +# CHECK-NEXT: 1 2 0.50 shrn v0.8b, v0.8h, #3 +# CHECK-NEXT: 1 2 0.50 shrn2 v0.16b, v0.8h, #3 +# CHECK-NEXT: 1 2 0.50 shrn2 v0.4s, v0.2d, #3 +# CHECK-NEXT: 1 2 0.50 shrn2 v0.8h, v0.4s, #3 +# CHECK-NEXT: 1 2 0.25 shsub v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 shsub v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.50 sli d10, d14, #12 +# CHECK-NEXT: 1 2 0.50 sli v0.16b, v0.16b, #3 +# CHECK-NEXT: 1 2 0.50 sli v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 2 0.50 sli v0.2s, v0.2s, #3 +# CHECK-NEXT: 1 2 0.50 sli v0.4h, v0.4h, #3 +# CHECK-NEXT: 1 2 0.50 sli v0.4s, v0.4s, #3 +# CHECK-NEXT: 1 2 0.50 sli v0.8b, v0.8b, #3 +# CHECK-NEXT: 1 2 0.50 sli v0.8h, v0.8h, #3 +# CHECK-NEXT: 1 2 0.25 smax v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 smax v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 smax v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 smaxp v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 smaxp v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 smaxp v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 2 4 0.50 smaxv b0, v0.8b +# CHECK-NEXT: 2 4 1.00 smaxv b0, v0.16b +# CHECK-NEXT: 1 2 0.50 smaxv h0, v0.4h +# CHECK-NEXT: 2 4 0.50 smaxv h0, v0.8h +# CHECK-NEXT: 1 2 0.50 smaxv s0, v0.4s +# CHECK-NEXT: 1 2 0.25 smin v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 smin v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 smin v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 sminp v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 sminp v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 sminp v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 2 4 0.50 sminv b0, v0.8b +# CHECK-NEXT: 2 4 1.00 sminv b0, v0.16b +# CHECK-NEXT: 1 2 0.50 sminv h0, v0.4h +# CHECK-NEXT: 2 4 0.50 sminv h0, v0.8h +# CHECK-NEXT: 1 2 0.50 sminv s0, v0.4s +# CHECK-NEXT: 1 4 0.50 smlal v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 4 0.50 smlal v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 4 0.50 smlal v0.8h, v0.8b, v0.8b +# CHECK-NEXT: 1 4 0.50 smlal2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.50 smlal2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.50 smlal2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: 1 4 0.50 smlsl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 4 0.50 smlsl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 4 0.50 smlsl v0.8h, v0.8b, v0.8b +# CHECK-NEXT: 1 4 0.50 smlsl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.50 smlsl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.50 smlsl2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: 1 3 0.25 smmla v0.4s, v0.16b, v0.16b +# CHECK-NEXT: 1 3 0.50 smull v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 3 0.50 smull v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 3 0.50 smull v0.8h, v0.8b, v0.8b +# CHECK-NEXT: 1 3 0.50 smull2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 3 0.50 smull2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 smull2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 sqabs b19, b14 +# CHECK-NEXT: 1 2 0.25 sqabs d18, d12 +# CHECK-NEXT: 1 2 0.25 sqabs h21, h15 +# CHECK-NEXT: 1 2 0.25 sqabs s20, s12 +# CHECK-NEXT: 1 2 0.25 sqabs v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 sqabs v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 sqabs v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 sqabs v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 sqabs v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 sqabs v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 sqabs v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 sqadd b20, b11, b15 +# CHECK-NEXT: 1 2 0.25 sqadd v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 sqadd v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 4 0.50 sqdmlal d19, s24, s12 +# CHECK-NEXT: 1 4 0.50 sqdmlal d8, s9, v0.s[1] +# CHECK-NEXT: 1 4 0.50 sqdmlal s0, h0, v0.h[3] +# CHECK-NEXT: 1 4 0.50 sqdmlal s17, h27, h12 +# CHECK-NEXT: 1 4 0.50 sqdmlal v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 4 0.50 sqdmlal v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 4 0.50 sqdmlal2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.50 sqdmlal2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.50 sqdmlsl d12, s23, s13 +# CHECK-NEXT: 1 4 0.50 sqdmlsl d8, s9, v0.s[1] +# CHECK-NEXT: 1 4 0.50 sqdmlsl s0, h0, v0.h[3] +# CHECK-NEXT: 1 4 0.50 sqdmlsl s14, h12, h25 +# CHECK-NEXT: 1 4 0.50 sqdmlsl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 4 0.50 sqdmlsl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 4 0.50 sqdmlsl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.50 sqdmlsl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.50 sqdmulh h10, h11, h12 +# CHECK-NEXT: 1 4 0.50 sqdmulh h7, h15, v0.h[3] +# CHECK-NEXT: 1 4 0.50 sqdmulh s15, s14, v0.s[1] +# CHECK-NEXT: 1 4 0.50 sqdmulh s20, s21, s2 +# CHECK-NEXT: 1 4 0.50 sqdmulh v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 4 0.50 sqdmulh v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 3 0.50 sqdmull d1, s1, v0.s[1] +# CHECK-NEXT: 1 3 0.50 sqdmull d15, s22, s12 +# CHECK-NEXT: 1 3 0.50 sqdmull s1, h1, v0.h[3] +# CHECK-NEXT: 1 3 0.50 sqdmull s12, h22, h12 +# CHECK-NEXT: 1 3 0.50 sqdmull v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 3 0.50 sqdmull v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 3 0.50 sqdmull2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 3 0.50 sqdmull2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 sqneg b19, b14 +# CHECK-NEXT: 1 2 0.25 sqneg d18, d12 +# CHECK-NEXT: 1 2 0.25 sqneg h21, h15 +# CHECK-NEXT: 1 2 0.25 sqneg s20, s12 +# CHECK-NEXT: 1 2 0.25 sqneg v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 sqneg v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 sqneg v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 sqneg v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 sqneg v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 sqneg v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 sqneg v0.8h, v0.8h +# CHECK-NEXT: 1 4 1.00 sqrdmlah h0, h1, v2.h[3] +# CHECK-NEXT: 1 4 1.00 sqrdmlah v0.4h, v1.4h, v2.h[3] +# CHECK-NEXT: 1 4 1.00 sqrdmlah v0.8h, v1.8h, v2.h[3] +# CHECK-NEXT: 1 4 1.00 sqrdmlah s0, s1, v2.s[1] +# CHECK-NEXT: 1 4 1.00 sqrdmlah v0.2s, v1.2s, v2.s[1] +# CHECK-NEXT: 1 4 1.00 sqrdmlah v0.4s, v1.4s, v2.s[1] +# CHECK-NEXT: 1 4 1.00 sqrdmlah h0, h1, h2 +# CHECK-NEXT: 1 4 1.00 sqrdmlah v0.4h, v1.4h, v2.4h +# CHECK-NEXT: 1 4 1.00 sqrdmlah v0.8h, v1.8h, v2.8h +# CHECK-NEXT: 1 4 1.00 sqrdmlah s0, s1, s2 +# CHECK-NEXT: 1 4 1.00 sqrdmlah v0.2s, v1.2s, v2.2s +# CHECK-NEXT: 1 4 1.00 sqrdmlah v0.4s, v1.4s, v2.4s +# CHECK-NEXT: 1 4 1.00 sqrdmlsh h0, h1, v2.h[3] +# CHECK-NEXT: 1 4 1.00 sqrdmlsh v0.4h, v1.4h, v2.h[3] +# CHECK-NEXT: 1 4 1.00 sqrdmlsh v0.8h, v1.8h, v2.h[3] +# CHECK-NEXT: 1 4 1.00 sqrdmlsh s0, s1, v2.s[1] +# CHECK-NEXT: 1 4 1.00 sqrdmlsh v0.2s, v1.2s, v2.s[1] +# CHECK-NEXT: 1 4 1.00 sqrdmlsh v0.4s, v1.4s, v2.s[1] +# CHECK-NEXT: 1 4 1.00 sqrdmlsh h0, h1, h2 +# CHECK-NEXT: 1 4 1.00 sqrdmlsh v0.4h, v1.4h, v2.4h +# CHECK-NEXT: 1 4 1.00 sqrdmlsh v0.8h, v1.8h, v2.8h +# CHECK-NEXT: 1 4 1.00 sqrdmlsh s0, s1, s2 +# CHECK-NEXT: 1 4 1.00 sqrdmlsh v0.2s, v1.2s, v2.2s +# CHECK-NEXT: 1 4 1.00 sqrdmlsh v0.4s, v1.4s, v2.4s +# CHECK-NEXT: 1 4 0.50 sqrdmulh h10, h11, h12 +# CHECK-NEXT: 1 4 0.50 sqrdmulh h7, h15, v0.h[3] +# CHECK-NEXT: 1 4 0.50 sqrdmulh s15, s14, v0.s[1] +# CHECK-NEXT: 1 4 0.50 sqrdmulh s20, s21, s2 +# CHECK-NEXT: 1 4 0.50 sqrdmulh v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 4 0.50 sqrdmulh v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.50 sqrshl d31, d31, d31 +# CHECK-NEXT: 1 4 0.50 sqrshl h3, h4, h15 +# CHECK-NEXT: 1 4 0.50 sqrshl v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 4 0.50 sqrshl v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 4 0.50 sqrshl v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 4 0.50 sqrshrn b10, h13, #2 +# CHECK-NEXT: 1 4 0.50 sqrshrn h15, s10, #6 +# CHECK-NEXT: 1 4 0.50 sqrshrn s15, d12, #9 +# CHECK-NEXT: 1 4 0.50 sqrshrn v0.2s, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 sqrshrn v0.4h, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 sqrshrn v0.8b, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 sqrshrn2 v0.16b, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 sqrshrn2 v0.4s, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 sqrshrn2 v0.8h, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 sqrshrun b17, h10, #6 +# CHECK-NEXT: 1 4 0.50 sqrshrun h10, s13, #15 +# CHECK-NEXT: 1 4 0.50 sqrshrun s22, d16, #31 +# CHECK-NEXT: 1 4 0.50 sqrshrun v0.2s, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 sqrshrun v0.4h, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 sqrshrun v0.8b, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 sqrshrun2 v0.16b, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 sqrshrun2 v0.4s, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 sqrshrun2 v0.8h, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 sqshl b11, b19, #7 +# CHECK-NEXT: 1 4 0.50 sqshl d15, d16, #51 +# CHECK-NEXT: 1 4 0.50 sqshl d31, d31, d31 +# CHECK-NEXT: 1 4 0.50 sqshl h13, h18, #11 +# CHECK-NEXT: 1 4 0.50 sqshl h3, h4, h15 +# CHECK-NEXT: 1 4 0.50 sqshl s14, s17, #22 +# CHECK-NEXT: 1 4 0.50 sqshl v0.16b, v0.16b, #3 +# CHECK-NEXT: 1 4 0.50 sqshl v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 sqshl v0.2s, v0.2s, #3 +# CHECK-NEXT: 1 4 0.50 sqshl v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 4 0.50 sqshl v0.4h, v0.4h, #3 +# CHECK-NEXT: 1 4 0.50 sqshl v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 4 0.50 sqshl v0.4s, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 sqshl v0.8b, v0.8b, #3 +# CHECK-NEXT: 1 4 0.50 sqshl v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 4 0.50 sqshl v0.8h, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 sqshlu b15, b18, #6 +# CHECK-NEXT: 1 4 0.50 sqshlu d11, d13, #32 +# CHECK-NEXT: 1 4 0.50 sqshlu h19, h17, #6 +# CHECK-NEXT: 1 4 0.50 sqshlu s16, s14, #25 +# CHECK-NEXT: 1 4 0.50 sqshlu v0.16b, v0.16b, #3 +# CHECK-NEXT: 1 4 0.50 sqshlu v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 sqshlu v0.2s, v0.2s, #3 +# CHECK-NEXT: 1 4 0.50 sqshlu v0.4h, v0.4h, #3 +# CHECK-NEXT: 1 4 0.50 sqshlu v0.4s, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 sqshlu v0.8b, v0.8b, #3 +# CHECK-NEXT: 1 4 0.50 sqshlu v0.8h, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 sqshrn b10, h15, #5 +# CHECK-NEXT: 1 4 0.50 sqshrn h17, s10, #4 +# CHECK-NEXT: 1 4 0.50 sqshrn s18, d10, #31 +# CHECK-NEXT: 1 4 0.50 sqshrn v0.2s, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 sqshrn v0.4h, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 sqshrn v0.8b, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 sqshrn2 v0.16b, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 sqshrn2 v0.4s, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 sqshrn2 v0.8h, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 sqshrun b15, h10, #7 +# CHECK-NEXT: 1 4 0.50 sqshrun h20, s14, #3 +# CHECK-NEXT: 1 4 0.50 sqshrun s10, d15, #15 +# CHECK-NEXT: 1 4 0.50 sqshrun v0.2s, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 sqshrun v0.4h, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 sqshrun v0.8b, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 sqshrun2 v0.16b, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 sqshrun2 v0.4s, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 sqshrun2 v0.8h, v0.4s, #3 +# CHECK-NEXT: 1 2 0.25 sqsub s20, s10, s7 +# CHECK-NEXT: 1 2 0.25 sqsub v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 sqsub v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 sqsub v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 4 0.50 sqxtn b18, h18 +# CHECK-NEXT: 1 4 0.50 sqxtn h20, s17 +# CHECK-NEXT: 1 4 0.50 sqxtn s19, d14 +# CHECK-NEXT: 1 4 0.50 sqxtn v0.2s, v0.2d +# CHECK-NEXT: 1 4 0.50 sqxtn v0.4h, v0.4s +# CHECK-NEXT: 1 4 0.50 sqxtn v0.8b, v0.8h +# CHECK-NEXT: 1 4 0.50 sqxtn2 v0.16b, v0.8h +# CHECK-NEXT: 1 4 0.50 sqxtn2 v0.4s, v0.2d +# CHECK-NEXT: 1 4 0.50 sqxtn2 v0.8h, v0.4s +# CHECK-NEXT: 1 4 0.50 sqxtun b19, h14 +# CHECK-NEXT: 1 4 0.50 sqxtun h21, s15 +# CHECK-NEXT: 1 4 0.50 sqxtun s20, d12 +# CHECK-NEXT: 1 4 0.50 sqxtun v0.2s, v0.2d +# CHECK-NEXT: 1 4 0.50 sqxtun v0.4h, v0.4s +# CHECK-NEXT: 1 4 0.50 sqxtun v0.8b, v0.8h +# CHECK-NEXT: 1 4 0.50 sqxtun2 v0.16b, v0.8h +# CHECK-NEXT: 1 4 0.50 sqxtun2 v0.4s, v0.2d +# CHECK-NEXT: 1 4 0.50 sqxtun2 v0.8h, v0.4s +# CHECK-NEXT: 1 2 0.25 srhadd v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 srhadd v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 srhadd v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.50 sri d10, d12, #14 +# CHECK-NEXT: 1 2 0.50 sri v0.16b, v0.16b, #3 +# CHECK-NEXT: 1 2 0.50 sri v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 2 0.50 sri v0.2s, v0.2s, #3 +# CHECK-NEXT: 1 2 0.50 sri v0.4h, v0.4h, #3 +# CHECK-NEXT: 1 2 0.50 sri v0.4s, v0.4s, #3 +# CHECK-NEXT: 1 2 0.50 sri v0.8b, v0.8b, #3 +# CHECK-NEXT: 1 2 0.50 sri v0.8h, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 srshl d16, d16, d16 +# CHECK-NEXT: 1 4 0.50 srshl v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 4 0.50 srshl v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 4 0.50 srshl v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 4 0.50 srshr d19, d18, #7 +# CHECK-NEXT: 1 4 0.50 srshr v0.16b, v0.16b, #3 +# CHECK-NEXT: 1 4 0.50 srshr v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 srshr v0.2s, v0.2s, #3 +# CHECK-NEXT: 1 4 0.50 srshr v0.4h, v0.4h, #3 +# CHECK-NEXT: 1 4 0.50 srshr v0.4s, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 srshr v0.8b, v0.8b, #3 +# CHECK-NEXT: 1 4 0.50 srshr v0.8h, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 srsra d15, d11, #19 +# CHECK-NEXT: 1 4 0.50 srsra v0.16b, v0.16b, #3 +# CHECK-NEXT: 1 4 0.50 srsra v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 srsra v0.2s, v0.2s, #3 +# CHECK-NEXT: 1 4 0.50 srsra v0.4h, v0.4h, #3 +# CHECK-NEXT: 1 4 0.50 srsra v0.4s, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 srsra v0.8b, v0.8b, #3 +# CHECK-NEXT: 1 4 0.50 srsra v0.8h, v0.8h, #3 +# CHECK-NEXT: 1 2 0.50 sshl d31, d31, d31 +# CHECK-NEXT: 1 2 0.50 sshl v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.50 sshl v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.50 sshl v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.50 sshl v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.50 sshll v0.2d, v0.2s, #3 +# CHECK-NEXT: 1 2 0.50 sshll2 v0.4s, v0.8h, #3 +# CHECK-NEXT: 1 2 0.50 sshr d15, d16, #12 +# CHECK-NEXT: 1 2 0.50 sshr v0.16b, v0.16b, #3 +# CHECK-NEXT: 1 2 0.50 sshr v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 2 0.50 sshr v0.2s, v0.2s, #3 +# CHECK-NEXT: 1 2 0.50 sshr v0.4h, v0.4h, #3 +# CHECK-NEXT: 1 2 0.50 sshr v0.4s, v0.4s, #3 +# CHECK-NEXT: 1 2 0.50 sshr v0.8b, v0.8b, #3 +# CHECK-NEXT: 1 2 0.50 sshr v0.8h, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 ssra d18, d12, #21 +# CHECK-NEXT: 1 4 0.50 ssra v0.16b, v0.16b, #3 +# CHECK-NEXT: 1 4 0.50 ssra v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 ssra v0.2s, v0.2s, #3 +# CHECK-NEXT: 1 4 0.50 ssra v0.4h, v0.4h, #3 +# CHECK-NEXT: 1 4 0.50 ssra v0.4s, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 ssra v0.8b, v0.8b, #3 +# CHECK-NEXT: 1 4 0.50 ssra v0.8h, v0.8h, #3 +# CHECK-NEXT: 1 2 0.25 ssubl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 ssubl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 ssubl v0.8h, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 ssubl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 ssubl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 ssubl2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 ssubw v0.2d, v0.2d, v0.2s +# CHECK-NEXT: 1 2 0.25 ssubw v0.4s, v0.4s, v0.4h +# CHECK-NEXT: 1 2 0.25 ssubw v0.8h, v0.8h, v0.8b +# CHECK-NEXT: 1 2 0.25 ssubw2 v0.2d, v0.2d, v0.4s +# CHECK-NEXT: 1 2 0.25 ssubw2 v0.4s, v0.4s, v0.8h +# CHECK-NEXT: 1 2 0.25 ssubw2 v0.8h, v0.8h, v0.16b +# CHECK-NEXT: 2 2 0.50 * st1 { v0.16b }, [x0] +# CHECK-NEXT: 7 2 1.50 * st1 { v0.2d, v1.2d, v2.2d }, [x0], #48 +# CHECK-NEXT: 8 2 2.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] +# CHECK-NEXT: 5 2 1.00 * st1 { v0.4s, v1.4s }, [sp], #32 +# CHECK-NEXT: 6 2 1.50 * st1 { v0.4s, v1.4s, v2.4s }, [sp] +# CHECK-NEXT: 5 2 1.00 * st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 +# CHECK-NEXT: 3 2 0.50 * st1 { v0.8h }, [x15], x2 +# CHECK-NEXT: 4 2 1.00 * st1 { v0.8h, v1.8h }, [x15] +# CHECK-NEXT: 3 4 1.00 * st1 { v0.d }[1], [x0] +# CHECK-NEXT: 4 4 1.00 * st1 { v0.d }[1], [x0], #8 +# CHECK-NEXT: 7 4 2.00 * st2 { v0.16b, v1.16b }, [x0], x1 +# CHECK-NEXT: 3 4 1.00 * st2 { v0.8b, v1.8b }, [x0] +# CHECK-NEXT: 3 4 1.00 * st2 { v0.s, v1.s }[3], [sp] +# CHECK-NEXT: 4 4 1.00 * st2 { v0.s, v1.s }[3], [sp], #8 +# CHECK-NEXT: 6 5 2.00 * st3 { v0.4h, v1.4h, v2.4h }, [x15] +# CHECK-NEXT: 10 6 3.00 * st3 { v0.8h, v1.8h, v2.8h }, [x15], x2 +# CHECK-NEXT: 6 5 2.00 * st3 { v0.h, v1.h, v2.h }[7], [x15] +# CHECK-NEXT: 7 5 2.00 * st3 { v0.h, v1.h, v2.h }[7], [x15], #6 +# CHECK-NEXT: 8 6 3.00 * st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp] +# CHECK-NEXT: 17 7 6.00 * st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64 +# CHECK-NEXT: 4 6 1.50 * st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] +# CHECK-NEXT: 7 4 2.00 * st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], x5 +# CHECK-NEXT: 1 2 0.25 sub d15, d5, d16 +# CHECK-NEXT: 1 2 0.25 sub v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 3 0.25 sudot v0.2s, v0.8b, v0.4b[2] +# CHECK-NEXT: 1 3 0.25 sudot v0.4s, v0.16b, v0.4b[2] +# CHECK-NEXT: 1 2 0.25 suqadd b19, b14 +# CHECK-NEXT: 1 2 0.25 suqadd d18, d22 +# CHECK-NEXT: 1 2 0.25 suqadd h20, h15 +# CHECK-NEXT: 1 2 0.25 suqadd s21, s12 +# CHECK-NEXT: 1 2 0.25 suqadd v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 suqadd v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 suqadd v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 suqadd v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 suqadd v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 suqadd v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 suqadd v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.50 tbl v0.16b, { v0.16b }, v0.16b +# CHECK-NEXT: 1 2 0.50 tbl v0.16b, { v0.16b, v1.16b }, v0.16b +# CHECK-NEXT: 2 4 1.00 tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b +# CHECK-NEXT: 3 4 1.50 tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b +# CHECK-NEXT: 1 2 0.50 tbl v0.8b, { v0.16b }, v0.8b +# CHECK-NEXT: 1 2 0.50 tbl v0.8b, { v0.16b, v1.16b }, v0.8b +# CHECK-NEXT: 2 4 1.00 tbl v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b +# CHECK-NEXT: 3 4 1.50 tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b +# CHECK-NEXT: 1 2 0.25 tbx v0.16b, { v0.16b }, v0.16b +# CHECK-NEXT: 2 4 0.50 tbx v0.16b, { v0.16b, v1.16b }, v0.16b +# CHECK-NEXT: 3 6 0.75 tbx v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b +# CHECK-NEXT: 5 6 1.25 tbx v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b +# CHECK-NEXT: 1 2 0.25 tbx v0.8b, { v0.16b }, v0.8b +# CHECK-NEXT: 2 4 0.50 tbx v0.8b, { v0.16b, v1.16b }, v0.8b +# CHECK-NEXT: 3 6 0.75 tbx v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b +# CHECK-NEXT: 5 6 1.25 tbx v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b +# CHECK-NEXT: 1 2 0.25 trn1 v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 trn1 v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 trn1 v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 trn1 v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 trn1 v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 trn1 v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 trn1 v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 trn2 v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 trn2 v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 trn2 v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 trn2 v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 trn2 v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 trn2 v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 trn2 v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.50 uaba v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 4 0.50 uabal v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 4 0.50 uabal v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 4 0.50 uabal v0.8h, v0.8b, v0.8b +# CHECK-NEXT: 1 4 0.50 uabal2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.50 uabal2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.50 uabal2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 uabd v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 uabdl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 uabdl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 uabdl v0.8h, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 uabdl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 uabdl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 uabdl2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: 1 4 0.50 uadalp v0.1d, v0.2s +# CHECK-NEXT: 1 4 0.50 uadalp v0.2d, v0.4s +# CHECK-NEXT: 1 4 0.50 uadalp v0.2s, v0.4h +# CHECK-NEXT: 1 4 0.50 uadalp v0.4h, v0.8b +# CHECK-NEXT: 1 4 0.50 uadalp v0.4s, v0.8h +# CHECK-NEXT: 1 4 0.50 uadalp v0.8h, v0.16b +# CHECK-NEXT: 1 2 0.25 uaddl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 uaddl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 uaddl v0.8h, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 uaddl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 uaddl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 uaddl2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 uaddlp v0.1d, v0.2s +# CHECK-NEXT: 1 2 0.25 uaddlp v0.2d, v0.4s +# CHECK-NEXT: 1 2 0.25 uaddlp v0.2s, v0.4h +# CHECK-NEXT: 1 2 0.25 uaddlp v0.4h, v0.8b +# CHECK-NEXT: 1 2 0.25 uaddlp v0.4s, v0.8h +# CHECK-NEXT: 1 2 0.25 uaddlp v0.8h, v0.16b +# CHECK-NEXT: 1 2 0.50 uaddlv d0, v0.4s +# CHECK-NEXT: 1 2 0.50 uaddlv s0, v0.4h +# CHECK-NEXT: 2 4 0.50 uaddlv s0, v0.8h +# CHECK-NEXT: 2 4 0.50 uaddlv h0, v0.8b +# CHECK-NEXT: 2 4 1.00 uaddlv h0, v0.16b +# CHECK-NEXT: 1 2 0.25 uaddw v0.2d, v0.2d, v0.2s +# CHECK-NEXT: 1 2 0.25 uaddw v0.4s, v0.4s, v0.4h +# CHECK-NEXT: 1 2 0.25 uaddw v0.8h, v0.8h, v0.8b +# CHECK-NEXT: 1 2 0.25 uaddw2 v0.2d, v0.2d, v0.4s +# CHECK-NEXT: 1 2 0.25 uaddw2 v0.4s, v0.4s, v0.8h +# CHECK-NEXT: 1 2 0.25 uaddw2 v0.8h, v0.8h, v0.16b +# CHECK-NEXT: 1 3 0.50 ucvtf d21, d14 +# CHECK-NEXT: 1 3 0.50 ucvtf d21, d14, #64 +# CHECK-NEXT: 2 4 1.00 ucvtf s22, s13 +# CHECK-NEXT: 2 4 1.00 ucvtf s22, s13, #32 +# CHECK-NEXT: 1 3 0.50 ucvtf v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 ucvtf v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 3 0.50 ucvtf v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 ucvtf v0.2s, v0.2s, #3 +# CHECK-NEXT: 2 4 1.00 ucvtf v0.4h, v0.4h +# CHECK-NEXT: 2 4 1.00 ucvtf v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 ucvtf v0.4s, v0.4s, #3 +# CHECK-NEXT: 4 6 2.00 ucvtf v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.25 udot v0.2s, v0.8b, v0.4b[2] +# CHECK-NEXT: 1 3 0.25 udot v0.2s, v0.8b, v0.8b +# CHECK-NEXT: 1 3 0.25 udot v0.4s, v0.16b, v0.16b +# CHECK-NEXT: 1 3 0.25 udot v0.4s, v0.16b, v0.4b[2] +# CHECK-NEXT: 1 2 0.25 uhadd v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 uhadd v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 uhsub v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 umax v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 umax v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 umax v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 umaxp v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 umaxp v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 umaxp v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 2 4 0.50 umaxv b0, v0.8b +# CHECK-NEXT: 2 4 1.00 umaxv b0, v0.16b +# CHECK-NEXT: 1 2 0.50 umaxv h0, v0.4h +# CHECK-NEXT: 2 4 0.50 umaxv h0, v0.8h +# CHECK-NEXT: 1 2 0.50 umaxv s0, v0.4s +# CHECK-NEXT: 1 2 0.25 umin v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 umin v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 umin v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 uminp v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 uminp v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 uminp v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 2 4 0.50 uminv b0, v0.8b +# CHECK-NEXT: 2 4 1.00 uminv b0, v0.16b +# CHECK-NEXT: 1 2 0.50 uminv h0, v0.4h +# CHECK-NEXT: 2 4 0.50 uminv h0, v0.8h +# CHECK-NEXT: 1 2 0.50 uminv s0, v0.4s +# CHECK-NEXT: 1 4 0.50 umlal v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 4 0.50 umlal v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 4 0.50 umlal v0.8h, v0.8b, v0.8b +# CHECK-NEXT: 1 4 0.50 umlal2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.50 umlal2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.50 umlal2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: 1 4 0.50 umlsl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 4 0.50 umlsl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 4 0.50 umlsl v0.8h, v0.8b, v0.8b +# CHECK-NEXT: 1 4 0.50 umlsl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.50 umlsl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.50 umlsl2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: 1 3 0.25 ummla v0.4s, v0.16b, v0.16b +# CHECK-NEXT: 2 2 1.00 umov w0, v0.b[1] +# CHECK-NEXT: 2 2 1.00 umov w0, v0.h[1] +# CHECK-NEXT: 2 2 1.00 mov w0, v0.s[1] +# CHECK-NEXT: 2 2 1.00 mov x0, v0.d[1] +# CHECK-NEXT: 1 3 0.50 umull v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 3 0.50 umull v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 3 0.50 umull v0.8h, v0.8b, v0.8b +# CHECK-NEXT: 1 3 0.50 umull2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 3 0.50 umull2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 3 0.50 umull2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 uqadd h0, h1, h5 +# CHECK-NEXT: 1 2 0.25 uqadd v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.50 uqrshl b11, b20, b30 +# CHECK-NEXT: 1 4 0.50 uqrshl s23, s20, s16 +# CHECK-NEXT: 1 4 0.50 uqrshl v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 4 0.50 uqrshl v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.50 uqrshl v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.50 uqrshl v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.50 uqrshrn b10, h12, #5 +# CHECK-NEXT: 1 4 0.50 uqrshrn h12, s10, #14 +# CHECK-NEXT: 1 4 0.50 uqrshrn s10, d10, #25 +# CHECK-NEXT: 1 4 0.50 uqrshrn v0.2s, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 uqrshrn v0.4h, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 uqrshrn v0.8b, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 uqrshrn2 v0.16b, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 uqrshrn2 v0.4s, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 uqrshrn2 v0.8h, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 uqshl b11, b20, b30 +# CHECK-NEXT: 1 4 0.50 uqshl b18, b15, #6 +# CHECK-NEXT: 1 4 0.50 uqshl d15, d12, #19 +# CHECK-NEXT: 1 4 0.50 uqshl h11, h18, #7 +# CHECK-NEXT: 1 4 0.50 uqshl s14, s19, #18 +# CHECK-NEXT: 1 4 0.50 uqshl s23, s20, s16 +# CHECK-NEXT: 1 4 0.50 uqshl v0.16b, v0.16b, #3 +# CHECK-NEXT: 1 4 0.50 uqshl v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 4 0.50 uqshl v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 uqshl v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 4 0.50 uqshl v0.2s, v0.2s, #3 +# CHECK-NEXT: 1 4 0.50 uqshl v0.4h, v0.4h, #3 +# CHECK-NEXT: 1 4 0.50 uqshl v0.4s, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 uqshl v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.50 uqshl v0.8b, v0.8b, #3 +# CHECK-NEXT: 1 4 0.50 uqshl v0.8h, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 uqshl v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.50 uqshrn b12, h10, #7 +# CHECK-NEXT: 1 4 0.50 uqshrn h10, s14, #5 +# CHECK-NEXT: 1 4 0.50 uqshrn s10, d12, #13 +# CHECK-NEXT: 1 4 0.50 uqshrn v0.2s, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 uqshrn v0.4h, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 uqshrn v0.8b, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 uqshrn2 v0.16b, v0.8h, #3 +# CHECK-NEXT: 1 4 0.50 uqshrn2 v0.4s, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 uqshrn2 v0.8h, v0.4s, #3 +# CHECK-NEXT: 1 2 0.25 uqsub d16, d16, d16 +# CHECK-NEXT: 1 2 0.25 uqsub v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 4 0.50 uqxtn b18, h18 +# CHECK-NEXT: 1 4 0.50 uqxtn h20, s17 +# CHECK-NEXT: 1 4 0.50 uqxtn s19, d14 +# CHECK-NEXT: 1 4 0.50 uqxtn v0.2s, v0.2d +# CHECK-NEXT: 1 4 0.50 uqxtn v0.4h, v0.4s +# CHECK-NEXT: 1 4 0.50 uqxtn v0.8b, v0.8h +# CHECK-NEXT: 1 4 0.50 uqxtn2 v0.16b, v0.8h +# CHECK-NEXT: 1 4 0.50 uqxtn2 v0.4s, v0.2d +# CHECK-NEXT: 1 4 0.50 uqxtn2 v0.8h, v0.4s +# CHECK-NEXT: 1 3 0.50 urecpe v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 urecpe v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 urhadd v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 urhadd v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 urhadd v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.50 urshl d8, d7, d4 +# CHECK-NEXT: 1 4 0.50 urshl v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 4 0.50 urshl v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 4 0.50 urshl v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.50 urshl v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.50 urshr d20, d23, #31 +# CHECK-NEXT: 1 4 0.50 urshr v0.16b, v0.16b, #3 +# CHECK-NEXT: 1 4 0.50 urshr v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 urshr v0.2s, v0.2s, #3 +# CHECK-NEXT: 1 4 0.50 urshr v0.4h, v0.4h, #3 +# CHECK-NEXT: 1 4 0.50 urshr v0.4s, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 urshr v0.8b, v0.8b, #3 +# CHECK-NEXT: 1 4 0.50 urshr v0.8h, v0.8h, #3 +# CHECK-NEXT: 1 3 0.50 ursqrte v0.2s, v0.2s +# CHECK-NEXT: 2 4 1.00 ursqrte v0.4s, v0.4s +# CHECK-NEXT: 1 4 0.50 ursra d18, d10, #13 +# CHECK-NEXT: 1 4 0.50 ursra v0.16b, v0.16b, #3 +# CHECK-NEXT: 1 4 0.50 ursra v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 ursra v0.2s, v0.2s, #3 +# CHECK-NEXT: 1 4 0.50 ursra v0.4h, v0.4h, #3 +# CHECK-NEXT: 1 4 0.50 ursra v0.4s, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 ursra v0.8b, v0.8b, #3 +# CHECK-NEXT: 1 4 0.50 ursra v0.8h, v0.8h, #3 +# CHECK-NEXT: 1 3 0.25 usdot v0.2s, v0.8b, v0.4b[2] +# CHECK-NEXT: 1 3 0.25 usdot v0.2s, v0.8b, v0.8b +# CHECK-NEXT: 1 3 0.25 usdot v0.4s, v0.16b, v0.16b +# CHECK-NEXT: 1 3 0.25 usdot v0.4s, v0.16b, v0.4b[2] +# CHECK-NEXT: 1 2 0.50 ushl d0, d0, d0 +# CHECK-NEXT: 1 2 0.50 ushl v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.50 ushl v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.50 ushl v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.50 ushll v0.4s, v0.4h, #3 +# CHECK-NEXT: 1 2 0.50 ushll2 v0.8h, v0.16b, #3 +# CHECK-NEXT: 1 2 0.50 ushr d10, d17, #18 +# CHECK-NEXT: 1 2 0.50 ushr v0.16b, v0.16b, #3 +# CHECK-NEXT: 1 2 0.50 ushr v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 2 0.50 ushr v0.2s, v0.2s, #3 +# CHECK-NEXT: 1 2 0.50 ushr v0.4h, v0.4h, #3 +# CHECK-NEXT: 1 2 0.50 ushr v0.4s, v0.4s, #3 +# CHECK-NEXT: 1 2 0.50 ushr v0.8b, v0.8b, #3 +# CHECK-NEXT: 1 2 0.50 ushr v0.8h, v0.8h, #3 +# CHECK-NEXT: 1 3 0.25 usmmla v0.4s, v0.16b, v0.16b +# CHECK-NEXT: 2 2 1.00 smov w0, v0.b[1] +# CHECK-NEXT: 2 2 1.00 smov w0, v0.h[1] +# CHECK-NEXT: 2 2 1.00 smov x0, v0.b[1] +# CHECK-NEXT: 2 2 1.00 smov x0, v0.h[1] +# CHECK-NEXT: 2 2 1.00 smov x0, v0.s[1] +# CHECK-NEXT: 1 2 0.25 usqadd b19, b14 +# CHECK-NEXT: 1 2 0.25 usqadd d18, d22 +# CHECK-NEXT: 1 2 0.25 usqadd h20, h15 +# CHECK-NEXT: 1 2 0.25 usqadd s21, s12 +# CHECK-NEXT: 1 2 0.25 usqadd v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 usqadd v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 usqadd v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 usqadd v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 usqadd v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 usqadd v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 usqadd v0.8h, v0.8h +# CHECK-NEXT: 1 4 0.50 usra d20, d13, #61 +# CHECK-NEXT: 1 4 0.50 usra v0.16b, v0.16b, #3 +# CHECK-NEXT: 1 4 0.50 usra v0.2d, v0.2d, #3 +# CHECK-NEXT: 1 4 0.50 usra v0.2s, v0.2s, #3 +# CHECK-NEXT: 1 4 0.50 usra v0.4h, v0.4h, #3 +# CHECK-NEXT: 1 4 0.50 usra v0.4s, v0.4s, #3 +# CHECK-NEXT: 1 4 0.50 usra v0.8b, v0.8b, #3 +# CHECK-NEXT: 1 4 0.50 usra v0.8h, v0.8h, #3 +# CHECK-NEXT: 1 2 0.25 usubl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 usubl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 usubl v0.8h, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 usubl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 usubl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 usubl2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 usubw v0.2d, v0.2d, v0.2s +# CHECK-NEXT: 1 2 0.25 usubw v0.4s, v0.4s, v0.4h +# CHECK-NEXT: 1 2 0.25 usubw v0.8h, v0.8h, v0.8b +# CHECK-NEXT: 1 2 0.25 usubw2 v0.2d, v0.2d, v0.4s +# CHECK-NEXT: 1 2 0.25 usubw2 v0.4s, v0.4s, v0.8h +# CHECK-NEXT: 1 2 0.25 usubw2 v0.8h, v0.8h, v0.16b +# CHECK-NEXT: 1 2 0.25 uzp1 v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 uzp1 v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 uzp1 v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 uzp1 v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 uzp1 v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 uzp1 v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 uzp1 v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 uzp2 v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 uzp2 v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 uzp2 v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 uzp2 v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 uzp2 v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 uzp2 v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 uzp2 v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 xtn v0.2s, v0.2d +# CHECK-NEXT: 1 2 0.25 xtn v0.4h, v0.4s +# CHECK-NEXT: 1 2 0.25 xtn v0.8b, v0.8h +# CHECK-NEXT: 1 2 0.25 xtn2 v0.16b, v0.8h +# CHECK-NEXT: 1 2 0.25 xtn2 v0.4s, v0.2d +# CHECK-NEXT: 1 2 0.25 xtn2 v0.8h, v0.4s +# CHECK-NEXT: 1 2 0.25 zip1 v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 zip1 v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 zip1 v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 zip1 v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 zip1 v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 zip1 v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 zip1 v0.8h, v0.8h, v0.8h +# CHECK-NEXT: 1 2 0.25 zip2 v0.16b, v0.16b, v0.16b +# CHECK-NEXT: 1 2 0.25 zip2 v0.2d, v0.2d, v0.2d +# CHECK-NEXT: 1 2 0.25 zip2 v0.2s, v0.2s, v0.2s +# CHECK-NEXT: 1 2 0.25 zip2 v0.4h, v0.4h, v0.4h +# CHECK-NEXT: 1 2 0.25 zip2 v0.4s, v0.4s, v0.4s +# CHECK-NEXT: 1 2 0.25 zip2 v0.8b, v0.8b, v0.8b +# CHECK-NEXT: 1 2 0.25 zip2 v0.8h, v0.8h, v0.8h + +# CHECK: Resources: +# CHECK-NEXT: [0.0] - V2UnitB +# CHECK-NEXT: [0.1] - V2UnitB +# CHECK-NEXT: [1.0] - V2UnitD +# CHECK-NEXT: [1.1] - V2UnitD +# CHECK-NEXT: [2] - V2UnitL2 +# CHECK-NEXT: [3.0] - V2UnitL01 +# CHECK-NEXT: [3.1] - V2UnitL01 +# CHECK-NEXT: [4] - V2UnitM0 +# CHECK-NEXT: [5] - V2UnitM1 +# CHECK-NEXT: [6] - V2UnitS0 +# CHECK-NEXT: [7] - V2UnitS1 +# CHECK-NEXT: [8] - V2UnitS2 +# CHECK-NEXT: [9] - V2UnitS3 +# CHECK-NEXT: [10] - V2UnitV0 +# CHECK-NEXT: [11] - V2UnitV1 +# CHECK-NEXT: [12] - V2UnitV2 +# CHECK-NEXT: [13] - V2UnitV3 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] +# CHECK-NEXT: - - - - 27.33 48.83 48.83 16.17 5.17 5.17 5.17 5.17 5.17 498.25 379.25 446.75 327.75 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 abs d29, d24 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 abs v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 abs v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 abs v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 abs v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 abs v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 abs v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 abs v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add d17, d31, d29 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 addhn v0.2s, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 addhn v0.4h, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 addhn v0.8b, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 addhn2 v0.16b, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 addhn2 v0.4s, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 addhn2 v0.8h, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 addp v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 addp v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 addv s0, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 addv h0, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.75 0.25 0.75 addv h0, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.75 0.25 0.75 addv b0, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - 1.00 addv b0, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 aesd v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 aese v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 aesimc v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 aesmc v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 and v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - bfcvt h0, s0 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - bfcvtn v0.4h, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - bfcvtn2 v0.8h, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 bfdot v0.2s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 bfdot v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 bfmlalb v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 bfmlalb v0.4s, v0.8h, v0.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 bfmlalt v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 bfmlalt v0.4s, v0.8h, v0.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 bfmmla v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 bic v0.4h, #15, lsl #8 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 bic v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 bif v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 bit v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 bsl v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cls v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cls v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cls v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cls v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cls v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cls v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 clz v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 clz v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 clz v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 clz v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 clz v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 clz v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmeq d20, d21, #0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmeq d20, d21, d22 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmeq v0.16b, v0.16b, #0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmeq v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmge d20, d21, #0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmge d20, d21, d22 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmge v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmge v0.8b, v0.8b, #0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmgt d20, d21, #0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmgt d20, d21, d22 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmgt v0.2s, v0.2s, #0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmgt v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmhi d20, d21, d22 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmhi v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmhs d20, d21, d22 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmhs v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmle d20, d21, #0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmle v0.2d, v0.2d, #0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmlt d20, d21, #0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmlt v0.8h, v0.8h, #0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmtst d20, d21, d22 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cmtst v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cnt v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 cnt v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - dup v0.16b, w28 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - dup v0.2d, x28 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - dup v0.2s, w28 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - dup v0.4h, w28 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - dup v0.4s, w28 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - dup v0.8b, w28 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - dup v0.8h, w28 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mov b0, v0.b[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mov d0, v0.d[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mov h0, v0.h[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mov s0, v0.s[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 dup v0.16b, v0.b[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 dup v0.2d, v0.d[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 dup v0.2s, v0.s[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 dup v0.4h, v0.h[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 dup v0.4s, v0.s[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 dup v0.8b, v0.b[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 dup v0.8h, v0.h[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 eor v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ext v0.16b, v0.16b, v0.16b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ext v0.8b, v0.8b, v0.8b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fabd d29, d24, d20 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fabd s29, s24, s20 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fabd v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fabs v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fabs v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fabs v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fabs v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fabs v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 facge d20, d21, d22 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 facge s10, s11, s12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 facge v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 facgt d20, d21, d22 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 facgt s10, s11, s12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 facgt v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fadd v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 faddp v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 faddp v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcadd v0.2s, v0.2s, v0.2s, #90 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcadd v0.4s, v0.4s, v0.4s, #270 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmeq d20, d21, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmeq d20, d21, d22 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmeq s10, s11, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmeq s10, s11, s12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmeq v0.2s, v0.2s, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmeq v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmge d20, d21, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmge d20, d21, d22 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmge s10, s11, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmge s10, s11, s12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmge v0.2d, v0.2d, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmge v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmgt d20, d21, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmgt d20, d21, d22 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmgt s10, s11, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmgt s10, s11, s12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmgt v0.4s, v0.4s, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmgt v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmla v0.2s, v0.2s, v0.2s, #90 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmla v0.4s, v0.4s, v0.s[1], #0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmle d20, d21, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmle s10, s11, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmle v0.2d, v0.2d, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmlt d20, d21, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmlt s10, s11, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcmlt v0.4s, v0.4s, #0.0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtas d21, d14 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtas s12, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtas h12, h13 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtas v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtas v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtas v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtas v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtas v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtau d21, d14 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtau s12, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtau h12, h13 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtau v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtau v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtau v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtau v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtau v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtl v0.2d, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtl v0.4s, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtl2 v0.2d, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtl2 v0.4s, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtms d21, d14 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtms s22, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtms h22, h13 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtms v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtms v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtms v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtms v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtms v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtmu d21, d14 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtmu s12, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtmu h12, h13 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtmu v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtmu v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtmu v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtmu v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtmu v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtn v0.2s, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtn v0.4h, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtn2 v0.4s, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtn2 v0.8h, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtns d21, d14 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtns s22, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtns h22, h13 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtns v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtns v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtns v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtns v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtns v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtnu d21, d14 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtnu s12, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtnu h12, h13 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtnu v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtnu v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtnu v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtnu v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtnu v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtps d21, d14 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtps s22, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtps h22, h13 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtps v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtps v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtps v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtps v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtps v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtpu d21, d14 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtpu s12, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtpu h12, h13 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtpu v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtpu v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtpu v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtpu v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtpu v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtxn s22, d13 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtxn v0.2s, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtxn2 v0.4s, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtzs d21, d12, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtzs d21, d14 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtzs s12, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtzs s21, s12, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtzs h21, h14 +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtzs h21, h12, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtzs v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcvtzs v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtzs v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcvtzs v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtzs v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtzs v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcvtzs v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtzs v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtzu d21, d12, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtzu d21, d14 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtzu s12, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtzu s21, s12, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtzu h12, h13 +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtzu h21, h12, #1 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtzu v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcvtzu v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - fcvtzu v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcvtzu v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtzu v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - fcvtzu v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fcvtzu v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - fcvtzu v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 7.00 - 7.00 - fdiv v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 2.50 - 2.50 - fdiv v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 3.50 - 3.50 - fdiv v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 5.00 - 5.00 - fdiv v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 6.50 - 6.50 - fdiv v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmax v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmax v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmax v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmaxnm v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmaxnm v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmaxnm v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmaxnmp v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmaxnmp v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmaxnmp v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmaxp v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmaxp v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmaxp v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 fmaxv h0, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.75 0.75 0.75 0.75 fmaxv h0, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 fmaxv s0, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmin v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmin v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmin v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fminnm v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fminnm v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fminnm v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fminnmp v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fminnmp v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fminnmp v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fminp v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fminp v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fminp v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmla d0, d1, v0.d[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmla s0, s1, v0.s[3] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmla v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmlal v0.2s, v0.2h, v0.h[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmlal v0.4s, v0.4h, v0.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmlal v0.2s, v0.2h, v0.2h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmlal v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmlal2 v0.2s, v0.2h, v0.h[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmlal2 v0.4s, v0.4h, v0.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmlal2 v0.2s, v0.2h, v0.2h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmlal2 v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmls d0, d4, v0.d[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmls s3, s5, v0.s[3] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmls v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmlsl v0.2s, v0.2h, v0.h[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmlsl v0.4s, v0.4h, v0.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmlsl v0.2s, v0.2h, v0.2h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmlsl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmlsl2 v0.2s, v0.2h, v0.h[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmlsl2 v0.4s, v0.4h, v0.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmlsl2 v0.2s, v0.2h, v0.2h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmlsl2 v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmov v0.2d, #-1.25000000 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmov v0.2s, #13.00000000 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmov v0.4s, #1.00000000 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmul d0, d1, v0.d[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmul s0, s1, v0.s[3] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmul v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmulx d0, d4, v0.d[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmulx d23, d11, d1 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmulx s20, s22, s15 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmulx s3, s5, v0.s[3] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmulx v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmulx v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmulx v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fneg v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fneg v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fneg v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fneg v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fneg v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frecpe d13, d13 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frecpe s19, s14 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 frecpe v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frecpe v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frecpe v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frecpe v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - frecpe v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 frecps v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 frecps d22, d30, d21 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 frecps s21, s16, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frecpx d16, d19 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frecpx s18, s10 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frint32x v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frint32x v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frint32x v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frint32z v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frint32z v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frint32z v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frint64x v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frint64x v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frint64x v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frint64z v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frint64z v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frint64z v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frinta v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frinta v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frinta v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frinta v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - frinta v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frinti v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frinti v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frinti v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frinti v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - frinti v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintm v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintm v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frintm v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frintm v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - frintm v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintn v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintn v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frintn v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frintn v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - frintn v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintp v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintp v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frintp v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frintp v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - frintp v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintx v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintx v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frintx v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frintx v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - frintx v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintz v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frintz v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frintz v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frintz v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - frintz v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frsqrte d21, d12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frsqrte s22, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 frsqrte v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - frsqrte v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frsqrte v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - frsqrte v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - frsqrte v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 frsqrts d8, d22, d18 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 frsqrts s21, s5, s12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 frsqrts v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 7.50 - 7.50 - fsqrt v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 2.50 - 2.50 - fsqrt v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 3.50 - 3.50 - fsqrt v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 4.50 - 4.50 - fsqrt v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 6.50 - 6.50 - fsqrt v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fsub v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - ld1 { v0.16b }, [x0] +# CHECK-NEXT: - - - - 1.00 1.00 1.00 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48 +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - - - - ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] +# CHECK-NEXT: - - - - 0.67 0.67 0.67 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ld1 { v0.4s, v1.4s }, [sp], #32 +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - - - - ld1 { v0.4s, v1.4s, v2.4s }, [sp] +# CHECK-NEXT: - - - - 1.33 1.33 1.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 - - - - ld1 { v0.8h }, [x15], x2 +# CHECK-NEXT: - - - - 0.67 0.67 0.67 - - - - - - - - - - ld1 { v0.8h, v1.8h }, [x15] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - 0.25 0.25 0.25 0.25 ld1 { v0.b }[9], [x0] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 0.25 0.25 0.25 0.25 ld1 { v0.b }[9], [x0], #1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - 0.25 0.25 0.25 0.25 ld1r { v0.16b }, [x0] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 0.25 0.25 0.25 0.25 ld1r { v0.16b }, [x0], #1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - 0.25 0.25 0.25 0.25 ld1r { v0.8h }, [x15] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 0.25 0.25 0.25 0.25 ld1r { v0.8h }, [x15], #2 +# CHECK-NEXT: - - - - 0.67 0.67 0.67 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.50 0.50 ld2 { v0.16b, v1.16b }, [x0], x1 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 0.50 0.50 ld2 { v0.8b, v1.8b }, [x0] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 0.50 0.50 ld2 { v0.h, v1.h }[7], [x15] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.50 0.50 ld2 { v0.h, v1.h }[7], [x15], #4 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 0.50 0.50 ld2r { v0.2d, v1.2d }, [x0] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.50 0.50 ld2r { v0.2d, v1.2d }, [x0], #16 +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 0.50 0.50 ld2r { v0.4s, v1.4s }, [sp] +# CHECK-NEXT: - - - - 0.33 0.33 0.33 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.50 0.50 ld2r { v0.4s, v1.4s }, [sp], #8 +# CHECK-NEXT: - - - - 0.67 0.67 0.67 - - - - - - 0.75 0.75 0.75 0.75 ld3 { v0.4h, v1.4h, v2.4h }, [x15] +# CHECK-NEXT: - - - - 1.00 1.00 1.00 0.17 0.17 0.17 0.17 0.17 0.17 0.75 0.75 0.75 0.75 ld3 { v0.8h, v1.8h, v2.8h }, [x15], x2 +# CHECK-NEXT: - - - - 0.67 0.67 0.67 - - - - - - 0.75 0.75 0.75 0.75 ld3 { v0.s, v1.s, v2.s }[3], [sp] +# CHECK-NEXT: - - - - 0.67 0.67 0.67 0.17 0.17 0.17 0.17 0.17 0.17 0.75 0.75 0.75 0.75 ld3 { v0.s, v1.s, v2.s }[3], [sp], x3 +# CHECK-NEXT: - - - - 0.67 0.67 0.67 - - - - - - 0.75 0.75 0.75 0.75 ld3r { v0.4h, v1.4h, v2.4h }, [x15] +# CHECK-NEXT: - - - - 0.67 0.67 0.67 0.17 0.17 0.17 0.17 0.17 0.17 0.75 0.75 0.75 0.75 ld3r { v0.4h, v1.4h, v2.4h }, [x15], #6 +# CHECK-NEXT: - - - - 0.67 0.67 0.67 - - - - - - 0.75 0.75 0.75 0.75 ld3r { v0.8b, v1.8b, v2.8b }, [x0] +# CHECK-NEXT: - - - - 0.67 0.67 0.67 0.17 0.17 0.17 0.17 0.17 0.17 0.75 0.75 0.75 0.75 ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3 +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - 1.00 1.00 1.00 1.00 ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp] +# CHECK-NEXT: - - - - 2.00 2.00 2.00 0.17 0.17 0.17 0.17 0.17 0.17 1.00 1.00 1.00 1.00 ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64 +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - 1.00 1.00 1.00 1.00 ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] +# CHECK-NEXT: - - - - 1.00 1.00 1.00 0.17 0.17 0.17 0.17 0.17 0.17 1.00 1.00 1.00 1.00 ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 +# CHECK-NEXT: - - - - 1.00 1.00 1.00 0.17 0.17 0.17 0.17 0.17 0.17 1.00 1.00 1.00 1.00 ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0 +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - 1.00 1.00 1.00 1.00 ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp] +# CHECK-NEXT: - - - - 1.00 1.00 1.00 0.17 0.17 0.17 0.17 0.17 0.17 1.00 1.00 1.00 1.00 ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp], x7 +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - 1.00 1.00 1.00 1.00 ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp] +# CHECK-NEXT: - - - - 1.00 1.00 1.00 0.17 0.17 0.17 0.17 0.17 0.17 1.00 1.00 1.00 1.00 ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x30 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - mla v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - mls v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mov b0, v0.b[15] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mov d6, v0.d[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mov h2, v0.h[5] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mov s17, v0.s[2] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mov v2.b[0], v0.b[0] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mov v2.h[1], v0.h[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mov v2.s[2], v0.s[2] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mov v2.d[1], v0.d[1] +# CHECK-NEXT: - - - - - - - 1.00 - - - - - 0.25 0.25 0.25 0.25 mov v0.b[0], w8 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - 0.25 0.25 0.25 0.25 mov v0.h[1], w8 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - 0.25 0.25 0.25 0.25 mov v0.s[2], w8 +# CHECK-NEXT: - - - - - - - 1.00 - - - - - 0.25 0.25 0.25 0.25 mov v0.d[1], x8 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mov v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mov v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 movi d15, #0xff00ff00ff00ff +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 movi v0.16b, #31 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 movi v0.2d, #0xff0000ff0000ffff +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 movi v0.2s, #8, msl #8 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 movi v0.4s, #255, lsl #24 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 movi v0.8b, #255 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - mul v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mvni v0.2s, #0 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mvni v0.4s, #16, msl #16 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 neg d29, d24 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 neg v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 neg v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 neg v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 neg v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 neg v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 neg v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 neg v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mvn v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mvn v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 orn v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 mov v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 orr v0.8h, #31 +# CHECK-NEXT: - - - - - - - - - - - - - - - 0.50 0.50 pmul v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - - - 0.50 0.50 pmul v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - - 0.50 0.50 pmull v0.8h, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - - 0.50 0.50 pmull2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 raddhn v0.2s, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 raddhn v0.4h, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 raddhn v0.8b, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 raddhn2 v0.16b, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 raddhn2 v0.4s, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 raddhn2 v0.8h, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rbit v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rbit v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rev16 v21.8b, v1.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rev16 v30.16b, v31.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rev32 v0.4h, v9.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rev32 v21.8b, v1.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rev32 v30.16b, v31.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rev32 v4.8h, v7.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rev64 v0.16b, v31.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rev64 v1.8b, v9.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rev64 v13.4h, v21.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rev64 v2.8h, v4.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rev64 v4.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rev64 v6.4s, v8.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 rshrn v0.2s, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 rshrn v0.4h, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 rshrn v0.8b, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 rshrn2 v0.16b, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 rshrn2 v0.4s, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 rshrn2 v0.8h, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rsubhn v0.2s, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rsubhn v0.4h, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rsubhn v0.8b, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rsubhn2 v0.16b, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rsubhn2 v0.4s, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 rsubhn2 v0.8h, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 saba v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sabal v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sabal v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sabal v0.8h, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sabal2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sabal2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sabal2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sabd v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sabdl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sabdl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sabdl v0.8h, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sabdl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sabdl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sabdl2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sadalp v0.1d, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sadalp v0.2d, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sadalp v0.2s, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sadalp v0.4h, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sadalp v0.4s, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sadalp v0.8h, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddl v0.8h, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddl2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddlp v0.1d, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddlp v0.2d, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddlp v0.2s, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddlp v0.4h, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddlp v0.4s, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddlp v0.8h, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 saddlv d0, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 saddlv s0, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.75 0.25 0.75 saddlv s0, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.75 0.25 0.75 saddlv h0, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - 1.00 saddlv h0, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddw v0.2d, v0.2d, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddw v0.4s, v0.4s, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddw v0.8h, v0.8h, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddw2 v0.2d, v0.2d, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddw2 v0.4s, v0.4s, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 saddw2 v0.8h, v0.8h, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - scvtf d21, d12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - scvtf d21, d12, #64 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - scvtf s22, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - scvtf s22, s13, #32 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - scvtf v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 scvtf v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - scvtf v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 scvtf v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - scvtf v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - scvtf v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 scvtf v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - scvtf v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sdot v0.2s, v0.8b, v0.4b[2] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sdot v0.2s, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sdot v0.4s, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sdot v0.4s, v0.16b, v0.4b[2] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 shadd v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shl d7, d10, #12 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shl v0.16b, v0.16b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shl v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shl v0.4h, v0.4h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shl v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shll v0.2d, v0.2s, #32 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shll v0.4s, v0.4h, #16 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shll v0.8h, v0.8b, #8 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shll v0.2d, v0.2s, #32 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shll v0.4s, v0.4h, #16 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shll v0.8h, v0.8b, #8 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shll2 v0.2d, v0.4s, #32 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shll2 v0.4s, v0.8h, #16 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shll2 v0.8h, v0.16b, #8 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shll2 v0.2d, v0.4s, #32 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shll2 v0.4s, v0.8h, #16 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shll2 v0.8h, v0.16b, #8 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shrn v0.2s, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shrn v0.4h, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shrn v0.8b, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shrn2 v0.16b, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shrn2 v0.4s, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 shrn2 v0.8h, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 shsub v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 shsub v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sli d10, d14, #12 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sli v0.16b, v0.16b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sli v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sli v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sli v0.4h, v0.4h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sli v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sli v0.8b, v0.8b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sli v0.8h, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 smax v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 smax v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 smax v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 smaxp v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 smaxp v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 smaxp v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.75 0.25 0.75 smaxv b0, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - 1.00 smaxv b0, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 smaxv h0, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.75 0.25 0.75 smaxv h0, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 smaxv s0, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 smin v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 smin v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 smin v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sminp v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sminp v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sminp v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.75 0.25 0.75 sminv b0, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - 1.00 sminv b0, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sminv h0, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.75 0.25 0.75 sminv h0, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sminv s0, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smlal v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smlal v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smlal v0.8h, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smlal2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smlal2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smlal2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smlsl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smlsl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smlsl v0.8h, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smlsl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smlsl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smlsl2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 smmla v0.4s, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smull v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smull v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smull v0.8h, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smull2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smull2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - smull2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqabs b19, b14 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqabs d18, d12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqabs h21, h15 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqabs s20, s12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqabs v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqabs v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqabs v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqabs v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqabs v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqabs v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqabs v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqadd b20, b11, b15 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqadd v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqadd v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmlal d19, s24, s12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmlal d8, s9, v0.s[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmlal s0, h0, v0.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmlal s17, h27, h12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmlal v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmlal v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmlal2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmlal2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmlsl d12, s23, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmlsl d8, s9, v0.s[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmlsl s0, h0, v0.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmlsl s14, h12, h25 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmlsl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmlsl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmlsl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmlsl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmulh h10, h11, h12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmulh h7, h15, v0.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmulh s15, s14, v0.s[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmulh s20, s21, s2 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmulh v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmulh v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmull d1, s1, v0.s[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmull d15, s22, s12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmull s1, h1, v0.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmull s12, h22, h12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmull v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmull v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmull2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqdmull2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqneg b19, b14 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqneg d18, d12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqneg h21, h15 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqneg s20, s12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqneg v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqneg v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqneg v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqneg v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqneg v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqneg v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqneg v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlah h0, h1, v2.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlah v0.4h, v1.4h, v2.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlah v0.8h, v1.8h, v2.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlah s0, s1, v2.s[1] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlah v0.2s, v1.2s, v2.s[1] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlah v0.4s, v1.4s, v2.s[1] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlah h0, h1, h2 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlah v0.4h, v1.4h, v2.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlah v0.8h, v1.8h, v2.8h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlah s0, s1, s2 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlah v0.2s, v1.2s, v2.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlah v0.4s, v1.4s, v2.4s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlsh h0, h1, v2.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlsh v0.4h, v1.4h, v2.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlsh v0.8h, v1.8h, v2.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlsh s0, s1, v2.s[1] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlsh v0.2s, v1.2s, v2.s[1] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlsh v0.4s, v1.4s, v2.s[1] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlsh h0, h1, h2 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlsh v0.4h, v1.4h, v2.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlsh v0.8h, v1.8h, v2.8h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlsh s0, s1, s2 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlsh v0.2s, v1.2s, v2.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - sqrdmlsh v0.4s, v1.4s, v2.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqrdmulh h10, h11, h12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqrdmulh h7, h15, v0.h[3] +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqrdmulh s15, s14, v0.s[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqrdmulh s20, s21, s2 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqrdmulh v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - sqrdmulh v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshl d31, d31, d31 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshl h3, h4, h15 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshl v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshl v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshl v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrn b10, h13, #2 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrn h15, s10, #6 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrn s15, d12, #9 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrn v0.2s, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrn v0.4h, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrn v0.8b, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrn2 v0.16b, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrn2 v0.4s, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrn2 v0.8h, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrun b17, h10, #6 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrun h10, s13, #15 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrun s22, d16, #31 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrun v0.2s, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrun v0.4h, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrun v0.8b, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrun2 v0.16b, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrun2 v0.4s, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqrshrun2 v0.8h, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshl b11, b19, #7 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshl d15, d16, #51 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshl d31, d31, d31 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshl h13, h18, #11 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshl h3, h4, h15 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshl s14, s17, #22 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshl v0.16b, v0.16b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshl v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshl v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshl v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshl v0.4h, v0.4h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshl v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshl v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshl v0.8b, v0.8b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshl v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshl v0.8h, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshlu b15, b18, #6 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshlu d11, d13, #32 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshlu h19, h17, #6 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshlu s16, s14, #25 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshlu v0.16b, v0.16b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshlu v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshlu v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshlu v0.4h, v0.4h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshlu v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshlu v0.8b, v0.8b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshlu v0.8h, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrn b10, h15, #5 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrn h17, s10, #4 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrn s18, d10, #31 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrn v0.2s, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrn v0.4h, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrn v0.8b, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrn2 v0.16b, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrn2 v0.4s, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrn2 v0.8h, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrun b15, h10, #7 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrun h20, s14, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrun s10, d15, #15 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrun v0.2s, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrun v0.4h, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrun v0.8b, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrun2 v0.16b, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrun2 v0.4s, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqshrun2 v0.8h, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqsub s20, s10, s7 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqsub v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqsub v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sqsub v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtn b18, h18 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtn h20, s17 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtn s19, d14 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtn v0.2s, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtn v0.4h, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtn v0.8b, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtn2 v0.16b, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtn2 v0.4s, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtn2 v0.8h, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtun b19, h14 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtun h21, s15 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtun s20, d12 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtun v0.2s, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtun v0.4h, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtun v0.8b, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtun2 v0.16b, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtun2 v0.4s, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sqxtun2 v0.8h, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 srhadd v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 srhadd v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 srhadd v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sri d10, d12, #14 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sri v0.16b, v0.16b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sri v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sri v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sri v0.4h, v0.4h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sri v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sri v0.8b, v0.8b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sri v0.8h, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srshl d16, d16, d16 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srshl v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srshl v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srshl v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srshr d19, d18, #7 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srshr v0.16b, v0.16b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srshr v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srshr v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srshr v0.4h, v0.4h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srshr v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srshr v0.8b, v0.8b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srshr v0.8h, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srsra d15, d11, #19 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srsra v0.16b, v0.16b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srsra v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srsra v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srsra v0.4h, v0.4h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srsra v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srsra v0.8b, v0.8b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 srsra v0.8h, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sshl d31, d31, d31 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sshl v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sshl v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sshl v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sshl v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sshll v0.2d, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sshll2 v0.4s, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sshr d15, d16, #12 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sshr v0.16b, v0.16b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sshr v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sshr v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sshr v0.4h, v0.4h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sshr v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sshr v0.8b, v0.8b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 sshr v0.8h, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ssra d18, d12, #21 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ssra v0.16b, v0.16b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ssra v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ssra v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ssra v0.4h, v0.4h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ssra v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ssra v0.8b, v0.8b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ssra v0.8h, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ssubl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ssubl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ssubl v0.8h, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ssubl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ssubl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ssubl2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ssubw v0.2d, v0.2d, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ssubw v0.4s, v0.4s, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ssubw v0.8h, v0.8h, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ssubw2 v0.2d, v0.2d, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ssubw2 v0.4s, v0.4s, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ssubw2 v0.8h, v0.8h, v0.16b +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - st1 { v0.16b }, [x0] +# CHECK-NEXT: - - - - - 1.50 1.50 0.17 0.17 0.17 0.17 0.17 0.17 1.50 1.50 - - st1 { v0.2d, v1.2d, v2.2d }, [x0], #48 +# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - 2.00 2.00 - - st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] +# CHECK-NEXT: - - - - - 1.00 1.00 0.17 0.17 0.17 0.17 0.17 0.17 1.00 1.00 - - st1 { v0.4s, v1.4s }, [sp], #32 +# CHECK-NEXT: - - - - - 1.50 1.50 - - - - - - 1.50 1.50 - - st1 { v0.4s, v1.4s, v2.4s }, [sp] +# CHECK-NEXT: - - - - - 1.00 1.00 0.17 0.17 0.17 0.17 0.17 0.17 1.00 1.00 - - st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 +# CHECK-NEXT: - - - - - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 - - st1 { v0.8h }, [x15], x2 +# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - 1.00 1.00 - - st1 { v0.8h, v1.8h }, [x15] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 1.00 1.00 - - st1 { v0.d }[1], [x0] +# CHECK-NEXT: - - - - - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 1.00 1.00 - - st1 { v0.d }[1], [x0], #8 +# CHECK-NEXT: - - - - - 1.00 1.00 0.17 0.17 0.17 0.17 0.17 0.17 2.00 2.00 - - st2 { v0.16b, v1.16b }, [x0], x1 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 1.00 1.00 - - st2 { v0.8b, v1.8b }, [x0] +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 1.00 1.00 - - st2 { v0.s, v1.s }[3], [sp] +# CHECK-NEXT: - - - - - 0.50 0.50 0.17 0.17 0.17 0.17 0.17 0.17 1.00 1.00 - - st2 { v0.s, v1.s }[3], [sp], #8 +# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - 2.00 2.00 - - st3 { v0.4h, v1.4h, v2.4h }, [x15] +# CHECK-NEXT: - - - - - 1.50 1.50 0.17 0.17 0.17 0.17 0.17 0.17 3.00 3.00 - - st3 { v0.8h, v1.8h, v2.8h }, [x15], x2 +# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - 2.00 2.00 - - st3 { v0.h, v1.h, v2.h }[7], [x15] +# CHECK-NEXT: - - - - - 1.00 1.00 0.17 0.17 0.17 0.17 0.17 0.17 2.00 2.00 - - st3 { v0.h, v1.h, v2.h }[7], [x15], #6 +# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - 3.00 3.00 - - st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp] +# CHECK-NEXT: - - - - - 2.00 2.00 0.17 0.17 0.17 0.17 0.17 0.17 6.00 6.00 - - st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - 1.50 1.50 - - st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] +# CHECK-NEXT: - - - - - 1.00 1.00 0.17 0.17 0.17 0.17 0.17 0.17 2.00 2.00 - - st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], x5 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sub d15, d5, d16 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sub v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sudot v0.2s, v0.8b, v0.4b[2] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 sudot v0.4s, v0.16b, v0.4b[2] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 suqadd b19, b14 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 suqadd d18, d22 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 suqadd h20, h15 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 suqadd s21, s12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 suqadd v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 suqadd v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 suqadd v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 suqadd v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 suqadd v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 suqadd v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 suqadd v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 0.50 - - tbl v0.16b, { v0.16b }, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 0.50 - - tbl v0.16b, { v0.16b, v1.16b }, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 1.50 1.50 - - tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 0.50 - - tbl v0.8b, { v0.16b }, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 0.50 - - tbl v0.8b, { v0.16b, v1.16b }, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - tbl v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 1.50 1.50 - - tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 tbx v0.16b, { v0.16b }, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 tbx v0.16b, { v0.16b, v1.16b }, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.75 0.75 0.75 0.75 tbx v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 1.25 1.25 1.25 1.25 tbx v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 tbx v0.8b, { v0.16b }, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 tbx v0.8b, { v0.16b, v1.16b }, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.75 0.75 0.75 0.75 tbx v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 1.25 1.25 1.25 1.25 tbx v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 trn1 v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 trn1 v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 trn1 v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 trn1 v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 trn1 v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 trn1 v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 trn1 v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 trn2 v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 trn2 v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 trn2 v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 trn2 v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 trn2 v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 trn2 v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 trn2 v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uaba v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uabal v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uabal v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uabal v0.8h, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uabal2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uabal2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uabal2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uabd v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uabdl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uabdl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uabdl v0.8h, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uabdl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uabdl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uabdl2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uadalp v0.1d, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uadalp v0.2d, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uadalp v0.2s, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uadalp v0.4h, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uadalp v0.4s, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uadalp v0.8h, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddl v0.8h, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddl2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddlp v0.1d, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddlp v0.2d, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddlp v0.2s, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddlp v0.4h, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddlp v0.4s, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddlp v0.8h, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uaddlv d0, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uaddlv s0, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.75 0.25 0.75 uaddlv s0, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.75 0.25 0.75 uaddlv h0, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - 1.00 uaddlv h0, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddw v0.2d, v0.2d, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddw v0.4s, v0.4s, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddw v0.8h, v0.8h, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddw2 v0.2d, v0.2d, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddw2 v0.4s, v0.4s, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uaddw2 v0.8h, v0.8h, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - ucvtf d21, d14 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - ucvtf d21, d14, #64 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - ucvtf s22, s13 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - ucvtf s22, s13, #32 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - ucvtf v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ucvtf v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - ucvtf v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ucvtf v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - ucvtf v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - ucvtf v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ucvtf v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 - 2.00 - ucvtf v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 udot v0.2s, v0.8b, v0.4b[2] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 udot v0.2s, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 udot v0.4s, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 udot v0.4s, v0.16b, v0.4b[2] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uhadd v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uhadd v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uhsub v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 umax v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 umax v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 umax v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 umaxp v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 umaxp v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 umaxp v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.75 0.25 0.75 umaxv b0, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - 1.00 umaxv b0, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 umaxv h0, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.75 0.25 0.75 umaxv h0, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 umaxv s0, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 umin v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 umin v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 umin v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uminp v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uminp v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uminp v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.75 0.25 0.75 uminv b0, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - 1.00 uminv b0, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uminv h0, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.75 0.25 0.75 uminv h0, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uminv s0, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umlal v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umlal v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umlal v0.8h, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umlal2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umlal2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umlal2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umlsl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umlsl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umlsl v0.8h, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umlsl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umlsl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umlsl2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 ummla v0.4s, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - umov w0, v0.b[1] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - umov w0, v0.h[1] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - mov w0, v0.s[1] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - mov x0, v0.d[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umull v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umull v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umull v0.8h, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umull2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umull2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - umull2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uqadd h0, h1, h5 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uqadd v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqrshl b11, b20, b30 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqrshl s23, s20, s16 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqrshl v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqrshl v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqrshl v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqrshl v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqrshrn b10, h12, #5 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqrshrn h12, s10, #14 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqrshrn s10, d10, #25 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqrshrn v0.2s, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqrshrn v0.4h, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqrshrn v0.8b, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqrshrn2 v0.16b, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqrshrn2 v0.4s, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqrshrn2 v0.8h, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl b11, b20, b30 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl b18, b15, #6 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl d15, d12, #19 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl h11, h18, #7 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl s14, s19, #18 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl s23, s20, s16 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl v0.16b, v0.16b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl v0.4h, v0.4h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl v0.8b, v0.8b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl v0.8h, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshl v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshrn b12, h10, #7 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshrn h10, s14, #5 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshrn s10, d12, #13 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshrn v0.2s, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshrn v0.4h, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshrn v0.8b, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshrn2 v0.16b, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshrn2 v0.4s, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqshrn2 v0.8h, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uqsub d16, d16, d16 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uqsub v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqxtn b18, h18 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqxtn h20, s17 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqxtn s19, d14 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqxtn v0.2s, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqxtn v0.4h, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqxtn v0.8b, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqxtn2 v0.16b, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqxtn2 v0.4s, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 uqxtn2 v0.8h, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - urecpe v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - urecpe v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 urhadd v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 urhadd v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 urhadd v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 urshl d8, d7, d4 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 urshl v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 urshl v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 urshl v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 urshl v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 urshr d20, d23, #31 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 urshr v0.16b, v0.16b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 urshr v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 urshr v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 urshr v0.4h, v0.4h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 urshr v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 urshr v0.8b, v0.8b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 urshr v0.8h, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.50 - 0.50 - ursqrte v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - 1.00 - ursqrte v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ursra d18, d10, #13 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ursra v0.16b, v0.16b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ursra v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ursra v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ursra v0.4h, v0.4h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ursra v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ursra v0.8b, v0.8b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ursra v0.8h, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usdot v0.2s, v0.8b, v0.4b[2] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usdot v0.2s, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usdot v0.4s, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usdot v0.4s, v0.16b, v0.4b[2] +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ushl d0, d0, d0 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ushl v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ushl v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ushl v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ushll v0.4s, v0.4h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ushll2 v0.8h, v0.16b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ushr d10, d17, #18 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ushr v0.16b, v0.16b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ushr v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ushr v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ushr v0.4h, v0.4h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ushr v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ushr v0.8b, v0.8b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 ushr v0.8h, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usmmla v0.4s, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - smov w0, v0.b[1] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - smov w0, v0.h[1] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - smov x0, v0.b[1] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - smov x0, v0.h[1] +# CHECK-NEXT: - - - - - - - - - - - - - 1.00 1.00 - - smov x0, v0.s[1] +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usqadd b19, b14 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usqadd d18, d22 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usqadd h20, h15 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usqadd s21, s12 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usqadd v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usqadd v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usqadd v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usqadd v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usqadd v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usqadd v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usqadd v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 usra d20, d13, #61 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 usra v0.16b, v0.16b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 usra v0.2d, v0.2d, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 usra v0.2s, v0.2s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 usra v0.4h, v0.4h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 usra v0.4s, v0.4s, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 usra v0.8b, v0.8b, #3 +# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 usra v0.8h, v0.8h, #3 +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usubl v0.2d, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usubl v0.4s, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usubl v0.8h, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usubl2 v0.2d, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usubl2 v0.4s, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usubl2 v0.8h, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usubw v0.2d, v0.2d, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usubw v0.4s, v0.4s, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usubw v0.8h, v0.8h, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usubw2 v0.2d, v0.2d, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usubw2 v0.4s, v0.4s, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 usubw2 v0.8h, v0.8h, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uzp1 v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uzp1 v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uzp1 v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uzp1 v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uzp1 v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uzp1 v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uzp1 v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uzp2 v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uzp2 v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uzp2 v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uzp2 v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uzp2 v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uzp2 v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 uzp2 v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 xtn v0.2s, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 xtn v0.4h, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 xtn v0.8b, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 xtn2 v0.16b, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 xtn2 v0.4s, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 xtn2 v0.8h, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 zip1 v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 zip1 v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 zip1 v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 zip1 v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 zip1 v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 zip1 v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 zip1 v0.8h, v0.8h, v0.8h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 zip2 v0.16b, v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 zip2 v0.2d, v0.2d, v0.2d +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 zip2 v0.2s, v0.2s, v0.2s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 zip2 v0.4h, v0.4h, v0.4h +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 zip2 v0.4s, v0.4s, v0.4s +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 zip2 v0.8b, v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 zip2 v0.8h, v0.8h, v0.8h diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-sve-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-sve-instructions.s new file mode 100644 --- /dev/null +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-sve-instructions.s @@ -0,0 +1,10281 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -instruction-tables < %s | FileCheck %s + +abs z0.b, p0/m, z0.b +abs z0.d, p0/m, z0.d +abs z0.h, p0/m, z0.h +abs z0.s, p0/m, z0.s +abs z31.b, p7/m, z31.b +abs z31.d, p7/m, z31.d +abs z31.h, p7/m, z31.h +abs z31.s, p7/m, z31.s +adclb z0.d, z1.d, z31.d +adclb z0.s, z1.s, z31.s +adclt z0.d, z1.d, z31.d +adclt z0.s, z1.s, z31.s +add z0.b, p0/m, z0.b, z0.b +add z0.b, z0.b, #0 +add z0.b, z0.b, z0.b +add z0.d, p0/m, z0.d, z0.d +add z0.d, z0.d, #0 +add z0.d, z0.d, #0, lsl #8 +add z0.d, z0.d, z0.d +add z0.h, p0/m, z0.h, z0.h +add z0.h, z0.h, #0 +add z0.h, z0.h, #0, lsl #8 +add z0.h, z0.h, z0.h +add z0.s, p0/m, z0.s, z0.s +add z0.s, z0.s, #0 +add z0.s, z0.s, #0, lsl #8 +add z0.s, z0.s, z0.s +add z0.s, z1.s, z2.s +add z21.b, p5/m, z21.b, z10.b +add z21.b, z10.b, z21.b +add z21.d, p5/m, z21.d, z10.d +add z21.d, z10.d, z21.d +add z21.h, p5/m, z21.h, z10.h +add z21.h, z10.h, z21.h +add z21.s, p5/m, z21.s, z10.s +add z21.s, z10.s, z21.s +add z23.b, p3/m, z23.b, z13.b +add z23.b, z13.b, z8.b +add z23.d, p3/m, z23.d, z13.d +add z23.d, z13.d, z8.d +add z23.h, p3/m, z23.h, z13.h +add z23.h, z13.h, z8.h +add z23.s, p3/m, z23.s, z13.s +add z23.s, z13.s, z8.s +add z31.b, p7/m, z31.b, z31.b +add z31.b, z31.b, #255 +add z31.b, z31.b, z31.b +add z31.d, p7/m, z31.d, z31.d +add z31.d, z31.d, #65280 +add z31.d, z31.d, z31.d +add z31.h, p7/m, z31.h, z31.h +add z31.h, z31.h, #65280 +add z31.h, z31.h, z31.h +add z31.s, p7/m, z31.s, z31.s +add z31.s, z31.s, #65280 +add z31.s, z31.s, z31.s +addhnb z0.b, z1.h, z31.h +addhnb z0.h, z1.s, z31.s +addhnb z0.s, z1.d, z31.d +addhnt z0.b, z1.h, z31.h +addhnt z0.h, z1.s, z31.s +addhnt z0.s, z1.d, z31.d +addp z0.b, p0/m, z0.b, z1.b +addp z0.h, p0/m, z0.h, z1.h +addp z29.s, p7/m, z29.s, z30.s +addp z31.d, p7/m, z31.d, z30.d +addpl sp, sp, #31 +addpl x0, x0, #-32 +addpl x21, x21, #0 +addpl x23, x8, #-1 +addvl sp, sp, #31 +addvl x0, x0, #-32 +addvl x21, x21, #0 +addvl x23, x8, #-1 +adr z0.d, [z0.d, z0.d, lsl #1] +adr z0.d, [z0.d, z0.d, lsl #2] +adr z0.d, [z0.d, z0.d, lsl #3] +adr z0.d, [z0.d, z0.d, sxtw #1] +adr z0.d, [z0.d, z0.d, sxtw #2] +adr z0.d, [z0.d, z0.d, sxtw #3] +adr z0.d, [z0.d, z0.d, sxtw] +adr z0.d, [z0.d, z0.d, uxtw #1] +adr z0.d, [z0.d, z0.d, uxtw #2] +adr z0.d, [z0.d, z0.d, uxtw #3] +adr z0.d, [z0.d, z0.d, uxtw] +adr z0.d, [z0.d, z0.d] +adr z0.s, [z0.s, z0.s, lsl #1] +adr z0.s, [z0.s, z0.s, lsl #2] +adr z0.s, [z0.s, z0.s, lsl #3] +adr z0.s, [z0.s, z0.s] +aesd z0.b, z0.b, z31.b +aese z0.b, z0.b, z31.b +aesimc z0.b, z0.b +aesimc z31.b, z31.b +aesmc z0.b, z0.b +aesmc z31.b, z31.b +and p0.b, p0/z, p0.b, p1.b +and z0.d, z0.d, #0x6 +and z0.d, z0.d, #0xfffffffffffffff9 +and z0.d, z0.d, z0.d +and z0.s, z0.s, #0x6 +and z0.s, z0.s, #0xfffffff9 +and z23.d, z13.d, z8.d +and z23.h, z23.h, #0x6 +and z23.h, z23.h, #0xfff9 +and z31.b, p7/m, z31.b, z31.b +and z31.d, p7/m, z31.d, z31.d +and z31.h, p7/m, z31.h, z31.h +and z31.s, p7/m, z31.s, z31.s +and z5.b, z5.b, #0x6 +and z5.b, z5.b, #0xf9 +ands p0.b, p0/z, p0.b, p1.b +andv b0, p7, z31.b +andv d0, p7, z31.d +andv h0, p7, z31.h +andv s0, p7, z31.s +asr z0.b, p0/m, z0.b, #1 +asr z0.b, p0/m, z0.b, z0.b +asr z0.b, p0/m, z0.b, z1.d +asr z0.b, z0.b, #1 +asr z0.b, z1.b, z2.d +asr z0.d, p0/m, z0.d, #1 +asr z0.d, p0/m, z0.d, z0.d +asr z0.d, z0.d, #1 +asr z0.h, p0/m, z0.h, #1 +asr z0.h, p0/m, z0.h, z0.h +asr z0.h, p0/m, z0.h, z1.d +asr z0.h, z0.h, #1 +asr z0.h, z1.h, z2.d +asr z0.s, p0/m, z0.s, #1 +asr z0.s, p0/m, z0.s, z0.s +asr z0.s, p0/m, z0.s, z1.d +asr z0.s, z0.s, #1 +asr z0.s, z1.s, z2.d +asr z31.b, p0/m, z31.b, #8 +asr z31.b, z31.b, #8 +asr z31.d, p0/m, z31.d, #64 +asr z31.d, z31.d, #64 +asr z31.h, p0/m, z31.h, #16 +asr z31.h, z31.h, #16 +asr z31.s, p0/m, z31.s, #32 +asr z31.s, z31.s, #32 +asrd z0.b, p0/m, z0.b, #1 +asrd z0.d, p0/m, z0.d, #1 +asrd z0.h, p0/m, z0.h, #1 +asrd z0.s, p0/m, z0.s, #1 +asrd z31.b, p0/m, z31.b, #8 +asrd z31.d, p0/m, z31.d, #64 +asrd z31.h, p0/m, z31.h, #16 +asrd z31.s, p0/m, z31.s, #32 +asrr z0.b, p0/m, z0.b, z0.b +asrr z0.d, p0/m, z0.d, z0.d +asrr z0.h, p0/m, z0.h, z0.h +asrr z0.s, p0/m, z0.s, z0.s +bcax z29.d, z29.d, z30.d, z31.d +bdep z0.b, z1.b, z31.b +bdep z0.d, z1.d, z31.d +bdep z0.h, z1.h, z31.h +bdep z0.s, z1.s, z31.s +bext z0.b, z1.b, z31.b +bext z0.d, z1.d, z31.d +bext z0.h, z1.h, z31.h +bext z0.s, z1.s, z31.s +bfcvt z0.h, p0/m, z1.s +bfcvtnt z0.h, p0/m, z1.s +bfdot z0.s, z1.h, z2.h +bfdot z0.s, z1.h, z2.h[0] +bfdot z0.s, z1.h, z2.h[3] +bfmlalb z0.s, z1.h, z2.h +bfmlalb z0.s, z1.h, z2.h[0] +bfmlalb z0.s, z1.h, z2.h[7] +bfmlalb z10.s, z21.h, z14.h +bfmlalb z21.s, z14.h, z3.h[2] +bfmlalt z0.s, z1.h, z2.h +bfmlalt z0.s, z1.h, z2.h[0] +bfmlalt z0.s, z1.h, z2.h[7] +bfmlalt z0.s, z1.h, z7.h[7] +bfmlalt z14.s, z10.h, z21.h +bfmmla z0.s, z1.h, z2.h +bgrp z0.b, z1.b, z31.b +bgrp z0.d, z1.d, z31.d +bgrp z0.h, z1.h, z31.h +bgrp z0.s, z1.s, z31.s +bic p0.b, p0/z, p0.b, p0.b +bic p15.b, p15/z, p15.b, p15.b +bic z0.d, z0.d, z0.d +bic z23.d, z13.d, z8.d +bic z31.b, p7/m, z31.b, z31.b +bic z31.d, p7/m, z31.d, z31.d +bic z31.h, p7/m, z31.h, z31.h +bic z31.s, p7/m, z31.s, z31.s +bics p0.b, p0/z, p0.b, p0.b +bics p15.b, p15/z, p15.b, p15.b +brka p0.b, p15/m, p15.b +brka p0.b, p15/z, p15.b +brkas p0.b, p15/z, p15.b +brkb p0.b, p15/m, p15.b +brkb p0.b, p15/z, p15.b +brkbs p0.b, p15/z, p15.b +brkn p0.b, p15/z, p1.b, p0.b +brkn p15.b, p15/z, p15.b, p15.b +brkns p0.b, p15/z, p1.b, p0.b +brkns p15.b, p15/z, p15.b, p15.b +brkpa p0.b, p15/z, p1.b, p2.b +brkpa p15.b, p15/z, p15.b, p15.b +brkpas p0.b, p15/z, p1.b, p2.b +brkpas p15.b, p15/z, p15.b, p15.b +brkpb p0.b, p15/z, p1.b, p2.b +brkpb p15.b, p15/z, p15.b, p15.b +brkpbs p0.b, p15/z, p1.b, p2.b +brkpbs p15.b, p15/z, p15.b, p15.b +bsl z0.d, z0.d, z1.d, z2.d +bsl1n z0.d, z0.d, z1.d, z2.d +bsl2n z0.d, z0.d, z1.d, z2.d +cadd z0.b, z0.b, z0.b, #90 +cadd z0.d, z0.d, z0.d, #90 +cadd z0.h, z0.h, z0.h, #90 +cadd z0.s, z0.s, z0.s, #90 +cadd z31.b, z31.b, z31.b, #270 +cadd z31.d, z31.d, z31.d, #270 +cadd z31.h, z31.h, z31.h, #270 +cadd z31.s, z31.s, z31.s, #270 +cdot z0.d, z1.h, z15.h[1], #0 +cdot z0.d, z1.h, z31.h, #0 +cdot z0.d, z1.h, z31.h, #180 +cdot z0.d, z1.h, z31.h, #270 +cdot z0.d, z1.h, z31.h, #90 +cdot z0.s, z1.b, z31.b, #0 +cdot z0.s, z1.b, z7.b[3], #0 +cdot z29.d, z30.h, z0.h[0], #180 +cdot z31.d, z30.h, z7.h[1], #270 +cdot z5.d, z6.h, z3.h[0], #90 +clasta b0, p7, b0, z31.b +clasta d0, p7, d0, z31.d +clasta h0, p7, h0, z31.h +clasta s0, p7, s0, z31.s +clasta w0, p7, w0, z31.b +clasta w0, p7, w0, z31.h +clasta w0, p7, w0, z31.s +clasta x0, p7, x0, z31.d +clasta z0.b, p7, z0.b, z31.b +clasta z0.d, p7, z0.d, z31.d +clasta z0.h, p7, z0.h, z31.h +clasta z0.s, p7, z0.s, z31.s +clastb b0, p7, b0, z31.b +clastb d0, p7, d0, z31.d +clastb h0, p7, h0, z31.h +clastb s0, p7, s0, z31.s +clastb w0, p7, w0, z31.b +clastb w0, p7, w0, z31.h +clastb w0, p7, w0, z31.s +clastb x0, p7, x0, z31.d +clastb z0.b, p7, z0.b, z31.b +clastb z0.d, p7, z0.d, z31.d +clastb z0.h, p7, z0.h, z31.h +clastb z0.s, p7, z0.s, z31.s +cls z31.b, p7/m, z31.b +cls z31.d, p7/m, z31.d +cls z31.h, p7/m, z31.h +cls z31.s, p7/m, z31.s +clz z31.b, p7/m, z31.b +clz z31.d, p7/m, z31.d +clz z31.h, p7/m, z31.h +clz z31.s, p7/m, z31.s +cmla z0.b, z1.b, z2.b, #0 +cmla z0.d, z1.d, z2.d, #0 +cmla z0.h, z1.h, z2.h, #0 +cmla z0.h, z1.h, z2.h[0], #0 +cmla z0.s, z1.s, z2.s, #0 +cmla z0.s, z1.s, z2.s[0], #0 +cmla z15.b, z16.b, z17.b, #270 +cmla z15.d, z16.d, z17.d, #270 +cmla z15.h, z16.h, z17.h, #270 +cmla z15.s, z16.s, z17.s, #270 +cmla z29.b, z30.b, z31.b, #90 +cmla z29.d, z30.d, z31.d, #90 +cmla z29.h, z30.h, z31.h, #90 +cmla z29.s, z30.s, z31.s, #90 +cmla z31.b, z31.b, z31.b, #180 +cmla z31.d, z31.d, z31.d, #180 +cmla z31.h, z30.h, z7.h[0], #180 +cmla z31.h, z31.h, z31.h, #180 +cmla z31.s, z30.s, z7.s[0], #180 +cmla z31.s, z31.s, z31.s, #180 +cmpeq p0.b, p0/z, z0.b, #-16 +cmpeq p0.b, p0/z, z0.b, #15 +cmpeq p0.b, p0/z, z0.b, z0.b +cmpeq p0.b, p0/z, z0.b, z0.d +cmpeq p0.d, p0/z, z0.d, #-16 +cmpeq p0.d, p0/z, z0.d, #15 +cmpeq p0.d, p0/z, z0.d, z0.d +cmpeq p0.h, p0/z, z0.h, #-16 +cmpeq p0.h, p0/z, z0.h, #15 +cmpeq p0.h, p0/z, z0.h, z0.d +cmpeq p0.h, p0/z, z0.h, z0.h +cmpeq p0.s, p0/z, z0.s, #-16 +cmpeq p0.s, p0/z, z0.s, #15 +cmpeq p0.s, p0/z, z0.s, z0.d +cmpeq p0.s, p0/z, z0.s, z0.s +cmpge p0.b, p0/z, z0.b, #-16 +cmpge p0.b, p0/z, z0.b, #15 +cmpge p0.b, p0/z, z0.b, z0.b +cmpge p0.b, p0/z, z0.b, z0.d +cmpge p0.b, p0/z, z1.b, z0.b +cmpge p0.d, p0/z, z0.d, #-16 +cmpge p0.d, p0/z, z0.d, #15 +cmpge p0.d, p0/z, z0.d, z0.d +cmpge p0.d, p0/z, z1.d, z0.d +cmpge p0.h, p0/z, z0.h, #-16 +cmpge p0.h, p0/z, z0.h, #15 +cmpge p0.h, p0/z, z0.h, z0.d +cmpge p0.h, p0/z, z0.h, z0.h +cmpge p0.h, p0/z, z1.h, z0.h +cmpge p0.s, p0/z, z0.s, #-16 +cmpge p0.s, p0/z, z0.s, #15 +cmpge p0.s, p0/z, z0.s, z0.d +cmpge p0.s, p0/z, z0.s, z0.s +cmpge p0.s, p0/z, z1.s, z0.s +cmpgt p0.b, p0/z, z0.b, #-16 +cmpgt p0.b, p0/z, z0.b, #15 +cmpgt p0.b, p0/z, z0.b, z0.b +cmpgt p0.b, p0/z, z0.b, z0.d +cmpgt p0.b, p0/z, z1.b, z0.b +cmpgt p0.d, p0/z, z0.d, #-16 +cmpgt p0.d, p0/z, z0.d, #15 +cmpgt p0.d, p0/z, z0.d, z0.d +cmpgt p0.d, p0/z, z1.d, z0.d +cmpgt p0.h, p0/z, z0.h, #-16 +cmpgt p0.h, p0/z, z0.h, #15 +cmpgt p0.h, p0/z, z0.h, z0.d +cmpgt p0.h, p0/z, z0.h, z0.h +cmpgt p0.h, p0/z, z1.h, z0.h +cmpgt p0.s, p0/z, z0.s, #-16 +cmpgt p0.s, p0/z, z0.s, #15 +cmpgt p0.s, p0/z, z0.s, z0.d +cmpgt p0.s, p0/z, z0.s, z0.s +cmpgt p0.s, p0/z, z1.s, z0.s +cmphi p0.b, p0/z, z0.b, #0 +cmphi p0.b, p0/z, z0.b, #127 +cmphi p0.b, p0/z, z0.b, z0.b +cmphi p0.b, p0/z, z0.b, z0.d +cmphi p0.b, p0/z, z1.b, z0.b +cmphi p0.d, p0/z, z0.d, #0 +cmphi p0.d, p0/z, z0.d, #127 +cmphi p0.d, p0/z, z0.d, z0.d +cmphi p0.d, p0/z, z1.d, z0.d +cmphi p0.h, p0/z, z0.h, #0 +cmphi p0.h, p0/z, z0.h, #127 +cmphi p0.h, p0/z, z0.h, z0.d +cmphi p0.h, p0/z, z0.h, z0.h +cmphi p0.h, p0/z, z1.h, z0.h +cmphi p0.s, p0/z, z0.s, #0 +cmphi p0.s, p0/z, z0.s, #127 +cmphi p0.s, p0/z, z0.s, z0.d +cmphi p0.s, p0/z, z0.s, z0.s +cmphi p0.s, p0/z, z1.s, z0.s +cmphs p0.b, p0/z, z0.b, #0 +cmphs p0.b, p0/z, z0.b, #127 +cmphs p0.b, p0/z, z0.b, z0.b +cmphs p0.b, p0/z, z0.b, z0.d +cmphs p0.b, p0/z, z1.b, z0.b +cmphs p0.d, p0/z, z0.d, #0 +cmphs p0.d, p0/z, z0.d, #127 +cmphs p0.d, p0/z, z0.d, z0.d +cmphs p0.d, p0/z, z1.d, z0.d +cmphs p0.h, p0/z, z0.h, #0 +cmphs p0.h, p0/z, z0.h, #127 +cmphs p0.h, p0/z, z0.h, z0.d +cmphs p0.h, p0/z, z0.h, z0.h +cmphs p0.h, p0/z, z1.h, z0.h +cmphs p0.s, p0/z, z0.s, #0 +cmphs p0.s, p0/z, z0.s, #127 +cmphs p0.s, p0/z, z0.s, z0.d +cmphs p0.s, p0/z, z0.s, z0.s +cmphs p0.s, p0/z, z1.s, z0.s +cmple p0.b, p0/z, z0.b, #-16 +cmple p0.b, p0/z, z0.b, #15 +cmple p0.b, p0/z, z0.b, z0.d +cmple p0.d, p0/z, z0.d, #-16 +cmple p0.d, p0/z, z0.d, #15 +cmple p0.h, p0/z, z0.h, #-16 +cmple p0.h, p0/z, z0.h, #15 +cmple p0.h, p0/z, z0.h, z0.d +cmple p0.s, p0/z, z0.s, #-16 +cmple p0.s, p0/z, z0.s, #15 +cmple p0.s, p0/z, z0.s, z0.d +cmplo p0.b, p0/z, z0.b, #0 +cmplo p0.b, p0/z, z0.b, #127 +cmplo p0.b, p0/z, z0.b, z0.d +cmplo p0.d, p0/z, z0.d, #0 +cmplo p0.d, p0/z, z0.d, #127 +cmplo p0.h, p0/z, z0.h, #0 +cmplo p0.h, p0/z, z0.h, #127 +cmplo p0.h, p0/z, z0.h, z0.d +cmplo p0.s, p0/z, z0.s, #0 +cmplo p0.s, p0/z, z0.s, #127 +cmplo p0.s, p0/z, z0.s, z0.d +cmpls p0.b, p0/z, z0.b, #0 +cmpls p0.b, p0/z, z0.b, #127 +cmpls p0.b, p0/z, z0.b, z0.d +cmpls p0.d, p0/z, z0.d, #0 +cmpls p0.d, p0/z, z0.d, #127 +cmpls p0.h, p0/z, z0.h, #0 +cmpls p0.h, p0/z, z0.h, #127 +cmpls p0.h, p0/z, z0.h, z0.d +cmpls p0.s, p0/z, z0.s, #0 +cmpls p0.s, p0/z, z0.s, #127 +cmpls p0.s, p0/z, z0.s, z0.d +cmplt p0.b, p0/z, z0.b, #-16 +cmplt p0.b, p0/z, z0.b, #15 +cmplt p0.b, p0/z, z0.b, z0.d +cmplt p0.d, p0/z, z0.d, #-16 +cmplt p0.d, p0/z, z0.d, #15 +cmplt p0.h, p0/z, z0.h, #-16 +cmplt p0.h, p0/z, z0.h, #15 +cmplt p0.h, p0/z, z0.h, z0.d +cmplt p0.s, p0/z, z0.s, #-16 +cmplt p0.s, p0/z, z0.s, #15 +cmplt p0.s, p0/z, z0.s, z0.d +cmpne p0.b, p0/z, z0.b, #-16 +cmpne p0.b, p0/z, z0.b, #15 +cmpne p0.b, p0/z, z0.b, z0.b +cmpne p0.b, p0/z, z0.b, z0.d +cmpne p0.d, p0/z, z0.d, #-16 +cmpne p0.d, p0/z, z0.d, #15 +cmpne p0.d, p0/z, z0.d, z0.d +cmpne p0.h, p0/z, z0.h, #-16 +cmpne p0.h, p0/z, z0.h, #15 +cmpne p0.h, p0/z, z0.h, z0.d +cmpne p0.h, p0/z, z0.h, z0.h +cmpne p0.s, p0/z, z0.s, #-16 +cmpne p0.s, p0/z, z0.s, #15 +cmpne p0.s, p0/z, z0.s, z0.d +cmpne p0.s, p0/z, z0.s, z0.s +cnot z31.b, p7/m, z31.b +cnot z31.d, p7/m, z31.d +cnot z31.h, p7/m, z31.h +cnot z31.s, p7/m, z31.s +cnt z31.b, p7/m, z31.b +cnt z31.d, p7/m, z31.d +cnt z31.h, p7/m, z31.h +cnt z31.s, p7/m, z31.s +cntb x0 +cntb x0, #28 +cntb x0, all, mul #16 +cntb x0, pow2 +cntd x0 +cntd x0, #28 +cntd x0, all, mul #16 +cntd x0, pow2 +cnth x0 +cnth x0, #28 +cnth x0, all, mul #16 +cnth x0, pow2 +cntp x0, p15, p0.b +cntp x0, p15, p0.d +cntp x0, p15, p0.h +cntp x0, p15, p0.s +cntw x0 +cntw x0, #28 +cntw x0, all, mul #16 +cntw x0, pow2 +compact z31.d, p7, z31.d +compact z31.s, p7, z31.s +ctermeq w30, wzr +ctermeq wzr, w30 +ctermeq x30, xzr +ctermeq xzr, x30 +ctermne w30, wzr +ctermne wzr, w30 +ctermne x30, xzr +ctermne xzr, x30 +decb x0 +decb x0, #14 +decb x0, all, mul #16 +decb x0, pow2 +decb x0, vl1 +decd x0 +decd x0, #14 +decd x0, all, mul #16 +decd x0, pow2 +decd x0, vl1 +dech x0 +dech x0, #14 +dech x0, all, mul #16 +dech x0, pow2 +dech x0, vl1 +decp x0, p0.b +decp x0, p0.d +decp x0, p0.h +decp x0, p0.s +decp xzr, p15.b +decp xzr, p15.d +decp xzr, p15.h +decp xzr, p15.s +decp z31.d, p15.d +decp z31.h, p15.h +decp z31.s, p15.s +decw x0 +decw x0, #14 +decw x0, all, mul #16 +decw x0, pow2 +decw x0, vl1 +dupm z0.d, #0xfffffffffffffff9 +dupm z0.s, #0xfffffff9 +dupm z23.h, #0xfff9 +dupm z5.b, #0xf9 +eor p0.b, p0/z, p0.b, p1.b +eor z0.d, z0.d, #0x6 +eor z0.d, z0.d, #0xfffffffffffffff9 +eor z0.d, z0.d, z0.d +eor z0.s, z0.s, #0x6 +eor z0.s, z0.s, #0xfffffff9 +eor z23.d, z13.d, z8.d +eor z23.h, z23.h, #0x6 +eor z23.h, z23.h, #0xfff9 +eor z31.b, p7/m, z31.b, z31.b +eor z31.d, p7/m, z31.d, z31.d +eor z31.h, p7/m, z31.h, z31.h +eor z31.s, p7/m, z31.s, z31.s +eor z5.b, z5.b, #0x6 +eor z5.b, z5.b, #0xf9 +eor3 z29.d, z29.d, z30.d, z31.d +eorbt z0.b, z1.b, z31.b +eorbt z0.d, z1.d, z31.d +eorbt z0.h, z1.h, z31.h +eorbt z0.s, z1.s, z31.s +eors p0.b, p0/z, p0.b, p1.b +eortb z0.b, z1.b, z31.b +eortb z0.d, z1.d, z31.d +eortb z0.h, z1.h, z31.h +eortb z0.s, z1.s, z31.s +eorv b0, p7, z31.b +eorv d0, p7, z31.d +eorv h0, p7, z31.h +eorv s0, p7, z31.s +ext z0.b, { z1.b, z2.b }, #0 +ext z31.b, z31.b, z0.b, #0 +ext z31.b, z31.b, z0.b, #255 +ext z31.b, { z30.b, z31.b }, #255 +fabd z0.d, p7/m, z0.d, z31.d +fabd z0.h, p7/m, z0.h, z31.h +fabd z0.s, p7/m, z0.s, z31.s +fabs z31.d, p7/m, z31.d +fabs z31.h, p7/m, z31.h +fabs z31.s, p7/m, z31.s +facge p0.d, p0/z, z0.d, z1.d +facge p0.d, p0/z, z1.d, z0.d +facge p0.h, p0/z, z0.h, z1.h +facge p0.h, p0/z, z1.h, z0.h +facge p0.s, p0/z, z0.s, z1.s +facge p0.s, p0/z, z1.s, z0.s +facgt p0.d, p0/z, z0.d, z1.d +facgt p0.d, p0/z, z1.d, z0.d +facgt p0.h, p0/z, z0.h, z1.h +facgt p0.h, p0/z, z1.h, z0.h +facgt p0.s, p0/z, z0.s, z1.s +facgt p0.s, p0/z, z1.s, z0.s +fadd z0.d, p0/m, z0.d, #0.5 +fadd z0.d, p7/m, z0.d, z31.d +fadd z0.d, z1.d, z31.d +fadd z0.h, p0/m, z0.h, #0.5 +fadd z0.h, p7/m, z0.h, z31.h +fadd z0.h, z1.h, z31.h +fadd z0.s, p0/m, z0.s, #0.5 +fadd z0.s, p7/m, z0.s, z31.s +fadd z0.s, z1.s, z31.s +fadd z31.d, p7/m, z31.d, #1.0 +fadd z31.h, p7/m, z31.h, #1.0 +fadd z31.s, p7/m, z31.s, #1.0 +fadda d0, p7, d0, z31.d +fadda h0, p7, h0, z31.h +fadda s0, p7, s0, z31.s +faddp z0.h, p0/m, z0.h, z1.h +faddp z29.s, p3/m, z29.s, z30.s +faddp z31.d, p7/m, z31.d, z30.d +faddv d0, p7, z31.d +faddv h0, p7, z31.h +faddv s0, p7, z31.s +fcadd z0.d, p0/m, z0.d, z0.d, #90 +fcadd z0.h, p0/m, z0.h, z0.h, #90 +fcadd z0.s, p0/m, z0.s, z0.s, #90 +fcadd z31.d, p7/m, z31.d, z31.d, #270 +fcadd z31.h, p7/m, z31.h, z31.h, #270 +fcadd z31.s, p7/m, z31.s, z31.s, #270 +fcmeq p0.d, p0/z, z0.d, #0.0 +fcmeq p0.d, p0/z, z0.d, z1.d +fcmeq p0.h, p0/z, z0.h, #0.0 +fcmeq p0.h, p0/z, z0.h, z1.h +fcmeq p0.s, p0/z, z0.s, #0.0 +fcmeq p0.s, p0/z, z0.s, z1.s +fcmge p0.d, p0/z, z0.d, #0.0 +fcmge p0.d, p0/z, z0.d, z1.d +fcmge p0.d, p0/z, z1.d, z0.d +fcmge p0.h, p0/z, z0.h, #0.0 +fcmge p0.h, p0/z, z0.h, z1.h +fcmge p0.h, p0/z, z1.h, z0.h +fcmge p0.s, p0/z, z0.s, #0.0 +fcmge p0.s, p0/z, z0.s, z1.s +fcmge p0.s, p0/z, z1.s, z0.s +fcmgt p0.d, p0/z, z0.d, #0.0 +fcmgt p0.d, p0/z, z0.d, z1.d +fcmgt p0.d, p0/z, z1.d, z0.d +fcmgt p0.h, p0/z, z0.h, #0.0 +fcmgt p0.h, p0/z, z0.h, z1.h +fcmgt p0.h, p0/z, z1.h, z0.h +fcmgt p0.s, p0/z, z0.s, #0.0 +fcmgt p0.s, p0/z, z0.s, z1.s +fcmgt p0.s, p0/z, z1.s, z0.s +fcmla z0.d, p0/m, z0.d, z0.d, #0 +fcmla z0.d, p0/m, z1.d, z2.d, #90 +fcmla z0.h, p0/m, z0.h, z0.h, #0 +fcmla z0.h, p0/m, z1.h, z2.h, #90 +fcmla z0.h, z0.h, z0.h[0], #0 +fcmla z0.s, p0/m, z0.s, z0.s, #0 +fcmla z0.s, p0/m, z1.s, z2.s, #90 +fcmla z21.s, z10.s, z5.s[1], #90 +fcmla z23.s, z13.s, z8.s[0], #270 +fcmla z29.d, p7/m, z30.d, z31.d, #180 +fcmla z29.h, p7/m, z30.h, z31.h, #180 +fcmla z29.s, p7/m, z30.s, z31.s, #180 +fcmla z31.d, p7/m, z31.d, z31.d, #270 +fcmla z31.h, p7/m, z31.h, z31.h, #270 +fcmla z31.h, z31.h, z7.h[3], #270 +fcmla z31.s, p7/m, z31.s, z31.s, #270 +fcmle p0.d, p0/z, z0.d, #0.0 +fcmle p0.h, p0/z, z0.h, #0.0 +fcmle p0.s, p0/z, z0.s, #0.0 +fcmlt p0.d, p0/z, z0.d, #0.0 +fcmlt p0.h, p0/z, z0.h, #0.0 +fcmlt p0.s, p0/z, z0.s, #0.0 +fcmne p0.d, p0/z, z0.d, #0.0 +fcmne p0.d, p0/z, z0.d, z1.d +fcmne p0.h, p0/z, z0.h, #0.0 +fcmne p0.h, p0/z, z0.h, z1.h +fcmne p0.s, p0/z, z0.s, #0.0 +fcmne p0.s, p0/z, z0.s, z1.s +fcmuo p0.d, p0/z, z0.d, z1.d +fcmuo p0.h, p0/z, z0.h, z1.h +fcmuo p0.s, p0/z, z0.s, z1.s +fcvt z0.d, p0/m, z0.h +fcvt z0.d, p0/m, z0.s +fcvt z0.h, p0/m, z0.d +fcvt z0.h, p0/m, z0.s +fcvt z0.s, p0/m, z0.d +fcvt z0.s, p0/m, z0.h +fcvtlt z0.s, p0/m, z1.h +fcvtlt z30.d, p7/m, z31.s +fcvtnt z0.h, p0/m, z1.s +fcvtnt z30.s, p7/m, z31.d +fcvtx z0.s, p0/m, z0.d +fcvtx z30.s, p7/m, z31.d +fcvtxnt z0.s, p0/m, z1.d +fcvtxnt z30.s, p7/m, z31.d +fcvtzs z0.d, p0/m, z0.d +fcvtzs z0.d, p0/m, z0.h +fcvtzs z0.d, p0/m, z0.s +fcvtzs z0.h, p0/m, z0.h +fcvtzs z0.s, p0/m, z0.d +fcvtzs z0.s, p0/m, z0.h +fcvtzs z0.s, p0/m, z0.s +fcvtzu z0.d, p0/m, z0.d +fcvtzu z0.d, p0/m, z0.h +fcvtzu z0.d, p0/m, z0.s +fcvtzu z0.h, p0/m, z0.h +fcvtzu z0.s, p0/m, z0.d +fcvtzu z0.s, p0/m, z0.h +fcvtzu z0.s, p0/m, z0.s +fdiv z0.d, p7/m, z0.d, z31.d +fdiv z0.h, p7/m, z0.h, z31.h +fdiv z0.s, p7/m, z0.s, z31.s +fdivr z0.d, p7/m, z0.d, z31.d +fdivr z0.h, p7/m, z0.h, z31.h +fdivr z0.s, p7/m, z0.s, z31.s +fexpa z0.d, z31.d +fexpa z0.h, z31.h +fexpa z0.s, z31.s +flogb z31.d, p7/m, z31.d +flogb z31.h, p7/m, z31.h +flogb z31.s, p7/m, z31.s +fmad z0.d, p7/m, z1.d, z31.d +fmad z0.h, p7/m, z1.h, z31.h +fmad z0.s, p7/m, z1.s, z31.s +fmax z0.d, p0/m, z0.d, #0.0 +fmax z0.d, p7/m, z0.d, z31.d +fmax z0.h, p0/m, z0.h, #0.0 +fmax z0.h, p7/m, z0.h, z31.h +fmax z0.s, p0/m, z0.s, #0.0 +fmax z0.s, p7/m, z0.s, z31.s +fmax z31.d, p7/m, z31.d, #1.0 +fmax z31.h, p7/m, z31.h, #1.0 +fmax z31.s, p7/m, z31.s, #1.0 +fmaxnm z0.d, p0/m, z0.d, #0.0 +fmaxnm z0.d, p7/m, z0.d, z31.d +fmaxnm z0.h, p0/m, z0.h, #0.0 +fmaxnm z0.h, p7/m, z0.h, z31.h +fmaxnm z0.s, p0/m, z0.s, #0.0 +fmaxnm z0.s, p7/m, z0.s, z31.s +fmaxnm z31.d, p7/m, z31.d, #1.0 +fmaxnm z31.h, p7/m, z31.h, #1.0 +fmaxnm z31.s, p7/m, z31.s, #1.0 +fmaxnmp z0.h, p0/m, z0.h, z1.h +fmaxnmp z29.s, p3/m, z29.s, z30.s +fmaxnmp z31.d, p7/m, z31.d, z30.d +fmaxnmv d0, p7, z31.d +fmaxnmv h0, p7, z31.h +fmaxnmv s0, p7, z31.s +fmaxp z0.h, p0/m, z0.h, z1.h +fmaxp z29.s, p3/m, z29.s, z30.s +fmaxp z31.d, p7/m, z31.d, z30.d +fmaxv d0, p7, z31.d +fmaxv h0, p7, z31.h +fmaxv s0, p7, z31.s +fmin z0.d, p0/m, z0.d, #0.0 +fmin z0.d, p7/m, z0.d, z31.d +fmin z0.h, p0/m, z0.h, #0.0 +fmin z0.h, p7/m, z0.h, z31.h +fmin z0.s, p0/m, z0.s, #0.0 +fmin z0.s, p7/m, z0.s, z31.s +fmin z31.d, p7/m, z31.d, #1.0 +fmin z31.h, p7/m, z31.h, #1.0 +fmin z31.s, p7/m, z31.s, #1.0 +fminnm z0.d, p0/m, z0.d, #0.0 +fminnm z0.d, p7/m, z0.d, z31.d +fminnm z0.h, p0/m, z0.h, #0.0 +fminnm z0.h, p7/m, z0.h, z31.h +fminnm z0.s, p0/m, z0.s, #0.0 +fminnm z0.s, p7/m, z0.s, z31.s +fminnm z31.d, p7/m, z31.d, #1.0 +fminnm z31.h, p7/m, z31.h, #1.0 +fminnm z31.s, p7/m, z31.s, #1.0 +fminnmp z0.h, p0/m, z0.h, z1.h +fminnmp z29.s, p3/m, z29.s, z30.s +fminnmp z31.d, p7/m, z31.d, z30.d +fminnmv d0, p7, z31.d +fminnmv h0, p7, z31.h +fminnmv s0, p7, z31.s +fminp z0.h, p0/m, z0.h, z1.h +fminp z29.s, p3/m, z29.s, z30.s +fminp z31.d, p7/m, z31.d, z30.d +fminv d0, p7, z31.d +fminv h0, p7, z31.h +fminv s0, p7, z31.s +fmla z0.d, p7/m, z1.d, z31.d +fmla z0.d, z1.d, z7.d[1] +fmla z0.h, p7/m, z1.h, z31.h +fmla z0.h, z1.h, z7.h[7] +fmla z0.s, p7/m, z1.s, z31.s +fmla z0.s, z1.s, z7.s[3] +fmlalb z0.s, z1.h, z7.h[0] +fmlalb z29.s, z30.h, z31.h +fmlalb z30.s, z31.h, z7.h[7] +fmlalt z0.s, z1.h, z7.h[0] +fmlalt z29.s, z30.h, z31.h +fmlalt z30.s, z31.h, z7.h[7] +fmls z0.d, p7/m, z1.d, z31.d +fmls z0.d, z1.d, z7.d[1] +fmls z0.h, p7/m, z1.h, z31.h +fmls z0.h, z1.h, z7.h[7] +fmls z0.s, p7/m, z1.s, z31.s +fmls z0.s, z1.s, z7.s[3] +fmlslb z0.s, z1.h, z7.h[0] +fmlslb z29.s, z30.h, z31.h +fmlslb z30.s, z31.h, z7.h[7] +fmlslt z0.s, z1.h, z7.h[0] +fmlslt z29.s, z30.h, z31.h +fmlslt z30.s, z31.h, z7.h[7] +fmov z0.d, #-10.00000000 +fmov z0.d, #0.12500000 +fmov z0.d, p0/m, #-10.00000000 +fmov z0.d, p0/m, #0.12500000 +fmov z0.h, #-0.12500000 +fmov z0.h, p0/m, #-0.12500000 +fmov z0.s, #-0.12500000 +fmov z0.s, p0/m, #-0.12500000 +fmsb z0.d, p7/m, z1.d, z31.d +fmsb z0.h, p7/m, z1.h, z31.h +fmsb z0.s, p7/m, z1.s, z31.s +fmul z0.d, p0/m, z0.d, #0.5 +fmul z0.d, p7/m, z0.d, z31.d +fmul z0.d, z0.d, z0.d[0] +fmul z0.d, z1.d, z31.d +fmul z0.h, p0/m, z0.h, #0.5 +fmul z0.h, p7/m, z0.h, z31.h +fmul z0.h, z0.h, z0.h[0] +fmul z0.h, z1.h, z31.h +fmul z0.s, p0/m, z0.s, #0.5 +fmul z0.s, p7/m, z0.s, z31.s +fmul z0.s, z0.s, z0.s[0] +fmul z0.s, z1.s, z31.s +fmul z31.d, p7/m, z31.d, #2.0 +fmul z31.d, z31.d, z15.d[1] +fmul z31.h, p7/m, z31.h, #2.0 +fmul z31.h, z31.h, z7.h[7] +fmul z31.s, p7/m, z31.s, #2.0 +fmul z31.s, z31.s, z7.s[3] +fmulx z0.d, p7/m, z0.d, z31.d +fmulx z0.h, p7/m, z0.h, z31.h +fmulx z0.s, p7/m, z0.s, z31.s +fneg z31.d, p7/m, z31.d +fneg z31.h, p7/m, z31.h +fneg z31.s, p7/m, z31.s +fnmad z0.d, p7/m, z1.d, z31.d +fnmad z0.h, p7/m, z1.h, z31.h +fnmad z0.s, p7/m, z1.s, z31.s +fnmla z0.d, p7/m, z1.d, z31.d +fnmla z0.h, p7/m, z1.h, z31.h +fnmla z0.s, p7/m, z1.s, z31.s +fnmls z0.d, p7/m, z1.d, z31.d +fnmls z0.h, p7/m, z1.h, z31.h +fnmls z0.s, p7/m, z1.s, z31.s +fnmsb z0.d, p7/m, z1.d, z31.d +fnmsb z0.h, p7/m, z1.h, z31.h +fnmsb z0.s, p7/m, z1.s, z31.s +frecpe z0.d, z31.d +frecpe z0.h, z31.h +frecpe z0.s, z31.s +frecps z0.d, z1.d, z31.d +frecps z0.h, z1.h, z31.h +frecps z0.s, z1.s, z31.s +frecpx z31.d, p7/m, z31.d +frecpx z31.h, p7/m, z31.h +frecpx z31.s, p7/m, z31.s +frinta z31.d, p7/m, z31.d +frinta z31.h, p7/m, z31.h +frinta z31.s, p7/m, z31.s +frinti z31.d, p7/m, z31.d +frinti z31.h, p7/m, z31.h +frinti z31.s, p7/m, z31.s +frintm z31.d, p7/m, z31.d +frintm z31.h, p7/m, z31.h +frintm z31.s, p7/m, z31.s +frintn z31.d, p7/m, z31.d +frintn z31.h, p7/m, z31.h +frintn z31.s, p7/m, z31.s +frintp z31.d, p7/m, z31.d +frintp z31.h, p7/m, z31.h +frintp z31.s, p7/m, z31.s +frintx z31.d, p7/m, z31.d +frintx z31.h, p7/m, z31.h +frintx z31.s, p7/m, z31.s +frintz z31.d, p7/m, z31.d +frintz z31.h, p7/m, z31.h +frintz z31.s, p7/m, z31.s +frsqrte z0.d, z31.d +frsqrte z0.h, z31.h +frsqrte z0.s, z31.s +frsqrts z0.d, z1.d, z31.d +frsqrts z0.h, z1.h, z31.h +frsqrts z0.s, z1.s, z31.s +fscale z0.d, p7/m, z0.d, z31.d +fscale z0.h, p7/m, z0.h, z31.h +fscale z0.s, p7/m, z0.s, z31.s +fsqrt z31.d, p7/m, z31.d +fsqrt z31.h, p7/m, z31.h +fsqrt z31.s, p7/m, z31.s +fsub z0.d, p0/m, z0.d, #0.5 +fsub z0.d, p7/m, z0.d, z31.d +fsub z0.d, z1.d, z31.d +fsub z0.h, p0/m, z0.h, #0.5 +fsub z0.h, p7/m, z0.h, z31.h +fsub z0.h, z1.h, z31.h +fsub z0.s, p0/m, z0.s, #0.5 +fsub z0.s, p7/m, z0.s, z31.s +fsub z0.s, z1.s, z31.s +fsub z31.d, p7/m, z31.d, #1.0 +fsub z31.h, p7/m, z31.h, #1.0 +fsub z31.s, p7/m, z31.s, #1.0 +fsubr z0.d, p0/m, z0.d, #0.5 +fsubr z0.d, p7/m, z0.d, z31.d +fsubr z0.h, p0/m, z0.h, #0.5 +fsubr z0.h, p7/m, z0.h, z31.h +fsubr z0.s, p0/m, z0.s, #0.5 +fsubr z0.s, p7/m, z0.s, z31.s +fsubr z31.d, p7/m, z31.d, #1.0 +fsubr z31.h, p7/m, z31.h, #1.0 +fsubr z31.s, p7/m, z31.s, #1.0 +ftmad z0.d, z0.d, z31.d, #7 +ftmad z0.h, z0.h, z31.h, #7 +ftmad z0.s, z0.s, z31.s, #7 +ftsmul z0.d, z1.d, z31.d +ftsmul z0.h, z1.h, z31.h +ftsmul z0.s, z1.s, z31.s +ftssel z0.d, z1.d, z31.d +ftssel z0.h, z1.h, z31.h +ftssel z0.s, z1.s, z31.s +histcnt z0.s, p0/z, z1.s, z2.s +histcnt z29.d, p7/z, z30.d, z31.d +histseg z0.b, z1.b, z31.b +incb x0 +incb x0, #14 +incb x0, all, mul #16 +incb x0, pow2 +incb x0, vl1 +incd x0 +incd x0, #14 +incd x0, all, mul #16 +incd x0, pow2 +incd x0, vl1 +incd z0.d +incd z0.d, all, mul #16 +inch x0 +inch x0, #14 +inch x0, all, mul #16 +inch x0, pow2 +inch x0, vl1 +inch z0.h +inch z0.h, all, mul #16 +incp x0, p0.b +incp x0, p0.d +incp x0, p0.h +incp x0, p0.s +incp xzr, p15.b +incp xzr, p15.d +incp xzr, p15.h +incp xzr, p15.s +incp z31.d, p15.d +incp z31.h, p15.h +incp z31.s, p15.s +incw x0 +incw x0, #14 +incw x0, all, mul #16 +incw x0, pow2 +incw x0, vl1 +incw z0.s +incw z0.s, all, mul #16 +index z0.b, #0, #0 +index z0.d, #0, #0 +index z0.h, #0, #0 +index z0.h, w0, w0 +index z0.s, #0, #0 +index z21.b, w10, w21 +index z21.d, x10, x21 +index z21.s, w10, w21 +index z23.b, #13, w8 +index z23.b, w13, #8 +index z23.d, #13, x8 +index z23.d, x13, #8 +index z23.h, #13, w8 +index z23.h, w13, #8 +index z23.s, #13, w8 +index z23.s, w13, #8 +index z31.b, #-1, #-1 +index z31.b, #-1, wzr +index z31.b, wzr, #-1 +index z31.b, wzr, wzr +index z31.d, #-1, #-1 +index z31.d, #-1, xzr +index z31.d, xzr, #-1 +index z31.d, xzr, xzr +index z31.h, #-1, #-1 +index z31.h, #-1, wzr +index z31.h, wzr, #-1 +index z31.h, wzr, wzr +index z31.s, #-1, #-1 +index z31.s, #-1, wzr +index z31.s, wzr, #-1 +index z31.s, wzr, wzr +insr z0.b, w0 +insr z0.d, x0 +insr z0.h, w0 +insr z0.s, w0 +insr z31.b, b31 +insr z31.b, wzr +insr z31.d, d31 +insr z31.d, xzr +insr z31.h, h31 +insr z31.h, wzr +insr z31.s, s31 +insr z31.s, wzr +lasta b0, p7, z31.b +lasta d0, p7, z31.d +lasta h0, p7, z31.h +lasta s0, p7, z31.s +lasta w0, p7, z31.b +lasta w0, p7, z31.h +lasta w0, p7, z31.s +lasta x0, p7, z31.d +lastb b0, p7, z31.b +lastb d0, p7, z31.d +lastb h0, p7, z31.h +lastb s0, p7, z31.s +lastb w0, p7, z31.b +lastb w0, p7, z31.h +lastb w0, p7, z31.s +lastb x0, p7, z31.d +ld1b { z0.b }, p0/z, [sp, x0] +ld1b { z0.b }, p0/z, [x0, x0] +ld1b { z0.b }, p0/z, [x0] +ld1b { z0.d }, p0/z, [x0] +ld1b { z0.d }, p0/z, [z0.d] +ld1b { z0.h }, p0/z, [x0] +ld1b { z0.s }, p0/z, [x0, z0.s, sxtw] +ld1b { z0.s }, p0/z, [x0, z0.s, uxtw] +ld1b { z0.s }, p0/z, [x0] +ld1b { z0.s }, p0/z, [z0.s] +ld1b { z21.b }, p5/z, [x10, #5, mul vl] +ld1b { z21.d }, p5/z, [x10, #5, mul vl] +ld1b { z21.d }, p5/z, [x10, z21.d, sxtw] +ld1b { z21.d }, p5/z, [x10, z21.d, uxtw] +ld1b { z21.h }, p5/z, [x10, #5, mul vl] +ld1b { z21.s }, p5/z, [x10, #5, mul vl] +ld1b { z21.s }, p5/z, [x10, x21] +ld1b { z23.d }, p3/z, [x13, x8] +ld1b { z31.b }, p7/z, [sp, #-1, mul vl] +ld1b { z31.d }, p7/z, [sp, #-1, mul vl] +ld1b { z31.d }, p7/z, [sp, z31.d] +ld1b { z31.d }, p7/z, [z31.d, #31] +ld1b { z31.h }, p7/z, [sp, #-1, mul vl] +ld1b { z31.s }, p7/z, [sp, #-1, mul vl] +ld1b { z31.s }, p7/z, [z31.s, #31] +ld1b { z5.h }, p3/z, [x17, x16] +ld1d { z0.d }, p0/z, [x0, z0.d, sxtw #3] +ld1d { z0.d }, p0/z, [x0, z0.d, uxtw #3] +ld1d { z0.d }, p0/z, [x0] +ld1d { z0.d }, p0/z, [z0.d] +ld1d { z21.d }, p5/z, [x10, #5, mul vl] +ld1d { z21.d }, p5/z, [x10, z21.d, sxtw] +ld1d { z21.d }, p5/z, [x10, z21.d, uxtw] +ld1d { z23.d }, p3/z, [sp, x8, lsl #3] +ld1d { z23.d }, p3/z, [x13, x8, lsl #3] +ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3] +ld1d { z31.d }, p7/z, [sp, #-1, mul vl] +ld1d { z31.d }, p7/z, [sp, z31.d] +ld1d { z31.d }, p7/z, [z31.d, #248] +ld1h { z0.d }, p0/z, [x0, z0.d, sxtw #1] +ld1h { z0.d }, p0/z, [x0, z0.d, uxtw #1] +ld1h { z0.d }, p0/z, [x0] +ld1h { z0.d }, p0/z, [z0.d] +ld1h { z0.h }, p0/z, [x0] +ld1h { z0.s }, p0/z, [x0, z0.s, sxtw] +ld1h { z0.s }, p0/z, [x0, z0.s, uxtw] +ld1h { z0.s }, p0/z, [x0] +ld1h { z0.s }, p0/z, [z0.s] +ld1h { z21.d }, p5/z, [x10, #5, mul vl] +ld1h { z21.d }, p5/z, [x10, z21.d, sxtw] +ld1h { z21.d }, p5/z, [x10, z21.d, uxtw] +ld1h { z21.h }, p5/z, [x10, #5, mul vl] +ld1h { z21.s }, p5/z, [x10, #5, mul vl] +ld1h { z21.s }, p5/z, [x10, x21, lsl #1] +ld1h { z23.d }, p3/z, [x13, x8, lsl #1] +ld1h { z23.d }, p3/z, [x13, z8.d, lsl #1] +ld1h { z31.d }, p7/z, [sp, #-1, mul vl] +ld1h { z31.d }, p7/z, [sp, z31.d] +ld1h { z31.d }, p7/z, [z31.d, #62] +ld1h { z31.h }, p7/z, [sp, #-1, mul vl] +ld1h { z31.s }, p7/z, [sp, #-1, mul vl] +ld1h { z31.s }, p7/z, [sp, z31.s, sxtw #1] +ld1h { z31.s }, p7/z, [sp, z31.s, uxtw #1] +ld1h { z31.s }, p7/z, [z31.s, #62] +ld1h { z5.h }, p3/z, [sp, x16, lsl #1] +ld1h { z5.h }, p3/z, [x17, x16, lsl #1] +ld1rb { z0.b }, p0/z, [x0] +ld1rb { z0.d }, p0/z, [x0] +ld1rb { z0.h }, p0/z, [x0] +ld1rb { z0.s }, p0/z, [x0] +ld1rb { z31.b }, p7/z, [sp, #63] +ld1rb { z31.d }, p7/z, [sp, #63] +ld1rb { z31.h }, p7/z, [sp, #63] +ld1rb { z31.s }, p7/z, [sp, #63] +ld1rd { z0.d }, p0/z, [x0] +ld1rd { z31.d }, p7/z, [sp, #504] +ld1rh { z0.d }, p0/z, [x0] +ld1rh { z0.h }, p0/z, [x0] +ld1rh { z0.s }, p0/z, [x0] +ld1rh { z31.d }, p7/z, [sp, #126] +ld1rh { z31.h }, p7/z, [sp, #126] +ld1rh { z31.s }, p7/z, [sp, #126] +ld1rqb { z0.b }, p0/z, [x0, x0] +ld1rqb { z0.b }, p0/z, [x0] +ld1rqb { z21.b }, p5/z, [x10, #112] +ld1rqb { z23.b }, p3/z, [x13, #-128] +ld1rqb { z31.b }, p7/z, [sp, #-16] +ld1rqd { z0.d }, p0/z, [x0, x0, lsl #3] +ld1rqd { z0.d }, p0/z, [x0] +ld1rqd { z23.d }, p3/z, [x13, #-128] +ld1rqd { z23.d }, p3/z, [x13, #112] +ld1rqd { z31.d }, p7/z, [sp, #-16] +ld1rqh { z0.h }, p0/z, [x0, x0, lsl #1] +ld1rqh { z0.h }, p0/z, [x0] +ld1rqh { z23.h }, p3/z, [x13, #-128] +ld1rqh { z23.h }, p3/z, [x13, #112] +ld1rqh { z31.h }, p7/z, [sp, #-16] +ld1rqw { z0.s }, p0/z, [x0, x0, lsl #2] +ld1rqw { z0.s }, p0/z, [x0] +ld1rqw { z23.s }, p3/z, [x13, #-128] +ld1rqw { z23.s }, p3/z, [x13, #112] +ld1rqw { z31.s }, p7/z, [sp, #-16] +ld1rsb { z0.d }, p0/z, [x0] +ld1rsb { z0.h }, p0/z, [x0] +ld1rsb { z0.s }, p0/z, [x0] +ld1rsb { z31.d }, p7/z, [sp, #63] +ld1rsb { z31.h }, p7/z, [sp, #63] +ld1rsb { z31.s }, p7/z, [sp, #63] +ld1rsh { z0.d }, p0/z, [x0] +ld1rsh { z0.s }, p0/z, [x0] +ld1rsh { z31.d }, p7/z, [sp, #126] +ld1rsh { z31.s }, p7/z, [sp, #126] +ld1rsw { z0.d }, p0/z, [x0] +ld1rsw { z31.d }, p7/z, [sp, #252] +ld1rw { z0.d }, p0/z, [x0] +ld1rw { z0.s }, p0/z, [x0] +ld1rw { z31.d }, p7/z, [sp, #252] +ld1rw { z31.s }, p7/z, [sp, #252] +ld1sb { z0.d }, p0/z, [x0] +ld1sb { z0.d }, p0/z, [z0.d] +ld1sb { z0.h }, p0/z, [sp, x0] +ld1sb { z0.h }, p0/z, [x0, x0] +ld1sb { z0.h }, p0/z, [x0] +ld1sb { z0.s }, p0/z, [x0, z0.s, sxtw] +ld1sb { z0.s }, p0/z, [x0] +ld1sb { z0.s }, p0/z, [z0.s] +ld1sb { z21.d }, p5/z, [x10, #5, mul vl] +ld1sb { z21.d }, p5/z, [x10, z21.d, sxtw] +ld1sb { z21.d }, p5/z, [x10, z21.d, uxtw] +ld1sb { z21.h }, p5/z, [x10, #5, mul vl] +ld1sb { z21.s }, p5/z, [x10, #5, mul vl] +ld1sb { z21.s }, p5/z, [x10, x21] +ld1sb { z23.d }, p3/z, [x13, x8] +ld1sb { z31.d }, p7/z, [sp, #-1, mul vl] +ld1sb { z31.d }, p7/z, [sp, z31.d] +ld1sb { z31.d }, p7/z, [z31.d, #31] +ld1sb { z31.h }, p7/z, [sp, #-1, mul vl] +ld1sb { z31.s }, p7/z, [sp, #-1, mul vl] +ld1sb { z31.s }, p7/z, [z31.s, #31] +ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1] +ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1] +ld1sh { z0.d }, p0/z, [x0] +ld1sh { z0.d }, p0/z, [z0.d] +ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw] +ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw] +ld1sh { z0.s }, p0/z, [x0] +ld1sh { z0.s }, p0/z, [z0.s] +ld1sh { z21.d }, p5/z, [x10, #5, mul vl] +ld1sh { z21.d }, p5/z, [x10, z21.d, sxtw] +ld1sh { z21.d }, p5/z, [x10, z21.d, uxtw] +ld1sh { z21.s }, p5/z, [sp, x21, lsl #1] +ld1sh { z21.s }, p5/z, [x10, #5, mul vl] +ld1sh { z21.s }, p5/z, [x10, x21, lsl #1] +ld1sh { z23.d }, p3/z, [x13, x8, lsl #1] +ld1sh { z23.d }, p3/z, [x13, z8.d, lsl #1] +ld1sh { z31.d }, p7/z, [sp, #-1, mul vl] +ld1sh { z31.d }, p7/z, [sp, z31.d] +ld1sh { z31.d }, p7/z, [z31.d, #62] +ld1sh { z31.s }, p7/z, [sp, #-1, mul vl] +ld1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1] +ld1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1] +ld1sh { z31.s }, p7/z, [z31.s, #62] +ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2] +ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2] +ld1sw { z0.d }, p0/z, [x0] +ld1sw { z0.d }, p0/z, [z0.d] +ld1sw { z21.d }, p5/z, [x10, #5, mul vl] +ld1sw { z21.d }, p5/z, [x10, z21.d, sxtw] +ld1sw { z21.d }, p5/z, [x10, z21.d, uxtw] +ld1sw { z23.d }, p3/z, [sp, x8, lsl #2] +ld1sw { z23.d }, p3/z, [x13, x8, lsl #2] +ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2] +ld1sw { z31.d }, p7/z, [sp, #-1, mul vl] +ld1sw { z31.d }, p7/z, [sp, z31.d] +ld1sw { z31.d }, p7/z, [z31.d, #124] +ld1w { z0.d }, p0/z, [x0, z0.d, sxtw #2] +ld1w { z0.d }, p0/z, [x0, z0.d, uxtw #2] +ld1w { z0.d }, p0/z, [x0] +ld1w { z0.d }, p0/z, [z0.d] +ld1w { z0.s }, p0/z, [x0, z0.s, sxtw] +ld1w { z0.s }, p0/z, [x0, z0.s, uxtw] +ld1w { z0.s }, p0/z, [x0] +ld1w { z0.s }, p0/z, [z0.s] +ld1w { z21.d }, p5/z, [x10, #5, mul vl] +ld1w { z21.d }, p5/z, [x10, z21.d, sxtw] +ld1w { z21.d }, p5/z, [x10, z21.d, uxtw] +ld1w { z21.s }, p5/z, [sp, x21, lsl #2] +ld1w { z21.s }, p5/z, [x10, #5, mul vl] +ld1w { z21.s }, p5/z, [x10, x21, lsl #2] +ld1w { z23.d }, p3/z, [x13, x8, lsl #2] +ld1w { z23.d }, p3/z, [x13, z8.d, lsl #2] +ld1w { z31.d }, p7/z, [sp, #-1, mul vl] +ld1w { z31.d }, p7/z, [sp, z31.d] +ld1w { z31.d }, p7/z, [z31.d, #124] +ld1w { z31.s }, p7/z, [sp, #-1, mul vl] +ld1w { z31.s }, p7/z, [sp, z31.s, sxtw #2] +ld1w { z31.s }, p7/z, [sp, z31.s, uxtw #2] +ld1w { z31.s }, p7/z, [z31.s, #124] +ld2b { z0.b, z1.b }, p0/z, [x0, x0] +ld2b { z0.b, z1.b }, p0/z, [x0] +ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl] +ld2b { z23.b, z24.b }, p3/z, [x13, #-16, mul vl] +ld2b { z5.b, z6.b }, p3/z, [x17, x16] +ld2d { z0.d, z1.d }, p0/z, [x0, x0, lsl #3] +ld2d { z0.d, z1.d }, p0/z, [x0] +ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl] +ld2d { z23.d, z24.d }, p3/z, [x13, #-16, mul vl] +ld2d { z5.d, z6.d }, p3/z, [x17, x16, lsl #3] +ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1] +ld2h { z0.h, z1.h }, p0/z, [x0] +ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl] +ld2h { z23.h, z24.h }, p3/z, [x13, #-16, mul vl] +ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1] +ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #2] +ld2w { z0.s, z1.s }, p0/z, [x0] +ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl] +ld2w { z23.s, z24.s }, p3/z, [x13, #-16, mul vl] +ld2w { z5.s, z6.s }, p3/z, [x17, x16, lsl #2] +ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, x0] +ld3b { z0.b, z1.b, z2.b }, p0/z, [x0] +ld3b { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl] +ld3b { z23.b, z24.b, z25.b }, p3/z, [x13, #-24, mul vl] +ld3b { z5.b, z6.b, z7.b }, p3/z, [x17, x16] +ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, x0, lsl #3] +ld3d { z0.d, z1.d, z2.d }, p0/z, [x0] +ld3d { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl] +ld3d { z23.d, z24.d, z25.d }, p3/z, [x13, #-24, mul vl] +ld3d { z5.d, z6.d, z7.d }, p3/z, [x17, x16, lsl #3] +ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #1] +ld3h { z0.h, z1.h, z2.h }, p0/z, [x0] +ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl] +ld3h { z23.h, z24.h, z25.h }, p3/z, [x13, #-24, mul vl] +ld3h { z5.h, z6.h, z7.h }, p3/z, [x17, x16, lsl #1] +ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, x0, lsl #2] +ld3w { z0.s, z1.s, z2.s }, p0/z, [x0] +ld3w { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl] +ld3w { z23.s, z24.s, z25.s }, p3/z, [x13, #-24, mul vl] +ld3w { z5.s, z6.s, z7.s }, p3/z, [x17, x16, lsl #2] +ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x0] +ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0] +ld4b { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl] +ld4b { z23.b, z24.b, z25.b, z26.b }, p3/z, [x13, #-32, mul vl] +ld4b { z5.b, z6.b, z7.b, z8.b }, p3/z, [x17, x16] +ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #3] +ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0] +ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl] +ld4d { z23.d, z24.d, z25.d, z26.d }, p3/z, [x13, #-32, mul vl] +ld4d { z5.d, z6.d, z7.d, z8.d }, p3/z, [x17, x16, lsl #3] +ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0, lsl #1] +ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0] +ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl] +ld4h { z23.h, z24.h, z25.h, z26.h }, p3/z, [x13, #-32, mul vl] +ld4h { z5.h, z6.h, z7.h, z8.h }, p3/z, [x17, x16, lsl #1] +ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0, lsl #2] +ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0] +ld4w { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl] +ld4w { z23.s, z24.s, z25.s, z26.s }, p3/z, [x13, #-32, mul vl] +ld4w { z5.s, z6.s, z7.s, z8.s }, p3/z, [x17, x16, lsl #2] +ldff1b { z0.d }, p0/z, [x0, x0] +ldff1b { z0.d }, p0/z, [z0.d] +ldff1b { z0.h }, p0/z, [x0, x0] +ldff1b { z0.s }, p0/z, [x0, x0] +ldff1b { z0.s }, p0/z, [x0, z0.s, sxtw] +ldff1b { z0.s }, p0/z, [x0, z0.s, uxtw] +ldff1b { z0.s }, p0/z, [z0.s] +ldff1b { z21.d }, p5/z, [x10, z21.d, sxtw] +ldff1b { z21.d }, p5/z, [x10, z21.d, uxtw] +ldff1b { z31.b }, p7/z, [sp] +ldff1b { z31.d }, p7/z, [sp, z31.d] +ldff1b { z31.d }, p7/z, [sp] +ldff1b { z31.d }, p7/z, [z31.d, #31] +ldff1b { z31.h }, p7/z, [sp] +ldff1b { z31.s }, p7/z, [sp] +ldff1b { z31.s }, p7/z, [z31.s, #31] +ldff1d { z0.d }, p0/z, [x0, x0, lsl #3] +ldff1d { z0.d }, p0/z, [x0, z0.d, sxtw #3] +ldff1d { z0.d }, p0/z, [x0, z0.d, uxtw #3] +ldff1d { z0.d }, p0/z, [z0.d] +ldff1d { z21.d }, p5/z, [x10, z21.d, sxtw] +ldff1d { z21.d }, p5/z, [x10, z21.d, uxtw] +ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3] +ldff1d { z31.d }, p7/z, [sp, z31.d] +ldff1d { z31.d }, p7/z, [sp] +ldff1d { z31.d }, p7/z, [z31.d, #248] +ldff1h { z0.d }, p0/z, [x0, x0, lsl #1] +ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw #1] +ldff1h { z0.d }, p0/z, [x0, z0.d, uxtw #1] +ldff1h { z0.d }, p0/z, [z0.d] +ldff1h { z0.h }, p0/z, [x0, x0, lsl #1] +ldff1h { z0.s }, p0/z, [x0, x0, lsl #1] +ldff1h { z0.s }, p0/z, [x0, z0.s, sxtw] +ldff1h { z0.s }, p0/z, [x0, z0.s, uxtw] +ldff1h { z0.s }, p0/z, [z0.s] +ldff1h { z21.d }, p5/z, [x10, z21.d, sxtw] +ldff1h { z21.d }, p5/z, [x10, z21.d, uxtw] +ldff1h { z23.d }, p3/z, [x13, z8.d, lsl #1] +ldff1h { z31.d }, p7/z, [sp, z31.d] +ldff1h { z31.d }, p7/z, [sp] +ldff1h { z31.d }, p7/z, [z31.d, #62] +ldff1h { z31.h }, p7/z, [sp] +ldff1h { z31.s }, p7/z, [sp, z31.s, sxtw #1] +ldff1h { z31.s }, p7/z, [sp, z31.s, uxtw #1] +ldff1h { z31.s }, p7/z, [sp] +ldff1h { z31.s }, p7/z, [z31.s, #62] +ldff1sb { z0.d }, p0/z, [x0, x0] +ldff1sb { z0.d }, p0/z, [z0.d] +ldff1sb { z0.h }, p0/z, [x0, x0] +ldff1sb { z0.s }, p0/z, [x0, x0] +ldff1sb { z0.s }, p0/z, [x0, z0.s, sxtw] +ldff1sb { z0.s }, p0/z, [x0, z0.s, uxtw] +ldff1sb { z0.s }, p0/z, [z0.s] +ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw] +ldff1sb { z21.d }, p5/z, [x10, z21.d, uxtw] +ldff1sb { z31.d }, p7/z, [sp, z31.d] +ldff1sb { z31.d }, p7/z, [sp] +ldff1sb { z31.d }, p7/z, [z31.d, #31] +ldff1sb { z31.h }, p7/z, [sp] +ldff1sb { z31.s }, p7/z, [sp] +ldff1sb { z31.s }, p7/z, [z31.s, #31] +ldff1sh { z0.d }, p0/z, [x0, x0, lsl #1] +ldff1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1] +ldff1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1] +ldff1sh { z0.d }, p0/z, [z0.d] +ldff1sh { z0.s }, p0/z, [x0, x0, lsl #1] +ldff1sh { z0.s }, p0/z, [x0, z0.s, sxtw] +ldff1sh { z0.s }, p0/z, [x0, z0.s, uxtw] +ldff1sh { z0.s }, p0/z, [z0.s] +ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw] +ldff1sh { z21.d }, p5/z, [x10, z21.d, uxtw] +ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1] +ldff1sh { z31.d }, p7/z, [sp, z31.d] +ldff1sh { z31.d }, p7/z, [sp] +ldff1sh { z31.d }, p7/z, [z31.d, #62] +ldff1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1] +ldff1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1] +ldff1sh { z31.s }, p7/z, [sp] +ldff1sh { z31.s }, p7/z, [z31.s, #62] +ldff1sw { z0.d }, p0/z, [x0, x0, lsl #2] +ldff1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2] +ldff1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2] +ldff1sw { z0.d }, p0/z, [z0.d] +ldff1sw { z21.d }, p5/z, [x10, z21.d, sxtw] +ldff1sw { z21.d }, p5/z, [x10, z21.d, uxtw] +ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2] +ldff1sw { z31.d }, p7/z, [sp, z31.d] +ldff1sw { z31.d }, p7/z, [sp] +ldff1sw { z31.d }, p7/z, [z31.d, #124] +ldff1w { z0.d }, p0/z, [x0, x0, lsl #2] +ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw #2] +ldff1w { z0.d }, p0/z, [x0, z0.d, uxtw #2] +ldff1w { z0.d }, p0/z, [z0.d] +ldff1w { z0.s }, p0/z, [x0, x0, lsl #2] +ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw] +ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw] +ldff1w { z0.s }, p0/z, [z0.s] +ldff1w { z21.d }, p5/z, [x10, z21.d, sxtw] +ldff1w { z21.d }, p5/z, [x10, z21.d, uxtw] +ldff1w { z23.d }, p3/z, [x13, z8.d, lsl #2] +ldff1w { z31.d }, p7/z, [sp, z31.d] +ldff1w { z31.d }, p7/z, [sp] +ldff1w { z31.d }, p7/z, [z31.d, #124] +ldff1w { z31.s }, p7/z, [sp, z31.s, sxtw #2] +ldff1w { z31.s }, p7/z, [sp, z31.s, uxtw #2] +ldff1w { z31.s }, p7/z, [sp] +ldff1w { z31.s }, p7/z, [z31.s, #124] +ldnf1b { z0.b }, p0/z, [x0] +ldnf1b { z0.d }, p0/z, [x0] +ldnf1b { z0.h }, p0/z, [x0] +ldnf1b { z0.s }, p0/z, [x0] +ldnf1b { z21.b }, p5/z, [x10, #5, mul vl] +ldnf1b { z21.d }, p5/z, [x10, #5, mul vl] +ldnf1b { z21.h }, p5/z, [x10, #5, mul vl] +ldnf1b { z21.s }, p5/z, [x10, #5, mul vl] +ldnf1b { z31.b }, p7/z, [sp, #-1, mul vl] +ldnf1b { z31.d }, p7/z, [sp, #-1, mul vl] +ldnf1b { z31.h }, p7/z, [sp, #-1, mul vl] +ldnf1b { z31.s }, p7/z, [sp, #-1, mul vl] +ldnf1d { z0.d }, p0/z, [x0] +ldnf1d { z21.d }, p5/z, [x10, #5, mul vl] +ldnf1d { z31.d }, p7/z, [sp, #-1, mul vl] +ldnf1h { z0.d }, p0/z, [x0] +ldnf1h { z0.h }, p0/z, [x0] +ldnf1h { z0.s }, p0/z, [x0] +ldnf1h { z21.d }, p5/z, [x10, #5, mul vl] +ldnf1h { z21.h }, p5/z, [x10, #5, mul vl] +ldnf1h { z21.s }, p5/z, [x10, #5, mul vl] +ldnf1h { z31.d }, p7/z, [sp, #-1, mul vl] +ldnf1h { z31.h }, p7/z, [sp, #-1, mul vl] +ldnf1h { z31.s }, p7/z, [sp, #-1, mul vl] +ldnf1sb { z0.d }, p0/z, [x0] +ldnf1sb { z0.h }, p0/z, [x0] +ldnf1sb { z0.s }, p0/z, [x0] +ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl] +ldnf1sb { z21.h }, p5/z, [x10, #5, mul vl] +ldnf1sb { z21.s }, p5/z, [x10, #5, mul vl] +ldnf1sb { z31.d }, p7/z, [sp, #-1, mul vl] +ldnf1sb { z31.h }, p7/z, [sp, #-1, mul vl] +ldnf1sb { z31.s }, p7/z, [sp, #-1, mul vl] +ldnf1sh { z0.d }, p0/z, [x0] +ldnf1sh { z0.s }, p0/z, [x0] +ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl] +ldnf1sh { z21.s }, p5/z, [x10, #5, mul vl] +ldnf1sh { z31.d }, p7/z, [sp, #-1, mul vl] +ldnf1sh { z31.s }, p7/z, [sp, #-1, mul vl] +ldnf1sw { z0.d }, p0/z, [x0] +ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl] +ldnf1sw { z31.d }, p7/z, [sp, #-1, mul vl] +ldnf1w { z0.d }, p0/z, [x0] +ldnf1w { z0.s }, p0/z, [x0] +ldnf1w { z21.d }, p5/z, [x10, #5, mul vl] +ldnf1w { z21.s }, p5/z, [x10, #5, mul vl] +ldnf1w { z31.d }, p7/z, [sp, #-1, mul vl] +ldnf1w { z31.s }, p7/z, [sp, #-1, mul vl] +ldnt1b { z0.b }, p0/z, [x0, x0] +ldnt1b { z0.b }, p0/z, [x0] +ldnt1b { z0.d }, p0/z, [z1.d] +ldnt1b { z0.s }, p0/z, [z1.s] +ldnt1b { z21.b }, p5/z, [x10, #7, mul vl] +ldnt1b { z23.b }, p3/z, [x13, #-8, mul vl] +ldnt1b { z31.d }, p7/z, [z31.d, x0] +ldnt1b { z31.d }, p7/z, [z31.d] +ldnt1b { z31.s }, p7/z, [z31.s, x0] +ldnt1b { z31.s }, p7/z, [z31.s] +ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3] +ldnt1d { z0.d }, p0/z, [x0] +ldnt1d { z0.d }, p0/z, [z1.d] +ldnt1d { z21.d }, p5/z, [x10, #7, mul vl] +ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl] +ldnt1d { z31.d }, p7/z, [z31.d, x0] +ldnt1d { z31.d }, p7/z, [z31.d] +ldnt1h { z0.d }, p0/z, [z1.d] +ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1] +ldnt1h { z0.h }, p0/z, [x0] +ldnt1h { z0.s }, p0/z, [z1.s] +ldnt1h { z21.h }, p5/z, [x10, #7, mul vl] +ldnt1h { z23.h }, p3/z, [x13, #-8, mul vl] +ldnt1h { z31.d }, p7/z, [z31.d, x0] +ldnt1h { z31.d }, p7/z, [z31.d] +ldnt1h { z31.s }, p7/z, [z31.s, x0] +ldnt1h { z31.s }, p7/z, [z31.s] +ldnt1sb { z0.d }, p0/z, [z1.d] +ldnt1sb { z0.s }, p0/z, [z1.s] +ldnt1sb { z31.d }, p7/z, [z31.d, x0] +ldnt1sb { z31.d }, p7/z, [z31.d] +ldnt1sb { z31.s }, p7/z, [z31.s, x0] +ldnt1sb { z31.s }, p7/z, [z31.s] +ldnt1sh { z0.d }, p0/z, [z1.d] +ldnt1sh { z0.s }, p0/z, [z1.s] +ldnt1sh { z31.d }, p7/z, [z31.d, x0] +ldnt1sh { z31.d }, p7/z, [z31.d] +ldnt1sh { z31.s }, p7/z, [z31.s, x0] +ldnt1sh { z31.s }, p7/z, [z31.s] +ldnt1sw { z0.d }, p0/z, [z1.d] +ldnt1sw { z31.d }, p7/z, [z31.d, x0] +ldnt1sw { z31.d }, p7/z, [z31.d] +ldnt1w { z0.d }, p0/z, [z1.d] +ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2] +ldnt1w { z0.s }, p0/z, [x0] +ldnt1w { z0.s }, p0/z, [z1.s] +ldnt1w { z21.s }, p5/z, [x10, #7, mul vl] +ldnt1w { z23.s }, p3/z, [x13, #-8, mul vl] +ldnt1w { z31.d }, p7/z, [z31.d, x0] +ldnt1w { z31.d }, p7/z, [z31.d] +ldnt1w { z31.s }, p7/z, [z31.s, x0] +ldnt1w { z31.s }, p7/z, [z31.s] +ldr p0, [x0] +ldr p5, [x10, #255, mul vl] +ldr p7, [x13, #-256, mul vl] +ldr z0, [x0] +ldr z23, [x13, #255, mul vl] +ldr z31, [sp, #-256, mul vl] +lsl z0.b, p0/m, z0.b, #0 +lsl z0.b, p0/m, z0.b, z0.b +lsl z0.b, p0/m, z0.b, z1.d +lsl z0.b, z0.b, #0 +lsl z0.b, z1.b, z2.d +lsl z0.d, p0/m, z0.d, #0 +lsl z0.d, p0/m, z0.d, z0.d +lsl z0.d, z0.d, #0 +lsl z0.h, p0/m, z0.h, #0 +lsl z0.h, p0/m, z0.h, z0.h +lsl z0.h, p0/m, z0.h, z1.d +lsl z0.h, z0.h, #0 +lsl z0.h, z1.h, z2.d +lsl z0.s, p0/m, z0.s, #0 +lsl z0.s, p0/m, z0.s, z0.s +lsl z0.s, p0/m, z0.s, z1.d +lsl z0.s, z0.s, #0 +lsl z0.s, z1.s, z2.d +lsl z31.b, p0/m, z31.b, #7 +lsl z31.b, z31.b, #7 +lsl z31.d, p0/m, z31.d, #63 +lsl z31.d, z31.d, #63 +lsl z31.h, p0/m, z31.h, #15 +lsl z31.h, z31.h, #15 +lsl z31.s, p0/m, z31.s, #31 +lsl z31.s, z31.s, #31 +lslr z0.b, p0/m, z0.b, z0.b +lslr z0.d, p0/m, z0.d, z0.d +lslr z0.h, p0/m, z0.h, z0.h +lslr z0.s, p0/m, z0.s, z0.s +lsr z0.b, p0/m, z0.b, #1 +lsr z0.b, p0/m, z0.b, z0.b +lsr z0.b, p0/m, z0.b, z1.d +lsr z0.b, z0.b, #1 +lsr z0.b, z1.b, z2.d +lsr z0.d, p0/m, z0.d, #1 +lsr z0.d, p0/m, z0.d, z0.d +lsr z0.d, z0.d, #1 +lsr z0.h, p0/m, z0.h, #1 +lsr z0.h, p0/m, z0.h, z0.h +lsr z0.h, p0/m, z0.h, z1.d +lsr z0.h, z0.h, #1 +lsr z0.h, z1.h, z2.d +lsr z0.s, p0/m, z0.s, #1 +lsr z0.s, p0/m, z0.s, z0.s +lsr z0.s, p0/m, z0.s, z1.d +lsr z0.s, z0.s, #1 +lsr z0.s, z1.s, z2.d +lsr z31.b, p0/m, z31.b, #8 +lsr z31.b, z31.b, #8 +lsr z31.d, p0/m, z31.d, #64 +lsr z31.d, z31.d, #64 +lsr z31.h, p0/m, z31.h, #16 +lsr z31.h, z31.h, #16 +lsr z31.s, p0/m, z31.s, #32 +lsr z31.s, z31.s, #32 +lsrr z0.b, p0/m, z0.b, z0.b +lsrr z0.d, p0/m, z0.d, z0.d +lsrr z0.h, p0/m, z0.h, z0.h +lsrr z0.s, p0/m, z0.s, z0.s +mad z0.b, p7/m, z1.b, z31.b +mad z0.d, p7/m, z1.d, z31.d +mad z0.h, p7/m, z1.h, z31.h +mad z0.s, p7/m, z1.s, z31.s +match p0.b, p0/z, z0.b, z0.b +match p0.h, p0/z, z0.h, z0.h +match p15.b, p7/z, z30.b, z31.b +match p15.h, p7/z, z30.h, z31.h +mla z0.b, p7/m, z1.b, z31.b +mla z0.d, p7/m, z1.d, z31.d +mla z0.d, z1.d, z7.d[1] +mla z0.h, p7/m, z1.h, z31.h +mla z0.h, z1.h, z7.h[7] +mla z0.s, p7/m, z1.s, z31.s +mla z0.s, z1.s, z7.s[3] +mls z0.b, p7/m, z1.b, z31.b +mls z0.d, p7/m, z1.d, z31.d +mls z0.d, z1.d, z7.d[1] +mls z0.h, p7/m, z1.h, z31.h +mls z0.h, z1.h, z7.h[7] +mls z0.s, p7/m, z1.s, z31.s +mls z0.s, z1.s, z7.s[3] +mov p0.b, p0.b +mov p0.b, p0/m, p0.b +mov p0.b, p0/z, p0.b +mov p15.b, p15.b +mov p15.b, p15/m, p15.b +mov p15.b, p15/z, p15.b +mov z0.b, #127 +mov z0.b, b0 +mov z0.b, p0/m, b0 +mov z0.b, p0/m, w0 +mov z0.b, p0/z, #127 +mov z0.b, w0 +mov z0.d, #0 +mov z0.d, #0xe0000000000003ff +mov z0.d, #0xffffffffffff7fff +mov z0.d, #32768 +mov z0.d, d0 +mov z0.d, p0/m, d0 +mov z0.d, p0/m, x0 +mov z0.d, x0 +mov z0.d, z0.d +mov z0.h, #-256 +mov z0.h, #-32768 +mov z0.h, #0 +mov z0.h, #32512 +mov z0.h, #32767 +mov z0.h, h0 +mov z0.h, p0/m, h0 +mov z0.h, p0/m, w0 +mov z0.h, p0/z, #32512 +mov z0.h, w0 +mov z0.q, q0 +mov z0.s, #0 +mov z0.s, #0xffff7fff +mov z0.s, #32768 +mov z0.s, p0/m, s0 +mov z0.s, p0/m, w0 +mov z0.s, s0 +mov z0.s, w0 +mov z21.d, #-128 +mov z21.d, #-32768 +mov z21.d, #127 +mov z21.d, #32512 +mov z21.d, p0/z, #-128 +mov z21.d, p0/z, #-32768 +mov z21.d, p0/z, #127 +mov z21.d, p0/z, #32512 +mov z21.d, p15/m, #-128 +mov z21.d, p15/m, #-32768 +mov z21.h, #-128 +mov z21.h, #-32768 +mov z21.h, #127 +mov z21.h, #32512 +mov z21.h, p0/z, #-128 +mov z21.h, p0/z, #-32768 +mov z21.h, p0/z, #127 +mov z21.h, p0/z, #32512 +mov z21.h, p15/m, #-128 +mov z21.h, p15/m, #-32768 +mov z21.s, #-128 +mov z21.s, #-32768 +mov z21.s, #127 +mov z21.s, #32512 +mov z21.s, p0/z, #-128 +mov z21.s, p0/z, #-32768 +mov z21.s, p0/z, #127 +mov z21.s, p0/z, #32512 +mov z21.s, p15/m, #-128 +mov z21.s, p15/m, #-32768 +mov z31.b, p15/m, z31.b +mov z31.b, p7/m, b31 +movprfx z31, z6 +mov z31.b, p7/m, wsp +mov z31.b, wsp +mov z31.b, z31.b[63] +mov z31.d, p15/m, z31.d +mov z31.d, p7/m, d31 +movprfx z31.d, p7/z, z6.d +mov z31.d, p7/m, sp +mov z31.d, sp +mov z31.d, z0.d +mov z31.d, z31.d[7] +mov z31.h, p15/m, z31.h +mov z31.h, p7/m, h31 +mov z31.h, p7/m, wsp +mov z31.h, wsp +mov z31.h, z31.h[31] +mov z31.s, p15/m, z31.s +mov z31.s, p7/m, s31 +mov z31.s, p7/m, wsp +mov z31.s, wsp +mov z31.s, z31.s[15] +mov z5.b, #-1 +mov z5.b, #-128 +mov z5.b, #127 +mov z5.b, p0/z, #-1 +mov z5.b, p0/z, #-128 +mov z5.b, p0/z, #127 +mov z5.b, p15/m, #-128 +mov z5.d, #-6 +mov z5.h, #-6 +mov z5.q, z17.q[3] +mov z5.s, #-6 +movs p0.b, p0.b +movs p0.b, p0/z, p0.b +movs p15.b, p15.b +movs p15.b, p15/z, p15.b +mrs x3, ID_AA64ZFR0_EL1 +mrs x3, ZCR_EL1 +mrs x3, ZCR_EL12 +mrs x3, ZCR_EL2 +mrs x3, ZCR_EL3 +msb z0.b, p7/m, z1.b, z31.b +msb z0.d, p7/m, z1.d, z31.d +msb z0.h, p7/m, z1.h, z31.h +msb z0.s, p7/m, z1.s, z31.s +msr ZCR_EL1, x3 +msr ZCR_EL12, x3 +msr ZCR_EL2, x3 +msr ZCR_EL3, x3 +mul z0.b, p7/m, z0.b, z31.b +mul z0.b, z1.b, z2.b +mul z0.d, p7/m, z0.d, z31.d +mul z0.d, z1.d, z15.d[1] +mul z0.h, p7/m, z0.h, z31.h +mul z0.h, z1.h, z2.h +mul z0.h, z1.h, z7.h[7] +mul z0.s, p7/m, z0.s, z31.s +mul z0.s, z1.s, z7.s[3] +mul z29.s, z30.s, z31.s +mul z31.b, z31.b, #-128 +mul z31.b, z31.b, #127 +mul z31.d, z31.d, #-128 +mul z31.d, z31.d, #127 +mul z31.d, z31.d, z31.d +mul z31.h, z31.h, #-128 +mul z31.h, z31.h, #127 +mul z31.s, z31.s, #-128 +mul z31.s, z31.s, #127 +nand p0.b, p0/z, p0.b, p0.b +nand p15.b, p15/z, p15.b, p15.b +nands p0.b, p0/z, p0.b, p0.b +nands p15.b, p15/z, p15.b, p15.b +nbsl z0.d, z0.d, z1.d, z2.d +neg z0.b, p0/m, z0.b +neg z0.d, p0/m, z0.d +neg z0.h, p0/m, z0.h +neg z0.s, p0/m, z0.s +neg z31.b, p7/m, z31.b +neg z31.d, p7/m, z31.d +neg z31.h, p7/m, z31.h +neg z31.s, p7/m, z31.s +nmatch p0.b, p0/z, z0.b, z0.b +nmatch p0.h, p0/z, z0.h, z0.h +nmatch p15.b, p7/z, z30.b, z31.b +nmatch p15.h, p7/z, z30.h, z31.h +nor p0.b, p0/z, p0.b, p0.b +nor p15.b, p15/z, p15.b, p15.b +nors p0.b, p0/z, p0.b, p0.b +nors p15.b, p15/z, p15.b, p15.b +not p0.b, p0/z, p0.b +not p15.b, p15/z, p15.b +not z31.b, p7/m, z31.b +not z31.d, p7/m, z31.d +not z31.h, p7/m, z31.h +not z31.s, p7/m, z31.s +nots p0.b, p0/z, p0.b +nots p15.b, p15/z, p15.b +orn p0.b, p0/z, p0.b, p0.b +orn p15.b, p15/z, p15.b, p15.b +orns p0.b, p0/z, p0.b, p0.b +orns p15.b, p15/z, p15.b, p15.b +orr p0.b, p0/z, p0.b, p1.b +orr z0.d, z0.d, #0x6 +orr z0.d, z0.d, #0xfffffffffffffff9 +orr z0.s, z0.s, #0x6 +orr z0.s, z0.s, #0xfffffff9 +orr z23.d, z13.d, z8.d +orr z23.h, z23.h, #0x6 +orr z23.h, z23.h, #0xfff9 +orr z31.b, p7/m, z31.b, z31.b +orr z31.d, p7/m, z31.d, z31.d +orr z31.h, p7/m, z31.h, z31.h +orr z31.s, p7/m, z31.s, z31.s +orr z5.b, z5.b, #0x6 +orr z5.b, z5.b, #0xf9 +orrs p0.b, p0/z, p0.b, p1.b +orv b0, p7, z31.b +orv d0, p7, z31.d +orv h0, p7, z31.h +orv s0, p7, z31.s +pfalse p15.b +pfirst p0.b, p15, p0.b +pfirst p15.b, p15, p15.b +pmul z0.b, z1.b, z2.b +pmul z29.b, z30.b, z31.b +pmullb z0.h, z1.b, z2.b +pmullb z29.q, z30.d, z31.d +pmullb z31.d, z31.s, z31.s +pmullt z0.h, z1.b, z2.b +pmullt z29.q, z30.d, z31.d +pmullt z31.d, z31.s, z31.s +pnext p0.b, p15, p0.b +pnext p0.d, p15, p0.d +pnext p0.h, p15, p0.h +pnext p0.s, p15, p0.s +pnext p15.b, p15, p15.b +prfb #14, p0, [x0] +prfb #15, p0, [x0] +prfb #6, p0, [x0] +prfb #7, p0, [x0] +prfb #7, p3, [z13.s, #31] +prfb #7, p3, [z13.s] +prfb pldl1keep, p0, [x0, z0.d, uxtw] +prfb pldl1keep, p0, [x0, z0.d] +prfb pldl1keep, p0, [x0, z0.s, uxtw] +prfb pldl1keep, p0, [x0] +prfb pldl1strm, p0, [x0, #-32, mul vl] +prfb pldl1strm, p0, [x0, #31, mul vl] +prfb pldl1strm, p0, [x0] +prfb pldl2keep, p0, [x0] +prfb pldl2strm, p0, [x0] +prfb pldl3keep, p0, [x0] +prfb pldl3strm, p0, [x0] +prfb pldl3strm, p5, [x10, z21.d, sxtw] +prfb pldl3strm, p5, [x10, z21.s, uxtw] +prfb pldl3strm, p5, [z10.d, #31] +prfb pldl3strm, p5, [z10.d] +prfb pstl1keep, p0, [x0] +prfb pstl1strm, p0, [x0] +prfb pstl2keep, p0, [x0] +prfb pstl2strm, p0, [x0] +prfb pstl3keep, p0, [x0] +prfb pstl3strm, p0, [x0] +prfd #14, p0, [x0] +prfd #15, p0, [x0] +prfd #15, p7, [z31.d, #248] +prfd #15, p7, [z31.d] +prfd #15, p7, [z31.s, #248] +prfd #15, p7, [z31.s] +prfd #6, p0, [x0] +prfd #7, p0, [x0] +prfd pldl1keep, p0, [x0, z0.d, lsl #3] +prfd pldl1keep, p0, [x0, z0.d, sxtw #3] +prfd pldl1keep, p0, [x0, z0.d, uxtw #3] +prfd pldl1keep, p0, [x0, z0.s, sxtw #3] +prfd pldl1keep, p0, [x0, z0.s, uxtw #3] +prfd pldl1keep, p0, [x0] +prfd pldl1strm, p0, [x0, #-32, mul vl] +prfd pldl1strm, p0, [x0, #31, mul vl] +prfd pldl1strm, p0, [x0] +prfd pldl2keep, p0, [x0] +prfd pldl2strm, p0, [x0] +prfd pldl3keep, p0, [x0] +prfd pldl3strm, p0, [x0] +prfd pstl1keep, p0, [x0] +prfd pstl1strm, p0, [x0] +prfd pstl2keep, p0, [x0] +prfd pstl2strm, p0, [x0] +prfd pstl3keep, p0, [x0] +prfd pstl3strm, p0, [x0] +prfh #14, p0, [x0] +prfh #15, p0, [x0] +prfh #15, p7, [z31.d, #62] +prfh #15, p7, [z31.d] +prfh #15, p7, [z31.s, #62] +prfh #15, p7, [z31.s] +prfh #6, p0, [x0] +prfh #7, p0, [x0] +prfh pldl1keep, p0, [x0, z0.d, lsl #1] +prfh pldl1keep, p0, [x0] +prfh pldl1strm, p0, [x0, #-32, mul vl] +prfh pldl1strm, p0, [x0, #31, mul vl] +prfh pldl1strm, p0, [x0] +prfh pldl2keep, p0, [x0] +prfh pldl2strm, p0, [x0] +prfh pldl3keep, p0, [x0] +prfh pldl3strm, p0, [x0] +prfh pldl3strm, p5, [x10, z21.d, sxtw #1] +prfh pldl3strm, p5, [x10, z21.d, uxtw #1] +prfh pldl3strm, p5, [x10, z21.s, sxtw #1] +prfh pldl3strm, p5, [x10, z21.s, uxtw #1] +prfh pstl1keep, p0, [x0] +prfh pstl1strm, p0, [x0] +prfh pstl2keep, p0, [x0] +prfh pstl2strm, p0, [x0] +prfh pstl3keep, p0, [x0] +prfh pstl3strm, p0, [x0] +prfw #14, p0, [x0] +prfw #15, p0, [x0] +prfw #15, p7, [z31.d, #124] +prfw #15, p7, [z31.d] +prfw #15, p7, [z31.s, #124] +prfw #15, p7, [z31.s] +prfw #6, p0, [x0] +prfw #7, p0, [x0] +prfw #7, p3, [x13, z8.d, uxtw #2] +prfw pldl1keep, p0, [x0, z0.d, sxtw #2] +prfw pldl1keep, p0, [x0, z0.s, uxtw #2] +prfw pldl1keep, p0, [x0] +prfw pldl1strm, p0, [x0, #-32, mul vl] +prfw pldl1strm, p0, [x0, #31, mul vl] +prfw pldl1strm, p0, [x0] +prfw pldl2keep, p0, [x0] +prfw pldl2strm, p0, [x0] +prfw pldl3keep, p0, [x0] +prfw pldl3strm, p0, [x0] +prfw pldl3strm, p5, [x10, z21.d, lsl #2] +prfw pldl3strm, p5, [x10, z21.s, sxtw #2] +prfw pstl1keep, p0, [x0] +prfw pstl1strm, p0, [x0] +prfw pstl2keep, p0, [x0] +prfw pstl2strm, p0, [x0] +prfw pstl3keep, p0, [x0] +prfw pstl3strm, p0, [x0] +ptest p15, p0.b +ptest p15, p15.b +ptrue p0.b, pow2 +ptrue p0.d, pow2 +ptrue p0.h, pow2 +ptrue p0.s, pow2 +ptrue p15.b +ptrue p15.d +ptrue p15.h +ptrue p15.s +ptrue p7.s +ptrue p7.s, #14 +ptrue p7.s, #15 +ptrue p7.s, #16 +ptrue p7.s, #17 +ptrue p7.s, #18 +ptrue p7.s, #19 +ptrue p7.s, #20 +ptrue p7.s, #21 +ptrue p7.s, #22 +ptrue p7.s, #23 +ptrue p7.s, #24 +ptrue p7.s, #25 +ptrue p7.s, #26 +ptrue p7.s, #27 +ptrue p7.s, #28 +ptrue p7.s, mul3 +ptrue p7.s, mul4 +ptrue p7.s, vl1 +ptrue p7.s, vl128 +ptrue p7.s, vl16 +ptrue p7.s, vl2 +ptrue p7.s, vl256 +ptrue p7.s, vl3 +ptrue p7.s, vl32 +ptrue p7.s, vl4 +ptrue p7.s, vl5 +ptrue p7.s, vl6 +ptrue p7.s, vl64 +ptrue p7.s, vl7 +ptrue p7.s, vl8 +ptrues p0.b, pow2 +ptrues p0.d, pow2 +ptrues p0.h, pow2 +ptrues p0.s, pow2 +ptrues p15.b +ptrues p15.d +ptrues p15.h +ptrues p15.s +ptrues p7.s +ptrues p7.s, #14 +ptrues p7.s, #15 +ptrues p7.s, #16 +ptrues p7.s, #17 +ptrues p7.s, #18 +ptrues p7.s, #19 +ptrues p7.s, #20 +ptrues p7.s, #21 +ptrues p7.s, #22 +ptrues p7.s, #23 +ptrues p7.s, #24 +ptrues p7.s, #25 +ptrues p7.s, #26 +ptrues p7.s, #27 +ptrues p7.s, #28 +ptrues p7.s, mul3 +ptrues p7.s, mul4 +ptrues p7.s, vl1 +ptrues p7.s, vl128 +ptrues p7.s, vl16 +ptrues p7.s, vl2 +ptrues p7.s, vl256 +ptrues p7.s, vl3 +ptrues p7.s, vl32 +ptrues p7.s, vl4 +ptrues p7.s, vl5 +ptrues p7.s, vl6 +ptrues p7.s, vl64 +ptrues p7.s, vl7 +ptrues p7.s, vl8 +punpkhi p0.h, p0.b +punpkhi p15.h, p15.b +punpklo p0.h, p0.b +punpklo p15.h, p15.b +raddhnb z0.b, z1.h, z31.h +raddhnb z0.h, z1.s, z31.s +raddhnb z0.s, z1.d, z31.d +raddhnt z0.b, z1.h, z31.h +raddhnt z0.h, z1.s, z31.s +raddhnt z0.s, z1.d, z31.d +rax1 z0.d, z1.d, z31.d +rbit z0.b, p7/m, z31.b +rbit z0.d, p7/m, z31.d +rbit z0.h, p7/m, z31.h +rbit z0.s, p7/m, z31.s +rdffr p0.b +rdffr p0.b, p0/z +rdffr p15.b +rdffr p15.b, p15/z +rdffrs p0.b, p0/z +rdffrs p15.b, p15/z +rdvl x0, #0 +rdvl x21, #-32 +rdvl x23, #31 +rdvl xzr, #-1 +rev p0.b, p1.b +rev p0.d, p1.d +rev p0.h, p1.h +rev p0.s, p1.s +rev z0.b, z31.b +rev z0.d, z31.d +rev z0.h, z31.h +rev z0.s, z31.s +revb z0.d, p7/m, z31.d +revb z0.h, p7/m, z31.h +revb z0.s, p7/m, z31.s +revh z0.d, p7/m, z31.d +revh z0.s, p7/m, z31.s +revw z0.d, p7/m, z31.d +rshrnb z0.b, z0.h, #1 +rshrnb z0.h, z0.s, #1 +rshrnb z0.s, z0.d, #1 +rshrnb z31.b, z31.h, #8 +rshrnb z31.h, z31.s, #16 +rshrnb z31.s, z31.d, #32 +rshrnt z0.b, z0.h, #1 +rshrnt z0.h, z0.s, #1 +rshrnt z0.s, z0.d, #1 +rshrnt z31.b, z31.h, #8 +rshrnt z31.h, z31.s, #16 +rshrnt z31.s, z31.d, #32 +rsubhnb z0.b, z1.h, z31.h +rsubhnb z0.h, z1.s, z31.s +rsubhnb z0.s, z1.d, z31.d +rsubhnt z0.b, z1.h, z31.h +rsubhnt z0.h, z1.s, z31.s +rsubhnt z0.s, z1.d, z31.d +saba z0.b, z1.b, z31.b +saba z0.d, z1.d, z31.d +saba z0.h, z1.h, z31.h +saba z0.s, z1.s, z31.s +sabalb z0.d, z1.s, z31.s +sabalb z0.h, z1.b, z31.b +sabalb z0.s, z1.h, z31.h +sabalt z0.d, z1.s, z31.s +sabalt z0.h, z1.b, z31.b +sabalt z0.s, z1.h, z31.h +sabd z31.b, p7/m, z31.b, z31.b +sabd z31.d, p7/m, z31.d, z31.d +sabd z31.h, p7/m, z31.h, z31.h +sabd z31.s, p7/m, z31.s, z31.s +sabdlb z0.h, z1.b, z2.b +sabdlb z29.s, z30.h, z31.h +sabdlb z31.d, z31.s, z31.s +sabdlt z0.h, z1.b, z2.b +sabdlt z29.s, z30.h, z31.h +sabdlt z31.d, z31.s, z31.s +sadalp z0.h, p0/m, z1.b +sadalp z29.s, p0/m, z30.h +sadalp z30.d, p7/m, z31.s +saddlb z0.h, z1.b, z2.b +saddlb z29.s, z30.h, z31.h +saddlb z31.d, z31.s, z31.s +saddlbt z0.d, z1.s, z31.s +saddlbt z0.h, z1.b, z31.b +saddlbt z0.s, z1.h, z31.h +saddlt z0.h, z1.b, z2.b +saddlt z29.s, z30.h, z31.h +saddlt z31.d, z31.s, z31.s +saddv d0, p7, z31.b +saddv d0, p7, z31.h +saddv d0, p7, z31.s +saddwb z0.h, z1.h, z2.b +saddwb z29.s, z30.s, z31.h +saddwb z31.d, z31.d, z31.s +saddwt z0.h, z1.h, z2.b +saddwt z29.s, z30.s, z31.h +saddwt z31.d, z31.d, z31.s +sbclb z0.d, z1.d, z31.d +sbclb z0.s, z1.s, z31.s +sbclt z0.d, z1.d, z31.d +sbclt z0.s, z1.s, z31.s +scvtf z0.d, p0/m, z0.d +scvtf z0.d, p0/m, z0.s +scvtf z0.h, p0/m, z0.d +scvtf z0.h, p0/m, z0.h +scvtf z0.h, p0/m, z0.s +scvtf z0.s, p0/m, z0.d +scvtf z0.s, p0/m, z0.s +sdiv z0.d, p7/m, z0.d, z31.d +sdiv z0.s, p7/m, z0.s, z31.s +sdivr z0.d, p7/m, z0.d, z31.d +sdivr z0.s, p7/m, z0.s, z31.s +sdot z0.d, z1.h, z15.h[1] +sdot z0.d, z1.h, z31.h +sdot z0.s, z1.b, z31.b +sdot z0.s, z1.b, z7.b[3] +sel p0.b, p1, p2.b, p3.b +sel z23.b, p11, z13.b, z8.b +sel z23.d, p11, z13.d, z8.d +sel z23.h, p11, z13.h, z8.h +sel z23.s, p11, z13.s, z8.s +setffr +shadd z0.b, p0/m, z0.b, z1.b +shadd z0.h, p0/m, z0.h, z1.h +shadd z29.s, p7/m, z29.s, z30.s +shadd z31.d, p7/m, z31.d, z30.d +shrnb z0.b, z0.h, #1 +shrnb z0.h, z0.s, #1 +shrnb z0.s, z0.d, #1 +shrnb z31.b, z31.h, #8 +shrnb z31.h, z31.s, #16 +shrnb z31.s, z31.d, #32 +shrnt z0.b, z0.h, #1 +shrnt z0.h, z0.s, #1 +shrnt z0.s, z0.d, #1 +shrnt z31.b, z31.h, #8 +shrnt z31.h, z31.s, #16 +shrnt z31.s, z31.d, #32 +shsub z0.b, p0/m, z0.b, z1.b +shsub z0.h, p0/m, z0.h, z1.h +shsub z29.s, p7/m, z29.s, z30.s +shsub z31.d, p7/m, z31.d, z30.d +shsubr z0.b, p0/m, z0.b, z1.b +shsubr z0.h, p0/m, z0.h, z1.h +shsubr z29.s, p7/m, z29.s, z30.s +shsubr z31.d, p7/m, z31.d, z30.d +sli z0.b, z0.b, #0 +sli z0.d, z0.d, #0 +sli z0.h, z0.h, #0 +sli z0.s, z0.s, #0 +sli z31.b, z31.b, #7 +sli z31.d, z31.d, #63 +sli z31.h, z31.h, #15 +sli z31.s, z31.s, #31 +sm4e z0.s, z0.s, z31.s +sm4ekey z0.s, z1.s, z31.s +smax z0.b, z0.b, #-128 +smax z0.d, z0.d, #-128 +smax z0.h, z0.h, #-128 +smax z0.s, z0.s, #-128 +smax z31.b, p7/m, z31.b, z31.b +smax z31.b, z31.b, #127 +smax z31.d, p7/m, z31.d, z31.d +smax z31.d, z31.d, #127 +smax z31.h, p7/m, z31.h, z31.h +smax z31.h, z31.h, #127 +smax z31.s, p7/m, z31.s, z31.s +smax z31.s, z31.s, #127 +smaxp z0.b, p0/m, z0.b, z1.b +smaxp z0.h, p0/m, z0.h, z1.h +smaxp z29.s, p7/m, z29.s, z30.s +smaxp z31.d, p7/m, z31.d, z30.d +smaxv b0, p7, z31.b +smaxv d0, p7, z31.d +smaxv h0, p7, z31.h +smaxv s0, p7, z31.s +smin z0.b, z0.b, #-128 +smin z0.d, z0.d, #-128 +smin z0.h, z0.h, #-128 +smin z0.s, z0.s, #-128 +smin z31.b, p7/m, z31.b, z31.b +smin z31.b, z31.b, #127 +smin z31.d, p7/m, z31.d, z31.d +smin z31.d, z31.d, #127 +smin z31.h, p7/m, z31.h, z31.h +smin z31.h, z31.h, #127 +smin z31.s, p7/m, z31.s, z31.s +smin z31.s, z31.s, #127 +sminp z0.b, p0/m, z0.b, z1.b +sminp z0.h, p0/m, z0.h, z1.h +sminp z29.s, p7/m, z29.s, z30.s +sminp z31.d, p7/m, z31.d, z30.d +sminv b0, p7, z31.b +sminv d0, p7, z31.d +sminv h0, p7, z31.h +sminv s0, p7, z31.s +smlalb z0.d, z1.s, z15.s[1] +smlalb z0.d, z1.s, z31.s +smlalb z0.h, z1.b, z31.b +smlalb z0.s, z1.h, z31.h +smlalb z0.s, z1.h, z7.h[7] +smlalt z0.d, z1.s, z15.s[1] +smlalt z0.d, z1.s, z31.s +smlalt z0.h, z1.b, z31.b +smlalt z0.s, z1.h, z31.h +smlalt z0.s, z1.h, z7.h[7] +smlslb z0.d, z1.s, z15.s[1] +smlslb z0.d, z1.s, z31.s +smlslb z0.h, z1.b, z31.b +smlslb z0.s, z1.h, z31.h +smlslb z0.s, z1.h, z7.h[7] +smlslt z0.d, z1.s, z15.s[1] +smlslt z0.d, z1.s, z31.s +smlslt z0.h, z1.b, z31.b +smlslt z0.s, z1.h, z31.h +smlslt z0.s, z1.h, z7.h[7] +smmla z0.s, z1.b, z2.b +smulh z0.b, p7/m, z0.b, z31.b +smulh z0.b, z1.b, z2.b +smulh z0.d, p7/m, z0.d, z31.d +smulh z0.h, p7/m, z0.h, z31.h +smulh z0.h, z1.h, z2.h +smulh z0.s, p7/m, z0.s, z31.s +smulh z29.s, z30.s, z31.s +smulh z31.d, z31.d, z31.d +smullb z0.d, z1.s, z15.s[1] +smullb z0.h, z1.b, z2.b +smullb z0.s, z1.h, z7.h[7] +smullb z29.s, z30.h, z31.h +smullb z31.d, z31.s, z31.s +smullt z0.d, z1.s, z15.s[1] +smullt z0.h, z1.b, z2.b +smullt z0.s, z1.h, z7.h[7] +smullt z29.s, z30.h, z31.h +smullt z31.d, z31.s, z31.s +splice z29.b, p7, { z30.b, z31.b } +splice z29.d, p7, { z30.d, z31.d } +splice z29.h, p7, { z30.h, z31.h } +splice z29.s, p7, { z30.s, z31.s } +splice z31.b, p7, z31.b, z31.b +splice z31.d, p7, z31.d, z31.d +splice z31.h, p7, z31.h, z31.h +splice z31.s, p7, z31.s, z31.s +sqabs z31.b, p7/m, z31.b +sqabs z31.d, p7/m, z31.d +sqabs z31.h, p7/m, z31.h +sqabs z31.s, p7/m, z31.s +sqadd z0.b, p0/m, z0.b, z1.b +sqadd z0.b, z0.b, #0 +sqadd z0.b, z0.b, z0.b +sqadd z0.d, z0.d, #0 +sqadd z0.d, z0.d, #0, lsl #8 +sqadd z0.d, z0.d, z0.d +sqadd z0.h, p0/m, z0.h, z1.h +sqadd z0.h, z0.h, #0 +sqadd z0.h, z0.h, #0, lsl #8 +sqadd z0.h, z0.h, z0.h +sqadd z0.s, z0.s, #0 +sqadd z0.s, z0.s, #0, lsl #8 +sqadd z0.s, z0.s, z0.s +sqadd z29.s, p7/m, z29.s, z30.s +sqadd z31.b, z31.b, #255 +sqadd z31.d, p7/m, z31.d, z30.d +sqadd z31.d, z31.d, #65280 +sqadd z31.h, z31.h, #65280 +sqadd z31.s, z31.s, #65280 +sqcadd z0.b, z0.b, z0.b, #90 +sqcadd z0.d, z0.d, z0.d, #90 +sqcadd z0.h, z0.h, z0.h, #90 +sqcadd z0.s, z0.s, z0.s, #90 +sqcadd z31.b, z31.b, z31.b, #270 +sqcadd z31.d, z31.d, z31.d, #270 +sqcadd z31.h, z31.h, z31.h, #270 +sqcadd z31.s, z31.s, z31.s, #270 +sqdecb x0 +sqdecb x0, #14 +sqdecb x0, all, mul #16 +sqdecb x0, pow2 +sqdecb x0, vl1 +sqdecb x0, w0 +sqdecb x0, w0, all, mul #16 +sqdecb x0, w0, pow2 +sqdecb x0, w0, pow2, mul #16 +sqdecd x0 +sqdecd x0, #14 +sqdecd x0, all, mul #16 +sqdecd x0, pow2 +sqdecd x0, vl1 +sqdecd x0, w0 +sqdecd x0, w0, all, mul #16 +sqdecd x0, w0, pow2 +sqdecd x0, w0, pow2, mul #16 +sqdecd z0.d +sqdecd z0.d, all, mul #16 +sqdecd z0.d, pow2 +sqdecd z0.d, pow2, mul #16 +sqdech x0 +sqdech x0, #14 +sqdech x0, all, mul #16 +sqdech x0, pow2 +sqdech x0, vl1 +sqdech x0, w0 +sqdech x0, w0, all, mul #16 +sqdech x0, w0, pow2 +sqdech x0, w0, pow2, mul #16 +sqdech z0.h +sqdech z0.h, all, mul #16 +sqdech z0.h, pow2 +sqdech z0.h, pow2, mul #16 +sqdecp x0, p0.b +sqdecp x0, p0.d +sqdecp x0, p0.h +sqdecp x0, p0.s +sqdecp xzr, p15.b, wzr +sqdecp xzr, p15.d, wzr +sqdecp xzr, p15.h, wzr +sqdecp xzr, p15.s, wzr +sqdecp z0.d, p0.d +sqdecp z0.h, p0.h +sqdecp z0.s, p0.s +sqdecw x0 +sqdecw x0, #14 +sqdecw x0, all, mul #16 +sqdecw x0, pow2 +sqdecw x0, vl1 +sqdecw x0, w0 +sqdecw x0, w0, all, mul #16 +sqdecw x0, w0, pow2 +sqdecw x0, w0, pow2, mul #16 +sqdecw z0.s +sqdecw z0.s, all, mul #16 +sqdecw z0.s, pow2 +sqdecw z0.s, pow2, mul #16 +sqdmlalb z0.d, z1.s, z15.s[3] +sqdmlalb z0.d, z1.s, z31.s +sqdmlalb z0.h, z1.b, z31.b +sqdmlalb z0.s, z1.h, z31.h +sqdmlalb z0.s, z1.h, z7.h[7] +sqdmlalbt z0.d, z1.s, z31.s +sqdmlalbt z0.h, z1.b, z31.b +sqdmlalbt z0.s, z1.h, z31.h +sqdmlalt z0.d, z1.s, z15.s[3] +sqdmlalt z0.d, z1.s, z31.s +sqdmlalt z0.h, z1.b, z31.b +sqdmlalt z0.s, z1.h, z31.h +sqdmlalt z0.s, z1.h, z7.h[7] +sqdmlslb z0.d, z1.s, z15.s[3] +sqdmlslb z0.d, z1.s, z31.s +sqdmlslb z0.h, z1.b, z31.b +sqdmlslb z0.s, z1.h, z31.h +sqdmlslb z0.s, z1.h, z7.h[7] +sqdmlslbt z0.d, z1.s, z31.s +sqdmlslbt z0.h, z1.b, z31.b +sqdmlslbt z0.s, z1.h, z31.h +sqdmlslt z0.d, z1.s, z15.s[3] +sqdmlslt z0.d, z1.s, z31.s +sqdmlslt z0.h, z1.b, z31.b +sqdmlslt z0.s, z1.h, z31.h +sqdmlslt z0.s, z1.h, z7.h[7] +sqdmulh z0.b, z1.b, z2.b +sqdmulh z0.d, z1.d, z15.d[1] +sqdmulh z0.h, z1.h, z2.h +sqdmulh z0.h, z1.h, z7.h[7] +sqdmulh z0.s, z1.s, z7.s[3] +sqdmulh z29.s, z30.s, z31.s +sqdmulh z31.d, z31.d, z31.d +sqdmullb z0.d, z1.s, z15.s[1] +sqdmullb z0.h, z1.b, z2.b +sqdmullb z0.s, z1.h, z7.h[7] +sqdmullb z29.s, z30.h, z31.h +sqdmullb z31.d, z31.s, z31.s +sqdmullt z0.d, z1.s, z15.s[1] +sqdmullt z0.h, z1.b, z2.b +sqdmullt z0.s, z1.h, z7.h[7] +sqdmullt z29.s, z30.h, z31.h +sqdmullt z31.d, z31.s, z31.s +sqincb x0 +sqincb x0, #14 +sqincb x0, all, mul #16 +sqincb x0, pow2 +sqincb x0, vl1 +sqincb x0, w0 +sqincb x0, w0, all, mul #16 +sqincb x0, w0, pow2 +sqincb x0, w0, pow2, mul #16 +sqincd x0 +sqincd x0, #14 +sqincd x0, all, mul #16 +sqincd x0, pow2 +sqincd x0, vl1 +sqincd x0, w0 +sqincd x0, w0, all, mul #16 +sqincd x0, w0, pow2 +sqincd x0, w0, pow2, mul #16 +sqincd z0.d +sqincd z0.d, all, mul #16 +sqincd z0.d, pow2 +sqincd z0.d, pow2, mul #16 +sqinch x0 +sqinch x0, #14 +sqinch x0, all, mul #16 +sqinch x0, pow2 +sqinch x0, vl1 +sqinch x0, w0 +sqinch x0, w0, all, mul #16 +sqinch x0, w0, pow2 +sqinch x0, w0, pow2, mul #16 +sqinch z0.h +sqinch z0.h, all, mul #16 +sqinch z0.h, pow2 +sqinch z0.h, pow2, mul #16 +sqincp x0, p0.b +sqincp x0, p0.d +sqincp x0, p0.h +sqincp x0, p0.s +sqincp xzr, p15.b, wzr +sqincp xzr, p15.d, wzr +sqincp xzr, p15.h, wzr +sqincp xzr, p15.s, wzr +sqincp z0.d, p0.d +sqincp z0.h, p0.h +sqincp z0.s, p0.s +sqincw x0 +sqincw x0, #14 +sqincw x0, all, mul #16 +sqincw x0, pow2 +sqincw x0, vl1 +sqincw x0, w0 +sqincw x0, w0, all, mul #16 +sqincw x0, w0, pow2 +sqincw x0, w0, pow2, mul #16 +sqincw z0.s +sqincw z0.s, all, mul #16 +sqincw z0.s, pow2 +sqincw z0.s, pow2, mul #16 +sqneg z31.b, p7/m, z31.b +sqneg z31.d, p7/m, z31.d +sqneg z31.h, p7/m, z31.h +sqneg z31.s, p7/m, z31.s +sqrdcmlah z0.b, z1.b, z2.b, #0 +sqrdcmlah z0.d, z1.d, z2.d, #0 +sqrdcmlah z0.h, z1.h, z2.h, #0 +sqrdcmlah z0.h, z1.h, z2.h[0], #0 +sqrdcmlah z0.s, z1.s, z2.s, #0 +sqrdcmlah z0.s, z1.s, z2.s[0], #0 +sqrdcmlah z15.b, z16.b, z17.b, #270 +sqrdcmlah z15.d, z16.d, z17.d, #270 +sqrdcmlah z15.h, z16.h, z17.h, #270 +sqrdcmlah z15.s, z16.s, z17.s, #270 +sqrdcmlah z29.b, z30.b, z31.b, #90 +sqrdcmlah z29.d, z30.d, z31.d, #90 +sqrdcmlah z29.h, z30.h, z31.h, #90 +sqrdcmlah z29.s, z30.s, z31.s, #90 +sqrdcmlah z31.b, z31.b, z31.b, #180 +sqrdcmlah z31.d, z31.d, z31.d, #180 +sqrdcmlah z31.h, z30.h, z7.h[0], #180 +sqrdcmlah z31.h, z31.h, z31.h, #180 +sqrdcmlah z31.s, z30.s, z7.s[0], #180 +sqrdcmlah z31.s, z31.s, z31.s, #180 +sqrdmlah z0.b, z1.b, z31.b +sqrdmlah z0.d, z1.d, z15.d[1] +sqrdmlah z0.d, z1.d, z31.d +sqrdmlah z0.h, z1.h, z31.h +sqrdmlah z0.h, z1.h, z7.h[7] +sqrdmlah z0.s, z1.s, z31.s +sqrdmlah z0.s, z1.s, z7.s[3] +sqrdmlsh z0.b, z1.b, z31.b +sqrdmlsh z0.d, z1.d, z15.d[1] +sqrdmlsh z0.d, z1.d, z31.d +sqrdmlsh z0.h, z1.h, z31.h +sqrdmlsh z0.h, z1.h, z7.h[7] +sqrdmlsh z0.s, z1.s, z31.s +sqrdmlsh z0.s, z1.s, z7.s[3] +sqrdmulh z0.b, z1.b, z2.b +sqrdmulh z0.d, z1.d, z15.d[1] +sqrdmulh z0.h, z1.h, z2.h +sqrdmulh z0.h, z1.h, z7.h[7] +sqrdmulh z0.s, z1.s, z7.s[3] +sqrdmulh z29.s, z30.s, z31.s +sqrdmulh z31.d, z31.d, z31.d +sqrshl z0.b, p0/m, z0.b, z1.b +sqrshl z0.h, p0/m, z0.h, z1.h +sqrshl z29.s, p7/m, z29.s, z30.s +sqrshl z31.d, p7/m, z31.d, z30.d +sqrshlr z0.b, p0/m, z0.b, z1.b +sqrshlr z0.h, p0/m, z0.h, z1.h +sqrshlr z29.s, p7/m, z29.s, z30.s +sqrshlr z31.d, p7/m, z31.d, z30.d +sqrshrnb z0.b, z0.h, #1 +sqrshrnb z0.h, z0.s, #1 +sqrshrnb z0.s, z0.d, #1 +sqrshrnb z31.b, z31.h, #8 +sqrshrnb z31.h, z31.s, #16 +sqrshrnb z31.s, z31.d, #32 +sqrshrnt z0.b, z0.h, #1 +sqrshrnt z0.h, z0.s, #1 +sqrshrnt z0.s, z0.d, #1 +sqrshrnt z31.b, z31.h, #8 +sqrshrnt z31.h, z31.s, #16 +sqrshrnt z31.s, z31.d, #32 +sqrshrunb z0.b, z0.h, #1 +sqrshrunb z0.h, z0.s, #1 +sqrshrunb z0.s, z0.d, #1 +sqrshrunb z31.b, z31.h, #8 +sqrshrunb z31.h, z31.s, #16 +sqrshrunb z31.s, z31.d, #32 +sqrshrunt z0.b, z0.h, #1 +sqrshrunt z0.h, z0.s, #1 +sqrshrunt z0.s, z0.d, #1 +sqrshrunt z31.b, z31.h, #8 +sqrshrunt z31.h, z31.s, #16 +sqrshrunt z31.s, z31.d, #32 +sqshl z0.b, p0/m, z0.b, #0 +sqshl z0.b, p0/m, z0.b, z1.b +sqshl z0.d, p0/m, z0.d, #0 +sqshl z0.h, p0/m, z0.h, #0 +sqshl z0.h, p0/m, z0.h, z1.h +sqshl z0.s, p0/m, z0.s, #0 +sqshl z29.s, p7/m, z29.s, z30.s +sqshl z31.b, p0/m, z31.b, #7 +sqshl z31.d, p0/m, z31.d, #63 +sqshl z31.d, p7/m, z31.d, z30.d +sqshl z31.h, p0/m, z31.h, #15 +sqshl z31.s, p0/m, z31.s, #31 +sqshlr z0.b, p0/m, z0.b, z1.b +sqshlr z0.h, p0/m, z0.h, z1.h +sqshlr z29.s, p7/m, z29.s, z30.s +sqshlr z31.d, p7/m, z31.d, z30.d +sqshlu z0.b, p0/m, z0.b, #0 +sqshlu z0.d, p0/m, z0.d, #0 +sqshlu z0.h, p0/m, z0.h, #0 +sqshlu z0.s, p0/m, z0.s, #0 +sqshlu z31.b, p0/m, z31.b, #7 +sqshlu z31.d, p0/m, z31.d, #63 +sqshlu z31.h, p0/m, z31.h, #15 +sqshlu z31.s, p0/m, z31.s, #31 +sqshrnb z0.b, z0.h, #1 +sqshrnb z0.h, z0.s, #1 +sqshrnb z0.s, z0.d, #1 +sqshrnb z31.b, z31.h, #8 +sqshrnb z31.h, z31.s, #16 +sqshrnb z31.s, z31.d, #32 +sqshrnt z0.b, z0.h, #1 +sqshrnt z0.h, z0.s, #1 +sqshrnt z0.s, z0.d, #1 +sqshrnt z31.b, z31.h, #8 +sqshrnt z31.h, z31.s, #16 +sqshrnt z31.s, z31.d, #32 +sqshrunb z0.b, z0.h, #1 +sqshrunb z0.h, z0.s, #1 +sqshrunb z0.s, z0.d, #1 +sqshrunb z31.b, z31.h, #8 +sqshrunb z31.h, z31.s, #16 +sqshrunb z31.s, z31.d, #32 +sqshrunt z0.b, z0.h, #1 +sqshrunt z0.h, z0.s, #1 +sqshrunt z0.s, z0.d, #1 +sqshrunt z31.b, z31.h, #8 +sqshrunt z31.h, z31.s, #16 +sqshrunt z31.s, z31.d, #32 +sqsub z0.b, p0/m, z0.b, z1.b +sqsub z0.b, z0.b, #0 +sqsub z0.b, z0.b, z0.b +sqsub z0.d, z0.d, #0 +sqsub z0.d, z0.d, #0, lsl #8 +sqsub z0.d, z0.d, z0.d +sqsub z0.h, p0/m, z0.h, z1.h +sqsub z0.h, z0.h, #0 +sqsub z0.h, z0.h, #0, lsl #8 +sqsub z0.h, z0.h, z0.h +sqsub z0.s, z0.s, #0 +sqsub z0.s, z0.s, #0, lsl #8 +sqsub z0.s, z0.s, z0.s +sqsub z29.s, p7/m, z29.s, z30.s +sqsub z31.b, z31.b, #255 +sqsub z31.d, p7/m, z31.d, z30.d +sqsub z31.d, z31.d, #65280 +sqsub z31.h, z31.h, #65280 +sqsub z31.s, z31.s, #65280 +sqsubr z0.b, p0/m, z0.b, z1.b +sqsubr z0.h, p0/m, z0.h, z1.h +sqsubr z29.s, p7/m, z29.s, z30.s +sqsubr z31.d, p7/m, z31.d, z30.d +sqxtnb z0.b, z31.h +sqxtnb z0.h, z31.s +sqxtnb z0.s, z31.d +sqxtnt z0.b, z31.h +sqxtnt z0.h, z31.s +sqxtnt z0.s, z31.d +sqxtunb z0.b, z31.h +sqxtunb z0.h, z31.s +sqxtunb z0.s, z31.d +sqxtunt z0.b, z31.h +sqxtunt z0.h, z31.s +sqxtunt z0.s, z31.d +srhadd z0.b, p0/m, z0.b, z1.b +srhadd z0.h, p0/m, z0.h, z1.h +srhadd z29.s, p7/m, z29.s, z30.s +srhadd z31.d, p7/m, z31.d, z30.d +sri z0.b, z0.b, #1 +sri z0.d, z0.d, #1 +sri z0.h, z0.h, #1 +sri z0.s, z0.s, #1 +sri z31.b, z31.b, #8 +sri z31.d, z31.d, #64 +sri z31.h, z31.h, #16 +sri z31.s, z31.s, #32 +srshl z0.b, p0/m, z0.b, z1.b +srshl z0.h, p0/m, z0.h, z1.h +srshl z29.s, p7/m, z29.s, z30.s +srshl z31.d, p7/m, z31.d, z30.d +srshlr z0.b, p0/m, z0.b, z1.b +srshlr z0.h, p0/m, z0.h, z1.h +srshlr z29.s, p7/m, z29.s, z30.s +srshlr z31.d, p7/m, z31.d, z30.d +srshr z0.b, p0/m, z0.b, #1 +srshr z0.d, p0/m, z0.d, #1 +srshr z0.h, p0/m, z0.h, #1 +srshr z0.s, p0/m, z0.s, #1 +srshr z31.b, p0/m, z31.b, #8 +srshr z31.d, p0/m, z31.d, #64 +srshr z31.h, p0/m, z31.h, #16 +srshr z31.s, p0/m, z31.s, #32 +srsra z0.b, z0.b, #1 +srsra z0.d, z0.d, #1 +srsra z0.h, z0.h, #1 +srsra z0.s, z0.s, #1 +srsra z31.b, z31.b, #8 +srsra z31.d, z31.d, #64 +srsra z31.h, z31.h, #16 +srsra z31.s, z31.s, #32 +sshllb z0.d, z0.s, #0 +sshllb z0.h, z0.b, #0 +sshllb z0.s, z0.h, #0 +sshllb z31.d, z31.s, #31 +sshllb z31.h, z31.b, #7 +sshllb z31.s, z31.h, #15 +sshllt z0.d, z0.s, #0 +sshllt z0.h, z0.b, #0 +sshllt z0.s, z0.h, #0 +sshllt z31.d, z31.s, #31 +sshllt z31.h, z31.b, #7 +sshllt z31.s, z31.h, #15 +ssra z0.b, z0.b, #1 +ssra z0.d, z0.d, #1 +ssra z0.h, z0.h, #1 +ssra z0.s, z0.s, #1 +ssra z31.b, z31.b, #8 +ssra z31.d, z31.d, #64 +ssra z31.h, z31.h, #16 +ssra z31.s, z31.s, #32 +ssublb z0.h, z1.b, z2.b +ssublb z29.s, z30.h, z31.h +ssublb z31.d, z31.s, z31.s +ssublbt z0.d, z1.s, z31.s +ssublbt z0.h, z1.b, z31.b +ssublbt z0.s, z1.h, z31.h +ssublt z0.h, z1.b, z2.b +ssublt z29.s, z30.h, z31.h +ssublt z31.d, z31.s, z31.s +ssubltb z0.d, z1.s, z31.s +ssubltb z0.h, z1.b, z31.b +ssubltb z0.s, z1.h, z31.h +ssubwb z0.h, z1.h, z2.b +ssubwb z29.s, z30.s, z31.h +ssubwb z31.d, z31.d, z31.s +ssubwt z0.h, z1.h, z2.b +ssubwt z29.s, z30.s, z31.h +ssubwt z31.d, z31.d, z31.s +st1b { z0.b }, p0, [x0, x0] +st1b { z0.b }, p0, [x0] +st1b { z0.d }, p0, [x0, x0] +st1b { z0.d }, p0, [x0, z0.d, sxtw] +st1b { z0.d }, p0, [x0, z0.d, uxtw] +st1b { z0.d }, p0, [x0, z0.d] +st1b { z0.d }, p0, [x0] +st1b { z0.d }, p7, [z0.d] +st1b { z0.h }, p0, [x0, x0] +st1b { z0.h }, p0, [x0] +st1b { z0.s }, p0, [x0, x0] +st1b { z0.s }, p0, [x0, z0.s, sxtw] +st1b { z0.s }, p0, [x0, z0.s, uxtw] +st1b { z0.s }, p0, [x0] +st1b { z0.s }, p7, [z0.s] +st1b { z21.b }, p5, [x10, #5, mul vl] +st1b { z21.d }, p5, [x10, #5, mul vl] +st1b { z21.h }, p5, [x10, #5, mul vl] +st1b { z21.s }, p5, [x10, #5, mul vl] +st1b { z31.b }, p7, [sp, #-1, mul vl] +st1b { z31.d }, p7, [sp, #-1, mul vl] +st1b { z31.d }, p7, [z31.d, #31] +st1b { z31.h }, p7, [sp, #-1, mul vl] +st1b { z31.s }, p7, [sp, #-1, mul vl] +st1b { z31.s }, p7, [z31.s, #31] +st1d { z0.d }, p0, [x0, x0, lsl #3] +st1d { z0.d }, p0, [x0, z0.d, lsl #3] +st1d { z0.d }, p0, [x0, z0.d, sxtw #3] +st1d { z0.d }, p0, [x0, z0.d, sxtw] +st1d { z0.d }, p0, [x0, z0.d, uxtw #3] +st1d { z0.d }, p0, [x0, z0.d, uxtw] +st1d { z0.d }, p0, [x0, z0.d] +st1d { z0.d }, p0, [x0] +st1d { z0.d }, p7, [z0.d] +st1d { z21.d }, p5, [x10, #5, mul vl] +st1d { z31.d }, p7, [sp, #-1, mul vl] +st1d { z31.d }, p7, [z31.d, #248] +st1h { z0.d }, p0, [x0, x0, lsl #1] +st1h { z0.d }, p0, [x0, z0.d, lsl #1] +st1h { z0.d }, p0, [x0, z0.d, sxtw #1] +st1h { z0.d }, p0, [x0, z0.d, sxtw] +st1h { z0.d }, p0, [x0, z0.d, uxtw #1] +st1h { z0.d }, p0, [x0, z0.d, uxtw] +st1h { z0.d }, p0, [x0, z0.d] +st1h { z0.d }, p0, [x0] +st1h { z0.d }, p7, [z0.d] +st1h { z0.h }, p0, [x0, x0, lsl #1] +st1h { z0.h }, p0, [x0] +st1h { z0.s }, p0, [x0, x0, lsl #1] +st1h { z0.s }, p0, [x0, z0.s, sxtw #1] +st1h { z0.s }, p0, [x0, z0.s, sxtw] +st1h { z0.s }, p0, [x0, z0.s, uxtw #1] +st1h { z0.s }, p0, [x0, z0.s, uxtw] +st1h { z0.s }, p0, [x0] +st1h { z0.s }, p7, [z0.s] +st1h { z21.d }, p5, [x10, #5, mul vl] +st1h { z21.h }, p5, [x10, #5, mul vl] +st1h { z21.s }, p5, [x10, #5, mul vl] +st1h { z31.d }, p7, [sp, #-1, mul vl] +st1h { z31.d }, p7, [z31.d, #62] +st1h { z31.h }, p7, [sp, #-1, mul vl] +st1h { z31.s }, p7, [sp, #-1, mul vl] +st1h { z31.s }, p7, [z31.s, #62] +st1w { z0.d }, p0, [x0, x0, lsl #2] +st1w { z0.d }, p0, [x0, z0.d, lsl #2] +st1w { z0.d }, p0, [x0, z0.d, sxtw #2] +st1w { z0.d }, p0, [x0, z0.d, sxtw] +st1w { z0.d }, p0, [x0, z0.d, uxtw #2] +st1w { z0.d }, p0, [x0, z0.d, uxtw] +st1w { z0.d }, p0, [x0, z0.d] +st1w { z0.d }, p0, [x0] +st1w { z0.d }, p7, [z0.d] +st1w { z0.s }, p0, [x0, x0, lsl #2] +st1w { z0.s }, p0, [x0, z0.s, sxtw #2] +st1w { z0.s }, p0, [x0, z0.s, sxtw] +st1w { z0.s }, p0, [x0, z0.s, uxtw #2] +st1w { z0.s }, p0, [x0, z0.s, uxtw] +st1w { z0.s }, p0, [x0] +st1w { z0.s }, p7, [z0.s] +st1w { z21.d }, p5, [x10, #5, mul vl] +st1w { z21.s }, p5, [x10, #5, mul vl] +st1w { z31.d }, p7, [sp, #-1, mul vl] +st1w { z31.d }, p7, [z31.d, #124] +st1w { z31.s }, p7, [sp, #-1, mul vl] +st1w { z31.s }, p7, [z31.s, #124] +st2b { z0.b, z1.b }, p0, [x0, x0] +st2b { z0.b, z1.b }, p0, [x0] +st2b { z21.b, z22.b }, p5, [x10, #10, mul vl] +st2b { z23.b, z24.b }, p3, [x13, #-16, mul vl] +st2b { z5.b, z6.b }, p3, [x17, x16] +st2d { z0.d, z1.d }, p0, [x0, x0, lsl #3] +st2d { z0.d, z1.d }, p0, [x0] +st2d { z21.d, z22.d }, p5, [x10, #10, mul vl] +st2d { z23.d, z24.d }, p3, [x13, #-16, mul vl] +st2d { z5.d, z6.d }, p3, [x17, x16, lsl #3] +st2h { z0.h, z1.h }, p0, [x0, x0, lsl #1] +st2h { z0.h, z1.h }, p0, [x0] +st2h { z21.h, z22.h }, p5, [x10, #10, mul vl] +st2h { z23.h, z24.h }, p3, [x13, #-16, mul vl] +st2h { z5.h, z6.h }, p3, [x17, x16, lsl #1] +st2w { z0.s, z1.s }, p0, [x0, x0, lsl #2] +st2w { z0.s, z1.s }, p0, [x0] +st2w { z21.s, z22.s }, p5, [x10, #10, mul vl] +st2w { z23.s, z24.s }, p3, [x13, #-16, mul vl] +st2w { z5.s, z6.s }, p3, [x17, x16, lsl #2] +st3b { z0.b, z1.b, z2.b }, p0, [x0, x0] +st3b { z0.b, z1.b, z2.b }, p0, [x0] +st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl] +st3b { z23.b, z24.b, z25.b }, p3, [x13, #-24, mul vl] +st3b { z5.b, z6.b, z7.b }, p3, [x17, x16] +st3d { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #3] +st3d { z0.d, z1.d, z2.d }, p0, [x0] +st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl] +st3d { z23.d, z24.d, z25.d }, p3, [x13, #-24, mul vl] +st3d { z5.d, z6.d, z7.d }, p3, [x17, x16, lsl #3] +st3h { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #1] +st3h { z0.h, z1.h, z2.h }, p0, [x0] +st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl] +st3h { z23.h, z24.h, z25.h }, p3, [x13, #-24, mul vl] +st3h { z5.h, z6.h, z7.h }, p3, [x17, x16, lsl #1] +st3w { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #2] +st3w { z0.s, z1.s, z2.s }, p0, [x0] +st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl] +st3w { z23.s, z24.s, z25.s }, p3, [x13, #-24, mul vl] +st3w { z5.s, z6.s, z7.s }, p3, [x17, x16, lsl #2] +st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0] +st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0] +st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl] +st4b { z23.b, z24.b, z25.b, z26.b }, p3, [x13, #-32, mul vl] +st4b { z5.b, z6.b, z7.b, z8.b }, p3, [x17, x16] +st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #3] +st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0] +st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl] +st4d { z23.d, z24.d, z25.d, z26.d }, p3, [x13, #-32, mul vl] +st4d { z5.d, z6.d, z7.d, z8.d }, p3, [x17, x16, lsl #3] +st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #1] +st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0] +st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl] +st4h { z23.h, z24.h, z25.h, z26.h }, p3, [x13, #-32, mul vl] +st4h { z5.h, z6.h, z7.h, z8.h }, p3, [x17, x16, lsl #1] +st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #2] +st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0] +st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl] +st4w { z23.s, z24.s, z25.s, z26.s }, p3, [x13, #-32, mul vl] +st4w { z5.s, z6.s, z7.s, z8.s }, p3, [x17, x16, lsl #2] +stnt1b { z0.b }, p0, [x0, x0] +stnt1b { z0.b }, p0, [x0] +stnt1b { z0.d }, p0, [z1.d] +stnt1b { z0.s }, p0, [z1.s] +stnt1b { z21.b }, p5, [x10, #7, mul vl] +stnt1b { z23.b }, p3, [x13, #-8, mul vl] +stnt1b { z31.d }, p7, [z31.d, x0] +stnt1b { z31.d }, p7, [z31.d] +stnt1b { z31.s }, p7, [z31.s, x0] +stnt1b { z31.s }, p7, [z31.s] +stnt1d { z0.d }, p0, [x0, x0, lsl #3] +stnt1d { z0.d }, p0, [x0] +stnt1d { z0.d }, p0, [z1.d] +stnt1d { z21.d }, p5, [x10, #7, mul vl] +stnt1d { z23.d }, p3, [x13, #-8, mul vl] +stnt1d { z31.d }, p7, [z31.d, x0] +stnt1d { z31.d }, p7, [z31.d] +stnt1h { z0.d }, p0, [z1.d] +stnt1h { z0.h }, p0, [x0, x0, lsl #1] +stnt1h { z0.h }, p0, [x0] +stnt1h { z0.s }, p0, [z1.s] +stnt1h { z21.h }, p5, [x10, #7, mul vl] +stnt1h { z23.h }, p3, [x13, #-8, mul vl] +stnt1h { z31.d }, p7, [z31.d, x0] +stnt1h { z31.d }, p7, [z31.d] +stnt1h { z31.s }, p7, [z31.s, x0] +stnt1h { z31.s }, p7, [z31.s] +stnt1w { z0.d }, p0, [z1.d] +stnt1w { z0.s }, p0, [x0, x0, lsl #2] +stnt1w { z0.s }, p0, [x0] +stnt1w { z0.s }, p0, [z1.s] +stnt1w { z21.s }, p5, [x10, #7, mul vl] +stnt1w { z23.s }, p3, [x13, #-8, mul vl] +stnt1w { z31.d }, p7, [z31.d, x0] +stnt1w { z31.d }, p7, [z31.d] +stnt1w { z31.s }, p7, [z31.s, x0] +stnt1w { z31.s }, p7, [z31.s] +str p0, [x0] +str p15, [sp, #-256, mul vl] +str p5, [x10, #255, mul vl] +str z0, [x0] +str z21, [x10, #-256, mul vl] +str z31, [sp, #255, mul vl] +sub z0.b, p0/m, z0.b, z0.b +sub z0.b, z0.b, #0 +sub z0.b, z0.b, z0.b +sub z0.d, p0/m, z0.d, z0.d +sub z0.d, z0.d, #0 +sub z0.d, z0.d, #0, lsl #8 +sub z0.d, z0.d, z0.d +sub z0.h, p0/m, z0.h, z0.h +sub z0.h, z0.h, #0 +sub z0.h, z0.h, #0, lsl #8 +sub z0.h, z0.h, z0.h +sub z0.s, p0/m, z0.s, z0.s +sub z0.s, z0.s, #0 +sub z0.s, z0.s, #0, lsl #8 +sub z0.s, z0.s, z0.s +sub z21.b, p5/m, z21.b, z10.b +sub z21.b, z10.b, z21.b +sub z21.d, p5/m, z21.d, z10.d +sub z21.d, z10.d, z21.d +sub z21.h, p5/m, z21.h, z10.h +sub z21.h, z10.h, z21.h +sub z21.s, p5/m, z21.s, z10.s +sub z21.s, z10.s, z21.s +sub z23.b, p3/m, z23.b, z13.b +sub z23.b, z13.b, z8.b +sub z23.d, p3/m, z23.d, z13.d +sub z23.d, z13.d, z8.d +sub z23.h, p3/m, z23.h, z13.h +sub z23.h, z13.h, z8.h +sub z23.s, p3/m, z23.s, z13.s +sub z23.s, z13.s, z8.s +sub z31.b, p7/m, z31.b, z31.b +sub z31.b, z31.b, #255 +sub z31.b, z31.b, z31.b +sub z31.d, p7/m, z31.d, z31.d +sub z31.d, z31.d, #65280 +sub z31.d, z31.d, z31.d +sub z31.h, p7/m, z31.h, z31.h +sub z31.h, z31.h, #65280 +sub z31.h, z31.h, z31.h +sub z31.s, p7/m, z31.s, z31.s +sub z31.s, z31.s, #65280 +sub z31.s, z31.s, z31.s +subhnb z0.b, z1.h, z31.h +subhnb z0.h, z1.s, z31.s +subhnb z0.s, z1.d, z31.d +subhnt z0.b, z1.h, z31.h +subhnt z0.h, z1.s, z31.s +subhnt z0.s, z1.d, z31.d +subr z0.b, p0/m, z0.b, z0.b +subr z0.b, z0.b, #0 +subr z0.d, p0/m, z0.d, z0.d +subr z0.d, z0.d, #0 +subr z0.d, z0.d, #0, lsl #8 +subr z0.h, p0/m, z0.h, z0.h +subr z0.h, z0.h, #0 +subr z0.h, z0.h, #0, lsl #8 +subr z0.s, p0/m, z0.s, z0.s +subr z0.s, z0.s, #0 +subr z0.s, z0.s, #0, lsl #8 +subr z31.b, z31.b, #255 +subr z31.d, z31.d, #65280 +subr z31.h, z31.h, #65280 +subr z31.s, z31.s, #65280 +sunpkhi z31.d, z31.s +sunpkhi z31.h, z31.b +sunpkhi z31.s, z31.h +sunpklo z31.d, z31.s +sunpklo z31.h, z31.b +sunpklo z31.s, z31.h +suqadd z0.b, p0/m, z0.b, z1.b +suqadd z0.h, p0/m, z0.h, z1.h +suqadd z29.s, p7/m, z29.s, z30.s +suqadd z31.d, p7/m, z31.d, z30.d +sxtb z0.d, p0/m, z0.d +sxtb z0.h, p0/m, z0.h +sxtb z0.s, p0/m, z0.s +sxtb z31.d, p7/m, z31.d +sxtb z31.h, p7/m, z31.h +sxtb z31.s, p7/m, z31.s +sxth z0.d, p0/m, z0.d +sxth z0.s, p0/m, z0.s +sxth z31.d, p7/m, z31.d +sxth z31.s, p7/m, z31.s +sxtw z0.d, p0/m, z0.d +sxtw z31.d, p7/m, z31.d +tbl z28.b, { z29.b, z30.b }, z31.b +tbl z28.d, { z29.d, z30.d }, z31.d +tbl z28.h, { z29.h, z30.h }, z31.h +tbl z28.s, { z29.s, z30.s }, z31.s +tbl z31.b, { z31.b }, z31.b +tbl z31.d, { z31.d }, z31.d +tbl z31.h, { z31.h }, z31.h +tbl z31.s, { z31.s }, z31.s +tbx z31.b, z31.b, z31.b +tbx z31.d, z31.d, z31.d +tbx z31.h, z31.h, z31.h +tbx z31.s, z31.s, z31.s +trn1 p15.b, p15.b, p15.b +trn1 p15.d, p15.d, p15.d +trn1 p15.h, p15.h, p15.h +trn1 p15.s, p15.s, p15.s +trn1 z31.b, z31.b, z31.b +trn1 z31.d, z31.d, z31.d +trn1 z31.h, z31.h, z31.h +trn1 z31.s, z31.s, z31.s +trn2 p15.b, p15.b, p15.b +trn2 p15.d, p15.d, p15.d +trn2 p15.h, p15.h, p15.h +trn2 p15.s, p15.s, p15.s +trn2 z31.b, z31.b, z31.b +trn2 z31.d, z31.d, z31.d +trn2 z31.h, z31.h, z31.h +trn2 z31.s, z31.s, z31.s +uaba z0.b, z1.b, z31.b +uaba z0.d, z1.d, z31.d +uaba z0.h, z1.h, z31.h +uaba z0.s, z1.s, z31.s +uabalb z0.d, z1.s, z31.s +uabalb z0.h, z1.b, z31.b +uabalb z0.s, z1.h, z31.h +uabalt z0.d, z1.s, z31.s +uabalt z0.h, z1.b, z31.b +uabalt z0.s, z1.h, z31.h +uabd z31.b, p7/m, z31.b, z31.b +uabd z31.d, p7/m, z31.d, z31.d +uabd z31.h, p7/m, z31.h, z31.h +uabd z31.s, p7/m, z31.s, z31.s +uabdlb z0.h, z1.b, z2.b +uabdlb z29.s, z30.h, z31.h +uabdlb z31.d, z31.s, z31.s +uabdlt z0.h, z1.b, z2.b +uabdlt z29.s, z30.h, z31.h +uabdlt z31.d, z31.s, z31.s +uadalp z0.h, p0/m, z1.b +uadalp z29.s, p0/m, z30.h +uadalp z30.d, p7/m, z31.s +uaddlb z0.h, z1.b, z2.b +uaddlb z29.s, z30.h, z31.h +uaddlb z31.d, z31.s, z31.s +uaddlt z0.h, z1.b, z2.b +uaddlt z29.s, z30.h, z31.h +uaddlt z31.d, z31.s, z31.s +uaddv d0, p7, z31.b +uaddv d0, p7, z31.d +uaddv d0, p7, z31.h +uaddv d0, p7, z31.s +uaddwb z0.h, z1.h, z2.b +uaddwb z29.s, z30.s, z31.h +uaddwb z31.d, z31.d, z31.s +uaddwt z0.h, z1.h, z2.b +uaddwt z29.s, z30.s, z31.h +uaddwt z31.d, z31.d, z31.s +ucvtf z0.d, p0/m, z0.d +ucvtf z0.d, p0/m, z0.s +ucvtf z0.h, p0/m, z0.d +ucvtf z0.h, p0/m, z0.h +ucvtf z0.h, p0/m, z0.s +ucvtf z0.s, p0/m, z0.d +ucvtf z0.s, p0/m, z0.s +udiv z0.d, p7/m, z0.d, z31.d +udiv z0.s, p7/m, z0.s, z31.s +udivr z0.d, p7/m, z0.d, z31.d +udivr z0.s, p7/m, z0.s, z31.s +udot z0.d, z1.h, z15.h[1] +udot z0.d, z1.h, z31.h +udot z0.s, z1.b, z31.b +udot z0.s, z1.b, z7.b[3] +uhadd z0.b, p0/m, z0.b, z1.b +uhadd z0.h, p0/m, z0.h, z1.h +uhadd z29.s, p7/m, z29.s, z30.s +uhadd z31.d, p7/m, z31.d, z30.d +uhsub z0.b, p0/m, z0.b, z1.b +uhsub z0.h, p0/m, z0.h, z1.h +uhsub z29.s, p7/m, z29.s, z30.s +uhsub z31.d, p7/m, z31.d, z30.d +uhsubr z0.b, p0/m, z0.b, z1.b +uhsubr z0.h, p0/m, z0.h, z1.h +uhsubr z29.s, p7/m, z29.s, z30.s +uhsubr z31.d, p7/m, z31.d, z30.d +umax z0.b, z0.b, #0 +umax z31.b, p7/m, z31.b, z31.b +umax z31.b, z31.b, #255 +umax z31.d, p7/m, z31.d, z31.d +umax z31.h, p7/m, z31.h, z31.h +umax z31.s, p7/m, z31.s, z31.s +umaxp z0.b, p0/m, z0.b, z1.b +umaxp z0.h, p0/m, z0.h, z1.h +umaxp z29.s, p7/m, z29.s, z30.s +umaxp z31.d, p7/m, z31.d, z30.d +umaxv b0, p7, z31.b +umaxv d0, p7, z31.d +umaxv h0, p7, z31.h +umaxv s0, p7, z31.s +umin z0.b, z0.b, #0 +umin z31.b, p7/m, z31.b, z31.b +umin z31.b, z31.b, #255 +umin z31.d, p7/m, z31.d, z31.d +umin z31.h, p7/m, z31.h, z31.h +umin z31.s, p7/m, z31.s, z31.s +uminp z0.b, p0/m, z0.b, z1.b +uminp z0.h, p0/m, z0.h, z1.h +uminp z29.s, p7/m, z29.s, z30.s +uminp z31.d, p7/m, z31.d, z30.d +uminv b0, p7, z31.b +uminv d0, p7, z31.d +uminv h0, p7, z31.h +uminv s0, p7, z31.s +umlalb z0.d, z1.s, z15.s[1] +umlalb z0.d, z1.s, z31.s +umlalb z0.h, z1.b, z31.b +umlalb z0.s, z1.h, z31.h +umlalb z0.s, z1.h, z7.h[7] +umlalt z0.d, z1.s, z15.s[1] +umlalt z0.d, z1.s, z31.s +umlalt z0.h, z1.b, z31.b +umlalt z0.s, z1.h, z31.h +umlalt z0.s, z1.h, z7.h[7] +umlslb z0.d, z1.s, z15.s[1] +umlslb z0.d, z1.s, z31.s +umlslb z0.h, z1.b, z31.b +umlslb z0.s, z1.h, z31.h +umlslb z0.s, z1.h, z7.h[7] +umlslt z0.d, z1.s, z15.s[1] +umlslt z0.d, z1.s, z31.s +umlslt z0.h, z1.b, z31.b +umlslt z0.s, z1.h, z31.h +umlslt z0.s, z1.h, z7.h[7] +ummla z0.s, z1.b, z2.b +umulh z0.b, p7/m, z0.b, z31.b +umulh z0.b, z1.b, z2.b +umulh z0.d, p7/m, z0.d, z31.d +umulh z0.h, p7/m, z0.h, z31.h +umulh z0.h, z1.h, z2.h +umulh z0.s, p7/m, z0.s, z31.s +umulh z29.s, z30.s, z31.s +umulh z31.d, z31.d, z31.d +umullb z0.d, z1.s, z15.s[1] +umullb z0.h, z1.b, z2.b +umullb z0.s, z1.h, z7.h[7] +umullb z29.s, z30.h, z31.h +umullb z31.d, z31.s, z31.s +umullt z0.d, z1.s, z15.s[1] +umullt z0.h, z1.b, z2.b +umullt z0.s, z1.h, z7.h[7] +umullt z29.s, z30.h, z31.h +umullt z31.d, z31.s, z31.s +uqadd z0.b, p0/m, z0.b, z1.b +uqadd z0.b, z0.b, #0 +uqadd z0.b, z0.b, z0.b +uqadd z0.d, z0.d, #0 +uqadd z0.d, z0.d, #0, lsl #8 +uqadd z0.d, z0.d, z0.d +uqadd z0.h, p0/m, z0.h, z1.h +uqadd z0.h, z0.h, #0 +uqadd z0.h, z0.h, #0, lsl #8 +uqadd z0.h, z0.h, z0.h +uqadd z0.s, z0.s, #0 +uqadd z0.s, z0.s, #0, lsl #8 +uqadd z0.s, z0.s, z0.s +uqadd z29.s, p7/m, z29.s, z30.s +uqadd z31.b, z31.b, #255 +uqadd z31.d, p7/m, z31.d, z30.d +uqadd z31.d, z31.d, #65280 +uqadd z31.h, z31.h, #65280 +uqadd z31.s, z31.s, #65280 +uqdecb w0 +uqdecb w0, all, mul #16 +uqdecb w0, pow2 +uqdecb w0, pow2, mul #16 +uqdecb x0 +uqdecb x0, #14 +uqdecb x0, all, mul #16 +uqdecb x0, pow2 +uqdecb x0, vl1 +uqdecd w0 +uqdecd w0, all, mul #16 +uqdecd w0, pow2 +uqdecd w0, pow2, mul #16 +uqdecd x0 +uqdecd x0, #14 +uqdecd x0, all, mul #16 +uqdecd x0, pow2 +uqdecd x0, vl1 +uqdecd z0.d +uqdecd z0.d, all, mul #16 +uqdecd z0.d, pow2 +uqdecd z0.d, pow2, mul #16 +uqdech w0 +uqdech w0, all, mul #16 +uqdech w0, pow2 +uqdech w0, pow2, mul #16 +uqdech x0 +uqdech x0, #14 +uqdech x0, all, mul #16 +uqdech x0, pow2 +uqdech x0, vl1 +uqdech z0.h +uqdech z0.h, all, mul #16 +uqdech z0.h, pow2 +uqdech z0.h, pow2, mul #16 +uqdecp wzr, p15.b +uqdecp wzr, p15.d +uqdecp wzr, p15.h +uqdecp wzr, p15.s +uqdecp x0, p0.b +uqdecp x0, p0.d +uqdecp x0, p0.h +uqdecp x0, p0.s +uqdecp z0.d, p0.d +uqdecp z0.h, p0.h +uqdecp z0.s, p0.s +uqdecw w0 +uqdecw w0, all, mul #16 +uqdecw w0, pow2 +uqdecw w0, pow2, mul #16 +uqdecw x0 +uqdecw x0, #14 +uqdecw x0, all, mul #16 +uqdecw x0, pow2 +uqdecw x0, vl1 +uqdecw z0.s +uqdecw z0.s, all, mul #16 +uqdecw z0.s, pow2 +uqdecw z0.s, pow2, mul #16 +uqincb w0 +uqincb w0, all, mul #16 +uqincb w0, pow2 +uqincb w0, pow2, mul #16 +uqincb x0 +uqincb x0, #14 +uqincb x0, all, mul #16 +uqincb x0, pow2 +uqincb x0, vl1 +uqincd w0 +uqincd w0, all, mul #16 +uqincd w0, pow2 +uqincd w0, pow2, mul #16 +uqincd x0 +uqincd x0, #14 +uqincd x0, all, mul #16 +uqincd x0, pow2 +uqincd x0, vl1 +uqincd z0.d +uqincd z0.d, all, mul #16 +uqincd z0.d, pow2 +uqincd z0.d, pow2, mul #16 +uqinch w0 +uqinch w0, all, mul #16 +uqinch w0, pow2 +uqinch w0, pow2, mul #16 +uqinch x0 +uqinch x0, #14 +uqinch x0, all, mul #16 +uqinch x0, pow2 +uqinch x0, vl1 +uqinch z0.h +uqinch z0.h, all, mul #16 +uqinch z0.h, pow2 +uqinch z0.h, pow2, mul #16 +uqincp wzr, p15.b +uqincp wzr, p15.d +uqincp wzr, p15.h +uqincp wzr, p15.s +uqincp x0, p0.b +uqincp x0, p0.d +uqincp x0, p0.h +uqincp x0, p0.s +uqincp z0.d, p0.d +uqincp z0.h, p0.h +uqincp z0.s, p0.s +uqincw w0 +uqincw w0, all, mul #16 +uqincw w0, pow2 +uqincw w0, pow2, mul #16 +uqincw x0 +uqincw x0, #14 +uqincw x0, all, mul #16 +uqincw x0, pow2 +uqincw x0, vl1 +uqincw z0.s +uqincw z0.s, all, mul #16 +uqincw z0.s, pow2 +uqincw z0.s, pow2, mul #16 +uqrshl z0.b, p0/m, z0.b, z1.b +uqrshl z0.h, p0/m, z0.h, z1.h +uqrshl z29.s, p7/m, z29.s, z30.s +uqrshl z31.d, p7/m, z31.d, z30.d +uqrshlr z0.b, p0/m, z0.b, z1.b +uqrshlr z0.h, p0/m, z0.h, z1.h +uqrshlr z29.s, p7/m, z29.s, z30.s +uqrshlr z31.d, p7/m, z31.d, z30.d +uqrshrnb z0.b, z0.h, #1 +uqrshrnb z0.h, z0.s, #1 +uqrshrnb z0.s, z0.d, #1 +uqrshrnb z31.b, z31.h, #8 +uqrshrnb z31.h, z31.s, #16 +uqrshrnb z31.s, z31.d, #32 +uqrshrnt z0.b, z0.h, #1 +uqrshrnt z0.h, z0.s, #1 +uqrshrnt z0.s, z0.d, #1 +uqrshrnt z31.b, z31.h, #8 +uqrshrnt z31.h, z31.s, #16 +uqrshrnt z31.s, z31.d, #32 +uqshl z0.b, p0/m, z0.b, #0 +uqshl z0.b, p0/m, z0.b, z1.b +uqshl z0.d, p0/m, z0.d, #0 +uqshl z0.h, p0/m, z0.h, #0 +uqshl z0.h, p0/m, z0.h, z1.h +uqshl z0.s, p0/m, z0.s, #0 +uqshl z29.s, p7/m, z29.s, z30.s +uqshl z31.b, p0/m, z31.b, #7 +uqshl z31.d, p0/m, z31.d, #63 +uqshl z31.d, p7/m, z31.d, z30.d +uqshl z31.h, p0/m, z31.h, #15 +uqshl z31.s, p0/m, z31.s, #31 +uqshlr z0.b, p0/m, z0.b, z1.b +uqshlr z0.h, p0/m, z0.h, z1.h +uqshlr z29.s, p7/m, z29.s, z30.s +uqshlr z31.d, p7/m, z31.d, z30.d +uqshrnb z0.b, z0.h, #1 +uqshrnb z0.h, z0.s, #1 +uqshrnb z0.s, z0.d, #1 +uqshrnb z31.b, z31.h, #8 +uqshrnb z31.h, z31.s, #16 +uqshrnb z31.s, z31.d, #32 +uqshrnt z0.b, z0.h, #1 +uqshrnt z0.h, z0.s, #1 +uqshrnt z0.s, z0.d, #1 +uqshrnt z31.b, z31.h, #8 +uqshrnt z31.h, z31.s, #16 +uqshrnt z31.s, z31.d, #32 +uqsub z0.b, p0/m, z0.b, z1.b +uqsub z0.b, z0.b, #0 +uqsub z0.b, z0.b, z0.b +uqsub z0.d, z0.d, #0 +uqsub z0.d, z0.d, #0, lsl #8 +uqsub z0.d, z0.d, z0.d +uqsub z0.h, p0/m, z0.h, z1.h +uqsub z0.h, z0.h, #0 +uqsub z0.h, z0.h, #0, lsl #8 +uqsub z0.h, z0.h, z0.h +uqsub z0.s, z0.s, #0 +uqsub z0.s, z0.s, #0, lsl #8 +uqsub z0.s, z0.s, z0.s +uqsub z29.s, p7/m, z29.s, z30.s +uqsub z31.b, z31.b, #255 +uqsub z31.d, p7/m, z31.d, z30.d +uqsub z31.d, z31.d, #65280 +uqsub z31.h, z31.h, #65280 +uqsub z31.s, z31.s, #65280 +uqsubr z0.b, p0/m, z0.b, z1.b +uqsubr z0.h, p0/m, z0.h, z1.h +uqsubr z29.s, p7/m, z29.s, z30.s +uqsubr z31.d, p7/m, z31.d, z30.d +uqxtnb z0.b, z31.h +uqxtnb z0.h, z31.s +uqxtnb z0.s, z31.d +uqxtnt z0.b, z31.h +uqxtnt z0.h, z31.s +uqxtnt z0.s, z31.d +urecpe z31.s, p7/m, z31.s +urhadd z0.b, p0/m, z0.b, z1.b +urhadd z0.h, p0/m, z0.h, z1.h +urhadd z29.s, p7/m, z29.s, z30.s +urhadd z31.d, p7/m, z31.d, z30.d +urshl z0.b, p0/m, z0.b, z1.b +urshl z0.h, p0/m, z0.h, z1.h +urshl z29.s, p7/m, z29.s, z30.s +urshl z31.d, p7/m, z31.d, z30.d +urshlr z0.b, p0/m, z0.b, z1.b +urshlr z0.h, p0/m, z0.h, z1.h +urshlr z29.s, p7/m, z29.s, z30.s +urshlr z31.d, p7/m, z31.d, z30.d +urshr z0.b, p0/m, z0.b, #1 +urshr z0.d, p0/m, z0.d, #1 +urshr z0.h, p0/m, z0.h, #1 +urshr z0.s, p0/m, z0.s, #1 +urshr z31.b, p0/m, z31.b, #8 +urshr z31.d, p0/m, z31.d, #64 +urshr z31.h, p0/m, z31.h, #16 +urshr z31.s, p0/m, z31.s, #32 +ursqrte z31.s, p7/m, z31.s +ursra z0.b, z0.b, #1 +ursra z0.d, z0.d, #1 +ursra z0.h, z0.h, #1 +ursra z0.s, z0.s, #1 +ursra z31.b, z31.b, #8 +ursra z31.d, z31.d, #64 +ursra z31.h, z31.h, #16 +ursra z31.s, z31.s, #32 +ushllb z0.d, z0.s, #0 +ushllb z0.h, z0.b, #0 +ushllb z0.s, z0.h, #0 +ushllb z31.d, z31.s, #31 +ushllb z31.h, z31.b, #7 +ushllb z31.s, z31.h, #15 +ushllt z0.d, z0.s, #0 +ushllt z0.h, z0.b, #0 +ushllt z0.s, z0.h, #0 +ushllt z31.d, z31.s, #31 +ushllt z31.h, z31.b, #7 +ushllt z31.s, z31.h, #15 +usmmla z0.s, z1.b, z2.b +usqadd z0.b, p0/m, z0.b, z1.b +usqadd z0.h, p0/m, z0.h, z1.h +usqadd z29.s, p7/m, z29.s, z30.s +usqadd z31.d, p7/m, z31.d, z30.d +usra z0.b, z0.b, #1 +usra z0.d, z0.d, #1 +usra z0.h, z0.h, #1 +usra z0.s, z0.s, #1 +usra z31.b, z31.b, #8 +usra z31.d, z31.d, #64 +usra z31.h, z31.h, #16 +usra z31.s, z31.s, #32 +usublb z0.h, z1.b, z2.b +usublb z29.s, z30.h, z31.h +usublb z31.d, z31.s, z31.s +usublt z0.h, z1.b, z2.b +usublt z29.s, z30.h, z31.h +usublt z31.d, z31.s, z31.s +usubwb z0.h, z1.h, z2.b +usubwb z29.s, z30.s, z31.h +usubwb z31.d, z31.d, z31.s +usubwt z0.h, z1.h, z2.b +usubwt z29.s, z30.s, z31.h +usubwt z31.d, z31.d, z31.s +uunpkhi z31.d, z31.s +uunpkhi z31.h, z31.b +uunpkhi z31.s, z31.h +uunpklo z31.d, z31.s +uunpklo z31.h, z31.b +uunpklo z31.s, z31.h +uxtb z0.d, p0/m, z0.d +uxtb z0.h, p0/m, z0.h +uxtb z0.s, p0/m, z0.s +uxtb z31.d, p7/m, z31.d +uxtb z31.h, p7/m, z31.h +uxtb z31.s, p7/m, z31.s +uxth z0.d, p0/m, z0.d +uxth z0.s, p0/m, z0.s +uxth z31.d, p7/m, z31.d +uxth z31.s, p7/m, z31.s +uxtw z0.d, p0/m, z0.d +uxtw z31.d, p7/m, z31.d +uzp1 p15.b, p15.b, p15.b +uzp1 p15.d, p15.d, p15.d +uzp1 p15.h, p15.h, p15.h +uzp1 p15.s, p15.s, p15.s +uzp1 z31.b, z31.b, z31.b +uzp1 z31.d, z31.d, z31.d +uzp1 z31.h, z31.h, z31.h +uzp1 z31.s, z31.s, z31.s +uzp2 p15.b, p15.b, p15.b +uzp2 p15.d, p15.d, p15.d +uzp2 p15.h, p15.h, p15.h +uzp2 p15.s, p15.s, p15.s +uzp2 z31.b, z31.b, z31.b +uzp2 z31.d, z31.d, z31.d +uzp2 z31.h, z31.h, z31.h +uzp2 z31.s, z31.s, z31.s +whilege p15.b, w0, wzr +whilege p15.b, wzr, w0 +whilege p15.b, x0, xzr +whilege p15.b, xzr, x0 +whilege p15.d, w0, wzr +whilege p15.d, x0, xzr +whilege p15.h, w0, wzr +whilege p15.h, x0, xzr +whilege p15.s, w0, wzr +whilege p15.s, x0, xzr +whilerw p15.b, x30, x30 +whilerw p15.d, x30, x30 +whilerw p15.h, x30, x30 +whilerw p15.s, x30, x30 +whilewr p15.b, x30, x30 +whilewr p15.d, x30, x30 +whilewr p15.h, x30, x30 +whilewr p15.s, x30, x30 +wrffr p0.b +wrffr p15.b +xar z0.b, z0.b, z1.b, #1 +xar z0.d, z0.d, z1.d, #1 +xar z0.h, z0.h, z1.h, #1 +xar z0.s, z0.s, z1.s, #1 +xar z31.b, z31.b, z30.b, #8 +xar z31.d, z31.d, z30.d, #64 +xar z31.h, z31.h, z30.h, #16 +xar z31.s, z31.s, z30.s, #32 +zip1 p0.b, p0.b, p0.b +zip1 p0.d, p0.d, p0.d +zip1 p0.h, p0.h, p0.h +zip1 p0.s, p0.s, p0.s +zip1 p15.b, p15.b, p15.b +zip1 p15.d, p15.d, p15.d +zip1 p15.h, p15.h, p15.h +zip1 p15.s, p15.s, p15.s +zip1 z0.b, z0.b, z0.b +zip1 z0.d, z0.d, z0.d +zip1 z0.h, z0.h, z0.h +zip1 z0.s, z0.s, z0.s +zip1 z31.b, z31.b, z31.b +zip1 z31.d, z31.d, z31.d +zip1 z31.h, z31.h, z31.h +zip1 z31.s, z31.s, z31.s +zip2 p0.b, p0.b, p0.b +zip2 p0.d, p0.d, p0.d +zip2 p0.h, p0.h, p0.h +zip2 p0.s, p0.s, p0.s +zip2 p15.b, p15.b, p15.b +zip2 p15.d, p15.d, p15.d +zip2 p15.h, p15.h, p15.h +zip2 p15.s, p15.s, p15.s +zip2 z0.b, z0.b, z0.b +zip2 z0.d, z0.d, z0.d +zip2 z0.h, z0.h, z0.h +zip2 z0.s, z0.s, z0.s +zip2 z31.b, z31.b, z31.b +zip2 z31.d, z31.d, z31.d +zip2 z31.h, z31.h, z31.h +zip2 z31.s, z31.s, z31.s + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 2 0.25 abs z0.b, p0/m, z0.b +# CHECK-NEXT: 1 2 0.25 abs z0.d, p0/m, z0.d +# CHECK-NEXT: 1 2 0.25 abs z0.h, p0/m, z0.h +# CHECK-NEXT: 1 2 0.25 abs z0.s, p0/m, z0.s +# CHECK-NEXT: 1 2 0.25 abs z31.b, p7/m, z31.b +# CHECK-NEXT: 1 2 0.25 abs z31.d, p7/m, z31.d +# CHECK-NEXT: 1 2 0.25 abs z31.h, p7/m, z31.h +# CHECK-NEXT: 1 2 0.25 abs z31.s, p7/m, z31.s +# CHECK-NEXT: 1 2 0.25 adclb z0.d, z1.d, z31.d +# CHECK-NEXT: 1 2 0.25 adclb z0.s, z1.s, z31.s +# CHECK-NEXT: 1 2 0.25 adclt z0.d, z1.d, z31.d +# CHECK-NEXT: 1 2 0.25 adclt z0.s, z1.s, z31.s +# CHECK-NEXT: 1 2 0.25 add z0.b, p0/m, z0.b, z0.b +# CHECK-NEXT: 1 2 0.25 add z0.b, z0.b, #0 +# CHECK-NEXT: 1 2 0.25 add z0.b, z0.b, z0.b +# CHECK-NEXT: 1 2 0.25 add z0.d, p0/m, z0.d, z0.d +# CHECK-NEXT: 1 2 0.25 add z0.d, z0.d, #0 +# CHECK-NEXT: 1 2 0.25 add z0.d, z0.d, #0, lsl #8 +# CHECK-NEXT: 1 2 0.25 add z0.d, z0.d, z0.d +# CHECK-NEXT: 1 2 0.25 add z0.h, p0/m, z0.h, z0.h +# CHECK-NEXT: 1 2 0.25 add z0.h, z0.h, #0 +# CHECK-NEXT: 1 2 0.25 add z0.h, z0.h, #0, lsl #8 +# CHECK-NEXT: 1 2 0.25 add z0.h, z0.h, z0.h +# CHECK-NEXT: 1 2 0.25 add z0.s, p0/m, z0.s, z0.s +# CHECK-NEXT: 1 2 0.25 add z0.s, z0.s, #0 +# CHECK-NEXT: 1 2 0.25 add z0.s, z0.s, #0, lsl #8 +# CHECK-NEXT: 1 2 0.25 add z0.s, z0.s, z0.s +# CHECK-NEXT: 1 2 0.25 add z0.s, z1.s, z2.s +# CHECK-NEXT: 1 2 0.25 add z21.b, p5/m, z21.b, z10.b +# CHECK-NEXT: 1 2 0.25 add z21.b, z10.b, z21.b +# CHECK-NEXT: 1 2 0.25 add z21.d, p5/m, z21.d, z10.d +# CHECK-NEXT: 1 2 0.25 add z21.d, z10.d, z21.d +# CHECK-NEXT: 1 2 0.25 add z21.h, p5/m, z21.h, z10.h +# CHECK-NEXT: 1 2 0.25 add z21.h, z10.h, z21.h +# CHECK-NEXT: 1 2 0.25 add z21.s, p5/m, z21.s, z10.s +# CHECK-NEXT: 1 2 0.25 add z21.s, z10.s, z21.s +# CHECK-NEXT: 1 2 0.25 add z23.b, p3/m, z23.b, z13.b +# CHECK-NEXT: 1 2 0.25 add z23.b, z13.b, z8.b +# CHECK-NEXT: 1 2 0.25 add z23.d, p3/m, z23.d, z13.d +# CHECK-NEXT: 1 2 0.25 add z23.d, z13.d, z8.d +# CHECK-NEXT: 1 2 0.25 add z23.h, p3/m, z23.h, z13.h +# CHECK-NEXT: 1 2 0.25 add z23.h, z13.h, z8.h +# CHECK-NEXT: 1 2 0.25 add z23.s, p3/m, z23.s, z13.s +# CHECK-NEXT: 1 2 0.25 add z23.s, z13.s, z8.s +# CHECK-NEXT: 1 2 0.25 add z31.b, p7/m, z31.b, z31.b +# CHECK-NEXT: 1 2 0.25 add z31.b, z31.b, #255 +# CHECK-NEXT: 1 2 0.25 add z31.b, z31.b, z31.b +# CHECK-NEXT: 1 2 0.25 add z31.d, p7/m, z31.d, z31.d +# CHECK-NEXT: 1 2 0.25 add z31.d, z31.d, #65280 +# CHECK-NEXT: 1 2 0.25 add z31.d, z31.d, z31.d +# CHECK-NEXT: 1 2 0.25 add z31.h, p7/m, z31.h, z31.h +# CHECK-NEXT: 1 2 0.25 add z31.h, z31.h, #65280 +# CHECK-NEXT: 1 2 0.25 add z31.h, z31.h, z31.h +# CHECK-NEXT: 1 2 0.25 add z31.s, p7/m, z31.s, z31.s +# CHECK-NEXT: 1 2 0.25 add z31.s, z31.s, #65280 +# CHECK-NEXT: 1 2 0.25 add z31.s, z31.s, z31.s +# CHECK-NEXT: 1 2 0.25 addhnb z0.b, z1.h, z31.h +# CHECK-NEXT: 1 2 0.25 addhnb z0.h, z1.s, z31.s +# CHECK-NEXT: 1 2 0.25 addhnb z0.s, z1.d, z31.d +# CHECK-NEXT: 1 2 0.25 addhnt z0.b, z1.h, z31.h +# CHECK-NEXT: 1 2 0.25 addhnt z0.h, z1.s, z31.s +# CHECK-NEXT: 1 2 0.25 addhnt z0.s, z1.d, z31.d +# CHECK-NEXT: 1 2 0.25 addp z0.b, p0/m, z0.b, z1.b +# CHECK-NEXT: 1 2 0.25 addp z0.h, p0/m, z0.h, z1.h +# CHECK-NEXT: 1 2 0.25 addp z29.s, p7/m, z29.s, z30.s +# CHECK-NEXT: 1 2 0.25 addp z31.d, p7/m, z31.d, z30.d +# CHECK-NEXT: 1 2 0.50 addpl sp, sp, #31 +# CHECK-NEXT: 1 2 0.50 addpl x0, x0, #-32 +# CHECK-NEXT: 1 2 0.50 addpl x21, x21, #0 +# CHECK-NEXT: 1 2 0.50 addpl x23, x8, #-1 +# CHECK-NEXT: 1 2 0.50 addvl sp, sp, #31 +# CHECK-NEXT: 1 2 0.50 addvl x0, x0, #-32 +# CHECK-NEXT: 1 2 0.50 addvl x21, x21, #0 +# CHECK-NEXT: 1 2 0.50 addvl x23, x8, #-1 +# CHECK-NEXT: 1 2 0.25 adr z0.d, [z0.d, z0.d, lsl #1] +# CHECK-NEXT: 1 2 0.25 adr z0.d, [z0.d, z0.d, lsl #2] +# CHECK-NEXT: 1 2 0.25 adr z0.d, [z0.d, z0.d, lsl #3] +# CHECK-NEXT: 1 2 0.25 adr z0.d, [z0.d, z0.d, sxtw #1] +# CHECK-NEXT: 1 2 0.25 adr z0.d, [z0.d, z0.d, sxtw #2] +# CHECK-NEXT: 1 2 0.25 adr z0.d, [z0.d, z0.d, sxtw #3] +# CHECK-NEXT: 1 2 0.25 adr z0.d, [z0.d, z0.d, sxtw] +# CHECK-NEXT: 1 2 0.25 adr z0.d, [z0.d, z0.d, uxtw #1] +# CHECK-NEXT: 1 2 0.25 adr z0.d, [z0.d, z0.d, uxtw #2] +# CHECK-NEXT: 1 2 0.25 adr z0.d, [z0.d, z0.d, uxtw #3] +# CHECK-NEXT: 1 2 0.25 adr z0.d, [z0.d, z0.d, uxtw] +# CHECK-NEXT: 1 2 0.25 adr z0.d, [z0.d, z0.d] +# CHECK-NEXT: 1 2 0.25 adr z0.s, [z0.s, z0.s, lsl #1] +# CHECK-NEXT: 1 2 0.25 adr z0.s, [z0.s, z0.s, lsl #2] +# CHECK-NEXT: 1 2 0.25 adr z0.s, [z0.s, z0.s, lsl #3] +# CHECK-NEXT: 1 2 0.25 adr z0.s, [z0.s, z0.s] +# CHECK-NEXT: 1 2 0.25 aesd z0.b, z0.b, z31.b +# CHECK-NEXT: 1 2 0.25 aese z0.b, z0.b, z31.b +# CHECK-NEXT: 1 2 0.25 aesimc z0.b, z0.b +# CHECK-NEXT: 1 2 0.25 aesimc z31.b, z31.b +# CHECK-NEXT: 1 2 0.25 aesmc z0.b, z0.b +# CHECK-NEXT: 1 2 0.25 aesmc z31.b, z31.b +# CHECK-NEXT: 1 2 1.00 and p0.b, p0/z, p0.b, p1.b +# CHECK-NEXT: 1 2 0.25 and z0.d, z0.d, #0x6 +# CHECK-NEXT: 1 2 0.25 and z0.d, z0.d, #0xfffffffffffffff9 +# CHECK-NEXT: 1 2 0.25 and z0.d, z0.d, z0.d +# CHECK-NEXT: 1 2 0.25 and z0.s, z0.s, #0x6 +# CHECK-NEXT: 1 2 0.25 and z0.s, z0.s, #0xfffffff9 +# CHECK-NEXT: 1 2 0.25 and z23.d, z13.d, z8.d +# CHECK-NEXT: 1 2 0.25 and z23.h, z23.h, #0x6 +# CHECK-NEXT: 1 2 0.25 and z23.h, z23.h, #0xfff9 +# CHECK-NEXT: 1 2 0.25 and z31.b, p7/m, z31.b, z31.b +# CHECK-NEXT: 1 2 0.25 and z31.d, p7/m, z31.d, z31.d +# CHECK-NEXT: 1 2 0.25 and z31.h, p7/m, z31.h, z31.h +# CHECK-NEXT: 1 2 0.25 and z31.s, p7/m, z31.s, z31.s +# CHECK-NEXT: 1 2 0.25 and z5.b, z5.b, #0x6 +# CHECK-NEXT: 1 2 0.25 and z5.b, z5.b, #0xf9 +# CHECK-NEXT: 2 2 1.00 ands p0.b, p0/z, p0.b, p1.b +# CHECK-NEXT: 2 6 0.50 andv b0, p7, z31.b +# CHECK-NEXT: 2 6 0.50 andv d0, p7, z31.d +# CHECK-NEXT: 2 6 0.50 andv h0, p7, z31.h +# CHECK-NEXT: 2 6 0.50 andv s0, p7, z31.s +# CHECK-NEXT: 1 2 0.50 asr z0.b, p0/m, z0.b, #1 +# CHECK-NEXT: 1 2 0.50 asr z0.b, p0/m, z0.b, z0.b +# CHECK-NEXT: 1 2 0.50 asr z0.b, p0/m, z0.b, z1.d +# CHECK-NEXT: 1 2 0.50 asr z0.b, z0.b, #1 +# CHECK-NEXT: 1 2 0.50 asr z0.b, z1.b, z2.d +# CHECK-NEXT: 1 2 0.50 asr z0.d, p0/m, z0.d, #1 +# CHECK-NEXT: 1 2 0.50 asr z0.d, p0/m, z0.d, z0.d +# CHECK-NEXT: 1 2 0.50 asr z0.d, z0.d, #1 +# CHECK-NEXT: 1 2 0.50 asr z0.h, p0/m, z0.h, #1 +# CHECK-NEXT: 1 2 0.50 asr z0.h, p0/m, z0.h, z0.h +# CHECK-NEXT: 1 2 0.50 asr z0.h, p0/m, z0.h, z1.d +# CHECK-NEXT: 1 2 0.50 asr z0.h, z0.h, #1 +# CHECK-NEXT: 1 2 0.50 asr z0.h, z1.h, z2.d +# CHECK-NEXT: 1 2 0.50 asr z0.s, p0/m, z0.s, #1 +# CHECK-NEXT: 1 2 0.50 asr z0.s, p0/m, z0.s, z0.s +# CHECK-NEXT: 1 2 0.50 asr z0.s, p0/m, z0.s, z1.d +# CHECK-NEXT: 1 2 0.50 asr z0.s, z0.s, #1 +# CHECK-NEXT: 1 2 0.50 asr z0.s, z1.s, z2.d +# CHECK-NEXT: 1 2 0.50 asr z31.b, p0/m, z31.b, #8 +# CHECK-NEXT: 1 2 0.50 asr z31.b, z31.b, #8 +# CHECK-NEXT: 1 2 0.50 asr z31.d, p0/m, z31.d, #64 +# CHECK-NEXT: 1 2 0.50 asr z31.d, z31.d, #64 +# CHECK-NEXT: 1 2 0.50 asr z31.h, p0/m, z31.h, #16 +# CHECK-NEXT: 1 2 0.50 asr z31.h, z31.h, #16 +# CHECK-NEXT: 1 2 0.50 asr z31.s, p0/m, z31.s, #32 +# CHECK-NEXT: 1 2 0.50 asr z31.s, z31.s, #32 +# CHECK-NEXT: 1 4 0.50 asrd z0.b, p0/m, z0.b, #1 +# CHECK-NEXT: 1 4 0.50 asrd z0.d, p0/m, z0.d, #1 +# CHECK-NEXT: 1 4 0.50 asrd z0.h, p0/m, z0.h, #1 +# CHECK-NEXT: 1 4 0.50 asrd z0.s, p0/m, z0.s, #1 +# CHECK-NEXT: 1 4 0.50 asrd z31.b, p0/m, z31.b, #8 +# CHECK-NEXT: 1 4 0.50 asrd z31.d, p0/m, z31.d, #64 +# CHECK-NEXT: 1 4 0.50 asrd z31.h, p0/m, z31.h, #16 +# CHECK-NEXT: 1 4 0.50 asrd z31.s, p0/m, z31.s, #32 +# CHECK-NEXT: 1 2 0.50 asrr z0.b, p0/m, z0.b, z0.b +# CHECK-NEXT: 1 2 0.50 asrr z0.d, p0/m, z0.d, z0.d +# CHECK-NEXT: 1 2 0.50 asrr z0.h, p0/m, z0.h, z0.h +# CHECK-NEXT: 1 2 0.50 asrr z0.s, p0/m, z0.s, z0.s +# CHECK-NEXT: 1 2 1.00 bcax z29.d, z29.d, z30.d, z31.d +# CHECK-NEXT: 2 6 2.00 bdep z0.b, z1.b, z31.b +# CHECK-NEXT: 2 6 2.00 bdep z0.d, z1.d, z31.d +# CHECK-NEXT: 2 6 2.00 bdep z0.h, z1.h, z31.h +# CHECK-NEXT: 2 6 2.00 bdep z0.s, z1.s, z31.s +# CHECK-NEXT: 2 6 2.00 bext z0.b, z1.b, z31.b +# CHECK-NEXT: 2 6 2.00 bext z0.d, z1.d, z31.d +# CHECK-NEXT: 2 6 2.00 bext z0.h, z1.h, z31.h +# CHECK-NEXT: 2 6 2.00 bext z0.s, z1.s, z31.s +# CHECK-NEXT: 1 4 0.50 bfcvt z0.h, p0/m, z1.s +# CHECK-NEXT: 1 4 0.50 bfcvtnt z0.h, p0/m, z1.s +# CHECK-NEXT: 1 5 0.25 bfdot z0.s, z1.h, z2.h +# CHECK-NEXT: 1 5 0.25 bfdot z0.s, z1.h, z2.h[0] +# CHECK-NEXT: 1 5 0.25 bfdot z0.s, z1.h, z2.h[3] +# CHECK-NEXT: 1 5 0.25 bfmlalb z0.s, z1.h, z2.h +# CHECK-NEXT: 1 5 0.25 bfmlalb z0.s, z1.h, z2.h[0] +# CHECK-NEXT: 1 5 0.25 bfmlalb z0.s, z1.h, z2.h[7] +# CHECK-NEXT: 1 5 0.25 bfmlalb z10.s, z21.h, z14.h +# CHECK-NEXT: 1 5 0.25 bfmlalb z21.s, z14.h, z3.h[2] +# CHECK-NEXT: 1 5 0.25 bfmlalt z0.s, z1.h, z2.h +# CHECK-NEXT: 1 5 0.25 bfmlalt z0.s, z1.h, z2.h[0] +# CHECK-NEXT: 1 5 0.25 bfmlalt z0.s, z1.h, z2.h[7] +# CHECK-NEXT: 1 5 0.25 bfmlalt z0.s, z1.h, z7.h[7] +# CHECK-NEXT: 1 5 0.25 bfmlalt z14.s, z10.h, z21.h +# CHECK-NEXT: 1 6 0.25 bfmmla z0.s, z1.h, z2.h +# CHECK-NEXT: 2 6 2.00 bgrp z0.b, z1.b, z31.b +# CHECK-NEXT: 2 6 2.00 bgrp z0.d, z1.d, z31.d +# CHECK-NEXT: 2 6 2.00 bgrp z0.h, z1.h, z31.h +# CHECK-NEXT: 2 6 2.00 bgrp z0.s, z1.s, z31.s +# CHECK-NEXT: 1 2 1.00 bic p0.b, p0/z, p0.b, p0.b +# CHECK-NEXT: 1 2 1.00 bic p15.b, p15/z, p15.b, p15.b +# CHECK-NEXT: 1 2 0.25 bic z0.d, z0.d, z0.d +# CHECK-NEXT: 1 2 0.25 bic z23.d, z13.d, z8.d +# CHECK-NEXT: 1 2 0.25 bic z31.b, p7/m, z31.b, z31.b +# CHECK-NEXT: 1 2 0.25 bic z31.d, p7/m, z31.d, z31.d +# CHECK-NEXT: 1 2 0.25 bic z31.h, p7/m, z31.h, z31.h +# CHECK-NEXT: 1 2 0.25 bic z31.s, p7/m, z31.s, z31.s +# CHECK-NEXT: 2 2 1.00 bics p0.b, p0/z, p0.b, p0.b +# CHECK-NEXT: 2 2 1.00 bics p15.b, p15/z, p15.b, p15.b +# CHECK-NEXT: 1 2 0.50 brka p0.b, p15/m, p15.b +# CHECK-NEXT: 1 2 0.50 brka p0.b, p15/z, p15.b +# CHECK-NEXT: 2 3 1.00 brkas p0.b, p15/z, p15.b +# CHECK-NEXT: 1 2 0.50 brkb p0.b, p15/m, p15.b +# CHECK-NEXT: 1 2 0.50 brkb p0.b, p15/z, p15.b +# CHECK-NEXT: 2 3 1.00 brkbs p0.b, p15/z, p15.b +# CHECK-NEXT: 1 2 1.00 brkn p0.b, p15/z, p1.b, p0.b +# CHECK-NEXT: 1 3 1.00 brkn p15.b, p15/z, p15.b, p15.b +# CHECK-NEXT: 2 3 1.00 brkns p0.b, p15/z, p1.b, p0.b +# CHECK-NEXT: 2 4 1.00 brkns p15.b, p15/z, p15.b, p15.b +# CHECK-NEXT: 1 2 1.00 brkpa p0.b, p15/z, p1.b, p2.b +# CHECK-NEXT: 1 3 1.00 brkpa p15.b, p15/z, p15.b, p15.b +# CHECK-NEXT: 2 3 1.00 brkpas p0.b, p15/z, p1.b, p2.b +# CHECK-NEXT: 2 4 1.00 brkpas p15.b, p15/z, p15.b, p15.b +# CHECK-NEXT: 1 2 1.00 brkpb p0.b, p15/z, p1.b, p2.b +# CHECK-NEXT: 1 3 1.00 brkpb p15.b, p15/z, p15.b, p15.b +# CHECK-NEXT: 2 3 1.00 brkpbs p0.b, p15/z, p1.b, p2.b +# CHECK-NEXT: 2 4 1.00 brkpbs p15.b, p15/z, p15.b, p15.b +# CHECK-NEXT: 1 2 0.25 bsl z0.d, z0.d, z1.d, z2.d +# CHECK-NEXT: 1 2 0.25 bsl1n z0.d, z0.d, z1.d, z2.d +# CHECK-NEXT: 1 2 0.25 bsl2n z0.d, z0.d, z1.d, z2.d +# CHECK-NEXT: 1 2 0.25 cadd z0.b, z0.b, z0.b, #90 +# CHECK-NEXT: 1 2 0.25 cadd z0.d, z0.d, z0.d, #90 +# CHECK-NEXT: 1 2 0.25 cadd z0.h, z0.h, z0.h, #90 +# CHECK-NEXT: 1 2 0.25 cadd z0.s, z0.s, z0.s, #90 +# CHECK-NEXT: 1 2 0.25 cadd z31.b, z31.b, z31.b, #270 +# CHECK-NEXT: 1 2 0.25 cadd z31.d, z31.d, z31.d, #270 +# CHECK-NEXT: 1 2 0.25 cadd z31.h, z31.h, z31.h, #270 +# CHECK-NEXT: 1 2 0.25 cadd z31.s, z31.s, z31.s, #270 +# CHECK-NEXT: 1 4 0.50 cdot z0.d, z1.h, z15.h[1], #0 +# CHECK-NEXT: 1 4 0.50 cdot z0.d, z1.h, z31.h, #0 +# CHECK-NEXT: 1 4 0.50 cdot z0.d, z1.h, z31.h, #180 +# CHECK-NEXT: 1 4 0.50 cdot z0.d, z1.h, z31.h, #270 +# CHECK-NEXT: 1 4 0.50 cdot z0.d, z1.h, z31.h, #90 +# CHECK-NEXT: 1 3 0.25 cdot z0.s, z1.b, z31.b, #0 +# CHECK-NEXT: 1 3 0.25 cdot z0.s, z1.b, z7.b[3], #0 +# CHECK-NEXT: 1 4 0.50 cdot z29.d, z30.h, z0.h[0], #180 +# CHECK-NEXT: 1 4 0.50 cdot z31.d, z30.h, z7.h[1], #270 +# CHECK-NEXT: 1 4 0.50 cdot z5.d, z6.h, z3.h[0], #90 +# CHECK-NEXT: 1 3 1.00 clasta b0, p7, b0, z31.b +# CHECK-NEXT: 1 3 1.00 clasta d0, p7, d0, z31.d +# CHECK-NEXT: 1 3 1.00 clasta h0, p7, h0, z31.h +# CHECK-NEXT: 1 3 1.00 clasta s0, p7, s0, z31.s +# CHECK-NEXT: 2 8 1.00 clasta w0, p7, w0, z31.b +# CHECK-NEXT: 2 8 1.00 clasta w0, p7, w0, z31.h +# CHECK-NEXT: 2 8 1.00 clasta w0, p7, w0, z31.s +# CHECK-NEXT: 2 8 1.00 clasta x0, p7, x0, z31.d +# CHECK-NEXT: 1 3 1.00 clasta z0.b, p7, z0.b, z31.b +# CHECK-NEXT: 1 3 1.00 clasta z0.d, p7, z0.d, z31.d +# CHECK-NEXT: 1 3 1.00 clasta z0.h, p7, z0.h, z31.h +# CHECK-NEXT: 1 3 1.00 clasta z0.s, p7, z0.s, z31.s +# CHECK-NEXT: 1 3 1.00 clastb b0, p7, b0, z31.b +# CHECK-NEXT: 1 3 1.00 clastb d0, p7, d0, z31.d +# CHECK-NEXT: 1 3 1.00 clastb h0, p7, h0, z31.h +# CHECK-NEXT: 1 3 1.00 clastb s0, p7, s0, z31.s +# CHECK-NEXT: 2 8 1.00 clastb w0, p7, w0, z31.b +# CHECK-NEXT: 2 8 1.00 clastb w0, p7, w0, z31.h +# CHECK-NEXT: 2 8 1.00 clastb w0, p7, w0, z31.s +# CHECK-NEXT: 2 8 1.00 clastb x0, p7, x0, z31.d +# CHECK-NEXT: 1 3 1.00 clastb z0.b, p7, z0.b, z31.b +# CHECK-NEXT: 1 3 1.00 clastb z0.d, p7, z0.d, z31.d +# CHECK-NEXT: 1 3 1.00 clastb z0.h, p7, z0.h, z31.h +# CHECK-NEXT: 1 3 1.00 clastb z0.s, p7, z0.s, z31.s +# CHECK-NEXT: 1 2 0.25 cls z31.b, p7/m, z31.b +# CHECK-NEXT: 1 2 0.25 cls z31.d, p7/m, z31.d +# CHECK-NEXT: 1 2 0.25 cls z31.h, p7/m, z31.h +# CHECK-NEXT: 1 2 0.25 cls z31.s, p7/m, z31.s +# CHECK-NEXT: 1 2 0.25 clz z31.b, p7/m, z31.b +# CHECK-NEXT: 1 2 0.25 clz z31.d, p7/m, z31.d +# CHECK-NEXT: 1 2 0.25 clz z31.h, p7/m, z31.h +# CHECK-NEXT: 1 2 0.25 clz z31.s, p7/m, z31.s +# CHECK-NEXT: 1 4 0.50 cmla z0.b, z1.b, z2.b, #0 +# CHECK-NEXT: 1 5 1.00 cmla z0.d, z1.d, z2.d, #0 +# CHECK-NEXT: 1 4 0.50 cmla z0.h, z1.h, z2.h, #0 +# CHECK-NEXT: 1 4 0.50 cmla z0.h, z1.h, z2.h[0], #0 +# CHECK-NEXT: 1 4 0.50 cmla z0.s, z1.s, z2.s, #0 +# CHECK-NEXT: 1 4 0.50 cmla z0.s, z1.s, z2.s[0], #0 +# CHECK-NEXT: 1 4 0.50 cmla z15.b, z16.b, z17.b, #270 +# CHECK-NEXT: 1 5 1.00 cmla z15.d, z16.d, z17.d, #270 +# CHECK-NEXT: 1 4 0.50 cmla z15.h, z16.h, z17.h, #270 +# CHECK-NEXT: 1 4 0.50 cmla z15.s, z16.s, z17.s, #270 +# CHECK-NEXT: 1 4 0.50 cmla z29.b, z30.b, z31.b, #90 +# CHECK-NEXT: 1 5 1.00 cmla z29.d, z30.d, z31.d, #90 +# CHECK-NEXT: 1 4 0.50 cmla z29.h, z30.h, z31.h, #90 +# CHECK-NEXT: 1 4 0.50 cmla z29.s, z30.s, z31.s, #90 +# CHECK-NEXT: 1 4 0.50 cmla z31.b, z31.b, z31.b, #180 +# CHECK-NEXT: 1 5 1.00 cmla z31.d, z31.d, z31.d, #180 +# CHECK-NEXT: 1 4 0.50 cmla z31.h, z30.h, z7.h[0], #180 +# CHECK-NEXT: 1 4 0.50 cmla z31.h, z31.h, z31.h, #180 +# CHECK-NEXT: 1 4 0.50 cmla z31.s, z30.s, z7.s[0], #180 +# CHECK-NEXT: 1 4 0.50 cmla z31.s, z31.s, z31.s, #180 +# CHECK-NEXT: 2 5 1.00 cmpeq p0.b, p0/z, z0.b, #-16 +# CHECK-NEXT: 2 5 1.00 cmpeq p0.b, p0/z, z0.b, #15 +# CHECK-NEXT: 2 5 1.00 cmpeq p0.b, p0/z, z0.b, z0.b +# CHECK-NEXT: 2 5 1.00 cmpeq p0.b, p0/z, z0.b, z0.d +# CHECK-NEXT: 2 5 1.00 cmpeq p0.d, p0/z, z0.d, #-16 +# CHECK-NEXT: 2 5 1.00 cmpeq p0.d, p0/z, z0.d, #15 +# CHECK-NEXT: 2 5 1.00 cmpeq p0.d, p0/z, z0.d, z0.d +# CHECK-NEXT: 2 5 1.00 cmpeq p0.h, p0/z, z0.h, #-16 +# CHECK-NEXT: 2 5 1.00 cmpeq p0.h, p0/z, z0.h, #15 +# CHECK-NEXT: 2 5 1.00 cmpeq p0.h, p0/z, z0.h, z0.d +# CHECK-NEXT: 2 5 1.00 cmpeq p0.h, p0/z, z0.h, z0.h +# CHECK-NEXT: 2 5 1.00 cmpeq p0.s, p0/z, z0.s, #-16 +# CHECK-NEXT: 2 5 1.00 cmpeq p0.s, p0/z, z0.s, #15 +# CHECK-NEXT: 2 5 1.00 cmpeq p0.s, p0/z, z0.s, z0.d +# CHECK-NEXT: 2 5 1.00 cmpeq p0.s, p0/z, z0.s, z0.s +# CHECK-NEXT: 2 5 1.00 cmpge p0.b, p0/z, z0.b, #-16 +# CHECK-NEXT: 2 5 1.00 cmpge p0.b, p0/z, z0.b, #15 +# CHECK-NEXT: 2 5 1.00 cmpge p0.b, p0/z, z0.b, z0.b +# CHECK-NEXT: 2 5 1.00 cmpge p0.b, p0/z, z0.b, z0.d +# CHECK-NEXT: 2 5 1.00 cmpge p0.b, p0/z, z1.b, z0.b +# CHECK-NEXT: 2 5 1.00 cmpge p0.d, p0/z, z0.d, #-16 +# CHECK-NEXT: 2 5 1.00 cmpge p0.d, p0/z, z0.d, #15 +# CHECK-NEXT: 2 5 1.00 cmpge p0.d, p0/z, z0.d, z0.d +# CHECK-NEXT: 2 5 1.00 cmpge p0.d, p0/z, z1.d, z0.d +# CHECK-NEXT: 2 5 1.00 cmpge p0.h, p0/z, z0.h, #-16 +# CHECK-NEXT: 2 5 1.00 cmpge p0.h, p0/z, z0.h, #15 +# CHECK-NEXT: 2 5 1.00 cmpge p0.h, p0/z, z0.h, z0.d +# CHECK-NEXT: 2 5 1.00 cmpge p0.h, p0/z, z0.h, z0.h +# CHECK-NEXT: 2 5 1.00 cmpge p0.h, p0/z, z1.h, z0.h +# CHECK-NEXT: 2 5 1.00 cmpge p0.s, p0/z, z0.s, #-16 +# CHECK-NEXT: 2 5 1.00 cmpge p0.s, p0/z, z0.s, #15 +# CHECK-NEXT: 2 5 1.00 cmpge p0.s, p0/z, z0.s, z0.d +# CHECK-NEXT: 2 5 1.00 cmpge p0.s, p0/z, z0.s, z0.s +# CHECK-NEXT: 2 5 1.00 cmpge p0.s, p0/z, z1.s, z0.s +# CHECK-NEXT: 2 5 1.00 cmpgt p0.b, p0/z, z0.b, #-16 +# CHECK-NEXT: 2 5 1.00 cmpgt p0.b, p0/z, z0.b, #15 +# CHECK-NEXT: 2 5 1.00 cmpgt p0.b, p0/z, z0.b, z0.b +# CHECK-NEXT: 2 5 1.00 cmpgt p0.b, p0/z, z0.b, z0.d +# CHECK-NEXT: 2 5 1.00 cmpgt p0.b, p0/z, z1.b, z0.b +# CHECK-NEXT: 2 5 1.00 cmpgt p0.d, p0/z, z0.d, #-16 +# CHECK-NEXT: 2 5 1.00 cmpgt p0.d, p0/z, z0.d, #15 +# CHECK-NEXT: 2 5 1.00 cmpgt p0.d, p0/z, z0.d, z0.d +# CHECK-NEXT: 2 5 1.00 cmpgt p0.d, p0/z, z1.d, z0.d +# CHECK-NEXT: 2 5 1.00 cmpgt p0.h, p0/z, z0.h, #-16 +# CHECK-NEXT: 2 5 1.00 cmpgt p0.h, p0/z, z0.h, #15 +# CHECK-NEXT: 2 5 1.00 cmpgt p0.h, p0/z, z0.h, z0.d +# CHECK-NEXT: 2 5 1.00 cmpgt p0.h, p0/z, z0.h, z0.h +# CHECK-NEXT: 2 5 1.00 cmpgt p0.h, p0/z, z1.h, z0.h +# CHECK-NEXT: 2 5 1.00 cmpgt p0.s, p0/z, z0.s, #-16 +# CHECK-NEXT: 2 5 1.00 cmpgt p0.s, p0/z, z0.s, #15 +# CHECK-NEXT: 2 5 1.00 cmpgt p0.s, p0/z, z0.s, z0.d +# CHECK-NEXT: 2 5 1.00 cmpgt p0.s, p0/z, z0.s, z0.s +# CHECK-NEXT: 2 5 1.00 cmpgt p0.s, p0/z, z1.s, z0.s +# CHECK-NEXT: 2 5 1.00 cmphi p0.b, p0/z, z0.b, #0 +# CHECK-NEXT: 2 5 1.00 cmphi p0.b, p0/z, z0.b, #127 +# CHECK-NEXT: 2 5 1.00 cmphi p0.b, p0/z, z0.b, z0.b +# CHECK-NEXT: 2 5 1.00 cmphi p0.b, p0/z, z0.b, z0.d +# CHECK-NEXT: 2 5 1.00 cmphi p0.b, p0/z, z1.b, z0.b +# CHECK-NEXT: 2 5 1.00 cmphi p0.d, p0/z, z0.d, #0 +# CHECK-NEXT: 2 5 1.00 cmphi p0.d, p0/z, z0.d, #127 +# CHECK-NEXT: 2 5 1.00 cmphi p0.d, p0/z, z0.d, z0.d +# CHECK-NEXT: 2 5 1.00 cmphi p0.d, p0/z, z1.d, z0.d +# CHECK-NEXT: 2 5 1.00 cmphi p0.h, p0/z, z0.h, #0 +# CHECK-NEXT: 2 5 1.00 cmphi p0.h, p0/z, z0.h, #127 +# CHECK-NEXT: 2 5 1.00 cmphi p0.h, p0/z, z0.h, z0.d +# CHECK-NEXT: 2 5 1.00 cmphi p0.h, p0/z, z0.h, z0.h +# CHECK-NEXT: 2 5 1.00 cmphi p0.h, p0/z, z1.h, z0.h +# CHECK-NEXT: 2 5 1.00 cmphi p0.s, p0/z, z0.s, #0 +# CHECK-NEXT: 2 5 1.00 cmphi p0.s, p0/z, z0.s, #127 +# CHECK-NEXT: 2 5 1.00 cmphi p0.s, p0/z, z0.s, z0.d +# CHECK-NEXT: 2 5 1.00 cmphi p0.s, p0/z, z0.s, z0.s +# CHECK-NEXT: 2 5 1.00 cmphi p0.s, p0/z, z1.s, z0.s +# CHECK-NEXT: 2 5 1.00 cmphs p0.b, p0/z, z0.b, #0 +# CHECK-NEXT: 2 5 1.00 cmphs p0.b, p0/z, z0.b, #127 +# CHECK-NEXT: 2 5 1.00 cmphs p0.b, p0/z, z0.b, z0.b +# CHECK-NEXT: 2 5 1.00 cmphs p0.b, p0/z, z0.b, z0.d +# CHECK-NEXT: 2 5 1.00 cmphs p0.b, p0/z, z1.b, z0.b +# CHECK-NEXT: 2 5 1.00 cmphs p0.d, p0/z, z0.d, #0 +# CHECK-NEXT: 2 5 1.00 cmphs p0.d, p0/z, z0.d, #127 +# CHECK-NEXT: 2 5 1.00 cmphs p0.d, p0/z, z0.d, z0.d +# CHECK-NEXT: 2 5 1.00 cmphs p0.d, p0/z, z1.d, z0.d +# CHECK-NEXT: 2 5 1.00 cmphs p0.h, p0/z, z0.h, #0 +# CHECK-NEXT: 2 5 1.00 cmphs p0.h, p0/z, z0.h, #127 +# CHECK-NEXT: 2 5 1.00 cmphs p0.h, p0/z, z0.h, z0.d +# CHECK-NEXT: 2 5 1.00 cmphs p0.h, p0/z, z0.h, z0.h +# CHECK-NEXT: 2 5 1.00 cmphs p0.h, p0/z, z1.h, z0.h +# CHECK-NEXT: 2 5 1.00 cmphs p0.s, p0/z, z0.s, #0 +# CHECK-NEXT: 2 5 1.00 cmphs p0.s, p0/z, z0.s, #127 +# CHECK-NEXT: 2 5 1.00 cmphs p0.s, p0/z, z0.s, z0.d +# CHECK-NEXT: 2 5 1.00 cmphs p0.s, p0/z, z0.s, z0.s +# CHECK-NEXT: 2 5 1.00 cmphs p0.s, p0/z, z1.s, z0.s +# CHECK-NEXT: 2 5 1.00 cmple p0.b, p0/z, z0.b, #-16 +# CHECK-NEXT: 2 5 1.00 cmple p0.b, p0/z, z0.b, #15 +# CHECK-NEXT: 2 5 1.00 cmple p0.b, p0/z, z0.b, z0.d +# CHECK-NEXT: 2 5 1.00 cmple p0.d, p0/z, z0.d, #-16 +# CHECK-NEXT: 2 5 1.00 cmple p0.d, p0/z, z0.d, #15 +# CHECK-NEXT: 2 5 1.00 cmple p0.h, p0/z, z0.h, #-16 +# CHECK-NEXT: 2 5 1.00 cmple p0.h, p0/z, z0.h, #15 +# CHECK-NEXT: 2 5 1.00 cmple p0.h, p0/z, z0.h, z0.d +# CHECK-NEXT: 2 5 1.00 cmple p0.s, p0/z, z0.s, #-16 +# CHECK-NEXT: 2 5 1.00 cmple p0.s, p0/z, z0.s, #15 +# CHECK-NEXT: 2 5 1.00 cmple p0.s, p0/z, z0.s, z0.d +# CHECK-NEXT: 2 5 1.00 cmplo p0.b, p0/z, z0.b, #0 +# CHECK-NEXT: 2 5 1.00 cmplo p0.b, p0/z, z0.b, #127 +# CHECK-NEXT: 2 5 1.00 cmplo p0.b, p0/z, z0.b, z0.d +# CHECK-NEXT: 2 5 1.00 cmplo p0.d, p0/z, z0.d, #0 +# CHECK-NEXT: 2 5 1.00 cmplo p0.d, p0/z, z0.d, #127 +# CHECK-NEXT: 2 5 1.00 cmplo p0.h, p0/z, z0.h, #0 +# CHECK-NEXT: 2 5 1.00 cmplo p0.h, p0/z, z0.h, #127 +# CHECK-NEXT: 2 5 1.00 cmplo p0.h, p0/z, z0.h, z0.d +# CHECK-NEXT: 2 5 1.00 cmplo p0.s, p0/z, z0.s, #0 +# CHECK-NEXT: 2 5 1.00 cmplo p0.s, p0/z, z0.s, #127 +# CHECK-NEXT: 2 5 1.00 cmplo p0.s, p0/z, z0.s, z0.d +# CHECK-NEXT: 2 5 1.00 cmpls p0.b, p0/z, z0.b, #0 +# CHECK-NEXT: 2 5 1.00 cmpls p0.b, p0/z, z0.b, #127 +# CHECK-NEXT: 2 5 1.00 cmpls p0.b, p0/z, z0.b, z0.d +# CHECK-NEXT: 2 5 1.00 cmpls p0.d, p0/z, z0.d, #0 +# CHECK-NEXT: 2 5 1.00 cmpls p0.d, p0/z, z0.d, #127 +# CHECK-NEXT: 2 5 1.00 cmpls p0.h, p0/z, z0.h, #0 +# CHECK-NEXT: 2 5 1.00 cmpls p0.h, p0/z, z0.h, #127 +# CHECK-NEXT: 2 5 1.00 cmpls p0.h, p0/z, z0.h, z0.d +# CHECK-NEXT: 2 5 1.00 cmpls p0.s, p0/z, z0.s, #0 +# CHECK-NEXT: 2 5 1.00 cmpls p0.s, p0/z, z0.s, #127 +# CHECK-NEXT: 2 5 1.00 cmpls p0.s, p0/z, z0.s, z0.d +# CHECK-NEXT: 2 5 1.00 cmplt p0.b, p0/z, z0.b, #-16 +# CHECK-NEXT: 2 5 1.00 cmplt p0.b, p0/z, z0.b, #15 +# CHECK-NEXT: 2 5 1.00 cmplt p0.b, p0/z, z0.b, z0.d +# CHECK-NEXT: 2 5 1.00 cmplt p0.d, p0/z, z0.d, #-16 +# CHECK-NEXT: 2 5 1.00 cmplt p0.d, p0/z, z0.d, #15 +# CHECK-NEXT: 2 5 1.00 cmplt p0.h, p0/z, z0.h, #-16 +# CHECK-NEXT: 2 5 1.00 cmplt p0.h, p0/z, z0.h, #15 +# CHECK-NEXT: 2 5 1.00 cmplt p0.h, p0/z, z0.h, z0.d +# CHECK-NEXT: 2 5 1.00 cmplt p0.s, p0/z, z0.s, #-16 +# CHECK-NEXT: 2 5 1.00 cmplt p0.s, p0/z, z0.s, #15 +# CHECK-NEXT: 2 5 1.00 cmplt p0.s, p0/z, z0.s, z0.d +# CHECK-NEXT: 2 5 1.00 cmpne p0.b, p0/z, z0.b, #-16 +# CHECK-NEXT: 2 5 1.00 cmpne p0.b, p0/z, z0.b, #15 +# CHECK-NEXT: 2 5 1.00 cmpne p0.b, p0/z, z0.b, z0.b +# CHECK-NEXT: 2 5 1.00 cmpne p0.b, p0/z, z0.b, z0.d +# CHECK-NEXT: 2 5 1.00 cmpne p0.d, p0/z, z0.d, #-16 +# CHECK-NEXT: 2 5 1.00 cmpne p0.d, p0/z, z0.d, #15 +# CHECK-NEXT: 2 5 1.00 cmpne p0.d, p0/z, z0.d, z0.d +# CHECK-NEXT: 2 5 1.00 cmpne p0.h, p0/z, z0.h, #-16 +# CHECK-NEXT: 2 5 1.00 cmpne p0.h, p0/z, z0.h, #15 +# CHECK-NEXT: 2 5 1.00 cmpne p0.h, p0/z, z0.h, z0.d +# CHECK-NEXT: 2 5 1.00 cmpne p0.h, p0/z, z0.h, z0.h +# CHECK-NEXT: 2 5 1.00 cmpne p0.s, p0/z, z0.s, #-16 +# CHECK-NEXT: 2 5 1.00 cmpne p0.s, p0/z, z0.s, #15 +# CHECK-NEXT: 2 5 1.00 cmpne p0.s, p0/z, z0.s, z0.d +# CHECK-NEXT: 2 5 1.00 cmpne p0.s, p0/z, z0.s, z0.s +# CHECK-NEXT: 1 2 0.25 cnot z31.b, p7/m, z31.b +# CHECK-NEXT: 1 2 0.25 cnot z31.d, p7/m, z31.d +# CHECK-NEXT: 1 2 0.25 cnot z31.h, p7/m, z31.h +# CHECK-NEXT: 1 2 0.25 cnot z31.s, p7/m, z31.s +# CHECK-NEXT: 1 2 0.25 cnt z31.b, p7/m, z31.b +# CHECK-NEXT: 1 2 0.25 cnt z31.d, p7/m, z31.d +# CHECK-NEXT: 1 2 0.25 cnt z31.h, p7/m, z31.h +# CHECK-NEXT: 1 2 0.25 cnt z31.s, p7/m, z31.s +# CHECK-NEXT: 1 2 0.50 cntb x0 +# CHECK-NEXT: 1 2 0.50 cntb x0, #28 +# CHECK-NEXT: 1 2 0.50 cntb x0, all, mul #16 +# CHECK-NEXT: 1 2 0.50 cntb x0, pow2 +# CHECK-NEXT: 1 2 0.50 cntd x0 +# CHECK-NEXT: 1 2 0.50 cntd x0, #28 +# CHECK-NEXT: 1 2 0.50 cntd x0, all, mul #16 +# CHECK-NEXT: 1 2 0.50 cntd x0, pow2 +# CHECK-NEXT: 1 2 0.50 cnth x0 +# CHECK-NEXT: 1 2 0.50 cnth x0, #28 +# CHECK-NEXT: 1 2 0.50 cnth x0, all, mul #16 +# CHECK-NEXT: 1 2 0.50 cnth x0, pow2 +# CHECK-NEXT: 1 2 0.50 cntp x0, p15, p0.b +# CHECK-NEXT: 1 2 0.50 cntp x0, p15, p0.d +# CHECK-NEXT: 1 2 0.50 cntp x0, p15, p0.h +# CHECK-NEXT: 1 2 0.50 cntp x0, p15, p0.s +# CHECK-NEXT: 1 2 0.50 cntw x0 +# CHECK-NEXT: 1 2 0.50 cntw x0, #28 +# CHECK-NEXT: 1 2 0.50 cntw x0, all, mul #16 +# CHECK-NEXT: 1 2 0.50 cntw x0, pow2 +# CHECK-NEXT: 1 3 1.00 compact z31.d, p7, z31.d +# CHECK-NEXT: 1 3 1.00 compact z31.s, p7, z31.s +# CHECK-NEXT: 2 1 1.00 ctermeq w30, wzr +# CHECK-NEXT: 2 1 1.00 ctermeq wzr, w30 +# CHECK-NEXT: 2 1 1.00 ctermeq x30, xzr +# CHECK-NEXT: 2 1 1.00 ctermeq xzr, x30 +# CHECK-NEXT: 2 1 1.00 ctermne w30, wzr +# CHECK-NEXT: 2 1 1.00 ctermne wzr, w30 +# CHECK-NEXT: 2 1 1.00 ctermne x30, xzr +# CHECK-NEXT: 2 1 1.00 ctermne xzr, x30 +# CHECK-NEXT: 1 1 0.25 decb x0 +# CHECK-NEXT: 1 2 0.50 decb x0, #14 +# CHECK-NEXT: 1 2 0.50 decb x0, all, mul #16 +# CHECK-NEXT: 1 2 0.50 decb x0, pow2 +# CHECK-NEXT: 1 2 0.50 decb x0, vl1 +# CHECK-NEXT: 1 1 0.25 decd x0 +# CHECK-NEXT: 1 2 0.50 decd x0, #14 +# CHECK-NEXT: 1 2 0.50 decd x0, all, mul #16 +# CHECK-NEXT: 1 2 0.50 decd x0, pow2 +# CHECK-NEXT: 1 2 0.50 decd x0, vl1 +# CHECK-NEXT: 1 1 0.25 dech x0 +# CHECK-NEXT: 1 2 0.50 dech x0, #14 +# CHECK-NEXT: 1 2 0.50 dech x0, all, mul #16 +# CHECK-NEXT: 1 2 0.50 dech x0, pow2 +# CHECK-NEXT: 1 2 0.50 dech x0, vl1 +# CHECK-NEXT: 1 2 0.50 decp x0, p0.b +# CHECK-NEXT: 1 2 0.50 decp x0, p0.d +# CHECK-NEXT: 1 2 0.50 decp x0, p0.h +# CHECK-NEXT: 1 2 0.50 decp x0, p0.s +# CHECK-NEXT: 1 2 0.50 decp xzr, p15.b +# CHECK-NEXT: 1 2 0.50 decp xzr, p15.d +# CHECK-NEXT: 1 2 0.50 decp xzr, p15.h +# CHECK-NEXT: 1 2 0.50 decp xzr, p15.s +# CHECK-NEXT: 3 7 1.00 decp z31.d, p15.d +# CHECK-NEXT: 3 7 1.00 decp z31.h, p15.h +# CHECK-NEXT: 3 7 1.00 decp z31.s, p15.s +# CHECK-NEXT: 1 1 0.25 decw x0 +# CHECK-NEXT: 1 2 0.50 decw x0, #14 +# CHECK-NEXT: 1 2 0.50 decw x0, all, mul #16 +# CHECK-NEXT: 1 2 0.50 decw x0, pow2 +# CHECK-NEXT: 1 2 0.50 decw x0, vl1 +# CHECK-NEXT: 1 2 0.25 dupm z0.d, #0xfffffffffffffff9 +# CHECK-NEXT: 1 2 0.25 dupm z0.s, #0xfffffff9 +# CHECK-NEXT: 1 2 0.25 dupm z23.h, #0xfff9 +# CHECK-NEXT: 1 2 0.25 dupm z5.b, #0xf9 +# CHECK-NEXT: 1 2 1.00 eor p0.b, p0/z, p0.b, p1.b +# CHECK-NEXT: 1 2 0.25 eor z0.d, z0.d, #0x6 +# CHECK-NEXT: 1 2 0.25 eor z0.d, z0.d, #0xfffffffffffffff9 +# CHECK-NEXT: 1 2 0.25 eor z0.d, z0.d, z0.d +# CHECK-NEXT: 1 2 0.25 eor z0.s, z0.s, #0x6 +# CHECK-NEXT: 1 2 0.25 eor z0.s, z0.s, #0xfffffff9 +# CHECK-NEXT: 1 2 0.25 eor z23.d, z13.d, z8.d +# CHECK-NEXT: 1 2 0.25 eor z23.h, z23.h, #0x6 +# CHECK-NEXT: 1 2 0.25 eor z23.h, z23.h, #0xfff9 +# CHECK-NEXT: 1 2 0.25 eor z31.b, p7/m, z31.b, z31.b +# CHECK-NEXT: 1 2 0.25 eor z31.d, p7/m, z31.d, z31.d +# CHECK-NEXT: 1 2 0.25 eor z31.h, p7/m, z31.h, z31.h +# CHECK-NEXT: 1 2 0.25 eor z31.s, p7/m, z31.s, z31.s +# CHECK-NEXT: 1 2 0.25 eor z5.b, z5.b, #0x6 +# CHECK-NEXT: 1 2 0.25 eor z5.b, z5.b, #0xf9 +# CHECK-NEXT: 1 2 1.00 eor3 z29.d, z29.d, z30.d, z31.d +# CHECK-NEXT: 1 2 0.25 eorbt z0.b, z1.b, z31.b +# CHECK-NEXT: 1 2 0.25 eorbt z0.d, z1.d, z31.d +# CHECK-NEXT: 1 2 0.25 eorbt z0.h, z1.h, z31.h +# CHECK-NEXT: 1 2 0.25 eorbt z0.s, z1.s, z31.s +# CHECK-NEXT: 2 2 1.00 eors p0.b, p0/z, p0.b, p1.b +# CHECK-NEXT: 1 2 0.25 eortb z0.b, z1.b, z31.b +# CHECK-NEXT: 1 2 0.25 eortb z0.d, z1.d, z31.d +# CHECK-NEXT: 1 2 0.25 eortb z0.h, z1.h, z31.h +# CHECK-NEXT: 1 2 0.25 eortb z0.s, z1.s, z31.s +# CHECK-NEXT: 2 6 0.50 eorv b0, p7, z31.b +# CHECK-NEXT: 2 6 0.50 eorv d0, p7, z31.d +# CHECK-NEXT: 2 6 0.50 eorv h0, p7, z31.h +# CHECK-NEXT: 2 6 0.50 eorv s0, p7, z31.s +# CHECK-NEXT: 1 2 0.25 ext z0.b, { z1.b, z2.b }, #0 +# CHECK-NEXT: 1 2 0.25 ext z31.b, z31.b, z0.b, #0 +# CHECK-NEXT: 1 2 0.25 ext z31.b, z31.b, z0.b, #255 +# CHECK-NEXT: 1 2 0.25 ext z31.b, { z30.b, z31.b }, #255 +# CHECK-NEXT: 1 2 0.25 fabd z0.d, p7/m, z0.d, z31.d +# CHECK-NEXT: 1 2 0.25 fabd z0.h, p7/m, z0.h, z31.h +# CHECK-NEXT: 1 2 0.25 fabd z0.s, p7/m, z0.s, z31.s +# CHECK-NEXT: 1 2 0.25 fabs z31.d, p7/m, z31.d +# CHECK-NEXT: 1 2 0.25 fabs z31.h, p7/m, z31.h +# CHECK-NEXT: 1 2 0.25 fabs z31.s, p7/m, z31.s +# CHECK-NEXT: 1 2 1.00 facge p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: 1 2 1.00 facge p0.d, p0/z, z1.d, z0.d +# CHECK-NEXT: 1 2 1.00 facge p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: 1 2 1.00 facge p0.h, p0/z, z1.h, z0.h +# CHECK-NEXT: 1 2 1.00 facge p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: 1 2 1.00 facge p0.s, p0/z, z1.s, z0.s +# CHECK-NEXT: 1 2 1.00 facgt p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: 1 2 1.00 facgt p0.d, p0/z, z1.d, z0.d +# CHECK-NEXT: 1 2 1.00 facgt p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: 1 2 1.00 facgt p0.h, p0/z, z1.h, z0.h +# CHECK-NEXT: 1 2 1.00 facgt p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: 1 2 1.00 facgt p0.s, p0/z, z1.s, z0.s +# CHECK-NEXT: 1 2 0.25 fadd z0.d, p0/m, z0.d, #0.5 +# CHECK-NEXT: 1 2 0.25 fadd z0.d, p7/m, z0.d, z31.d +# CHECK-NEXT: 1 2 0.25 fadd z0.d, z1.d, z31.d +# CHECK-NEXT: 1 2 0.25 fadd z0.h, p0/m, z0.h, #0.5 +# CHECK-NEXT: 1 2 0.25 fadd z0.h, p7/m, z0.h, z31.h +# CHECK-NEXT: 1 2 0.25 fadd z0.h, z1.h, z31.h +# CHECK-NEXT: 1 2 0.25 fadd z0.s, p0/m, z0.s, #0.5 +# CHECK-NEXT: 1 2 0.25 fadd z0.s, p7/m, z0.s, z31.s +# CHECK-NEXT: 1 2 0.25 fadd z0.s, z1.s, z31.s +# CHECK-NEXT: 1 2 0.25 fadd z31.d, p7/m, z31.d, #1.0 +# CHECK-NEXT: 1 2 0.25 fadd z31.h, p7/m, z31.h, #1.0 +# CHECK-NEXT: 1 2 0.25 fadd z31.s, p7/m, z31.s, #1.0 +# CHECK-NEXT: 1 4 0.25 fadda d0, p7, d0, z31.d +# CHECK-NEXT: 1 10 9.00 fadda h0, p7, h0, z31.h +# CHECK-NEXT: 1 6 5.00 fadda s0, p7, s0, z31.s +# CHECK-NEXT: 1 2 0.25 faddp z0.h, p0/m, z0.h, z1.h +# CHECK-NEXT: 1 2 0.25 faddp z29.s, p3/m, z29.s, z30.s +# CHECK-NEXT: 1 2 0.25 faddp z31.d, p7/m, z31.d, z30.d +# CHECK-NEXT: 2 4 0.50 faddv d0, p7, z31.d +# CHECK-NEXT: 4 8 1.00 faddv h0, p7, z31.h +# CHECK-NEXT: 3 6 0.75 faddv s0, p7, z31.s +# CHECK-NEXT: 1 3 0.25 fcadd z0.d, p0/m, z0.d, z0.d, #90 +# CHECK-NEXT: 1 3 0.25 fcadd z0.h, p0/m, z0.h, z0.h, #90 +# CHECK-NEXT: 1 3 0.25 fcadd z0.s, p0/m, z0.s, z0.s, #90 +# CHECK-NEXT: 1 3 0.25 fcadd z31.d, p7/m, z31.d, z31.d, #270 +# CHECK-NEXT: 1 3 0.25 fcadd z31.h, p7/m, z31.h, z31.h, #270 +# CHECK-NEXT: 1 3 0.25 fcadd z31.s, p7/m, z31.s, z31.s, #270 +# CHECK-NEXT: 1 2 1.00 fcmeq p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmeq p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: 1 2 1.00 fcmeq p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmeq p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: 1 2 1.00 fcmeq p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmeq p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: 1 2 1.00 fcmge p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmge p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: 1 2 1.00 fcmge p0.d, p0/z, z1.d, z0.d +# CHECK-NEXT: 1 2 1.00 fcmge p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmge p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: 1 2 1.00 fcmge p0.h, p0/z, z1.h, z0.h +# CHECK-NEXT: 1 2 1.00 fcmge p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmge p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: 1 2 1.00 fcmge p0.s, p0/z, z1.s, z0.s +# CHECK-NEXT: 1 2 1.00 fcmgt p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmgt p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: 1 2 1.00 fcmgt p0.d, p0/z, z1.d, z0.d +# CHECK-NEXT: 1 2 1.00 fcmgt p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmgt p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: 1 2 1.00 fcmgt p0.h, p0/z, z1.h, z0.h +# CHECK-NEXT: 1 2 1.00 fcmgt p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmgt p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: 1 2 1.00 fcmgt p0.s, p0/z, z1.s, z0.s +# CHECK-NEXT: 1 5 0.25 fcmla z0.d, p0/m, z0.d, z0.d, #0 +# CHECK-NEXT: 1 5 0.25 fcmla z0.d, p0/m, z1.d, z2.d, #90 +# CHECK-NEXT: 1 5 0.25 fcmla z0.h, p0/m, z0.h, z0.h, #0 +# CHECK-NEXT: 1 5 0.25 fcmla z0.h, p0/m, z1.h, z2.h, #90 +# CHECK-NEXT: 1 5 0.25 fcmla z0.h, z0.h, z0.h[0], #0 +# CHECK-NEXT: 1 5 0.25 fcmla z0.s, p0/m, z0.s, z0.s, #0 +# CHECK-NEXT: 1 5 0.25 fcmla z0.s, p0/m, z1.s, z2.s, #90 +# CHECK-NEXT: 1 5 0.25 fcmla z21.s, z10.s, z5.s[1], #90 +# CHECK-NEXT: 1 5 0.25 fcmla z23.s, z13.s, z8.s[0], #270 +# CHECK-NEXT: 1 5 0.25 fcmla z29.d, p7/m, z30.d, z31.d, #180 +# CHECK-NEXT: 1 5 0.25 fcmla z29.h, p7/m, z30.h, z31.h, #180 +# CHECK-NEXT: 1 5 0.25 fcmla z29.s, p7/m, z30.s, z31.s, #180 +# CHECK-NEXT: 1 5 0.25 fcmla z31.d, p7/m, z31.d, z31.d, #270 +# CHECK-NEXT: 1 5 0.25 fcmla z31.h, p7/m, z31.h, z31.h, #270 +# CHECK-NEXT: 1 5 0.25 fcmla z31.h, z31.h, z7.h[3], #270 +# CHECK-NEXT: 1 5 0.25 fcmla z31.s, p7/m, z31.s, z31.s, #270 +# CHECK-NEXT: 1 2 1.00 fcmle p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmle p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmle p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmlt p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmlt p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmlt p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmne p0.d, p0/z, z0.d, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmne p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: 1 2 1.00 fcmne p0.h, p0/z, z0.h, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmne p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: 1 2 1.00 fcmne p0.s, p0/z, z0.s, #0.0 +# CHECK-NEXT: 1 2 1.00 fcmne p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: 1 2 1.00 fcmuo p0.d, p0/z, z0.d, z1.d +# CHECK-NEXT: 1 2 1.00 fcmuo p0.h, p0/z, z0.h, z1.h +# CHECK-NEXT: 1 2 1.00 fcmuo p0.s, p0/z, z0.s, z1.s +# CHECK-NEXT: 1 3 0.50 fcvt z0.d, p0/m, z0.h +# CHECK-NEXT: 1 3 0.50 fcvt z0.d, p0/m, z0.s +# CHECK-NEXT: 1 3 0.50 fcvt z0.h, p0/m, z0.d +# CHECK-NEXT: 2 4 1.00 fcvt z0.h, p0/m, z0.s +# CHECK-NEXT: 1 3 0.50 fcvt z0.s, p0/m, z0.d +# CHECK-NEXT: 2 4 1.00 fcvt z0.s, p0/m, z0.h +# CHECK-NEXT: 2 4 1.00 fcvtlt z0.s, p0/m, z1.h +# CHECK-NEXT: 1 3 0.50 fcvtlt z30.d, p7/m, z31.s +# CHECK-NEXT: 2 4 1.00 fcvtnt z0.h, p0/m, z1.s +# CHECK-NEXT: 1 3 0.50 fcvtnt z30.s, p7/m, z31.d +# CHECK-NEXT: 1 3 0.50 fcvtx z0.s, p0/m, z0.d +# CHECK-NEXT: 1 3 0.50 fcvtx z30.s, p7/m, z31.d +# CHECK-NEXT: 1 3 0.50 fcvtxnt z0.s, p0/m, z1.d +# CHECK-NEXT: 1 3 0.50 fcvtxnt z30.s, p7/m, z31.d +# CHECK-NEXT: 1 3 0.50 fcvtzs z0.d, p0/m, z0.d +# CHECK-NEXT: 1 3 0.50 fcvtzs z0.d, p0/m, z0.h +# CHECK-NEXT: 1 3 0.50 fcvtzs z0.d, p0/m, z0.s +# CHECK-NEXT: 4 6 2.00 fcvtzs z0.h, p0/m, z0.h +# CHECK-NEXT: 1 3 0.50 fcvtzs z0.s, p0/m, z0.d +# CHECK-NEXT: 2 4 1.00 fcvtzs z0.s, p0/m, z0.h +# CHECK-NEXT: 2 4 1.00 fcvtzs z0.s, p0/m, z0.s +# CHECK-NEXT: 1 3 0.50 fcvtzu z0.d, p0/m, z0.d +# CHECK-NEXT: 1 3 0.50 fcvtzu z0.d, p0/m, z0.h +# CHECK-NEXT: 1 3 0.50 fcvtzu z0.d, p0/m, z0.s +# CHECK-NEXT: 4 6 2.00 fcvtzu z0.h, p0/m, z0.h +# CHECK-NEXT: 1 3 0.50 fcvtzu z0.s, p0/m, z0.d +# CHECK-NEXT: 2 4 1.00 fcvtzu z0.s, p0/m, z0.h +# CHECK-NEXT: 2 4 1.00 fcvtzu z0.s, p0/m, z0.s +# CHECK-NEXT: 1 15 7.00 fdiv z0.d, p7/m, z0.d, z31.d +# CHECK-NEXT: 1 13 6.00 fdiv z0.h, p7/m, z0.h, z31.h +# CHECK-NEXT: 1 10 4.50 fdiv z0.s, p7/m, z0.s, z31.s +# CHECK-NEXT: 1 15 7.00 fdivr z0.d, p7/m, z0.d, z31.d +# CHECK-NEXT: 1 13 6.00 fdivr z0.h, p7/m, z0.h, z31.h +# CHECK-NEXT: 1 10 4.50 fdivr z0.s, p7/m, z0.s, z31.s +# CHECK-NEXT: 1 3 1.00 fexpa z0.d, z31.d +# CHECK-NEXT: 1 3 1.00 fexpa z0.h, z31.h +# CHECK-NEXT: 1 3 1.00 fexpa z0.s, z31.s +# CHECK-NEXT: 1 3 0.50 flogb z31.d, p7/m, z31.d +# CHECK-NEXT: 4 6 2.00 flogb z31.h, p7/m, z31.h +# CHECK-NEXT: 2 4 1.00 flogb z31.s, p7/m, z31.s +# CHECK-NEXT: 1 4 0.25 fmad z0.d, p7/m, z1.d, z31.d +# CHECK-NEXT: 1 4 0.25 fmad z0.h, p7/m, z1.h, z31.h +# CHECK-NEXT: 1 4 0.25 fmad z0.s, p7/m, z1.s, z31.s +# CHECK-NEXT: 1 2 0.25 fmax z0.d, p0/m, z0.d, #0.0 +# CHECK-NEXT: 1 2 0.25 fmax z0.d, p7/m, z0.d, z31.d +# CHECK-NEXT: 1 2 0.25 fmax z0.h, p0/m, z0.h, #0.0 +# CHECK-NEXT: 1 2 0.25 fmax z0.h, p7/m, z0.h, z31.h +# CHECK-NEXT: 1 2 0.25 fmax z0.s, p0/m, z0.s, #0.0 +# CHECK-NEXT: 1 2 0.25 fmax z0.s, p7/m, z0.s, z31.s +# CHECK-NEXT: 1 2 0.25 fmax z31.d, p7/m, z31.d, #1.0 +# CHECK-NEXT: 1 2 0.25 fmax z31.h, p7/m, z31.h, #1.0 +# CHECK-NEXT: 1 2 0.25 fmax z31.s, p7/m, z31.s, #1.0 +# CHECK-NEXT: 1 2 0.25 fmaxnm z0.d, p0/m, z0.d, #0.0 +# CHECK-NEXT: 1 2 0.25 fmaxnm z0.d, p7/m, z0.d, z31.d +# CHECK-NEXT: 1 2 0.25 fmaxnm z0.h, p0/m, z0.h, #0.0 +# CHECK-NEXT: 1 2 0.25 fmaxnm z0.h, p7/m, z0.h, z31.h +# CHECK-NEXT: 1 2 0.25 fmaxnm z0.s, p0/m, z0.s, #0.0 +# CHECK-NEXT: 1 2 0.25 fmaxnm z0.s, p7/m, z0.s, z31.s +# CHECK-NEXT: 1 2 0.25 fmaxnm z31.d, p7/m, z31.d, #1.0 +# CHECK-NEXT: 1 2 0.25 fmaxnm z31.h, p7/m, z31.h, #1.0 +# CHECK-NEXT: 1 2 0.25 fmaxnm z31.s, p7/m, z31.s, #1.0 +# CHECK-NEXT: 1 2 0.25 fmaxnmp z0.h, p0/m, z0.h, z1.h +# CHECK-NEXT: 1 2 0.25 fmaxnmp z29.s, p3/m, z29.s, z30.s +# CHECK-NEXT: 1 2 0.25 fmaxnmp z31.d, p7/m, z31.d, z30.d +# CHECK-NEXT: 2 4 0.50 fmaxnmv d0, p7, z31.d +# CHECK-NEXT: 4 8 1.00 fmaxnmv h0, p7, z31.h +# CHECK-NEXT: 3 6 0.75 fmaxnmv s0, p7, z31.s +# CHECK-NEXT: 1 2 0.25 fmaxp z0.h, p0/m, z0.h, z1.h +# CHECK-NEXT: 1 2 0.25 fmaxp z29.s, p3/m, z29.s, z30.s +# CHECK-NEXT: 1 2 0.25 fmaxp z31.d, p7/m, z31.d, z30.d +# CHECK-NEXT: 2 4 0.50 fmaxv d0, p7, z31.d +# CHECK-NEXT: 4 8 1.00 fmaxv h0, p7, z31.h +# CHECK-NEXT: 3 6 0.75 fmaxv s0, p7, z31.s +# CHECK-NEXT: 1 2 0.25 fmin z0.d, p0/m, z0.d, #0.0 +# CHECK-NEXT: 1 2 0.25 fmin z0.d, p7/m, z0.d, z31.d +# CHECK-NEXT: 1 2 0.25 fmin z0.h, p0/m, z0.h, #0.0 +# CHECK-NEXT: 1 2 0.25 fmin z0.h, p7/m, z0.h, z31.h +# CHECK-NEXT: 1 2 0.25 fmin z0.s, p0/m, z0.s, #0.0 +# CHECK-NEXT: 1 2 0.25 fmin z0.s, p7/m, z0.s, z31.s +# CHECK-NEXT: 1 2 0.25 fmin z31.d, p7/m, z31.d, #1.0 +# CHECK-NEXT: 1 2 0.25 fmin z31.h, p7/m, z31.h, #1.0 +# CHECK-NEXT: 1 2 0.25 fmin z31.s, p7/m, z31.s, #1.0 +# CHECK-NEXT: 1 2 0.25 fminnm z0.d, p0/m, z0.d, #0.0 +# CHECK-NEXT: 1 2 0.25 fminnm z0.d, p7/m, z0.d, z31.d +# CHECK-NEXT: 1 2 0.25 fminnm z0.h, p0/m, z0.h, #0.0 +# CHECK-NEXT: 1 2 0.25 fminnm z0.h, p7/m, z0.h, z31.h +# CHECK-NEXT: 1 2 0.25 fminnm z0.s, p0/m, z0.s, #0.0 +# CHECK-NEXT: 1 2 0.25 fminnm z0.s, p7/m, z0.s, z31.s +# CHECK-NEXT: 1 2 0.25 fminnm z31.d, p7/m, z31.d, #1.0 +# CHECK-NEXT: 1 2 0.25 fminnm z31.h, p7/m, z31.h, #1.0 +# CHECK-NEXT: 1 2 0.25 fminnm z31.s, p7/m, z31.s, #1.0 +# CHECK-NEXT: 1 2 0.25 fminnmp z0.h, p0/m, z0.h, z1.h +# CHECK-NEXT: 1 2 0.25 fminnmp z29.s, p3/m, z29.s, z30.s +# CHECK-NEXT: 1 2 0.25 fminnmp z31.d, p7/m, z31.d, z30.d +# CHECK-NEXT: 2 4 0.50 fminnmv d0, p7, z31.d +# CHECK-NEXT: 4 8 1.00 fminnmv h0, p7, z31.h +# CHECK-NEXT: 3 6 0.75 fminnmv s0, p7, z31.s +# CHECK-NEXT: 1 2 0.25 fminp z0.h, p0/m, z0.h, z1.h +# CHECK-NEXT: 1 2 0.25 fminp z29.s, p3/m, z29.s, z30.s +# CHECK-NEXT: 1 2 0.25 fminp z31.d, p7/m, z31.d, z30.d +# CHECK-NEXT: 2 4 0.50 fminv d0, p7, z31.d +# CHECK-NEXT: 4 8 1.00 fminv h0, p7, z31.h +# CHECK-NEXT: 3 6 0.75 fminv s0, p7, z31.s +# CHECK-NEXT: 1 4 0.25 fmla z0.d, p7/m, z1.d, z31.d +# CHECK-NEXT: 1 4 0.25 fmla z0.d, z1.d, z7.d[1] +# CHECK-NEXT: 1 4 0.25 fmla z0.h, p7/m, z1.h, z31.h +# CHECK-NEXT: 1 4 0.25 fmla z0.h, z1.h, z7.h[7] +# CHECK-NEXT: 1 4 0.25 fmla z0.s, p7/m, z1.s, z31.s +# CHECK-NEXT: 1 4 0.25 fmla z0.s, z1.s, z7.s[3] +# CHECK-NEXT: 1 4 0.25 fmlalb z0.s, z1.h, z7.h[0] +# CHECK-NEXT: 1 4 0.25 fmlalb z29.s, z30.h, z31.h +# CHECK-NEXT: 1 4 0.25 fmlalb z30.s, z31.h, z7.h[7] +# CHECK-NEXT: 1 4 0.25 fmlalt z0.s, z1.h, z7.h[0] +# CHECK-NEXT: 1 4 0.25 fmlalt z29.s, z30.h, z31.h +# CHECK-NEXT: 1 4 0.25 fmlalt z30.s, z31.h, z7.h[7] +# CHECK-NEXT: 1 4 0.25 fmls z0.d, p7/m, z1.d, z31.d +# CHECK-NEXT: 1 4 0.25 fmls z0.d, z1.d, z7.d[1] +# CHECK-NEXT: 1 4 0.25 fmls z0.h, p7/m, z1.h, z31.h +# CHECK-NEXT: 1 4 0.25 fmls z0.h, z1.h, z7.h[7] +# CHECK-NEXT: 1 4 0.25 fmls z0.s, p7/m, z1.s, z31.s +# CHECK-NEXT: 1 4 0.25 fmls z0.s, z1.s, z7.s[3] +# CHECK-NEXT: 1 4 0.25 fmlslb z0.s, z1.h, z7.h[0] +# CHECK-NEXT: 1 4 0.25 fmlslb z29.s, z30.h, z31.h +# CHECK-NEXT: 1 4 0.25 fmlslb z30.s, z31.h, z7.h[7] +# CHECK-NEXT: 1 4 0.25 fmlslt z0.s, z1.h, z7.h[0] +# CHECK-NEXT: 1 4 0.25 fmlslt z29.s, z30.h, z31.h +# CHECK-NEXT: 1 4 0.25 fmlslt z30.s, z31.h, z7.h[7] +# CHECK-NEXT: 1 2 0.25 fmov z0.d, #-10.00000000 +# CHECK-NEXT: 1 2 0.25 fmov z0.d, #0.12500000 +# CHECK-NEXT: 1 2 0.25 fmov z0.d, p0/m, #-10.00000000 +# CHECK-NEXT: 1 2 0.25 fmov z0.d, p0/m, #0.12500000 +# CHECK-NEXT: 1 2 0.25 fmov z0.h, #-0.12500000 +# CHECK-NEXT: 1 2 0.25 fmov z0.h, p0/m, #-0.12500000 +# CHECK-NEXT: 1 2 0.25 fmov z0.s, #-0.12500000 +# CHECK-NEXT: 1 2 0.25 fmov z0.s, p0/m, #-0.12500000 +# CHECK-NEXT: 1 4 0.25 fmsb z0.d, p7/m, z1.d, z31.d +# CHECK-NEXT: 1 4 0.25 fmsb z0.h, p7/m, z1.h, z31.h +# CHECK-NEXT: 1 4 0.25 fmsb z0.s, p7/m, z1.s, z31.s +# CHECK-NEXT: 1 3 0.25 fmul z0.d, p0/m, z0.d, #0.5 +# CHECK-NEXT: 1 3 0.25 fmul z0.d, p7/m, z0.d, z31.d +# CHECK-NEXT: 1 3 0.25 fmul z0.d, z0.d, z0.d[0] +# CHECK-NEXT: 1 3 0.25 fmul z0.d, z1.d, z31.d +# CHECK-NEXT: 1 3 0.25 fmul z0.h, p0/m, z0.h, #0.5 +# CHECK-NEXT: 1 3 0.25 fmul z0.h, p7/m, z0.h, z31.h +# CHECK-NEXT: 1 3 0.25 fmul z0.h, z0.h, z0.h[0] +# CHECK-NEXT: 1 3 0.25 fmul z0.h, z1.h, z31.h +# CHECK-NEXT: 1 3 0.25 fmul z0.s, p0/m, z0.s, #0.5 +# CHECK-NEXT: 1 3 0.25 fmul z0.s, p7/m, z0.s, z31.s +# CHECK-NEXT: 1 3 0.25 fmul z0.s, z0.s, z0.s[0] +# CHECK-NEXT: 1 3 0.25 fmul z0.s, z1.s, z31.s +# CHECK-NEXT: 1 3 0.25 fmul z31.d, p7/m, z31.d, #2.0 +# CHECK-NEXT: 1 3 0.25 fmul z31.d, z31.d, z15.d[1] +# CHECK-NEXT: 1 3 0.25 fmul z31.h, p7/m, z31.h, #2.0 +# CHECK-NEXT: 1 3 0.25 fmul z31.h, z31.h, z7.h[7] +# CHECK-NEXT: 1 3 0.25 fmul z31.s, p7/m, z31.s, #2.0 +# CHECK-NEXT: 1 3 0.25 fmul z31.s, z31.s, z7.s[3] +# CHECK-NEXT: 1 3 0.25 fmulx z0.d, p7/m, z0.d, z31.d +# CHECK-NEXT: 1 3 0.25 fmulx z0.h, p7/m, z0.h, z31.h +# CHECK-NEXT: 1 3 0.25 fmulx z0.s, p7/m, z0.s, z31.s +# CHECK-NEXT: 1 2 0.25 fneg z31.d, p7/m, z31.d +# CHECK-NEXT: 1 2 0.25 fneg z31.h, p7/m, z31.h +# CHECK-NEXT: 1 2 0.25 fneg z31.s, p7/m, z31.s +# CHECK-NEXT: 1 4 0.25 fnmad z0.d, p7/m, z1.d, z31.d +# CHECK-NEXT: 1 4 0.25 fnmad z0.h, p7/m, z1.h, z31.h +# CHECK-NEXT: 1 4 0.25 fnmad z0.s, p7/m, z1.s, z31.s +# CHECK-NEXT: 1 4 0.25 fnmla z0.d, p7/m, z1.d, z31.d +# CHECK-NEXT: 1 4 0.25 fnmla z0.h, p7/m, z1.h, z31.h +# CHECK-NEXT: 1 4 0.25 fnmla z0.s, p7/m, z1.s, z31.s +# CHECK-NEXT: 1 4 0.25 fnmls z0.d, p7/m, z1.d, z31.d +# CHECK-NEXT: 1 4 0.25 fnmls z0.h, p7/m, z1.h, z31.h +# CHECK-NEXT: 1 4 0.25 fnmls z0.s, p7/m, z1.s, z31.s +# CHECK-NEXT: 1 4 0.25 fnmsb z0.d, p7/m, z1.d, z31.d +# CHECK-NEXT: 1 4 0.25 fnmsb z0.h, p7/m, z1.h, z31.h +# CHECK-NEXT: 1 4 0.25 fnmsb z0.s, p7/m, z1.s, z31.s +# CHECK-NEXT: 1 3 0.50 frecpe z0.d, z31.d +# CHECK-NEXT: 4 6 2.00 frecpe z0.h, z31.h +# CHECK-NEXT: 2 4 1.00 frecpe z0.s, z31.s +# CHECK-NEXT: 1 4 0.25 frecps z0.d, z1.d, z31.d +# CHECK-NEXT: 1 4 0.25 frecps z0.h, z1.h, z31.h +# CHECK-NEXT: 1 4 0.25 frecps z0.s, z1.s, z31.s +# CHECK-NEXT: 1 3 0.50 frecpx z31.d, p7/m, z31.d +# CHECK-NEXT: 4 6 2.00 frecpx z31.h, p7/m, z31.h +# CHECK-NEXT: 2 4 1.00 frecpx z31.s, p7/m, z31.s +# CHECK-NEXT: 1 3 0.50 frinta z31.d, p7/m, z31.d +# CHECK-NEXT: 4 6 2.00 frinta z31.h, p7/m, z31.h +# CHECK-NEXT: 2 4 1.00 frinta z31.s, p7/m, z31.s +# CHECK-NEXT: 1 3 0.50 frinti z31.d, p7/m, z31.d +# CHECK-NEXT: 4 6 2.00 frinti z31.h, p7/m, z31.h +# CHECK-NEXT: 2 4 1.00 frinti z31.s, p7/m, z31.s +# CHECK-NEXT: 1 3 0.50 frintm z31.d, p7/m, z31.d +# CHECK-NEXT: 4 6 2.00 frintm z31.h, p7/m, z31.h +# CHECK-NEXT: 2 4 1.00 frintm z31.s, p7/m, z31.s +# CHECK-NEXT: 1 3 0.50 frintn z31.d, p7/m, z31.d +# CHECK-NEXT: 4 6 2.00 frintn z31.h, p7/m, z31.h +# CHECK-NEXT: 2 4 1.00 frintn z31.s, p7/m, z31.s +# CHECK-NEXT: 1 3 0.50 frintp z31.d, p7/m, z31.d +# CHECK-NEXT: 4 6 2.00 frintp z31.h, p7/m, z31.h +# CHECK-NEXT: 2 4 1.00 frintp z31.s, p7/m, z31.s +# CHECK-NEXT: 1 3 0.50 frintx z31.d, p7/m, z31.d +# CHECK-NEXT: 4 6 2.00 frintx z31.h, p7/m, z31.h +# CHECK-NEXT: 2 4 1.00 frintx z31.s, p7/m, z31.s +# CHECK-NEXT: 1 3 0.50 frintz z31.d, p7/m, z31.d +# CHECK-NEXT: 4 6 2.00 frintz z31.h, p7/m, z31.h +# CHECK-NEXT: 2 4 1.00 frintz z31.s, p7/m, z31.s +# CHECK-NEXT: 1 3 0.50 frsqrte z0.d, z31.d +# CHECK-NEXT: 4 6 2.00 frsqrte z0.h, z31.h +# CHECK-NEXT: 2 4 1.00 frsqrte z0.s, z31.s +# CHECK-NEXT: 1 4 0.25 frsqrts z0.d, z1.d, z31.d +# CHECK-NEXT: 1 4 0.25 frsqrts z0.h, z1.h, z31.h +# CHECK-NEXT: 1 4 0.25 frsqrts z0.s, z1.s, z31.s +# CHECK-NEXT: 1 3 0.25 fscale z0.d, p7/m, z0.d, z31.d +# CHECK-NEXT: 1 3 0.25 fscale z0.h, p7/m, z0.h, z31.h +# CHECK-NEXT: 1 3 0.25 fscale z0.s, p7/m, z0.s, z31.s +# CHECK-NEXT: 1 16 14.00 fsqrt z31.d, p7/m, z31.d +# CHECK-NEXT: 1 13 12.00 fsqrt z31.h, p7/m, z31.h +# CHECK-NEXT: 1 10 9.00 fsqrt z31.s, p7/m, z31.s +# CHECK-NEXT: 1 2 0.25 fsub z0.d, p0/m, z0.d, #0.5 +# CHECK-NEXT: 1 2 0.25 fsub z0.d, p7/m, z0.d, z31.d +# CHECK-NEXT: 1 2 0.25 fsub z0.d, z1.d, z31.d +# CHECK-NEXT: 1 2 0.25 fsub z0.h, p0/m, z0.h, #0.5 +# CHECK-NEXT: 1 2 0.25 fsub z0.h, p7/m, z0.h, z31.h +# CHECK-NEXT: 1 2 0.25 fsub z0.h, z1.h, z31.h +# CHECK-NEXT: 1 2 0.25 fsub z0.s, p0/m, z0.s, #0.5 +# CHECK-NEXT: 1 2 0.25 fsub z0.s, p7/m, z0.s, z31.s +# CHECK-NEXT: 1 2 0.25 fsub z0.s, z1.s, z31.s +# CHECK-NEXT: 1 2 0.25 fsub z31.d, p7/m, z31.d, #1.0 +# CHECK-NEXT: 1 2 0.25 fsub z31.h, p7/m, z31.h, #1.0 +# CHECK-NEXT: 1 2 0.25 fsub z31.s, p7/m, z31.s, #1.0 +# CHECK-NEXT: 1 2 0.25 fsubr z0.d, p0/m, z0.d, #0.5 +# CHECK-NEXT: 1 2 0.25 fsubr z0.d, p7/m, z0.d, z31.d +# CHECK-NEXT: 1 2 0.25 fsubr z0.h, p0/m, z0.h, #0.5 +# CHECK-NEXT: 1 2 0.25 fsubr z0.h, p7/m, z0.h, z31.h +# CHECK-NEXT: 1 2 0.25 fsubr z0.s, p0/m, z0.s, #0.5 +# CHECK-NEXT: 1 2 0.25 fsubr z0.s, p7/m, z0.s, z31.s +# CHECK-NEXT: 1 2 0.25 fsubr z31.d, p7/m, z31.d, #1.0 +# CHECK-NEXT: 1 2 0.25 fsubr z31.h, p7/m, z31.h, #1.0 +# CHECK-NEXT: 1 2 0.25 fsubr z31.s, p7/m, z31.s, #1.0 +# CHECK-NEXT: 1 4 0.25 ftmad z0.d, z0.d, z31.d, #7 +# CHECK-NEXT: 1 4 0.25 ftmad z0.h, z0.h, z31.h, #7 +# CHECK-NEXT: 1 4 0.25 ftmad z0.s, z0.s, z31.s, #7 +# CHECK-NEXT: 1 3 0.25 ftsmul z0.d, z1.d, z31.d +# CHECK-NEXT: 1 3 0.25 ftsmul z0.h, z1.h, z31.h +# CHECK-NEXT: 1 3 0.25 ftsmul z0.s, z1.s, z31.s +# CHECK-NEXT: 1 3 0.25 ftssel z0.d, z1.d, z31.d +# CHECK-NEXT: 1 3 0.25 ftssel z0.h, z1.h, z31.h +# CHECK-NEXT: 1 3 0.25 ftssel z0.s, z1.s, z31.s +# CHECK-NEXT: 1 2 0.25 histcnt z0.s, p0/z, z1.s, z2.s +# CHECK-NEXT: 1 2 0.25 histcnt z29.d, p7/z, z30.d, z31.d +# CHECK-NEXT: 1 2 0.25 histseg z0.b, z1.b, z31.b +# CHECK-NEXT: 1 1 0.25 incb x0 +# CHECK-NEXT: 1 2 0.50 incb x0, #14 +# CHECK-NEXT: 1 2 0.50 incb x0, all, mul #16 +# CHECK-NEXT: 1 2 0.50 incb x0, pow2 +# CHECK-NEXT: 1 2 0.50 incb x0, vl1 +# CHECK-NEXT: 1 1 0.25 incd x0 +# CHECK-NEXT: 1 2 0.50 incd x0, #14 +# CHECK-NEXT: 1 2 0.50 incd x0, all, mul #16 +# CHECK-NEXT: 1 2 0.50 incd x0, pow2 +# CHECK-NEXT: 1 2 0.50 incd x0, vl1 +# CHECK-NEXT: 1 2 0.25 incd z0.d +# CHECK-NEXT: 1 2 0.25 incd z0.d, all, mul #16 +# CHECK-NEXT: 1 1 0.25 inch x0 +# CHECK-NEXT: 1 2 0.50 inch x0, #14 +# CHECK-NEXT: 1 2 0.50 inch x0, all, mul #16 +# CHECK-NEXT: 1 2 0.50 inch x0, pow2 +# CHECK-NEXT: 1 2 0.50 inch x0, vl1 +# CHECK-NEXT: 1 2 0.25 inch z0.h +# CHECK-NEXT: 1 2 0.25 inch z0.h, all, mul #16 +# CHECK-NEXT: 1 2 0.50 incp x0, p0.b +# CHECK-NEXT: 1 2 0.50 incp x0, p0.d +# CHECK-NEXT: 1 2 0.50 incp x0, p0.h +# CHECK-NEXT: 1 2 0.50 incp x0, p0.s +# CHECK-NEXT: 1 2 0.50 incp xzr, p15.b +# CHECK-NEXT: 1 2 0.50 incp xzr, p15.d +# CHECK-NEXT: 1 2 0.50 incp xzr, p15.h +# CHECK-NEXT: 1 2 0.50 incp xzr, p15.s +# CHECK-NEXT: 3 7 1.00 incp z31.d, p15.d +# CHECK-NEXT: 3 7 1.00 incp z31.h, p15.h +# CHECK-NEXT: 3 7 1.00 incp z31.s, p15.s +# CHECK-NEXT: 1 1 0.25 incw x0 +# CHECK-NEXT: 1 2 0.50 incw x0, #14 +# CHECK-NEXT: 1 2 0.50 incw x0, all, mul #16 +# CHECK-NEXT: 1 2 0.50 incw x0, pow2 +# CHECK-NEXT: 1 2 0.50 incw x0, vl1 +# CHECK-NEXT: 1 2 0.25 incw z0.s +# CHECK-NEXT: 1 2 0.25 incw z0.s, all, mul #16 +# CHECK-NEXT: 1 4 0.50 index z0.b, #0, #0 +# CHECK-NEXT: 2 5 1.00 index z0.d, #0, #0 +# CHECK-NEXT: 1 4 0.50 index z0.h, #0, #0 +# CHECK-NEXT: 2 7 1.00 index z0.h, w0, w0 +# CHECK-NEXT: 1 4 0.50 index z0.s, #0, #0 +# CHECK-NEXT: 2 7 1.00 index z21.b, w10, w21 +# CHECK-NEXT: 4 8 2.00 index z21.d, x10, x21 +# CHECK-NEXT: 2 7 1.00 index z21.s, w10, w21 +# CHECK-NEXT: 2 7 1.00 index z23.b, #13, w8 +# CHECK-NEXT: 2 7 1.00 index z23.b, w13, #8 +# CHECK-NEXT: 4 8 2.00 index z23.d, #13, x8 +# CHECK-NEXT: 4 8 2.00 index z23.d, x13, #8 +# CHECK-NEXT: 2 7 1.00 index z23.h, #13, w8 +# CHECK-NEXT: 2 7 1.00 index z23.h, w13, #8 +# CHECK-NEXT: 2 7 1.00 index z23.s, #13, w8 +# CHECK-NEXT: 2 7 1.00 index z23.s, w13, #8 +# CHECK-NEXT: 1 4 0.50 index z31.b, #-1, #-1 +# CHECK-NEXT: 2 7 1.00 index z31.b, #-1, wzr +# CHECK-NEXT: 2 7 1.00 index z31.b, wzr, #-1 +# CHECK-NEXT: 2 7 1.00 index z31.b, wzr, wzr +# CHECK-NEXT: 2 5 1.00 index z31.d, #-1, #-1 +# CHECK-NEXT: 4 8 2.00 index z31.d, #-1, xzr +# CHECK-NEXT: 4 8 2.00 index z31.d, xzr, #-1 +# CHECK-NEXT: 4 8 2.00 index z31.d, xzr, xzr +# CHECK-NEXT: 1 4 0.50 index z31.h, #-1, #-1 +# CHECK-NEXT: 2 7 1.00 index z31.h, #-1, wzr +# CHECK-NEXT: 2 7 1.00 index z31.h, wzr, #-1 +# CHECK-NEXT: 2 7 1.00 index z31.h, wzr, wzr +# CHECK-NEXT: 1 4 0.50 index z31.s, #-1, #-1 +# CHECK-NEXT: 2 7 1.00 index z31.s, #-1, wzr +# CHECK-NEXT: 2 7 1.00 index z31.s, wzr, #-1 +# CHECK-NEXT: 2 7 1.00 index z31.s, wzr, wzr +# CHECK-NEXT: 2 6 1.00 insr z0.b, w0 +# CHECK-NEXT: 2 6 1.00 insr z0.d, x0 +# CHECK-NEXT: 2 6 1.00 insr z0.h, w0 +# CHECK-NEXT: 2 6 1.00 insr z0.s, w0 +# CHECK-NEXT: 1 3 1.00 insr z31.b, b31 +# CHECK-NEXT: 2 6 1.00 insr z31.b, wzr +# CHECK-NEXT: 1 3 1.00 insr z31.d, d31 +# CHECK-NEXT: 2 6 1.00 insr z31.d, xzr +# CHECK-NEXT: 1 3 1.00 insr z31.h, h31 +# CHECK-NEXT: 2 6 1.00 insr z31.h, wzr +# CHECK-NEXT: 1 3 1.00 insr z31.s, s31 +# CHECK-NEXT: 2 6 1.00 insr z31.s, wzr +# CHECK-NEXT: 1 3 1.00 lasta b0, p7, z31.b +# CHECK-NEXT: 1 3 1.00 lasta d0, p7, z31.d +# CHECK-NEXT: 1 3 1.00 lasta h0, p7, z31.h +# CHECK-NEXT: 1 3 1.00 lasta s0, p7, z31.s +# CHECK-NEXT: 2 6 1.00 lasta w0, p7, z31.b +# CHECK-NEXT: 2 6 1.00 lasta w0, p7, z31.h +# CHECK-NEXT: 2 6 1.00 lasta w0, p7, z31.s +# CHECK-NEXT: 2 6 1.00 lasta x0, p7, z31.d +# CHECK-NEXT: 1 3 1.00 lastb b0, p7, z31.b +# CHECK-NEXT: 1 3 1.00 lastb d0, p7, z31.d +# CHECK-NEXT: 1 3 1.00 lastb h0, p7, z31.h +# CHECK-NEXT: 1 3 1.00 lastb s0, p7, z31.s +# CHECK-NEXT: 2 6 1.00 lastb w0, p7, z31.b +# CHECK-NEXT: 2 6 1.00 lastb w0, p7, z31.h +# CHECK-NEXT: 2 6 1.00 lastb w0, p7, z31.s +# CHECK-NEXT: 2 6 1.00 lastb x0, p7, z31.d +# CHECK-NEXT: 1 6 0.33 * ld1b { z0.b }, p0/z, [sp, x0] +# CHECK-NEXT: 1 6 0.33 * ld1b { z0.b }, p0/z, [x0, x0] +# CHECK-NEXT: 1 6 0.33 * ld1b { z0.b }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1b { z0.d }, p0/z, [x0] +# CHECK-NEXT: 5 9 1.00 * ld1b { z0.d }, p0/z, [z0.d] +# CHECK-NEXT: 1 6 0.33 * ld1b { z0.h }, p0/z, [x0] +# CHECK-NEXT: 5 9 1.00 * ld1b { z0.s }, p0/z, [x0, z0.s, sxtw] +# CHECK-NEXT: 5 9 1.00 * ld1b { z0.s }, p0/z, [x0, z0.s, uxtw] +# CHECK-NEXT: 1 6 0.33 * ld1b { z0.s }, p0/z, [x0] +# CHECK-NEXT: 5 9 1.00 * ld1b { z0.s }, p0/z, [z0.s] +# CHECK-NEXT: 1 6 0.33 * ld1b { z21.b }, p5/z, [x10, #5, mul vl] +# CHECK-NEXT: 1 6 0.33 * ld1b { z21.d }, p5/z, [x10, #5, mul vl] +# CHECK-NEXT: 3 9 0.50 * ld1b { z21.d }, p5/z, [x10, z21.d, sxtw] +# CHECK-NEXT: 3 9 0.50 * ld1b { z21.d }, p5/z, [x10, z21.d, uxtw] +# CHECK-NEXT: 1 6 0.33 * ld1b { z21.h }, p5/z, [x10, #5, mul vl] +# CHECK-NEXT: 1 6 0.33 * ld1b { z21.s }, p5/z, [x10, #5, mul vl] +# CHECK-NEXT: 1 6 0.33 * ld1b { z21.s }, p5/z, [x10, x21] +# CHECK-NEXT: 1 6 0.33 * ld1b { z23.d }, p3/z, [x13, x8] +# CHECK-NEXT: 1 6 0.33 * ld1b { z31.b }, p7/z, [sp, #-1, mul vl] +# CHECK-NEXT: 1 6 0.33 * ld1b { z31.d }, p7/z, [sp, #-1, mul vl] +# CHECK-NEXT: 3 9 0.50 * ld1b { z31.d }, p7/z, [sp, z31.d] +# CHECK-NEXT: 5 9 1.00 * ld1b { z31.d }, p7/z, [z31.d, #31] +# CHECK-NEXT: 1 6 0.33 * ld1b { z31.h }, p7/z, [sp, #-1, mul vl] +# CHECK-NEXT: 1 6 0.33 * ld1b { z31.s }, p7/z, [sp, #-1, mul vl] +# CHECK-NEXT: 5 9 1.00 * ld1b { z31.s }, p7/z, [z31.s, #31] +# CHECK-NEXT: 1 6 0.33 * ld1b { z5.h }, p3/z, [x17, x16] +# CHECK-NEXT: 5 10 1.00 * ld1d { z0.d }, p0/z, [x0, z0.d, sxtw #3] +# CHECK-NEXT: 5 10 1.00 * ld1d { z0.d }, p0/z, [x0, z0.d, uxtw #3] +# CHECK-NEXT: 1 6 0.33 * ld1d { z0.d }, p0/z, [x0] +# CHECK-NEXT: 5 9 1.00 * ld1d { z0.d }, p0/z, [z0.d] +# CHECK-NEXT: 1 6 0.33 * ld1d { z21.d }, p5/z, [x10, #5, mul vl] +# CHECK-NEXT: 3 9 0.50 * ld1d { z21.d }, p5/z, [x10, z21.d, sxtw] +# CHECK-NEXT: 3 9 0.50 * ld1d { z21.d }, p5/z, [x10, z21.d, uxtw] +# CHECK-NEXT: 1 6 0.33 * ld1d { z23.d }, p3/z, [sp, x8, lsl #3] +# CHECK-NEXT: 1 6 0.33 * ld1d { z23.d }, p3/z, [x13, x8, lsl #3] +# CHECK-NEXT: 5 10 1.00 * ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3] +# CHECK-NEXT: 1 6 0.33 * ld1d { z31.d }, p7/z, [sp, #-1, mul vl] +# CHECK-NEXT: 3 9 0.50 * ld1d { z31.d }, p7/z, [sp, z31.d] +# CHECK-NEXT: 5 9 1.00 * ld1d { z31.d }, p7/z, [z31.d, #248] +# CHECK-NEXT: 5 10 1.00 * ld1h { z0.d }, p0/z, [x0, z0.d, sxtw #1] +# CHECK-NEXT: 5 10 1.00 * ld1h { z0.d }, p0/z, [x0, z0.d, uxtw #1] +# CHECK-NEXT: 1 6 0.33 * ld1h { z0.d }, p0/z, [x0] +# CHECK-NEXT: 5 9 1.00 * ld1h { z0.d }, p0/z, [z0.d] +# CHECK-NEXT: 1 6 0.33 * ld1h { z0.h }, p0/z, [x0] +# CHECK-NEXT: 5 9 1.00 * ld1h { z0.s }, p0/z, [x0, z0.s, sxtw] +# CHECK-NEXT: 5 9 1.00 * ld1h { z0.s }, p0/z, [x0, z0.s, uxtw] +# CHECK-NEXT: 1 6 0.33 * ld1h { z0.s }, p0/z, [x0] +# CHECK-NEXT: 5 9 1.00 * ld1h { z0.s }, p0/z, [z0.s] +# CHECK-NEXT: 1 6 0.33 * ld1h { z21.d }, p5/z, [x10, #5, mul vl] +# CHECK-NEXT: 3 9 0.50 * ld1h { z21.d }, p5/z, [x10, z21.d, sxtw] +# CHECK-NEXT: 3 9 0.50 * ld1h { z21.d }, p5/z, [x10, z21.d, uxtw] +# CHECK-NEXT: 1 6 0.33 * ld1h { z21.h }, p5/z, [x10, #5, mul vl] +# CHECK-NEXT: 1 6 0.33 * ld1h { z21.s }, p5/z, [x10, #5, mul vl] +# CHECK-NEXT: 1 6 0.33 * ld1h { z21.s }, p5/z, [x10, x21, lsl #1] +# CHECK-NEXT: 1 6 0.33 * ld1h { z23.d }, p3/z, [x13, x8, lsl #1] +# CHECK-NEXT: 5 10 1.00 * ld1h { z23.d }, p3/z, [x13, z8.d, lsl #1] +# CHECK-NEXT: 1 6 0.33 * ld1h { z31.d }, p7/z, [sp, #-1, mul vl] +# CHECK-NEXT: 3 9 0.50 * ld1h { z31.d }, p7/z, [sp, z31.d] +# CHECK-NEXT: 5 9 1.00 * ld1h { z31.d }, p7/z, [z31.d, #62] +# CHECK-NEXT: 1 6 0.33 * ld1h { z31.h }, p7/z, [sp, #-1, mul vl] +# CHECK-NEXT: 1 6 0.33 * ld1h { z31.s }, p7/z, [sp, #-1, mul vl] +# CHECK-NEXT: 9 10 2.00 * ld1h { z31.s }, p7/z, [sp, z31.s, sxtw #1] +# CHECK-NEXT: 9 10 2.00 * ld1h { z31.s }, p7/z, [sp, z31.s, uxtw #1] +# CHECK-NEXT: 5 9 1.00 * ld1h { z31.s }, p7/z, [z31.s, #62] +# CHECK-NEXT: 1 6 0.33 * ld1h { z5.h }, p3/z, [sp, x16, lsl #1] +# CHECK-NEXT: 1 6 0.33 * ld1h { z5.h }, p3/z, [x17, x16, lsl #1] +# CHECK-NEXT: 1 6 0.33 * ld1rb { z0.b }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rb { z0.d }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rb { z0.h }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rb { z0.s }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rb { z31.b }, p7/z, [sp, #63] +# CHECK-NEXT: 1 6 0.33 * ld1rb { z31.d }, p7/z, [sp, #63] +# CHECK-NEXT: 1 6 0.33 * ld1rb { z31.h }, p7/z, [sp, #63] +# CHECK-NEXT: 1 6 0.33 * ld1rb { z31.s }, p7/z, [sp, #63] +# CHECK-NEXT: 1 6 0.33 * ld1rd { z0.d }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rd { z31.d }, p7/z, [sp, #504] +# CHECK-NEXT: 1 6 0.33 * ld1rh { z0.d }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rh { z0.h }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rh { z0.s }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rh { z31.d }, p7/z, [sp, #126] +# CHECK-NEXT: 1 6 0.33 * ld1rh { z31.h }, p7/z, [sp, #126] +# CHECK-NEXT: 1 6 0.33 * ld1rh { z31.s }, p7/z, [sp, #126] +# CHECK-NEXT: 1 6 0.33 * ld1rqb { z0.b }, p0/z, [x0, x0] +# CHECK-NEXT: 1 6 0.33 * ld1rqb { z0.b }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rqb { z21.b }, p5/z, [x10, #112] +# CHECK-NEXT: 1 6 0.33 * ld1rqb { z23.b }, p3/z, [x13, #-128] +# CHECK-NEXT: 1 6 0.33 * ld1rqb { z31.b }, p7/z, [sp, #-16] +# CHECK-NEXT: 1 6 0.33 * ld1rqd { z0.d }, p0/z, [x0, x0, lsl #3] +# CHECK-NEXT: 1 6 0.33 * ld1rqd { z0.d }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rqd { z23.d }, p3/z, [x13, #-128] +# CHECK-NEXT: 1 6 0.33 * ld1rqd { z23.d }, p3/z, [x13, #112] +# CHECK-NEXT: 1 6 0.33 * ld1rqd { z31.d }, p7/z, [sp, #-16] +# CHECK-NEXT: 1 6 0.33 * ld1rqh { z0.h }, p0/z, [x0, x0, lsl #1] +# CHECK-NEXT: 1 6 0.33 * ld1rqh { z0.h }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rqh { z23.h }, p3/z, [x13, #-128] +# CHECK-NEXT: 1 6 0.33 * ld1rqh { z23.h }, p3/z, [x13, #112] +# CHECK-NEXT: 1 6 0.33 * ld1rqh { z31.h }, p7/z, [sp, #-16] +# CHECK-NEXT: 1 6 0.33 * ld1rqw { z0.s }, p0/z, [x0, x0, lsl #2] +# CHECK-NEXT: 1 6 0.33 * ld1rqw { z0.s }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rqw { z23.s }, p3/z, [x13, #-128] +# CHECK-NEXT: 1 6 0.33 * ld1rqw { z23.s }, p3/z, [x13, #112] +# CHECK-NEXT: 1 6 0.33 * ld1rqw { z31.s }, p7/z, [sp, #-16] +# CHECK-NEXT: 1 6 0.33 * ld1rsb { z0.d }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rsb { z0.h }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rsb { z0.s }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rsb { z31.d }, p7/z, [sp, #63] +# CHECK-NEXT: 1 6 0.33 * ld1rsb { z31.h }, p7/z, [sp, #63] +# CHECK-NEXT: 1 6 0.33 * ld1rsb { z31.s }, p7/z, [sp, #63] +# CHECK-NEXT: 1 6 0.33 * ld1rsh { z0.d }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rsh { z0.s }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rsh { z31.d }, p7/z, [sp, #126] +# CHECK-NEXT: 1 6 0.33 * ld1rsh { z31.s }, p7/z, [sp, #126] +# CHECK-NEXT: 1 6 0.33 * ld1rsw { z0.d }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rsw { z31.d }, p7/z, [sp, #252] +# CHECK-NEXT: 1 6 0.33 * ld1rw { z0.d }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rw { z0.s }, p0/z, [x0] +# CHECK-NEXT: 1 6 0.33 * ld1rw { z31.d }, p7/z, [sp, #252] +# CHECK-NEXT: 1 6 0.33 * ld1rw { z31.s }, p7/z, [sp, #252] +# CHECK-NEXT: 1 6 0.33 * ld1sb { z0.d }, p0/z, [x0] +# CHECK-NEXT: 5 9 1.00 * ld1sb { z0.d }, p0/z, [z0.d] +# CHECK-NEXT: 1 6 0.33 * ld1sb { z0.h }, p0/z, [sp, x0] +# CHECK-NEXT: 1 6 0.33 * ld1sb { z0.h }, p0/z, [x0, x0] +# CHECK-NEXT: 1 6 0.33 * ld1sb { z0.h }, p0/z, [x0] +# CHECK-NEXT: 5 9 1.00 * ld1sb { z0.s }, p0/z, [x0, z0.s, sxtw] +# CHECK-NEXT: 1 6 0.33 * ld1sb { z0.s }, p0/z, [x0] +# CHECK-NEXT: 5 9 1.00 * ld1sb { z0.s }, p0/z, [z0.s] +# CHECK-NEXT: 1 6 0.33 * ld1sb { z21.d }, p5/z, [x10, #5, mul vl] +# CHECK-NEXT: 3 9 0.50 * ld1sb { z21.d }, p5/z, [x10, z21.d, sxtw] +# CHECK-NEXT: 3 9 0.50 * ld1sb { z21.d }, p5/z, [x10, z21.d, uxtw] +# CHECK-NEXT: 1 6 0.33 * ld1sb { z21.h }, p5/z, [x10, #5, mul vl] +# CHECK-NEXT: 1 6 0.33 * ld1sb { z21.s }, p5/z, [x10, #5, mul vl] +# CHECK-NEXT: 1 6 0.33 * ld1sb { z21.s }, p5/z, [x10, x21] +# CHECK-NEXT: 1 6 0.33 * ld1sb { z23.d }, p3/z, [x13, x8] +# CHECK-NEXT: 1 6 0.33 * ld1sb { z31.d }, p7/z, [sp, #-1, mul vl] +# CHECK-NEXT: 3 9 0.50 * ld1sb { z31.d }, p7/z, [sp, z31.d] +# CHECK-NEXT: 5 9 1.00 * ld1sb { z31.d }, p7/z, [z31.d, #31] +# CHECK-NEXT: 1 6 0.33 * ld1sb { z31.h }, p7/z, [sp, #-1, mul vl] +# CHECK-NEXT: 1 6 0.33 * ld1sb { z31.s }, p7/z, [sp, #-1, mul vl] +# CHECK-NEXT: 5 9 1.00 * ld1sb { z31.s }, p7/z, [z31.s, #31] +# CHECK-NEXT: 5 10 1.00 * ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1] +# CHECK-NEXT: 5 10 1.00 * ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1] +# CHECK-NEXT: 1 6 0.33 * ld1sh { z0.d }, p0/z, [x0] +# CHECK-NEXT: 5 9 1.00 * ld1sh { z0.d }, p0/z, [z0.d] +# CHECK-NEXT: 5 9 1.00 * ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw] +# CHECK-NEXT: 5 9 1.00 * ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw] +# CHECK-NEXT: 1 6 0.33 * ld1sh { z0.s }, p0/z, [x0] +# CHECK-NEXT: 5 9 1.00 * ld1sh { z0.s }, p0/z, [z0.s] +# CHECK-NEXT: 1 6 0.33 * ld1sh { z21.d }, p5/z, [x10, #5, mul vl] +# CHECK-NEXT: 3 9 0.50 * ld1sh { z21.d }, p5/z, [x10, z21.d, sxtw] +# CHECK-NEXT: 3 9 0.50 * ld1sh { z21.d }, p5/z, [x10, z21.d, uxtw] +# CHECK-NEXT: 1 6 0.33 * ld1sh { z21.s }, p5/z, [sp, x21, lsl #1] +# CHECK-NEXT: 1 6 0.33 * ld1sh { z21.s }, p5/z, [x10, #5, mul vl] +# CHECK-NEXT: 1 6 0.33 * ld1sh { z21.s }, p5/z, [x10, x21, lsl #1] +# CHECK-NEXT: 1 6 0.33 * ld1sh { z23.d }, p3/z, [x13, x8, lsl #1] +# CHECK-NEXT: 5 10 1.00 * ld1sh { z23.d }, p3/z, [x13, z8.d, lsl #1] +# CHECK-NEXT: 1 6 0.33 * ld1sh { z31.d }, p7/z, [sp, #-1, mul vl] +# CHECK-NEXT: 3 9 0.50 * ld1sh { z31.d }, p7/z, [sp, z31.d] +# CHECK-NEXT: 5 9 1.00 * ld1sh { z31.d }, p7/z, [z31.d, #62] +# CHECK-NEXT: 1 6 0.33 * ld1sh { z31.s }, p7/z, [sp, #-1, mul vl] +# CHECK-NEXT: 9 10 2.00 * ld1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1] +# CHECK-NEXT: 9 10 2.00 * ld1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1] +# CHECK-NEXT: 5 9 1.00 * ld1sh { z31.s }, p7/z, [z31.s, #62] +# CHECK-NEXT: 5 10 1.00 * ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2] +# CHECK-NEXT: 5 10 1.00 * ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2] +# CHECK-NEXT: 1 6 0.33 * ld1sw { z0.d }, p0/z, [x0] +# CHECK-NEXT: 5 9 1.00 * ld1sw { z0.d }, p0/z, [z0.d] +# CHECK-NEXT: 1 6 0.33 * ld1sw { z21.d }, p5/z, [x10, #5, mul vl] +# CHECK-NEXT: 3 9 0.50 * ld1sw { z21.d }, p5/z, [x10, z21.d, sxtw] +# CHECK-NEXT: 3 9 0.50 * ld1sw { z21.d }, p5/z, [x10, z21.d, uxtw] +# CHECK-NEXT: 1 6 0.33 * ld1sw { z23.d }, p3/z, [sp, x8, lsl #2] +# CHECK-NEXT: 1 6 0.33 * ld1sw { z23.d }, p3/z, [x13, x8, lsl #2] +# CHECK-NEXT: 5 10 1.00 * ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2] +# CHECK-NEXT: 1 6 0.33 * ld1sw { z31.d }, p7/z, [sp, #-1, mul vl] +# CHECK-NEXT: 3 9 0.50 * ld1sw { z31.d }, p7/z, [sp, z31.d] +# CHECK-NEXT: 5 9 1.00 * ld1sw { z31.d }, p7/z, [z31.d, #124] +# CHECK-NEXT: 5 10 1.00 * ld1w { z0.d }, p0/z, [x0, z0.d, sxtw #2] +# CHECK-NEXT: 5 10 1.00 * ld1w { z0.d }, p0/z, [x0, z0.d, uxtw #2] +# CHECK-NEXT: 1 6 0.33 * ld1w { z0.d }, p0/z, [x0] +# CHECK-NEXT: 5 9 1.00 * ld1w { z0.d }, p0/z, [z0.d] +# CHECK-NEXT: 5 9 1.00 * ld1w { z0.s }, p0/z, [x0, z0.s, sxtw] +# CHECK-NEXT: 5 9 1.00 * ld1w { z0.s }, p0/z, [x0, z0.s, uxtw] +# CHECK-NEXT: 1 6 0.33 * ld1w { z0.s }, p0/z, [x0] +# CHECK-NEXT: 5 9 1.00 * ld1w { z0.s }, p0/z, [z0.s] +# CHECK-NEXT: 1 6 0.33 * ld1w { z21.d }, p5/z, [x10, #5, mul vl] +# CHECK-NEXT: 3 9 0.50 * ld1w { z21.d }, p5/z, [x10, z21.d, sxtw] +# CHECK-NEXT: 3 9 0.50 * ld1w { z21.d }, p5/z, [x10, z21.d, uxtw] +# CHECK-NEXT: 1 6 0.33 * ld1w { z21.s }, p5/z, [sp, x21, lsl #2] +# CHECK-NEXT: 1 6 0.33 * ld1w { z21.s }, p5/z, [x10, #5, mul vl] +# CHECK-NEXT: 1 6 0.33 * ld1w { z21.s }, p5/z, [x10, x21, lsl #2] +# CHECK-NEXT: 1 6 0.33 * ld1w { z23.d }, p3/z, [x13, x8, lsl #2] +# CHECK-NEXT: 5 10 1.00 * ld1w { z23.d }, p3/z, [x13, z8.d, lsl #2] +# CHECK-NEXT: 1 6 0.33 * ld1w { z31.d }, p7/z, [sp, #-1, mul vl] +# CHECK-NEXT: 3 9 0.50 * ld1w { z31.d }, p7/z, [sp, z31.d] +# CHECK-NEXT: 5 9 1.00 * ld1w { z31.d }, p7/z, [z31.d, #124] +# CHECK-NEXT: 1 6 0.33 * ld1w { z31.s }, p7/z, [sp, #-1, mul vl] +# CHECK-NEXT: 9 10 2.00 * ld1w { z31.s }, p7/z, [sp, z31.s, sxtw #2] +# CHECK-NEXT: 9 10 2.00 * ld1w { z31.s }, p7/z, [sp, z31.s, uxtw #2] +# CHECK-NEXT: 5 9 1.00 * ld1w { z31.s }, p7/z, [z31.s, #124] +# CHECK-NEXT: 6 9 0.67 * ld2b { z0.b, z1.b }, p0/z, [x0, x0] +# CHECK-NEXT: 4 8 0.67 * ld2b { z0.b, z1.b }, p0/z, [x0] +# CHECK-NEXT: 4 8 0.67 * ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl] +# CHECK-NEXT: 4 8 0.67 * ld2b { z23.b, z24.b }, p3/z, [x13, #-16, mul vl] +# CHECK-NEXT: 6 9 0.67 * ld2b { z5.b, z6.b }, p3/z, [x17, x16] +# CHECK-NEXT: 6 9 0.67 * ld2d { z0.d, z1.d }, p0/z, [x0, x0, lsl #3] +# CHECK-NEXT: 4 8 0.67 * ld2d { z0.d, z1.d }, p0/z, [x0] +# CHECK-NEXT: 4 8 0.67 * ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl] +# CHECK-NEXT: 4 8 0.67 * ld2d { z23.d, z24.d }, p3/z, [x13, #-16, mul vl] +# CHECK-NEXT: 6 9 0.67 * ld2d { z5.d, z6.d }, p3/z, [x17, x16, lsl #3] +# CHECK-NEXT: 6 9 0.67 * ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1] +# CHECK-NEXT: 4 8 0.67 * ld2h { z0.h, z1.h }, p0/z, [x0] +# CHECK-NEXT: 4 8 0.67 * ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl] +# CHECK-NEXT: 4 8 0.67 * ld2h { z23.h, z24.h }, p3/z, [x13, #-16, mul vl] +# CHECK-NEXT: 6 9 0.67 * ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1] +# CHECK-NEXT: 6 9 0.67 * ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #2] +# CHECK-NEXT: 4 8 0.67 * ld2w { z0.s, z1.s }, p0/z, [x0] +# CHECK-NEXT: 4 8 0.67 * ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl] +# CHECK-NEXT: 4 8 0.67 * ld2w { z23.s, z24.s }, p3/z, [x13, #-16, mul vl] +# CHECK-NEXT: 6 9 0.67 * ld2w { z5.s, z6.s }, p3/z, [x17, x16, lsl #2] +# CHECK-NEXT: 9 10 1.00 * ld3b { z0.b - z2.b }, p0/z, [x0, x0] +# CHECK-NEXT: 6 9 1.00 * ld3b { z0.b - z2.b }, p0/z, [x0] +# CHECK-NEXT: 6 9 1.00 * ld3b { z21.b - z23.b }, p5/z, [x10, #15, mul vl] +# CHECK-NEXT: 6 9 1.00 * ld3b { z23.b - z25.b }, p3/z, [x13, #-24, mul vl] +# CHECK-NEXT: 9 10 1.00 * ld3b { z5.b - z7.b }, p3/z, [x17, x16] +# CHECK-NEXT: 9 10 1.00 * ld3d { z0.d - z2.d }, p0/z, [x0, x0, lsl #3] +# CHECK-NEXT: 6 9 1.00 * ld3d { z0.d - z2.d }, p0/z, [x0] +# CHECK-NEXT: 6 9 1.00 * ld3d { z21.d - z23.d }, p5/z, [x10, #15, mul vl] +# CHECK-NEXT: 6 9 1.00 * ld3d { z23.d - z25.d }, p3/z, [x13, #-24, mul vl] +# CHECK-NEXT: 9 10 1.00 * ld3d { z5.d - z7.d }, p3/z, [x17, x16, lsl #3] +# CHECK-NEXT: 9 10 1.00 * ld3h { z0.h - z2.h }, p0/z, [x0, x0, lsl #1] +# CHECK-NEXT: 6 9 1.00 * ld3h { z0.h - z2.h }, p0/z, [x0] +# CHECK-NEXT: 6 9 1.00 * ld3h { z21.h - z23.h }, p5/z, [x10, #15, mul vl] +# CHECK-NEXT: 6 9 1.00 * ld3h { z23.h - z25.h }, p3/z, [x13, #-24, mul vl] +# CHECK-NEXT: 9 10 1.00 * ld3h { z5.h - z7.h }, p3/z, [x17, x16, lsl #1] +# CHECK-NEXT: 9 10 1.00 * ld3w { z0.s - z2.s }, p0/z, [x0, x0, lsl #2] +# CHECK-NEXT: 6 9 1.00 * ld3w { z0.s - z2.s }, p0/z, [x0] +# CHECK-NEXT: 6 9 1.00 * ld3w { z21.s - z23.s }, p5/z, [x10, #15, mul vl] +# CHECK-NEXT: 6 9 1.00 * ld3w { z23.s - z25.s }, p3/z, [x13, #-24, mul vl] +# CHECK-NEXT: 9 10 1.00 * ld3w { z5.s - z7.s }, p3/z, [x17, x16, lsl #2] +# CHECK-NEXT: 16 10 2.00 * ld4b { z0.b - z3.b }, p0/z, [x0, x0] +# CHECK-NEXT: 12 9 2.00 * ld4b { z0.b - z3.b }, p0/z, [x0] +# CHECK-NEXT: 12 9 2.00