diff --git a/clang/test/CodeGen/ms-inline-asm-64.c b/clang/test/CodeGen/ms-inline-asm-64.c
--- a/clang/test/CodeGen/ms-inline-asm-64.c
+++ b/clang/test/CodeGen/ms-inline-asm-64.c
@@ -72,3 +72,10 @@
   // CHECK-SAME: jmp ${1:P}
   // CHECK-SAME: "*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(void (...)) @bar, ptr elementtype(void (...)) @bar)
 }
+
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm enqcmds rax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "enqcmds rax, zmmword ptr $0", "*m,~{flags},~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}
diff --git a/clang/test/CodeGen/ms-inline-asm.c b/clang/test/CodeGen/ms-inline-asm.c
--- a/clang/test/CodeGen/ms-inline-asm.c
+++ b/clang/test/CodeGen/ms-inline-asm.c
@@ -675,6 +675,13 @@
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", "~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm enqcmds eax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "enqcmds eax, zmmword ptr $0", "*m,~{flags},~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}
+
 void dot_operator(void){
   // CHECK-LABEL: define{{.*}} void @dot_operator
 	__asm { mov eax, 3[ebx]A.b}
diff --git a/llvm/lib/Target/X86/AsmParser/X86Operand.h b/llvm/lib/Target/X86/AsmParser/X86Operand.h
--- a/llvm/lib/Target/X86/AsmParser/X86Operand.h
+++ b/llvm/lib/Target/X86/AsmParser/X86Operand.h
@@ -383,6 +383,8 @@
   bool isMem512_GR16() const {
     if (!isMem512())
       return false;
+    if (getMemDisp()->getKind() == llvm::MCExpr::SymbolRef)
+      return true;
     if (getMemBaseReg() &&
         !X86MCRegisterClasses[X86::GR16RegClassID].contains(getMemBaseReg()))
       return false;
@@ -391,6 +393,8 @@
   bool isMem512_GR32() const {
     if (!isMem512())
       return false;
+    if (getMemDisp()->getKind() == llvm::MCExpr::SymbolRef)
+      return true;
     if (getMemBaseReg() &&
         !X86MCRegisterClasses[X86::GR32RegClassID].contains(getMemBaseReg()) &&
         getMemBaseReg() != X86::EIP)
@@ -404,6 +408,8 @@
   bool isMem512_GR64() const {
     if (!isMem512())
       return false;
+    if (getMemDisp()->getKind() == llvm::MCExpr::SymbolRef)
+      return true;
     if (getMemBaseReg() &&
         !X86MCRegisterClasses[X86::GR64RegClassID].contains(getMemBaseReg()) &&
         getMemBaseReg() != X86::RIP)
diff --git a/llvm/test/MC/X86/x86-64-movdir64b-intel.s b/llvm/test/MC/X86/x86-64-movdir64b-intel.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/X86/x86-64-movdir64b-intel.s
@@ -0,0 +1,4 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// CHECK: movdir64b rax, zmmword ptr [rax - 4096]
+// CHECK: encoding: [0x66,0x0f,0x38,0xf8,0x80,0x00,0xf0,0xff,0xff]
+          movdir64b rax, zmmword ptr [rax - 4096]