diff --git a/llvm/test/Transforms/InstCombine/pr62311.ll b/llvm/test/Transforms/InstCombine/pr62311.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/pr62311.ll
@@ -0,0 +1,299 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+; C++ version of test case
+; #include <x86intrin.h>
+;
+; bool allonesandwithequal(__m512i x) {
+;   return
+;     x[0] == -1 && x[1] == -1 &&
+;     x[2] == -1 && x[3] == -1 &&
+;     x[4] == -1 && x[5] == -1 &&
+;     x[6] == -1 && x[7] == -1;
+; }
+
+; Function Attrs: mustprogress nounwind uwtable
+define noundef zeroext i1 @allonesandwithequal(<8 x i64> noundef %x) {
+; CHECK-LABEL: @allonesandwithequal(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <8 x i64> [[X:%.*]], i64 0
+; CHECK-NEXT:    [[VECEXT1:%.*]] = extractelement <8 x i64> [[X]], i64 1
+; CHECK-NEXT:    [[TMP0:%.*]] = and i64 [[VECEXT]], [[VECEXT1]]
+; CHECK-NEXT:    [[VECEXT4:%.*]] = extractelement <8 x i64> [[X]], i64 2
+; CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], [[VECEXT4]]
+; CHECK-NEXT:    [[VECEXT7:%.*]] = extractelement <8 x i64> [[X]], i64 3
+; CHECK-NEXT:    [[TMP2:%.*]] = and i64 [[TMP1]], [[VECEXT7]]
+; CHECK-NEXT:    [[VECEXT10:%.*]] = extractelement <8 x i64> [[X]], i64 4
+; CHECK-NEXT:    [[TMP3:%.*]] = and i64 [[TMP2]], [[VECEXT10]]
+; CHECK-NEXT:    [[VECEXT13:%.*]] = extractelement <8 x i64> [[X]], i64 5
+; CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], [[VECEXT13]]
+; CHECK-NEXT:    [[VECEXT16:%.*]] = extractelement <8 x i64> [[X]], i64 6
+; CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], [[VECEXT16]]
+; CHECK-NEXT:    [[OR_COND24:%.*]] = icmp eq i64 [[TMP5]], -1
+; CHECK-NEXT:    br i1 [[OR_COND24]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]]
+; CHECK:       land.rhs:
+; CHECK-NEXT:    [[VECEXT18:%.*]] = extractelement <8 x i64> [[X]], i64 7
+; CHECK-NEXT:    [[CMP19:%.*]] = icmp eq i64 [[VECEXT18]], -1
+; CHECK-NEXT:    br label [[LAND_END]]
+; CHECK:       land.end:
+; CHECK-NEXT:    [[TMP6:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[CMP19]], [[LAND_RHS]] ]
+; CHECK-NEXT:    ret i1 [[TMP6]]
+;
+entry:
+  %vecext = extractelement <8 x i64> %x, i32 0
+  %cmp = icmp eq i64 %vecext, -1
+  %vecext1 = extractelement <8 x i64> %x, i32 1
+  %cmp2 = icmp eq i64 %vecext1, -1
+  %or.cond = select i1 %cmp, i1 %cmp2, i1 false
+  %vecext4 = extractelement <8 x i64> %x, i32 2
+  %cmp5 = icmp eq i64 %vecext4, -1
+  %or.cond20 = select i1 %or.cond, i1 %cmp5, i1 false
+  %vecext7 = extractelement <8 x i64> %x, i32 3
+  %cmp8 = icmp eq i64 %vecext7, -1
+  %or.cond21 = select i1 %or.cond20, i1 %cmp8, i1 false
+  %vecext10 = extractelement <8 x i64> %x, i32 4
+  %cmp11 = icmp eq i64 %vecext10, -1
+  %or.cond22 = select i1 %or.cond21, i1 %cmp11, i1 false
+  %vecext13 = extractelement <8 x i64> %x, i32 5
+  %cmp14 = icmp eq i64 %vecext13, -1
+  %or.cond23 = select i1 %or.cond22, i1 %cmp14, i1 false
+  %vecext16 = extractelement <8 x i64> %x, i32 6
+  %cmp17 = icmp eq i64 %vecext16, -1
+  %or.cond24 = select i1 %or.cond23, i1 %cmp17, i1 false
+  br i1 %or.cond24, label %land.rhs, label %land.end
+
+land.rhs:                                         ; preds = %entry
+  %vecext18 = extractelement <8 x i64> %x, i32 7
+
+  %cmp19 = icmp eq i64 %vecext18, -1
+  br label %land.end
+
+land.end:                                         ; preds = %land.rhs, %entry
+  %0 = phi i1 [ false, %entry ], [ %cmp19, %land.rhs ]
+  ret i1 %0
+}
+
+; C++ version of test case
+; #include <x86intrin.h>
+;
+; bool allonesandwithnotequal(__m512i x) {
+;   return
+;     x[0] != -1 && x[1] != -1 &&
+;     x[2] != -1 && x[3] != -1 &&
+;     x[4] != -1 && x[5] != -1 &&
+;     x[6] != -1 && x[7] != -1;
+; }
+
+; Function Attrs: mustprogress nounwind uwtable
+define noundef zeroext i1 @allonesandwithnotequal(<8 x i64> noundef %x) {
+; CHECK-LABEL: @allonesandwithnotequal(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <8 x i64> [[X:%.*]], i64 0
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i64 [[VECEXT]], -1
+; CHECK-NEXT:    [[VECEXT1:%.*]] = extractelement <8 x i64> [[X]], i64 1
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i64 [[VECEXT1]], -1
+; CHECK-NEXT:    [[OR_COND:%.*]] = and i1 [[CMP]], [[CMP2]]
+; CHECK-NEXT:    [[VECEXT4:%.*]] = extractelement <8 x i64> [[X]], i64 2
+; CHECK-NEXT:    [[CMP5:%.*]] = icmp ne i64 [[VECEXT4]], -1
+; CHECK-NEXT:    [[OR_COND20:%.*]] = and i1 [[OR_COND]], [[CMP5]]
+; CHECK-NEXT:    [[VECEXT7:%.*]] = extractelement <8 x i64> [[X]], i64 3
+; CHECK-NEXT:    [[CMP8:%.*]] = icmp ne i64 [[VECEXT7]], -1
+; CHECK-NEXT:    [[OR_COND21:%.*]] = and i1 [[OR_COND20]], [[CMP8]]
+; CHECK-NEXT:    [[VECEXT10:%.*]] = extractelement <8 x i64> [[X]], i64 4
+; CHECK-NEXT:    [[CMP11:%.*]] = icmp ne i64 [[VECEXT10]], -1
+; CHECK-NEXT:    [[OR_COND22:%.*]] = and i1 [[OR_COND21]], [[CMP11]]
+; CHECK-NEXT:    [[VECEXT13:%.*]] = extractelement <8 x i64> [[X]], i64 5
+; CHECK-NEXT:    [[CMP14:%.*]] = icmp ne i64 [[VECEXT13]], -1
+; CHECK-NEXT:    [[OR_COND23:%.*]] = and i1 [[OR_COND22]], [[CMP14]]
+; CHECK-NEXT:    [[VECEXT16:%.*]] = extractelement <8 x i64> [[X]], i64 6
+; CHECK-NEXT:    [[CMP17:%.*]] = icmp ne i64 [[VECEXT16]], -1
+; CHECK-NEXT:    [[OR_COND24:%.*]] = and i1 [[OR_COND23]], [[CMP17]]
+; CHECK-NEXT:    br i1 [[OR_COND24]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]]
+; CHECK:       land.rhs:
+; CHECK-NEXT:    [[VECEXT18:%.*]] = extractelement <8 x i64> [[X]], i64 7
+; CHECK-NEXT:    [[CMP19:%.*]] = icmp ne i64 [[VECEXT18]], -1
+; CHECK-NEXT:    br label [[LAND_END]]
+; CHECK:       land.end:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[CMP19]], [[LAND_RHS]] ]
+; CHECK-NEXT:    ret i1 [[TMP0]]
+;
+entry:
+  %vecext = extractelement <8 x i64> %x, i32 0
+  %cmp = icmp ne i64 %vecext, -1
+  %vecext1 = extractelement <8 x i64> %x, i32 1
+  %cmp2 = icmp ne i64 %vecext1, -1
+  %or.cond = select i1 %cmp, i1 %cmp2, i1 false
+  %vecext4 = extractelement <8 x i64> %x, i32 2
+  %cmp5 = icmp ne i64 %vecext4, -1
+  %or.cond20 = select i1 %or.cond, i1 %cmp5, i1 false
+  %vecext7 = extractelement <8 x i64> %x, i32 3
+  %cmp8 = icmp ne i64 %vecext7, -1
+  %or.cond21 = select i1 %or.cond20, i1 %cmp8, i1 false
+  %vecext10 = extractelement <8 x i64> %x, i32 4
+  %cmp11 = icmp ne i64 %vecext10, -1
+  %or.cond22 = select i1 %or.cond21, i1 %cmp11, i1 false
+  %vecext13 = extractelement <8 x i64> %x, i32 5
+  %cmp14 = icmp ne i64 %vecext13, -1
+  %or.cond23 = select i1 %or.cond22, i1 %cmp14, i1 false
+  %vecext16 = extractelement <8 x i64> %x, i32 6
+  %cmp17 = icmp ne i64 %vecext16, -1
+  %or.cond24 = select i1 %or.cond23, i1 %cmp17, i1 false
+  br i1 %or.cond24, label %land.rhs, label %land.end
+
+land.rhs:                                         ; preds = %entry
+  %vecext18 = extractelement <8 x i64> %x, i32 7
+  %cmp19 = icmp ne i64 %vecext18, -1
+  br label %land.end
+
+land.end:                                         ; preds = %land.rhs, %entry
+  %0 = phi i1 [ false, %entry ], [ %cmp19, %land.rhs ]
+  ret i1 %0
+}
+
+; C++ version of test case
+; #include <x86intrin.h>
+;
+; bool allonesorwithnotequal(__m512i x) {
+;   return
+;     x[0] != -1 || x[1] != -1 ||
+;     x[2] != -1 || x[3] != -1 ||
+;     x[4] != -1 || x[5] != -1 ||
+;     x[6] != -1 || x[7] != -1;
+; }
+
+; Function Attrs: mustprogress nounwind uwtable
+define noundef zeroext i1 @allonesorwithnotequal(<8 x i64> noundef %x) {
+; CHECK-LABEL: @allonesorwithnotequal(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <8 x i64> [[X:%.*]], i64 0
+; CHECK-NEXT:    [[VECEXT1:%.*]] = extractelement <8 x i64> [[X]], i64 1
+; CHECK-NEXT:    [[TMP0:%.*]] = and i64 [[VECEXT]], [[VECEXT1]]
+; CHECK-NEXT:    [[VECEXT4:%.*]] = extractelement <8 x i64> [[X]], i64 2
+; CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], [[VECEXT4]]
+; CHECK-NEXT:    [[VECEXT7:%.*]] = extractelement <8 x i64> [[X]], i64 3
+; CHECK-NEXT:    [[TMP2:%.*]] = and i64 [[TMP1]], [[VECEXT7]]
+; CHECK-NEXT:    [[VECEXT10:%.*]] = extractelement <8 x i64> [[X]], i64 4
+; CHECK-NEXT:    [[TMP3:%.*]] = and i64 [[TMP2]], [[VECEXT10]]
+; CHECK-NEXT:    [[VECEXT13:%.*]] = extractelement <8 x i64> [[X]], i64 5
+; CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], [[VECEXT13]]
+; CHECK-NEXT:    [[VECEXT16:%.*]] = extractelement <8 x i64> [[X]], i64 6
+; CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], [[VECEXT16]]
+; CHECK-NEXT:    [[OR_COND24_NOT:%.*]] = icmp eq i64 [[TMP5]], -1
+; CHECK-NEXT:    br i1 [[OR_COND24_NOT]], label [[LOR_RHS:%.*]], label [[LOR_END:%.*]]
+; CHECK:       lor.rhs:
+; CHECK-NEXT:    [[VECEXT18:%.*]] = extractelement <8 x i64> [[X]], i64 7
+; CHECK-NEXT:    [[CMP19:%.*]] = icmp ne i64 [[VECEXT18]], -1
+; CHECK-NEXT:    br label [[LOR_END]]
+; CHECK:       lor.end:
+; CHECK-NEXT:    [[TMP6:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ [[CMP19]], [[LOR_RHS]] ]
+; CHECK-NEXT:    ret i1 [[TMP6]]
+;
+entry:
+  %vecext = extractelement <8 x i64> %x, i32 0
+  %cmp = icmp ne i64 %vecext, -1
+  %vecext1 = extractelement <8 x i64> %x, i32 1
+  %cmp2 = icmp ne i64 %vecext1, -1
+  %or.cond = select i1 %cmp, i1 true, i1 %cmp2
+  %vecext4 = extractelement <8 x i64> %x, i32 2
+  %cmp5 = icmp ne i64 %vecext4, -1
+  %or.cond20 = select i1 %or.cond, i1 true, i1 %cmp5
+  %vecext7 = extractelement <8 x i64> %x, i32 3
+  %cmp8 = icmp ne i64 %vecext7, -1
+  %or.cond21 = select i1 %or.cond20, i1 true, i1 %cmp8
+  %vecext10 = extractelement <8 x i64> %x, i32 4
+  %cmp11 = icmp ne i64 %vecext10, -1
+  %or.cond22 = select i1 %or.cond21, i1 true, i1 %cmp11
+  %vecext13 = extractelement <8 x i64> %x, i32 5
+  %cmp14 = icmp ne i64 %vecext13, -1
+  %or.cond23 = select i1 %or.cond22, i1 true, i1 %cmp14
+  %vecext16 = extractelement <8 x i64> %x, i32 6
+  %cmp17 = icmp ne i64 %vecext16, -1
+  %or.cond24 = select i1 %or.cond23, i1 true, i1 %cmp17
+  br i1 %or.cond24, label %lor.end, label %lor.rhs
+
+lor.rhs:                                          ; preds = %entry
+  %vecext18 = extractelement <8 x i64> %x, i32 7
+  %cmp19 = icmp ne i64 %vecext18, -1
+  br label %lor.end
+
+lor.end:                                          ; preds = %lor.rhs, %entry
+  %0 = phi i1 [ true, %entry ], [ %cmp19, %lor.rhs ]
+  ret i1 %0
+}
+
+; C++ version of test case
+; #include <x86intrin.h>
+;
+; bool allonesorwithequal(__m512i x) {
+;   return
+;     x[0] == -1 || x[1] == -1 ||
+;     x[2] == -1 || x[3] == -1 ||
+;     x[4] == -1 || x[5] == -1 ||
+;     x[6] == -1 || x[7] == -1;
+; }
+
+; Function Attrs: mustprogress nounwind uwtable
+define noundef zeroext i1 @allonesorwithequal(<8 x i64> noundef %x) {
+; CHECK-LABEL: @allonesorwithequal(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <8 x i64> [[X:%.*]], i64 0
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i64 [[VECEXT]], -1
+; CHECK-NEXT:    [[VECEXT1:%.*]] = extractelement <8 x i64> [[X]], i64 1
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i64 [[VECEXT1]], -1
+; CHECK-NEXT:    [[OR_COND:%.*]] = or i1 [[CMP]], [[CMP2]]
+; CHECK-NEXT:    [[VECEXT4:%.*]] = extractelement <8 x i64> [[X]], i64 2
+; CHECK-NEXT:    [[CMP5:%.*]] = icmp eq i64 [[VECEXT4]], -1
+; CHECK-NEXT:    [[OR_COND20:%.*]] = or i1 [[OR_COND]], [[CMP5]]
+; CHECK-NEXT:    [[VECEXT7:%.*]] = extractelement <8 x i64> [[X]], i64 3
+; CHECK-NEXT:    [[CMP8:%.*]] = icmp eq i64 [[VECEXT7]], -1
+; CHECK-NEXT:    [[OR_COND21:%.*]] = or i1 [[OR_COND20]], [[CMP8]]
+; CHECK-NEXT:    [[VECEXT10:%.*]] = extractelement <8 x i64> [[X]], i64 4
+; CHECK-NEXT:    [[CMP11:%.*]] = icmp eq i64 [[VECEXT10]], -1
+; CHECK-NEXT:    [[OR_COND22:%.*]] = or i1 [[OR_COND21]], [[CMP11]]
+; CHECK-NEXT:    [[VECEXT13:%.*]] = extractelement <8 x i64> [[X]], i64 5
+; CHECK-NEXT:    [[CMP14:%.*]] = icmp eq i64 [[VECEXT13]], -1
+; CHECK-NEXT:    [[OR_COND23:%.*]] = or i1 [[OR_COND22]], [[CMP14]]
+; CHECK-NEXT:    [[VECEXT16:%.*]] = extractelement <8 x i64> [[X]], i64 6
+; CHECK-NEXT:    [[CMP17:%.*]] = icmp eq i64 [[VECEXT16]], -1
+; CHECK-NEXT:    [[OR_COND24:%.*]] = or i1 [[OR_COND23]], [[CMP17]]
+; CHECK-NEXT:    br i1 [[OR_COND24]], label [[LOR_END:%.*]], label [[LOR_RHS:%.*]]
+; CHECK:       lor.rhs:
+; CHECK-NEXT:    [[VECEXT18:%.*]] = extractelement <8 x i64> [[X]], i64 7
+; CHECK-NEXT:    [[CMP19:%.*]] = icmp eq i64 [[VECEXT18]], -1
+; CHECK-NEXT:    br label [[LOR_END]]
+; CHECK:       lor.end:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ [[CMP19]], [[LOR_RHS]] ]
+; CHECK-NEXT:    ret i1 [[TMP0]]
+;
+entry:
+  %vecext = extractelement <8 x i64> %x, i32 0
+  %cmp = icmp eq i64 %vecext, -1
+  %vecext1 = extractelement <8 x i64> %x, i32 1
+  %cmp2 = icmp eq i64 %vecext1, -1
+  %or.cond = select i1 %cmp, i1 true, i1 %cmp2
+  %vecext4 = extractelement <8 x i64> %x, i32 2
+  %cmp5 = icmp eq i64 %vecext4, -1
+  %or.cond20 = select i1 %or.cond, i1 true, i1 %cmp5
+  %vecext7 = extractelement <8 x i64> %x, i32 3
+  %cmp8 = icmp eq i64 %vecext7, -1
+  %or.cond21 = select i1 %or.cond20, i1 true, i1 %cmp8
+  %vecext10 = extractelement <8 x i64> %x, i32 4
+  %cmp11 = icmp eq i64 %vecext10, -1
+  %or.cond22 = select i1 %or.cond21, i1 true, i1 %cmp11
+  %vecext13 = extractelement <8 x i64> %x, i32 5
+  %cmp14 = icmp eq i64 %vecext13, -1
+  %or.cond23 = select i1 %or.cond22, i1 true, i1 %cmp14
+  %vecext16 = extractelement <8 x i64> %x, i32 6
+  %cmp17 = icmp eq i64 %vecext16, -1
+  %or.cond24 = select i1 %or.cond23, i1 true, i1 %cmp17
+  br i1 %or.cond24, label %lor.end, label %lor.rhs
+
+lor.rhs:                                          ; preds = %entry
+  %vecext18 = extractelement <8 x i64> %x, i32 7
+  %cmp19 = icmp eq i64 %vecext18, -1
+  br label %lor.end
+
+lor.end:                                          ; preds = %lor.rhs, %entry
+  %0 = phi i1 [ true, %entry ], [ %cmp19, %lor.rhs ]
+  ret i1 %0
+}
diff --git a/llvm/test/Transforms/PhaseOrdering/pr62311.ll b/llvm/test/Transforms/PhaseOrdering/pr62311.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/pr62311.ll
@@ -0,0 +1,58 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes='default<O3>' -S | FileCheck %s
+
+; C++ version of test case
+; #include <x86intrin.h>
+;
+; bool allones(__m512i x) {
+;   return
+;     x[0] == -1 && x[1] == -1 &&
+;     x[2] == -1 && x[3] == -1 &&
+;     x[4] == -1 && x[5] == -1 &&
+;     x[6] == -1 && x[7] == -1;
+; }
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; Function Attrs: mustprogress nounwind uwtable
+define noundef zeroext i1 @allones(<8 x i64> noundef %x) {
+; CHECK-LABEL: @allones(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> [[X:%.*]])
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i64 [[TMP0]], -1
+; CHECK-NEXT:    ret i1 [[TMP1]]
+;
+entry:
+  %vecext = extractelement <8 x i64> %x, i32 0
+  %cmp = icmp eq i64 %vecext, -1
+  %vecext1 = extractelement <8 x i64> %x, i32 1
+  %cmp2 = icmp eq i64 %vecext1, -1
+  %or.cond = select i1 %cmp, i1 %cmp2, i1 false
+  %vecext4 = extractelement <8 x i64> %x, i32 2
+  %cmp5 = icmp eq i64 %vecext4, -1
+  %or.cond20 = select i1 %or.cond, i1 %cmp5, i1 false
+  %vecext7 = extractelement <8 x i64> %x, i32 3
+  %cmp8 = icmp eq i64 %vecext7, -1
+  %or.cond21 = select i1 %or.cond20, i1 %cmp8, i1 false
+  %vecext10 = extractelement <8 x i64> %x, i32 4
+  %cmp11 = icmp eq i64 %vecext10, -1
+  %or.cond22 = select i1 %or.cond21, i1 %cmp11, i1 false
+  %vecext13 = extractelement <8 x i64> %x, i32 5
+  %cmp14 = icmp eq i64 %vecext13, -1
+  %or.cond23 = select i1 %or.cond22, i1 %cmp14, i1 false
+  %vecext16 = extractelement <8 x i64> %x, i32 6
+  %cmp17 = icmp eq i64 %vecext16, -1
+  %or.cond24 = select i1 %or.cond23, i1 %cmp17, i1 false
+  br i1 %or.cond24, label %land.rhs, label %land.end
+
+land.rhs:                                         ; preds = %entry
+  %vecext18 = extractelement <8 x i64> %x, i32 7
+
+  %cmp19 = icmp eq i64 %vecext18, -1
+  br label %land.end
+
+land.end:                                         ; preds = %land.rhs, %entry
+  %0 = phi i1 [ false, %entry ], [ %cmp19, %land.rhs ]
+  ret i1 %0
+}