Index: llvm/lib/Analysis/IVUsers.cpp
===================================================================
--- llvm/lib/Analysis/IVUsers.cpp
+++ llvm/lib/Analysis/IVUsers.cpp
@@ -55,6 +55,10 @@
 /// given loop.
 static bool isInteresting(const SCEV *S, const Instruction *I, const Loop *L,
                           ScalarEvolution *SE, LoopInfo *LI) {
+  // The SCEV for URem instruction is SCEVAddExpr, but URem is uninteresting.
+  if (I->getOpcode() == Instruction::URem)
+    return false;
+
   // An addrec is interesting if it's affine or if it has an interesting start.
   if (const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(S)) {
     // Keep things simple. Don't touch loop-variant strides unless they're
Index: llvm/test/Transforms/LoopStrengthReduce/scaling-factor-incompat-type.ll
===================================================================
--- llvm/test/Transforms/LoopStrengthReduce/scaling-factor-incompat-type.ll
+++ llvm/test/Transforms/LoopStrengthReduce/scaling-factor-incompat-type.ll
@@ -17,14 +17,16 @@
 ; CHECK:       bb4:
 ; CHECK-NEXT:    [[LSR_IV1:%.*]] = phi i16 [ [[LSR_IV_NEXT2:%.*]], [[BB13:%.*]] ], [ 6, [[BB:%.*]] ]
 ; CHECK-NEXT:    [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT]], [[BB13]] ], [ 8589934593, [[BB]] ]
-; CHECK-NEXT:    [[LSR_IV_NEXT]] = add nuw nsw i64 [[LSR_IV]], 25769803776
-; CHECK-NEXT:    [[LSR_IV_NEXT2]] = add nuw nsw i16 [[LSR_IV1]], 6
-; CHECK-NEXT:    [[T10:%.*]] = icmp eq i16 1, 0
+; CHECK-NEXT:    [[T8:%.*]] = urem i16 [[LSR_IV1]], 3
+; CHECK-NEXT:    [[T9:%.*]] = mul i16 [[T8]], 2
+; CHECK-NEXT:    [[T10:%.*]] = icmp eq i16 [[T9]], 1
 ; CHECK-NEXT:    br i1 [[T10]], label [[BB11:%.*]], label [[BB13]]
 ; CHECK:       bb11:
 ; CHECK-NEXT:    [[T12:%.*]] = udiv i16 1, [[LSR_IV1]]
 ; CHECK-NEXT:    unreachable
 ; CHECK:       bb13:
+; CHECK-NEXT:    [[LSR_IV_NEXT]] = add nuw nsw i64 [[LSR_IV]], 25769803776
+; CHECK-NEXT:    [[LSR_IV_NEXT2]] = add nuw nsw i16 [[LSR_IV1]], 6
 ; CHECK-NEXT:    br i1 true, label [[BB1:%.*]], label [[BB4]]
 ;
 bb:
Index: llvm/test/Transforms/LoopStrengthReduce/urem-use-type-conversion.ll
===================================================================
--- /dev/null
+++ llvm/test/Transforms/LoopStrengthReduce/urem-use-type-conversion.ll
@@ -0,0 +1,57 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -loop-reduce -S | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+@l = global i64 0
+@i = global i64 0
+@.str = private constant [4 x i8] c"%d\0A\00"
+
+define i32 @main() {
+; CHECK-LABEL: define i32 @main() {
+; CHECK-NEXT:  for.body8.1.preheader:
+; CHECK-NEXT:    br label [[FOR_BODY8_1:%.*]]
+; CHECK:       for.body8.1:
+; CHECK-NEXT:    [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[FOR_BODY8_1]] ], [ 1, [[FOR_BODY8_1_PREHEADER:%.*]] ]
+; CHECK-NEXT:    [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], -1
+; CHECK-NEXT:    [[TMP0:%.*]] = add i64 [[LSR_IV_NEXT]], 1
+; CHECK-NEXT:    [[TMP:%.*]] = trunc i64 [[TMP0]] to i32
+; CHECK-NEXT:    [[CMP6_1:%.*]] = icmp sgt i32 [[TMP]], 0
+; CHECK-NEXT:    br i1 [[CMP6_1]], label [[FOR_BODY8_1]], label [[FOR_INC10_1:%.*]]
+; CHECK:       for.inc10.1:
+; CHECK-NEXT:    [[TMP1:%.*]] = mul i64 [[LSR_IV_NEXT]], -1
+; CHECK-NEXT:    br label [[FOR_END15:%.*]]
+; CHECK:       for.end15:
+; CHECK-NEXT:    [[TMP2:%.*]] = add i64 [[LSR_IV_NEXT]], 1
+; CHECK-NEXT:    store i64 [[TMP1]], ptr @l, align 8
+; CHECK-NEXT:    store i64 [[TMP2]], ptr @i, align 8
+; CHECK-NEXT:    [[TMP3:%.*]] = trunc i64 [[LSR_IV_NEXT]] to i32
+; CHECK-NEXT:    [[REM:%.*]] = urem i32 [[TMP3]], 53
+; CHECK-NEXT:    [[CALL:%.*]] = tail call i32 (ptr, ...) @printf(ptr @.str, i32 [[REM]])
+; CHECK-NEXT:    ret i32 0
+;
+for.body8.1.preheader:
+  br label %for.body8.1
+
+for.body8.1:                                      ; preds = %for.body8.1, %for.body8.1.preheader
+  %dec.137 = phi i32 [ %dec.1, %for.body8.1 ], [ 1, %for.body8.1.preheader ]
+  %inc1821.1 = phi i64 [ %inc.1, %for.body8.1 ], [ 0, %for.body8.1.preheader ]
+  %inc.1 = add nsw i64 %inc1821.1, 1
+  %dec.1 = add nsw i32 %dec.137, -1
+  %cmp6.1 = icmp sgt i32 %dec.137, 0
+  br i1 %cmp6.1, label %for.body8.1, label %for.inc10.1
+
+for.inc10.1:                                      ; preds = %for.body8.1
+  br label %for.end15
+
+for.end15:                                        ; preds = %for.inc10.1
+  %conv9.le.le.le = zext i32 %dec.137 to i64
+  store i64 %inc1821.1, ptr @l, align 8
+  store i64 %conv9.le.le.le, ptr @i, align 8
+  %rem = urem i32 %dec.1, 53
+  %call = tail call i32 (ptr, ...) @printf(ptr @.str, i32 %rem)
+  ret i32 0
+}
+
+declare i32 @printf(ptr, ...)