Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7314,7 +7314,8 @@
   if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
        (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
       N0.getNode()->hasOneUse() && VT.isInteger() &&
-      !VT.isVector() && !N0.getValueType().isVector()) {
+      TLI.isTypeLegal(N0.getValueType()) && !VT.isVector() &&
+      !N0.getValueType().isVector()) {
     SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT,
                                   N0.getOperand(0));
     AddToWorklist(NewConv.getNode());
@@ -7335,7 +7336,9 @@
   // folded to an fneg or fabs.
   if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
       isa<ConstantFPSDNode>(N0.getOperand(0)) &&
-      VT.isInteger() && !VT.isVector()) {
+      TLI.isTypeLegal(N0.getOperand(0).getValueType()) &&
+      TLI.isTypeLegal(N0.getOperand(1).getValueType()) && VT.isInteger() &&
+      !VT.isVector()) {
     unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
     EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
     if (isTypeLegal(IntXVT)) {
Index: test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
@@ -0,0 +1,19 @@
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; CHECK-NOT:     {{((rldicl|clrldi|clrldi)|(rldicr|sldi|clrrdi))}}
+
+define i128 @test1(ppc_fp128 %x) nounwind  {
+entry:
+	%tmp2 = tail call ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128 %x)
+	%tmp210 = bitcast ppc_fp128 %tmp2 to i128
+	ret i128 %tmp210
+}
+
+define i128 @test2(ppc_fp128 %x) nounwind  {
+entry:
+	%tmp2 = tail call ppc_fp128 @copysignl(ppc_fp128 0xM3FF00000000000000000000000000000, ppc_fp128 %x)
+	%tmp210 = bitcast ppc_fp128 %tmp2 to i128
+	ret i128 %tmp210
+}
+
+declare ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128)
+declare ppc_fp128 @copysignl(ppc_fp128, ppc_fp128)