diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
--- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -171,6 +171,11 @@
     TOCType_EHBlock
   };
 
+  // Controls whether or not to emit a .ref reference to __tls_get_addr.
+  // This is currently used for TLS models that do not generate calls to
+  // TLS functions, such as for the local-exec model on AIX 64-bit.
+  bool HasRefGetTLSAddr = false;
+
   MCSymbol *lookUpOrCreateTOCEntry(const MCSymbol *Sym, TOCEntryType Type,
                                    MCSymbolRefExpr::VariantKind Kind =
                                        MCSymbolRefExpr::VariantKind::VK_None);
@@ -615,12 +620,17 @@
 /// This helper function creates the TlsGetAddr MCSymbol for AIX. We will
 /// create the csect and use the qual-name symbol instead of creating just the
 /// external symbol.
-static MCSymbol *createMCSymbolForTlsGetAddr(MCContext &Ctx, unsigned MIOpc) {
-  StringRef SymName =
-      MIOpc == PPC::GETtlsTpointer32AIX ? ".__get_tpointer" : ".__tls_get_addr";
+static MCSymbol *
+createMCSymbolForTlsGetAddr(MCContext &Ctx, unsigned MIOpc,
+                            XCOFF::StorageMappingClass SMC = XCOFF::XMC_PR) {
+  StringRef SymName;
+  if (MIOpc == PPC::GETtlsTpointer32AIX)
+    SymName = ".__get_tpointer";
+  else
+    SymName = (SMC == XCOFF::XMC_DS) ? "__tls_get_addr" : ".__tls_get_addr";
   return Ctx
       .getXCOFFSection(SymName, SectionKind::getText(),
-                       XCOFF::CsectProperties(XCOFF::XMC_PR, XCOFF::XTY_ER))
+                       XCOFF::CsectProperties(SMC, XCOFF::XTY_ER))
       ->getQualNameSymbol();
 }
 
@@ -832,8 +842,11 @@
     if (MO.getTargetFlags() & PPCII::MO_TPREL_FLAG) {
       assert(MO.isGlobal() && "Only expecting a global MachineOperand here!\n");
       TLSModel::Model Model = TM.getTLSModel(MO.getGlobal());
-      if (Model == TLSModel::LocalExec)
+      if (Model == TLSModel::LocalExec) {
+        if (IsPPC64)
+          HasRefGetTLSAddr = true;
         return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE;
+      }
       if (Model == TLSModel::InitialExec)
         return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSIE;
       llvm_unreachable("Only expecting local-exec or initial-exec accesses!");
@@ -2862,6 +2875,22 @@
     OutStreamer->doFinalizationAtSectionEnd(
         OutStreamer->getContext().getObjectFileInfo()->getTextSection());
 
+  // Add a single .ref reference to __tls_get_addr[DS] for the local-exec TLS
+  // model on AIX 64-bit. For TLS models that do not generate calls to TLS
+  // functions, this reference to __tls_get_addr helps generate a linker error
+  // to an undefined symbol to __tls_get_addr, which indicates to the user that
+  // compiling with -pthread is required for programs that use TLS variables.
+  if (HasRefGetTLSAddr) {
+    // Specifically for 64-bit AIX, a load from the TOC is generated to load
+    // the variable offset needed for local-exec accesses.
+    MCSymbol *TlsGetAddrDescriptor =
+        createMCSymbolForTlsGetAddr(OutContext, PPC::GETtlsADDR64AIX,
+                                    XCOFF::XMC_DS);
+
+    ExtSymSDNodeSymbols.insert(TlsGetAddrDescriptor);
+    OutStreamer->emitXCOFFRefDirective(TlsGetAddrDescriptor);
+  }
+
   for (MCSymbol *Sym : ExtSymSDNodeSymbols)
     OutStreamer->emitSymbolAttribute(Sym, MCSA_Extern);
   return PPCAsmPrinter::doFinalization(M);
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-double.ll b/llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-double.ll
--- a/llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-double.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-double.ll
@@ -635,6 +635,13 @@
   ret double %add
 }
 
+; (64-bit only) External symbol reference checks for __tls_get_addr[DS]
+
+; SMALL64: .ref __tls_get_addr[DS]
+; SMALL64: .extern __tls_get_addr[DS]
+; LARGE64: .ref __tls_get_addr[DS]
+; LARGE64: .extern __tls_get_addr[DS]
+
 ; TOC Entry Checks.
 
 ; SMALL64-LABEL: .toc
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-float.ll b/llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-float.ll
--- a/llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-float.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-float.ll
@@ -635,6 +635,13 @@
   ret float %add
 }
 
+; (64-bit only) External symbol reference checks for __tls_get_addr[DS]
+
+; SMALL64: .ref __tls_get_addr[DS]
+; SMALL64: .extern __tls_get_addr[DS]
+; LARGE64: .ref __tls_get_addr[DS]
+; LARGE64: .extern __tls_get_addr[DS]
+
 ; TOC Entry Checks.
 
 ; SMALL64-LABEL: .toc
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-int.ll b/llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-int.ll
--- a/llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-int.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-int.ll
@@ -651,6 +651,13 @@
   ret i32 %add
 }
 
+; (64-bit only) External symbol reference checks for __tls_get_addr[DS]
+
+; SMALL64: .ref __tls_get_addr[DS]
+; SMALL64: .extern __tls_get_addr[DS]
+; LARGE64: .ref __tls_get_addr[DS]
+; LARGE64: .extern __tls_get_addr[DS]
+
 ; TOC Entry Checks.
 
 ; SMALL64-LABEL: .toc
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-longlong.ll b/llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-longlong.ll
--- a/llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-longlong.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-longlong.ll
@@ -707,6 +707,13 @@
   ret i64 %add
 }
 
+; (64-bit only) External symbol reference checks for __tls_get_addr[DS]
+
+; SMALL64: .ref __tls_get_addr[DS]
+; SMALL64: .extern __tls_get_addr[DS]
+; LARGE64: .ref __tls_get_addr[DS]
+; LARGE64: .extern __tls_get_addr[DS]
+
 ; TOC Entry Checks.
 
 ; SMALL64-LABEL: .toc
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll
--- a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll
@@ -42,63 +42,70 @@
 ; RELOC-NEXT: AddressSize: 64bit
 ; RELOC-NEXT: Relocations [
 ; RELOC:       Virtual Address: 0x2
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (19)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (21)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCU (0x30)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x6
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (19)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (21)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCL (0x31)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x12
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (21)
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (23)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCU (0x30)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x1A
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (21)
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (23)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCL (0x31)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x36
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (25)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (27)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCU (0x30)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x42
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (25)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (27)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCL (0x31)
 ; RELOC-NEXT:     }
+; RELOC:      Virtual Address: 0x0
+; RELOC-NEXT:      Symbol: __tls_get_addr (1)
+; RELOC-NEXT:      IsSigned: No
+; RELOC-NEXT:      FixupBitValue: 0
+; RELOC-NEXT:      Length: 1
+; RELOC-NEXT:      Type: R_REF (0xF)
+; RELOC-NEXT:    }
 ; RELOC:       Virtual Address: 0xA8
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (29)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (31)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 64
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0xB0
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (27)
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (29)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 64
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0xC0
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (31)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (33)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 64
@@ -110,7 +117,25 @@
 ; SYM-NEXT: Arch: powerpc64
 ; SYM-NEXT: AddressSize: 64bit
 ; SYM-NEXT: Symbols [
-; SYM:     Index: 19
+; SYM:    Index: 1
+; SYM-NEXT:    Name: __tls_get_addr
+; SYM-NEXT:    Value (RelocatableAddress): 0x0
+; SYM-NEXT:    Section: N_UNDEF
+; SYM-NEXT:    Type: 0x0
+; SYM-NEXT:    StorageClass: C_EXT (0x2)
+; SYM-NEXT:    NumberOfAuxEntries: 1
+; SYM-NEXT:    CSECT Auxiliary Entry {
+; SYM-NEXT:      Index: 2
+; SYM-NEXT:      SectionLen: 0
+; SYM-NEXT:      ParameterHashIndex: 0x0
+; SYM-NEXT:      TypeChkSectNum: 0x0
+; SYM-NEXT:      SymbolAlignmentLog2: 0
+; SYM-NEXT:      SymbolType: XTY_ER (0x0)
+; SYM-NEXT:      StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:      Auxiliary Type: AUX_CSECT (0xFB)
+; SYM-NEXT:    }
+; SYM-NEXT:  }
+; SYM:     Index: 21
 ; SYM-NEXT:     Name: IThreadLocalVarUninit
 ; SYM-NEXT:     Value (RelocatableAddress): 0xA8
 ; SYM-NEXT:     Section: .data
@@ -118,7 +143,7 @@
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 20
+; SYM-NEXT:       Index: 22
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
@@ -128,7 +153,7 @@
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 21
+; SYM:     Index: 23
 ; SYM-NEXT:     Name: ThreadLocalVarInit
 ; SYM-NEXT:     Value (RelocatableAddress): 0xB0
 ; SYM-NEXT:     Section: .data
@@ -136,7 +161,7 @@
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 22
+; SYM-NEXT:       Index: 24
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
@@ -145,7 +170,7 @@
 ; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
-; SYM:     Index: 25
+; SYM:     Index: 27
 ; SYM-NEXT:     Name: IThreadLocalVarUninit2
 ; SYM-NEXT:     Value (RelocatableAddress): 0xC0
 ; SYM-NEXT:     Section: .data
@@ -153,7 +178,7 @@
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 26
+; SYM-NEXT:       Index: 28
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
@@ -163,7 +188,7 @@
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 27
+; SYM:     Index: 29
 ; SYM-NEXT:     Name: ThreadLocalVarInit
 ; SYM-NEXT:     Value (RelocatableAddress): 0x0
 ; SYM-NEXT:     Section: .tdata
@@ -171,7 +196,7 @@
 ; SYM-NEXT:     StorageClass: C_EXT (0x2)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 28
+; SYM-NEXT:       Index: 30
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
@@ -181,7 +206,7 @@
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 29
+; SYM:     Index: 31
 ; SYM-NEXT:     Name: IThreadLocalVarUninit
 ; SYM-NEXT:     Value (RelocatableAddress): 0x8
 ; SYM-NEXT:     Section: .tbss
@@ -189,7 +214,7 @@
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 30
+; SYM-NEXT:       Index: 32
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
@@ -199,7 +224,7 @@
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 31
+; SYM:     Index: 33
 ; SYM-NEXT:     Name: IThreadLocalVarUninit2
 ; SYM-NEXT:     Value (RelocatableAddress): 0x10
 ; SYM-NEXT:     Section: .tbss
@@ -207,7 +232,7 @@
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 32
+; SYM-NEXT:       Index: 34
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
@@ -220,91 +245,92 @@
 
 ; DIS:      {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o:	file format aix5coff64-rs6000
 ; DIS:      Disassembly of section .text:
-; DIS:      0000000000000000 (idx: 3) .storeITLUninit:
+; DIS:      0000000000000000 (idx: 5) .storeITLUninit:
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 4, 2, 0
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU	(idx: 19) IThreadLocalVarUninit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR]]:     R_REF	(idx: 1)  __tls_get_addr[DS]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU	(idx: 21) IThreadLocalVarUninit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 4, 0(4)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL	(idx: 19) IThreadLocalVarUninit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL	(idx: 21) IThreadLocalVarUninit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                stdx 3, 13, 4
 ; DIS-NEXT:                                       blr
-; DIS:      0000000000000010 (idx: 5) .loadTLInit:
+; DIS:      0000000000000010 (idx: 7) .loadTLInit:
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 3, 2, 0
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 21) ThreadLocalVarInit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 23) ThreadLocalVarInit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 4, 2, 0
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 23) VarInit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 25) VarInit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 3, 8(3)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 21) ThreadLocalVarInit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 23) ThreadLocalVarInit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 4, 16(4)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 23) VarInit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 25) VarInit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ldx 3, 13, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 4, 0(4)
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                add 3, 4, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                blr
-; DIS:      0000000000000030 (idx: 7) .loadTLUninit:
+; DIS:      0000000000000030 (idx: 9) .loadTLUninit:
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 3, 2, 0
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 19) IThreadLocalVarUninit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 21) IThreadLocalVarUninit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 4, 2, 0
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 25) IThreadLocalVarUninit2[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 27) IThreadLocalVarUninit2[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                li 5, 1
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 3, 0(3)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 19) IThreadLocalVarUninit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 21) IThreadLocalVarUninit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 4, 24(4)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 25) IThreadLocalVarUninit2[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 27) IThreadLocalVarUninit2[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                stdx 5, 13, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ldx 3, 13, 4
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addi 3, 3, 1
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                blr
 
 ; DIS:      Disassembly of section .data:
-; DIS:      0000000000000058 (idx: 9) VarInit[RW]:
+; DIS:      0000000000000058 (idx: 11) VarInit[RW]:
 ; DIS-NEXT:       58: 00 00 00 00
 ; DIS-NEXT:       5c: 00 00 00 57
-; DIS:      0000000000000060 (idx: 11) storeITLUninit[DS]:
+; DIS:      0000000000000060 (idx: 13) storeITLUninit[DS]:
 ; DIS-NEXT:       60: 00 00 00 00
-; DIS-NEXT: 0000000000000060:  R_POS        (idx: 3) .storeITLUninit
+; DIS-NEXT: 0000000000000060:  R_POS        (idx: 5) .storeITLUninit
 ; DIS-NEXT:       64: 00 00 00 00
 ; DIS-NEXT:       68: 00 00 00 00
-; DIS-NEXT: 0000000000000068:  R_POS        (idx: 17) TOC[TC0]
+; DIS-NEXT: 0000000000000068:  R_POS        (idx: 19) TOC[TC0]
 ; DIS-NEXT:       6c: 00 00 00 a8
-; DIS:      0000000000000078 (idx: 13) loadTLInit[DS]:
+; DIS:      0000000000000078 (idx: 15) loadTLInit[DS]:
 ; DIS-NEXT:       78: 00 00 00 00
-; DIS-NEXT: 0000000000000078:  R_POS        (idx: 5) .loadTLInit
+; DIS-NEXT: 0000000000000078:  R_POS        (idx: 7) .loadTLInit
 ; DIS-NEXT:       7c: 00 00 00 10
 ; DIS-NEXT:       80: 00 00 00 00
-; DIS-NEXT: 0000000000000080:  R_POS        (idx: 17) TOC[TC0]
+; DIS-NEXT: 0000000000000080:  R_POS        (idx: 19) TOC[TC0]
 ; DIS-NEXT:       84: 00 00 00 a8
-; DIS:      0000000000000090 (idx: 15) loadTLUninit[DS]:
+; DIS:      0000000000000090 (idx: 17) loadTLUninit[DS]:
 ; DIS-NEXT:       90: 00 00 00 00
-; DIS-NEXT: 0000000000000090:  R_POS        (idx: 7) .loadTLUninit
+; DIS-NEXT: 0000000000000090:  R_POS        (idx: 9) .loadTLUninit
 ; DIS-NEXT:       94: 00 00 00 30
 ; DIS-NEXT:       98: 00 00 00 00
-; DIS-NEXT: 0000000000000098:  R_POS        (idx: 17) TOC[TC0]
+; DIS-NEXT: 0000000000000098:  R_POS        (idx: 19) TOC[TC0]
 ; DIS-NEXT:       9c: 00 00 00 a8
-; DIS:      00000000000000a8 (idx: 19) IThreadLocalVarUninit[TE]:
+; DIS:      00000000000000a8 (idx: 21) IThreadLocalVarUninit[TE]:
 ; DIS-NEXT:       a8: 00 00 00 00
-; DIS-NEXT: 00000000000000a8:  R_TLS_LE     (idx: 29) IThreadLocalVarUninit[UL]
+; DIS-NEXT: 00000000000000a8:  R_TLS_LE     (idx: 31) IThreadLocalVarUninit[UL]
 ; DIS-NEXT:       ac: 00 00 00 08
-; DIS:      00000000000000b0 (idx: 21) ThreadLocalVarInit[TE]:
+; DIS:      00000000000000b0 (idx: 23) ThreadLocalVarInit[TE]:
 ; DIS-NEXT:       b0: 00 00 00 00
-; DIS-NEXT: 00000000000000b0:  R_TLS_LE     (idx: 27) ThreadLocalVarInit[TL]
+; DIS-NEXT: 00000000000000b0:  R_TLS_LE     (idx: 29) ThreadLocalVarInit[TL]
 ; DIS-NEXT:       b4: 00 00 00 00
-; DIS:      00000000000000b8 (idx: 23) VarInit[TE]:
+; DIS:      00000000000000b8 (idx: 25) VarInit[TE]:
 ; DIS-NEXT:       b8: 00 00 00 00
-; DIS-NEXT: 00000000000000b8:  R_POS        (idx: 9) VarInit[RW]
+; DIS-NEXT: 00000000000000b8:  R_POS        (idx: 11) VarInit[RW]
 ; DIS-NEXT:       bc: 00 00 00 58
-; DIS:      00000000000000c0 (idx: 25) IThreadLocalVarUninit2[TE]:
+; DIS:      00000000000000c0 (idx: 27) IThreadLocalVarUninit2[TE]:
 ; DIS-NEXT:       c0: 00 00 00 00
-; DIS-NEXT: 00000000000000c0:  R_TLS_LE     (idx: 31) IThreadLocalVarUninit2[UL]
+; DIS-NEXT: 00000000000000c0:  R_TLS_LE     (idx: 33) IThreadLocalVarUninit2[UL]
 ; DIS-NEXT:       c4: 00 00 00 10
 
 ; DIS:      Disassembly of section .tdata:
-; DIS:      0000000000000000 (idx: 27) ThreadLocalVarInit[TL]:
+; DIS:      0000000000000000 (idx: 29) ThreadLocalVarInit[TL]:
 ; DIS-NEXT:        0: 00 00 00 00
 ; DIS-NEXT:        4: 00 00 00 01
 
 ; DIS:      Disassembly of section .tbss:
-; DIS:      0000000000000008 (idx: 29) IThreadLocalVarUninit[UL]:
+; DIS:      0000000000000008 (idx: 31) IThreadLocalVarUninit[UL]:
 ; DIS-NEXT: ...
-; DIS:      0000000000000010 (idx: 31) IThreadLocalVarUninit2[UL]:
+; DIS:      0000000000000010 (idx: 33) IThreadLocalVarUninit2[UL]:
 ; DIS-NEXT: ...
 
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll
--- a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll
@@ -42,42 +42,49 @@
 ; RELOC-NEXT: AddressSize: 64bit
 ; RELOC-NEXT: Relocations [
 ; RELOC:       Virtual Address: 0x2
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (21)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (23)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOC (0x3)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x12
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (23)
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (25)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOC (0x3)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x36
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (27)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (29)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOC (0x3)
 ; RELOC-NEXT:     }
+; RELOC:      Virtual Address: 0x0
+; RELOC-NEXT:      Symbol: __tls_get_addr (1)
+; RELOC-NEXT:      IsSigned: No
+; RELOC-NEXT:      FixupBitValue: 0
+; RELOC-NEXT:      Length: 1
+; RELOC-NEXT:      Type: R_REF (0xF)
+; RELOC-NEXT:    }
 ; RELOC:       Virtual Address: 0xA0
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (33)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (35)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 64
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0xA8
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (31)
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (33)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 64
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0xB8
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (35)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (37)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 64
@@ -89,7 +96,25 @@
 ; SYM-NEXT: Arch: powerpc64
 ; SYM-NEXT: AddressSize: 64bit
 ; SYM-NEXT: Symbols [
-; SYM:     Index: 21
+; SYM:    Index: 1
+; SYM-NEXT:    Name: __tls_get_addr
+; SYM-NEXT:    Value (RelocatableAddress): 0x0
+; SYM-NEXT:    Section: N_UNDEF
+; SYM-NEXT:    Type: 0x0
+; SYM-NEXT:    StorageClass: C_EXT (0x2)
+; SYM-NEXT:    NumberOfAuxEntries: 1
+; SYM-NEXT:    CSECT Auxiliary Entry {
+; SYM-NEXT:      Index: 2
+; SYM-NEXT:      SectionLen: 0
+; SYM-NEXT:      ParameterHashIndex: 0x0
+; SYM-NEXT:      TypeChkSectNum: 0x0
+; SYM-NEXT:      SymbolAlignmentLog2: 0
+; SYM-NEXT:      SymbolType: XTY_ER (0x0)
+; SYM-NEXT:      StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:      Auxiliary Type: AUX_CSECT (0xFB)
+; SYM-NEXT:    }
+; SYM-NEXT:  }
+; SYM:     Index: 23
 ; SYM-NEXT:     Name: IThreadLocalVarUninit
 ; SYM-NEXT:     Value (RelocatableAddress): 0xA0
 ; SYM-NEXT:     Section: .data
@@ -97,7 +122,7 @@
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 22
+; SYM-NEXT:       Index: 24
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
@@ -107,7 +132,7 @@
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 23
+; SYM:     Index: 25
 ; SYM-NEXT:     Name: ThreadLocalVarInit
 ; SYM-NEXT:     Value (RelocatableAddress): 0xA8
 ; SYM-NEXT:     Section: .data
@@ -115,7 +140,7 @@
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 24
+; SYM-NEXT:       Index: 26
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
@@ -125,7 +150,7 @@
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 27
+; SYM:     Index: 29
 ; SYM-NEXT:     Name: IThreadLocalVarUninit2
 ; SYM-NEXT:     Value (RelocatableAddress): 0xB8
 ; SYM-NEXT:     Section: .data
@@ -133,7 +158,7 @@
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 28
+; SYM-NEXT:       Index: 30
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
@@ -143,7 +168,7 @@
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 31
+; SYM:     Index: 33
 ; SYM-NEXT:     Name: ThreadLocalVarInit
 ; SYM-NEXT:     Value (RelocatableAddress): 0x0
 ; SYM-NEXT:     Section: .tdata
@@ -151,8 +176,8 @@
 ; SYM-NEXT:     StorageClass: C_EXT (0x2)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 32
-; SYM-NEXT:       ContainingCsectSymbolIndex: 29
+; SYM-NEXT:       Index: 34
+; SYM-NEXT:       ContainingCsectSymbolIndex: 31
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 0
@@ -161,7 +186,7 @@
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 33
+; SYM:     Index: 35
 ; SYM-NEXT:     Name: IThreadLocalVarUninit
 ; SYM-NEXT:     Value (RelocatableAddress): 0x4
 ; SYM-NEXT:     Section: .tbss
@@ -169,7 +194,7 @@
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 34
+; SYM-NEXT:       Index: 36
 ; SYM-NEXT:       SectionLen: 4
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
@@ -179,7 +204,7 @@
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 35
+; SYM:     Index: 37
 ; SYM-NEXT:     Name: IThreadLocalVarUninit2
 ; SYM-NEXT:     Value (RelocatableAddress): 0x8
 ; SYM-NEXT:     Section: .tbss
@@ -187,7 +212,7 @@
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 36
+; SYM-NEXT:       Index: 38
 ; SYM-NEXT:       SectionLen: 4
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
@@ -200,26 +225,27 @@
 
 ; DIS:      {{.*}}aix-tls-le-xcoff-reloc.ll.tmp.o:	file format aix5coff64-rs6000
 ; DIS:      Disassembly of section .text:
-; DIS:      0000000000000000 (idx: 3) .storeITLUninit:
+; DIS:      0000000000000000 (idx: 5) .storeITLUninit:
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 4, 0(2)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 21) IThreadLocalVarUninit[TC]
+; DIS-NEXT: {{0*}}[[#ADDR]]:     R_REF	(idx: 1)  __tls_get_addr[DS]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 23) IThreadLocalVarUninit[TC]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               stwx 3, 13, 4
 ; DIS-NEXT:                                      blr
-; DIS:      0000000000000010 (idx: 5) .loadTLInit:
+; DIS:      0000000000000010 (idx: 7) .loadTLInit:
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 3, 8(2)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 23) ThreadLocalVarInit[TC]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 25) ThreadLocalVarInit[TC]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 4, 16(2)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 25) VarInit[TC]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 27) VarInit[TC]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwzx 3, 13, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwz 4, 0(4)
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               add 3, 4, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               extsw 3, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               blr
-; DIS:      0000000000000030 (idx: 7) .loadTLUninit:
+; DIS:      0000000000000030 (idx: 9) .loadTLUninit:
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 3, 0(2)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 21) IThreadLocalVarUninit[TC]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 23) IThreadLocalVarUninit[TC]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 4, 24(2)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 27) IThreadLocalVarUninit2[TC]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 29) IThreadLocalVarUninit2[TC]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               li 5, 1
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               stwx 5, 13, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwzx 3, 13, 4
@@ -228,53 +254,53 @@
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               blr
 
 ; DIS:      Disassembly of section .data:
-; DIS:      0000000000000050 (idx: 11) VarInit:
+; DIS:      0000000000000050 (idx: 13) VarInit:
 ; DIS-NEXT:       50: 00 00 00 57
-; DIS:      0000000000000058 (idx: 13) storeITLUninit[DS]:
+; DIS:      0000000000000058 (idx: 15) storeITLUninit[DS]:
 ; DIS-NEXT:       58: 00 00 00 00
-; DIS-NEXT: 0000000000000058:  R_POS        (idx: 3) .storeITLUninit
+; DIS-NEXT: 0000000000000058:  R_POS        (idx: 5) .storeITLUninit
 ; DIS-NEXT:       5c: 00 00 00 00
 ; DIS-NEXT:       60: 00 00 00 00
-; DIS-NEXT: 0000000000000060:  R_POS        (idx: 19) TOC[TC0]
+; DIS-NEXT: 0000000000000060:  R_POS        (idx: 21) TOC[TC0]
 ; DIS-NEXT:       64: 00 00 00 a0
-; DIS:      0000000000000070 (idx: 15) loadTLInit[DS]:
+; DIS:      0000000000000070 (idx: 17) loadTLInit[DS]:
 ; DIS-NEXT:       70: 00 00 00 00
-; DIS-NEXT: 0000000000000070:  R_POS        (idx: 5) .loadTLInit
+; DIS-NEXT: 0000000000000070:  R_POS        (idx: 7) .loadTLInit
 ; DIS-NEXT:       74: 00 00 00 10
 ; DIS-NEXT:       78: 00 00 00 00
-; DIS-NEXT: 0000000000000078:  R_POS        (idx: 19) TOC[TC0]
+; DIS-NEXT: 0000000000000078:  R_POS        (idx: 21) TOC[TC0]
 ; DIS-NEXT:       7c: 00 00 00 a0
-; DIS:      0000000000000088 (idx: 17) loadTLUninit[DS]:
+; DIS:      0000000000000088 (idx: 19) loadTLUninit[DS]:
 ; DIS-NEXT:       88: 00 00 00 00
-; DIS-NEXT: 0000000000000088:  R_POS        (idx: 7) .loadTLUninit
+; DIS-NEXT: 0000000000000088:  R_POS        (idx: 9) .loadTLUninit
 ; DIS-NEXT:       8c: 00 00 00 30
 ; DIS-NEXT:       90: 00 00 00 00
-; DIS-NEXT: 0000000000000090:  R_POS        (idx: 19) TOC[TC0]
+; DIS-NEXT: 0000000000000090:  R_POS        (idx: 21) TOC[TC0]
 ; DIS-NEXT:       94: 00 00 00 a0
-; DIS:      00000000000000a0 (idx: 21) IThreadLocalVarUninit[TC]:
+; DIS:      00000000000000a0 (idx: 23) IThreadLocalVarUninit[TC]:
 ; DIS-NEXT:       a0: 00 00 00 00
-; DIS-NEXT: 00000000000000a0:  R_TLS_LE     (idx: 33) IThreadLocalVarUninit[UL]
+; DIS-NEXT: 00000000000000a0:  R_TLS_LE     (idx: 35) IThreadLocalVarUninit[UL]
 ; DIS-NEXT:       a4: 00 00 00 04
-; DIS:      00000000000000a8 (idx: 23) ThreadLocalVarInit[TC]:
+; DIS:      00000000000000a8 (idx: 25) ThreadLocalVarInit[TC]:
 ; DIS-NEXT:       a8: 00 00 00 00
-; DIS-NEXT: 00000000000000a8:  R_TLS_LE     (idx: 31) ThreadLocalVarInit
+; DIS-NEXT: 00000000000000a8:  R_TLS_LE     (idx: 33) ThreadLocalVarInit
 ; DIS-NEXT:       ac: 00 00 00 00
-; DIS:      00000000000000b0 (idx: 25) VarInit[TC]:
+; DIS:      00000000000000b0 (idx: 27) VarInit[TC]:
 ; DIS-NEXT:       b0: 00 00 00 00
-; DIS-NEXT: 00000000000000b0:  R_POS        (idx: 11) VarInit
+; DIS-NEXT: 00000000000000b0:  R_POS        (idx: 13) VarInit
 ; DIS-NEXT:       b4: 00 00 00 50
-; DIS:      00000000000000b8 (idx: 27) IThreadLocalVarUninit2[TC]:
+; DIS:      00000000000000b8 (idx: 29) IThreadLocalVarUninit2[TC]:
 ; DIS-NEXT:       b8: 00 00 00 00
-; DIS-NEXT: 00000000000000b8:  R_TLS_LE     (idx: 35) IThreadLocalVarUninit2[UL]
+; DIS-NEXT: 00000000000000b8:  R_TLS_LE     (idx: 37) IThreadLocalVarUninit2[UL]
 ; DIS-NEXT:       bc: 00 00 00 08
 
 ; DIS:      Disassembly of section .tdata:
-; DIS:      0000000000000000 (idx: 31) ThreadLocalVarInit:
+; DIS:      0000000000000000 (idx: 33) ThreadLocalVarInit:
 ; DIS-NEXT:        0: 00 00 00 01
 
 ; DIS:      Disassembly of section .tbss:
-; DIS:      0000000000000004 (idx: 33) IThreadLocalVarUninit[UL]:
+; DIS:      0000000000000004 (idx: 35) IThreadLocalVarUninit[UL]:
 ; DIS-NEXT: ...
-; DIS:      0000000000000008 (idx: 35) IThreadLocalVarUninit2[UL]:
+; DIS:      0000000000000008 (idx: 37) IThreadLocalVarUninit2[UL]:
 ; DIS-NEXT: ...